# opensource-uvm

**Repository Path**: aiwep/opensource-uvm

## Basic Information

- **Project Name**: opensource-uvm
- **Description**: 提供一个 Hello, UVM World! 级最小环境，搭配 Verilator 即可跑通，适合第一次上手
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-08-19
- **Last Updated**: 2025-08-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Open-Source UVM with Verilator

This repository is a collection of experiments and resources that combine Universal Verification Methodology (UVM) with Verilator, the open-source RTL simulator.

## Experiments

- `minimal_uvm`: Contains a simple testbench with an empty UVM test to experiment with the compilation and simulation of UVM using Verilator.

## Getting Started

### Prerequisites

- Verilator
- SystemVerilog/UVM libraries

### Installation

1. Clone the repository:
    ```sh
    git clone https://github.com/verificationxpert/opensource-uvm.git
    cd opensource-uvm
    ```

2. Install Verilator:
    Follow the instructions on the [Verilator website](https://www.veripool.org/verilator/).

### Running the Experiments

Navigate to the `minimal_uvm` directory and follow the instructions in the README file within that directory to compile and run the UVM testbench with Verilator.

## Contributing

Contributions are welcome! Please fork the repository and submit a pull request.

## License

This project is licensed under the MIT License - see the [LICENSE](LICENSE) file for details.

## Acknowledgments

- [Verilator](https://www.veripool.org/verilator/)
- [UVM](https://accellera.org/downloads/standards/uvm)