# RISC-V-CPU

**Repository Path**: dongfenga/RISC-V-CPU

## Basic Information

- **Project Name**: RISC-V-CPU
- **Description**: 32-bit two-cycle processor based on RISC-V
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2020-07-01
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# RISC-V CPU

Using logisim-evolution to implement a 32-bit two-cycle processor based on RISC-V.

## Specifications:
http://inst.eecs.berkeley.edu/~cs61c/fa18/projs/03-1/

http://inst.eecs.berkeley.edu/~cs61c/fa18/projs/03-2/