# RISC-V-Single-Cycle-CPU

**Repository Path**: dongfenga/RISC-V-Single-Cycle-CPU

## Basic Information

- **Project Name**: RISC-V-Single-Cycle-CPU
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2020-07-01
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# RISC-V Single Cycle CPU

![Cover Image](cover.jpg)

---

![Result Image](result.jpg)

## Usage

### Play Bad Apple

1. Run `logisim-evolution.jar`.

2. Open `32b_single_cycle_cpu.circ` in Logisim.

3. Load IMEM and DMEM to the right memory modules. 

4. Enable clock.

### Compile your own program

Working on it...

## Notes

- Only instructions used in `bad_apple.s` is tested. Other instructions are NOT guaranteed to be functional. Will be tested later.

- Can achieve ~300 Hz clock rate on a i7-6700K computer.

## Terms and Conditions

The software [Logisim-evoluion](https://github.com/reds-heig/logisim-evolution) is under [GNU GENERAL PUBLIC LICENSE](https://github.com/reds-heig/logisim-evolution/blob/master/LICENSE.md).

This project is under GNU GENERAL PUBLIC LICENSE. Feel free to redistribute it and/or modify it under the terms of the GNU General Public License.