# PIMSim

**Repository Path**: ecnu_guben/PIMSim

## Basic Information

- **Project Name**: PIMSim
- **Description**: PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
- **Primary Language**: Unknown
- **License**: GPL-3.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 2
- **Forks**: 0
- **Created**: 2019-11-29
- **Last Updated**: 2023-10-21

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# PIMSim had updated to V2.0!

Add support to GEM5 full-sytem simulation.

+ Add PIM instructions in GEM5.
+ Executable PIM binary compiler.
+ Detailed User Instruction to help you custmize your own PIM system.
      
# Author

Xu Sheng, Yinhe Han ([HomePage](http://www.carch.ac.cn/~yinhes/)) , Xuehai Qian(University of Southern California)
      
This program is currently maintaind by Xingqi Zou (<zouxingqi@gmail.com>) and Liang Yan (<yanliang405@gmail.com>) .
      
Control Computing Laboratory, State Key Laboratory of Computer Architecture, ICT, CAS.
      
      
# Some recent PIM papers:

- [Buddy-ram: Improving the performance and efficiency of bulk bitwise operations using DRAM](https://arxiv.org/abs/1611.09988) (MICRO 17)

- [Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation](http://ieeexplore.ieee.org/abstract/document/7753257/) (ICCD 2016)

- [LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory](http://ieeexplore.ieee.org/abstract/document/7485993/) (CAL 2016)

- [PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture](http://ieeexplore.ieee.org/abstract/document/7284077/) (ISCA 15)

- [A scalable processing-in-memory accelerator for parallel graph processing](http://ieeexplore.ieee.org/abstract/document/7284059/) (ISCA 15)

- [Data-reorganization: Data Reorganization in Memory Using 3D-stacked DRAM](http://dl.acm.org/citation.cfm?id=2750397) (ISCA 2015)

- [Practical Near-Data Processing for In-memory Analytics Frameworks](http://ieeexplore.ieee.org/abstract/document/7429299/) (PACT 2015)

- [NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules](http://ieeexplore.ieee.org/abstract/document/7056040/) (HPCA 2015)

- [TOP-PIM: Throughput-Oriented Programmable Processing in Memory](http://dl.acm.org/citation.cfm?id=2600213) (HPDC, 2014)

- [RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization](http://ieeexplore.ieee.org/abstract/document/7847625/) (MICRO 2013)

- [ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing](http://dl.acm.org/citation.cfm?id=2744896) (DAC 15)



# And older ones:

- [Mapping irregular applications to DIVA, a PIM-based data-intensive architecture](http://dl.acm.org/citation.cfm?id=331589)

- [Intelligent RAM (IRAM): Chips that remember and compute](http://ieeexplore.ieee.org/abstract/document/585348/)

- [FlexRAM: Toward an advanced intelligent memory system](http://ieeexplore.ieee.org/abstract/document/6378608/) (ICCD 2012)

- [Active pages: A computation model for intelligent memory](http://dl.acm.org/citation.cfm?id=279387)

- [Cellular logic-in-memory arrays](http://ieeexplore.ieee.org/abstract/document/1671347/) (TC)