# SystemVerilogCourse

**Repository Path**: minglie/SystemVerilogCourse

## Basic Information

- **Project Name**: SystemVerilogCourse
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: production
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-08-31
- **Last Updated**: 2024-08-31

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# SystemVerilogCourse
This is a detailed SystemVerilog course with the requried labs to experiment

## Detailed Documentation 
https://github.com/mbits-mirafra/SystemVerilogCourse/wiki

## Latest LRM, year 2017 
https://github.com/mbits-mirafra/SystemVerilogCourse/blob/production/doc/ieee-standard-for-systemverilog-2017.pdf