From 272258317db704a21991a1d023b6ee6375738243 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=AC=91?= Date: Fri, 14 Nov 2025 17:27:47 +0000 Subject: [PATCH] [AArch64] Fix issue width for HIP12 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: 笑 --- llvm/lib/Target/AArch64/AArch64SchedHIP12.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td index 2dcb561a4882..b8ec7d4a39ee 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td +++ b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// def HIP12Model : SchedMachineModel { - let IssueWidth = 16; // HIP12 can dispatch 16 micro-ops per cycle. + let IssueWidth = 8; // HIP12 can dispatch 16 micro-ops per cycle. let MicroOpBufferSize = 320; // Based on the reorder buffer. let LoadLatency = 4; // Basic latency for most load instructions. let MispredictPenalty = 10; // Based on ALU pipeline depth. -- Gitee