Pull Requests · openEuler/llvm-project - Gitee

[WIP][BOLT][LoopDataPrefetch] create prefetch BinaryBasicBlocks

openeuler-cla/yes

ci_failed

sig/Compiler

stat/needs-squash

Draft

Jianghaibo:feature-bolt-data-prefetch openEuler:dev_19.1.7

!341 8

Reviewer：

2025-12-15 10:45

[LICM] Hoist conditional load with sve ffr can merge

openeuler-cla/yes

ci_failed

sig/Compiler

Jianghaibo:feature-hoist-conditional-load openEuler:dev_17.0.6

!340 12

Reviewer：

2025-12-15 10:40

[WIP]Support Profile-Guided Prefetch

openeuler-cla/no

ci_failed

sig/Compiler

newcomer

Draft

乐乐:Feat_pgo_prefetch openEuler:dev_17.0.6

!338 20

Reviewer：

2025-12-12 17:49

[Backport][NFC][SROA][DebugInfo] Reuse existing dbg_assigns where possible (#... conflicted

openeuler-cla/yes

ci_failed

sig/Compiler

stat/needs-squash

jiangning:at-sroa-perf openEuler:dev_16.0.6

!331 16

Reviewer：

2025-12-11 15:53

[Should Review?] Port from llvm-bolt repo can merge

openeuler-cla/yes

ci_failed

sig/Compiler

stat/needs-squash

eastb233:dev17-bolt-port openEuler:dev_17.0.6

!330 13

Reviewer：

2025-12-10 11:02

[WIP] Add Profile-Guilded Prefetch Support

openeuler-cla/no

ci_failed

sig/Compiler

stat/needs-squash

newcomer

Draft

sz-chen:poc-prefetch openEuler:dev_17.0.6

!328 9

Reviewer：

2025-12-06 20:58

[clang] Implement __builtin_ctzg can merge

openeuler-cla/yes

ci_failed

sig/Compiler

newcomer

张京儒:feature-ctzg-zjr openEuler:dev_17.0.6

!327 10

Reviewer：

2025-12-04 15:59

[AArch64] Add feature to disable LSE CAS and use LL/SC fallback

openeuler-cla/yes

ci_failed

sig/Compiler

Draft

jiangning:feature-disable-CAS openEuler:dev_17.0.6

!324 12

Reviewer：

2025-11-29 21:14

循环交换pass can merge

openeuler-cla/no

ci_failed

sig/Compiler

樊学润:dev_17.0.6 openEuler:dev_17.0.6

!323 5

Reviewer：

2025-11-26 13:32

[AArch64] update sve memcpy optimize can merge

openeuler-cla/yes

ci_failed

sig/Compiler

stat/needs-squash

yuxin:feature-addlatestmemcpy openEuler:dev_16.0.6

!316 14

Reviewer：

2025-11-09 15:34

1

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