# loongchip

**Repository Path**: xforcevesa/loongchip

## Basic Information

- **Project Name**: loongchip
- **Description**: An implementation of LoongArch32 Reduced architecture using verilog and verilator with 5-stage pipeline, inherited from chiplab.
- **Primary Language**: Verilog
- **License**: MulanPSL-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 6
- **Forks**: 1
- **Created**: 2024-06-03
- **Last Updated**: 2025-03-17

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# loongchip

An implementation of LoongArch32 Reduced architecture using verilog and verilator with 5-stage pipeline, inherited from [chiplab](https://gitee.com/loongson-edu/chiplab). 

IPC is as low as around 0.76 when running the linux kernel testcase, thus awaiting for further optimization.

## Runing Step

Providing you're to run the simulation, see the following if you've changed your work directory to the root of this project.

> **NOTICE**: Before this, you should following the instructions [here](toolchains/README.md) to install toolchains.

```bash
export CHIPLAB_HOME=$(pwd)
cd $CHIPLAB_HOME/sims/verilator/run_prog
# Examples in the software directory
# Run software/my_program
./configure.sh --run my_program
# Run linux kernel
./configure.sh --run linux
make -j$(nproc)
```

## Documentation

Inherited. TODO.