From 1fd87dc2e3adeab152d4f2dba611b604c9bc3628 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 00:45:17 +0800 Subject: [PATCH 01/57] =?UTF-8?q?feat(xdc):=20=E8=A7=84=E8=8C=83=E5=91=BD?= =?UTF-8?q?=E5=90=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 5 +++- xdc/Minisys_Uart.xdc | 4 +-- xdc/input/Minisys_Clock.xdc | 2 +- xdc/input/Minisys_Switches.xdc | 52 +++++++++++++++++----------------- xdc/output/Minisys_Lights.xdc | 52 +++++++++++++++++----------------- 5 files changed, 59 insertions(+), 56 deletions(-) diff --git a/.gitignore b/.gitignore index 3020201..16844cc 100644 --- a/.gitignore +++ b/.gitignore @@ -16,4 +16,7 @@ bin-release/ # Project files, i.e. `.project`, `.actionScriptProperties` and `.flexProperties` # should NOT be excluded as they contain compiler settings and other important # information for Eclipse / Flash Builder. -vivado/ \ No newline at end of file + +# ide specific +vivado/ +.vscode/ \ No newline at end of file diff --git a/xdc/Minisys_Uart.xdc b/xdc/Minisys_Uart.xdc index 4dc9b35..cfa27aa 100644 --- a/xdc/Minisys_Uart.xdc +++ b/xdc/Minisys_Uart.xdc @@ -1,2 +1,2 @@ -set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports EGO1_Uart_fromPC] -set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports EGO1_Uart_toPC] \ No newline at end of file +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports Minisys_Uart_fromPC] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports Minisys_Uart_toPC] \ No newline at end of file diff --git a/xdc/input/Minisys_Clock.xdc b/xdc/input/Minisys_Clock.xdc index 6fc3d9b..7f7b7f2 100644 --- a/xdc/input/Minisys_Clock.xdc +++ b/xdc/input/Minisys_Clock.xdc @@ -2,7 +2,7 @@ # Minisys的时钟信号是100MHz(1s有100M个cycle) set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports Minisys_Clock] # 板子上标记了S6的按钮是复位按钮。 -set_property -dict {PACKAGE_PIN S6 IOSTANDARD LVCMOS33} [get_ports Minisys_Reset] +# set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports Minisys_Reset] diff --git a/xdc/input/Minisys_Switches.xdc b/xdc/input/Minisys_Switches.xdc index 9b9ceec..7e240b6 100644 --- a/xdc/input/Minisys_Switches.xdc +++ b/xdc/input/Minisys_Switches.xdc @@ -1,32 +1,32 @@ ## 开关绑定 ## 是板子下面的24个开关。 ## 分为高（RLD）、中（YLD）、低（GLD）各8个。高中低表示作为二进制数，左边是高比特位(significant bit)。 -#set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[7]}] -#set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[6]}] -#set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[5]}] -#set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[4]}] -#set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[3]}] -#set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[2]}] -#set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[1]}] -#set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[0]}] -## -#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[7]}] -#set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[6]}] -#set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[5]}] -#set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[4]}] -#set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[3]}] -#set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[2]}] -#set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[1]}] -#set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[0]}] -## -#set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[7]}] -#set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[6]}] -#set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[5]}] -#set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[4]}] -#set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[3]}] -#set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[2]}] -#set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[1]}] -#set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[0]}] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[7]}] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[6]}] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[5]}] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[4]}] +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[3]}] +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[2]}] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[1]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_High[0]}] +# +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[7]}] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[6]}] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[5]}] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[4]}] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[3]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[2]}] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[1]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Middle[0]}] +# +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[7]}] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[6]}] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[5]}] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[4]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[3]}] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[2]}] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[1]}] +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches_Low[0]}] # 不区分左中右，也可以接受 set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {Minisys_Switches[23]}] diff --git a/xdc/output/Minisys_Lights.xdc b/xdc/output/Minisys_Lights.xdc index 31a8f13..c75a660 100644 --- a/xdc/output/Minisys_Lights.xdc +++ b/xdc/output/Minisys_Lights.xdc @@ -1,32 +1,32 @@ ## 灯光绑定 ## 是板子下面的24个小led灯。 ## 分为高（RLD）、中（YLD）、低（GLD）各8个。高中低表示作为二进制数，左边是高比特位(significant bit)。 -#set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[7]}] -#set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[6]}] -#set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[5]}] -#set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[4]}] -#set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[3]}] -#set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[2]}] -#set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[1]}] -#set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[0]}] -## -#set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[7]}] -#set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[6]}] -#set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[5]}] -#set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[4]}] -#set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[3]}] -#set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[2]}] -#set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[1]}] -#set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[0]}] -## -#set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[7]}] -#set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[6]}] -#set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[5]}] -#set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[4]}] -#set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[3]}] -#set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[2]}] -#set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[1]}] -#set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[0]}] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[7]}] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[6]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[5]}] +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[4]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[3]}] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[2]}] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[1]}] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_High[0]}] +# +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[7]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[6]}] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[5]}] +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[4]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[3]}] +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[2]}] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[1]}] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Middle[0]}] +# +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[7]}] +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[6]}] +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[5]}] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[4]}] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[3]}] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[2]}] +set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[1]}] +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights_Low[0]}] # 不区分左中右，也可以接受 set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports {Minisys_Lights[23]}] -- Gitee From dee1a54d33510ca6962a2d5b3dbc63c7ece05ea8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 01:08:00 +0800 Subject: [PATCH 02/57] =?UTF-8?q?refrac(main,test):=20=E6=96=87=E4=BB=B6?= =?UTF-8?q?=E5=A4=B9=E5=B1=82=E6=AC=A1=E6=9B=B4=E6=B8=85=E6=99=B0=EF=BC=8C?= =?UTF-8?q?mips=E8=AF=AD=E8=A8=80=E5=88=86=E6=96=87=E4=BB=B6=E5=A4=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../c_help}/demo_read_switch_write_led.c | 0 main/{test_coe => mips/coe}/dmem32.coe | 0 main/{test_coe => mips/coe}/prgmip32.coe | 0 main/{asm => mips/commons}/stdio_minisys.mips | 0 main/{asm => mips/commons}/stdsort.mips | 0 main/mips/cpu_test/cpu_test.md | 34 +++++++ main/{asm => mips/cpu_test}/demo_flow.mips | 0 .../cpu_test/demo_read_switch_write_led.mips} | 0 .../cpu_test/jaltest.mips} | 0 .../cpu_test/situation1.mips} | 0 .../cpu_test/situation2.mips} | 0 main/mips/test/test.md | 4 + main/{asm => mips/test}/testsort.mips | 0 main/{ => verilog}/basic_modules/CPUTOP.v | 0 main/{ => verilog}/basic_modules/Decoder.v | 0 main/{ => verilog}/basic_modules/Ifetc32.v | 0 main/{ => verilog}/basic_modules/LED.v | 0 main/{ => verilog}/basic_modules/MemOrIO.v | 0 main/{ => verilog}/basic_modules/TOP_all.v | 0 main/{ => verilog}/basic_modules/control32.v | 0 main/{ => verilog}/basic_modules/dmemory32.v | 0 main/{ => verilog}/basic_modules/executs32.v | 0 main/{ => verilog}/basic_modules/program.v | 90 +++++++++---------- main/{ => verilog}/basic_modules/switch.v | 0 main/{ => verilog}/testMinisys/light_switch.v | 0 main/sim/sim1.v => test/verilog/testCpuTop.v | 0 .../testMinisys/test_light_swich.v | 0 27 files changed, 83 insertions(+), 45 deletions(-) rename main/{asm => mips/c_help}/demo_read_switch_write_led.c (100%) rename main/{test_coe => mips/coe}/dmem32.coe (100%) rename main/{test_coe => mips/coe}/prgmip32.coe (100%) rename main/{asm => mips/commons}/stdio_minisys.mips (100%) rename main/{asm => mips/commons}/stdsort.mips (100%) create mode 100644 main/mips/cpu_test/cpu_test.md rename main/{asm => mips/cpu_test}/demo_flow.mips (100%) rename main/{asm/demo_read_switch_write_led.asm => mips/cpu_test/demo_read_switch_write_led.mips} (100%) rename main/{asm/jaltest.asm => mips/cpu_test/jaltest.mips} (100%) rename main/{asm/situation1.asm => mips/cpu_test/situation1.mips} (100%) rename main/{asm/situation2.asm => mips/cpu_test/situation2.mips} (100%) create mode 100644 main/mips/test/test.md rename main/{asm => mips/test}/testsort.mips (100%) rename main/{ => verilog}/basic_modules/CPUTOP.v (100%) rename main/{ => verilog}/basic_modules/Decoder.v (100%) rename main/{ => verilog}/basic_modules/Ifetc32.v (100%) rename main/{ => verilog}/basic_modules/LED.v (100%) rename main/{ => verilog}/basic_modules/MemOrIO.v (100%) rename main/{ => verilog}/basic_modules/TOP_all.v (100%) rename main/{ => verilog}/basic_modules/control32.v (100%) rename main/{ => verilog}/basic_modules/dmemory32.v (100%) rename main/{ => verilog}/basic_modules/executs32.v (100%) rename main/{ => verilog}/basic_modules/program.v (96%) rename main/{ => verilog}/basic_modules/switch.v (100%) rename main/{ => verilog}/testMinisys/light_switch.v (100%) rename main/sim/sim1.v => test/verilog/testCpuTop.v (100%) rename test/{ => verilog}/testMinisys/test_light_swich.v (100%) diff --git a/main/asm/demo_read_switch_write_led.c b/main/mips/c_help/demo_read_switch_write_led.c similarity index 100% rename from main/asm/demo_read_switch_write_led.c rename to main/mips/c_help/demo_read_switch_write_led.c diff --git a/main/test_coe/dmem32.coe b/main/mips/coe/dmem32.coe similarity index 100% rename from main/test_coe/dmem32.coe rename to main/mips/coe/dmem32.coe diff --git a/main/test_coe/prgmip32.coe b/main/mips/coe/prgmip32.coe similarity index 100% rename from main/test_coe/prgmip32.coe rename to main/mips/coe/prgmip32.coe diff --git a/main/asm/stdio_minisys.mips b/main/mips/commons/stdio_minisys.mips similarity index 100% rename from main/asm/stdio_minisys.mips rename to main/mips/commons/stdio_minisys.mips diff --git a/main/asm/stdsort.mips b/main/mips/commons/stdsort.mips similarity index 100% rename from main/asm/stdsort.mips rename to main/mips/commons/stdsort.mips diff --git a/main/mips/cpu_test/cpu_test.md b/main/mips/cpu_test/cpu_test.md new file mode 100644 index 0000000..f316120 --- /dev/null +++ b/main/mips/cpu_test/cpu_test.md @@ -0,0 +1,34 @@ +## mips/cpu_test 鏂囦欢澶 + +鏈枃浠跺す鏀剧疆mips姹囩紪鏂囦欢锛岃繖浜涙眹缂栨枃浠跺彲浠ュ湪缁忚繃MARS_GUI 鍙互瀵煎嚭涓簎art鏍煎紡鏂囦欢 +浠庤岃繍琛屽埌鏈」鐩疄鐜扮殑鍩轰簬Minisys寮鍙戞澘鐨凜PU涓娿 + +### 娴嬭瘯椤圭洰 + +- demo_read_swtich_write_led.mips + - 鏈熸湜琛屼负锛氳繖鏄渶绠鍗曠殑娴嬭瘯鍦烘櫙锛屽綋瀵煎叆鍒版垜浠殑CPU涓婂悗锛岀敤鎴锋寜浠涔堟寜閿氨浼氫寒浠涔堢伅銆 + - 楠岃瘉鐨勭‖浠跺姛鑳斤細lw, sw, j鐨勬敮鎸侊紱MemOrIOn妯″潡銆 +- jal_test.mips + - 鏈熸湜琛屼负锛氬彸杈圭殑16鐩忕伅鍏ㄤ寒璧锋潵 + - 楠岃瘉鐨勭‖浠跺姛鑳斤細jal, jr, j, sw鐨勬敮鎸侊紱 +- demo_flow.mips + - 鏈熸湜琛屼负锛氬乏杈圭殑鍏釜鐏瘡闅1s杞祦浜捣鏉ワ紝褰㈡垚娴佹按鐏 + - 楠岃瘉鐨勭‖浠跺姛鑳斤細jal, jr, j, sw, lw鐨勬敮鎸侊紱 + - 楠岃瘉鐨勮蒋浠跺姛鑳斤細commons/stdio_minisys.mips 鐨 sleep, write_control鍑芥暟銆 +- situation1.mips + - 濡俻roject鏂囨。鎵杩般 +- situation2.mips + - 濡俻roject鏂囨。鎵杩般 + +### 娴嬭瘯鐘舵 + +- demo_read_swtich_write_led.mips + - 閫氳繃 +- jal_test.mips + - 閫氳繃 +- demo_flow.mips + - 閫氳繃 +- situation1.mips + - 閫氳繃銆傞渶瑕乺eview銆 +- situation2.mips + - 缂栧啓涓 \ No newline at end of file diff --git a/main/asm/demo_flow.mips b/main/mips/cpu_test/demo_flow.mips similarity index 100% rename from main/asm/demo_flow.mips rename to main/mips/cpu_test/demo_flow.mips diff --git a/main/asm/demo_read_switch_write_led.asm b/main/mips/cpu_test/demo_read_switch_write_led.mips similarity index 100% rename from main/asm/demo_read_switch_write_led.asm rename to main/mips/cpu_test/demo_read_switch_write_led.mips diff --git a/main/asm/jaltest.asm b/main/mips/cpu_test/jaltest.mips similarity index 100% rename from main/asm/jaltest.asm rename to main/mips/cpu_test/jaltest.mips diff --git a/main/asm/situation1.asm b/main/mips/cpu_test/situation1.mips similarity index 100% rename from main/asm/situation1.asm rename to main/mips/cpu_test/situation1.mips diff --git a/main/asm/situation2.asm b/main/mips/cpu_test/situation2.mips similarity index 100% rename from main/asm/situation2.asm rename to main/mips/cpu_test/situation2.mips diff --git a/main/mips/test/test.md b/main/mips/test/test.md new file mode 100644 index 0000000..ea25b01 --- /dev/null +++ b/main/mips/test/test.md @@ -0,0 +1,4 @@ +## mips/test 鏂囦欢澶 + +鏈枃浠跺す鏀剧疆mips姹囩紪鏂囦欢锛岃繖浜涙眹缂栨枃浠跺彲浠ュ湪MARS浠跨湡鐜涓嬭繍琛屻 +浠庤岄獙璇乵ips姹囩紪绠楁硶銆佸嚱鏁扮殑姝ｇ‘鎬с \ No newline at end of file diff --git a/main/asm/testsort.mips b/main/mips/test/testsort.mips similarity index 100% rename from main/asm/testsort.mips rename to main/mips/test/testsort.mips diff --git a/main/basic_modules/CPUTOP.v b/main/verilog/basic_modules/CPUTOP.v similarity index 100% rename from main/basic_modules/CPUTOP.v rename to main/verilog/basic_modules/CPUTOP.v diff --git a/main/basic_modules/Decoder.v b/main/verilog/basic_modules/Decoder.v similarity index 100% rename from main/basic_modules/Decoder.v rename to main/verilog/basic_modules/Decoder.v diff --git a/main/basic_modules/Ifetc32.v b/main/verilog/basic_modules/Ifetc32.v similarity index 100% rename from main/basic_modules/Ifetc32.v rename to main/verilog/basic_modules/Ifetc32.v diff --git a/main/basic_modules/LED.v b/main/verilog/basic_modules/LED.v similarity index 100% rename from main/basic_modules/LED.v rename to main/verilog/basic_modules/LED.v diff --git a/main/basic_modules/MemOrIO.v b/main/verilog/basic_modules/MemOrIO.v similarity index 100% rename from main/basic_modules/MemOrIO.v rename to main/verilog/basic_modules/MemOrIO.v diff --git a/main/basic_modules/TOP_all.v b/main/verilog/basic_modules/TOP_all.v similarity index 100% rename from main/basic_modules/TOP_all.v rename to main/verilog/basic_modules/TOP_all.v diff --git a/main/basic_modules/control32.v b/main/verilog/basic_modules/control32.v similarity index 100% rename from main/basic_modules/control32.v rename to main/verilog/basic_modules/control32.v diff --git a/main/basic_modules/dmemory32.v b/main/verilog/basic_modules/dmemory32.v similarity index 100% rename from main/basic_modules/dmemory32.v rename to main/verilog/basic_modules/dmemory32.v diff --git a/main/basic_modules/executs32.v b/main/verilog/basic_modules/executs32.v similarity index 100% rename from main/basic_modules/executs32.v rename to main/verilog/basic_modules/executs32.v diff --git a/main/basic_modules/program.v b/main/verilog/basic_modules/program.v similarity index 96% rename from main/basic_modules/program.v rename to main/verilog/basic_modules/program.v index bd68174..ac27c97 100644 --- a/main/basic_modules/program.v +++ b/main/verilog/basic_modules/program.v @@ -1,45 +1,45 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2022/05/10 01:36:24 -// Design Name: -// Module Name: programrom -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module programrom ( -// Program ROM Pinouts -input rom_clk_i, // ROM clock -input[13:0] rom_adr_i, // From IFetch -output [31:0] Instruction_o, // To IFetch -// UART Programmer Pinouts -input upg_rst_i, // UPG reset (Active High) -input upg_clk_i, // UPG clock (10MHz) -input upg_wen_i, // UPG write enable -input[13:0] upg_adr_i, // UPG write address -input[31:0] upg_dat_i, // UPG write data -input upg_done_i // 1 if program finished -); -/* if kickOff is 1 means CPU work on normal mode, otherwise CPU work on Uart communication mode */ -wire kickOff = upg_rst_i | (~upg_rst_i & upg_done_i ); -prgrom instmem ( -.clka (kickOff ? rom_clk_i : upg_clk_i ), -.wea (kickOff ? 1'b0 : upg_wen_i ), -.addra (kickOff ? rom_adr_i : upg_adr_i ), -.dina (kickOff ? 32'h00000000 : upg_dat_i ), -.douta (Instruction_o) -); -endmodule +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2022/05/10 01:36:24 +// Design Name: +// Module Name: programrom +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module programrom ( +// Program ROM Pinouts +input rom_clk_i, // ROM clock +input[13:0] rom_adr_i, // From IFetch +output [31:0] Instruction_o, // To IFetch +// UART Programmer Pinouts +input upg_rst_i, // UPG reset (Active High) +input upg_clk_i, // UPG clock (10MHz) +input upg_wen_i, // UPG write enable +input[13:0] upg_adr_i, // UPG write address +input[31:0] upg_dat_i, // UPG write data +input upg_done_i // 1 if program finished +); +/* if kickOff is 1 means CPU work on normal mode, otherwise CPU work on Uart communication mode */ +wire kickOff = upg_rst_i | (~upg_rst_i & upg_done_i ); +prgrom instmem ( +.clka (kickOff ? rom_clk_i : upg_clk_i ), +.wea (kickOff ? 1'b0 : upg_wen_i ), +.addra (kickOff ? rom_adr_i : upg_adr_i ), +.dina (kickOff ? 32'h00000000 : upg_dat_i ), +.douta (Instruction_o) +); +endmodule diff --git a/main/basic_modules/switch.v b/main/verilog/basic_modules/switch.v similarity index 100% rename from main/basic_modules/switch.v rename to main/verilog/basic_modules/switch.v diff --git a/main/testMinisys/light_switch.v b/main/verilog/testMinisys/light_switch.v similarity index 100% rename from main/testMinisys/light_switch.v rename to main/verilog/testMinisys/light_switch.v diff --git a/main/sim/sim1.v b/test/verilog/testCpuTop.v similarity index 100% rename from main/sim/sim1.v rename to test/verilog/testCpuTop.v diff --git a/test/testMinisys/test_light_swich.v b/test/verilog/testMinisys/test_light_swich.v similarity index 100% rename from test/testMinisys/test_light_swich.v rename to test/verilog/testMinisys/test_light_swich.v -- Gitee From 96ab9ff13f740adb47c720e422d94987a5078537 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 01:14:06 +0800 Subject: [PATCH 03/57] =?UTF-8?q?refrac(main):=20readme=20=E8=A7=A3?= =?UTF-8?q?=E9=87=8A=E6=96=87=E4=BB=B6=E5=A4=B9=E5=88=86=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/commons.md | 18 ++++++++++++++++++ .../{stdsort.mips => std_algorithm.mips} | 0 ...{stdio_minisys.mips => std_io_minisys.mips} | 0 3 files changed, 18 insertions(+) create mode 100644 main/mips/commons/commons.md rename main/mips/commons/{stdsort.mips => std_algorithm.mips} (100%) rename main/mips/commons/{stdio_minisys.mips => std_io_minisys.mips} (100%) diff --git a/main/mips/commons/commons.md b/main/mips/commons/commons.md new file mode 100644 index 0000000..257af1b --- /dev/null +++ b/main/mips/commons/commons.md @@ -0,0 +1,18 @@ +## mips/commons 鏂囦欢澶 + +鏈枃浠跺す鏀剧疆mips鍑芥暟搴擄紝涓烘祴璇曞満鏅殑缂栧啓鎻愪緵寮哄ぇ銆佺ǔ瀹氥佸彲闈犵殑鍑芥暟鏀寔銆 + +### 搴 + +- std_io_minisys.mips + - 鎻忚堪 + - 涓簃inisys鐨刲ed鐏佸紑鍏崇殑杈撳叆杈撳嚭鎻愪緵鏍囧噯鎺ュ彛銆 + - 瀵规爣C璇█\ 澶存枃浠躲 + - 鍑芥暟鏂囨。 + + +- std_algorithm + - 鎻忚堪 + - 涓簃ips鍐呭瓨涓暟缁勭殑鍚勭绠楁硶鎿嶄綔鎻愪緵鏍囧噯鎺ュ彛涓庨珮鏁堢殑瀹炵幇銆 + - 瀵规爣C++璇█鐨刓澶存枃浠躲 + - 鍑芥暟鏂囨。 diff --git a/main/mips/commons/stdsort.mips b/main/mips/commons/std_algorithm.mips similarity index 100% rename from main/mips/commons/stdsort.mips rename to main/mips/commons/std_algorithm.mips diff --git a/main/mips/commons/stdio_minisys.mips b/main/mips/commons/std_io_minisys.mips similarity index 100% rename from main/mips/commons/stdio_minisys.mips rename to main/mips/commons/std_io_minisys.mips -- Gitee From 6bde1ec113317215dd879555f32a0886e731d54f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 02:38:08 +0800 Subject: [PATCH 04/57] =?UTF-8?q?feat(mips=20commons):=20=E5=A2=9E?= =?UTF-8?q?=E5=8A=A0max=E5=92=8Cmin=EF=BC=9Bstd=5Falgorithm=E6=B5=8B?= =?UTF-8?q?=E8=AF=95=E9=80=9A=E8=BF=87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_algorithm.mips | 33 ++++++++++++++++++++++++---- main/mips/test/test.md | 8 ++++++- main/mips/test/testsort.mips | 18 +++++++++++++-- 3 files changed, 52 insertions(+), 7 deletions(-) diff --git a/main/mips/commons/std_algorithm.mips b/main/mips/commons/std_algorithm.mips index cc1ed2d..50d1cf2 100644 --- a/main/mips/commons/std_algorithm.mips +++ b/main/mips/commons/std_algorithm.mips @@ -2,7 +2,7 @@ # v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛 a0 鐩爣鏁扮粍棣栧厓绱犲湴鍧; to_signed_array: for_to_signed_array: - beq $v0 $v1 end_for_to_signed_array# 纰板埌灏惧厓绱狅紝寰幆缁撴潫 + bge $v0 $v1 end_for_to_signed_array# 纰板埌灏惧厓绱狅紝寰幆缁撴潫 lw $t0 0($v0) sll $t0 $t0 24 sra $t0 $t0 24 @@ -16,7 +16,7 @@ to_signed_array: # v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛 a0 鐩爣鏁扮粍棣栧厓绱犲湴鍧; copy: for_copy: - beq $v0 $v1 end_for_copy + bge $v0 $v1 end_for_copy lw $t0 0($v0) sw $t0 0($a0) addi $a0 $a0 4 @@ -24,12 +24,37 @@ copy: j for_copy end_for_copy: jr $ra +# v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛涙眰鏁扮粍鐨勬渶澶у兼斁鍒癮0銆傞粯璁ゆ湁绗﹀彿姣旇緝锛屽8浣嶆棤绗﹀彿鐨勬瘮杈冧篃鏄湁鏁堢殑銆 +max: + lw $a0 0($v0) + for_max: + addi $v0 $v0 4 + bge $v0 $v1 end_for_max + lw $t0 0($v0) + ble $t0 $a0 for_max + move $a0 $t0 + j for_max + end_for_max: + jr $ra +# v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛涙眰鏁扮粍鐨勬渶灏忓兼斁鍒癮0銆傞粯璁ゆ湁绗﹀彿姣旇緝锛屽8浣嶆棤绗﹀彿鐨勬瘮杈冧篃鏄湁鏁堢殑銆 +min: + lw $a0 0($v0) + for_min: + addi $v0 $v0 4 + bge $v0 $v1 end_for_min + lw $t0 0($v0) + bge $t0 $a0 for_min + move $a0 $t0 + j for_min + end_for_min: + jr $ra + # 瀵规暟缁勫仛鎻掑叆鎺掑簭 -# v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛涢粯璁ゆ槸鏈夌鍙锋瘮杈冦傚8浣嶆棤绗﹀彿鐨勬瘮杈冧篃鏄湁鏁堢殑銆 +# v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛涢粯璁ゆ槸鏈夌鍙锋瘮杈冿紝瀵8浣嶆棤绗﹀彿鐨勬瘮杈冧篃鏄湁鏁堢殑銆 insertion_sort: addi $t2 $v0 4 # t2 鎸囬拡 琛ㄧず褰撳墠v0-t2閮芥帓濂藉簭浜嗭紙涓嶅惈t2锛 for_insertion_sort0: - beq $t2 $v1 end_for_insertion_sort0 # 纰板埌灏惧厓绱狅紝寰幆缁撴潫 + bge $t2 $v1 end_for_insertion_sort0 # 纰板埌灏惧厓绱狅紝寰幆缁撴潫 addi $t1 $t2 -4 # t1 鎸囬拡锛岀敤鏉ラ亶鍘嗗墠闈㈢殑鍏冪礌銆 lw $t0 0($t2) # t0 涓哄綋鍓嶆柊鍏冪礌 for_insertion_sort1: diff --git a/main/mips/test/test.md b/main/mips/test/test.md index ea25b01..237c599 100644 --- a/main/mips/test/test.md +++ b/main/mips/test/test.md @@ -1,4 +1,10 @@ ## mips/test 鏂囦欢澶 鏈枃浠跺す鏀剧疆mips姹囩紪鏂囦欢锛岃繖浜涙眹缂栨枃浠跺彲浠ュ湪MARS浠跨湡鐜涓嬭繍琛屻 -浠庤岄獙璇乵ips姹囩紪绠楁硶銆佸嚱鏁扮殑姝ｇ‘鎬с \ No newline at end of file +浠庤岄獙璇乵ips姹囩紪绠楁硶銆佸嚱鏁扮殑姝ｇ‘鎬с + +### 娴嬭瘯椤圭洰 +- testsort.mips + - 鏈熸湜琛屼负锛氳繖鏄渶绠鍗曠殑娴嬭瘯鍦烘櫙锛屽綋瀵煎叆鍒版垜浠殑CPU涓婂悗锛岀敤鎴锋寜浠涔堟寜閿氨浼氫寒浠涔堢伅銆 + - 楠岃瘉鐨勮蒋浠跺姛鑳斤細std_algorithm.mips 搴撶殑鎺掑簭銆佹眰鏈澶ф渶灏忓笺佹棤绗﹀彿杞湁绗﹀彿绛夌畻娉曘 +### 娴嬭瘯鐘舵 diff --git a/main/mips/test/testsort.mips b/main/mips/test/testsort.mips index 71ae1d0..e36e384 100644 --- a/main/mips/test/testsort.mips +++ b/main/mips/test/testsort.mips @@ -15,11 +15,25 @@ move $v0 $s0 addi $v1 $v0 20 move $a0 $v1 - jal copy + # jal copy + jal to_signed_array addi $v0 $s0 20 addi $v1 $v0 20 jal insertion_sort + addi $v0 $s0 20 + addi $v1 $v0 20 + jal max + li $v0 1 + syscall + addi $v0 $s0 20 + addi $v1 $v0 20 + jal min + li $v0 1 + syscall + + li $v0 10 + syscall -.include "stdsort.mips" +.include "../commons/std_algorithm.mips" -- Gitee From d4848bfdac5b4560b4c744a69bb07aa9bd96883b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 03:13:43 +0800 Subject: [PATCH 05/57] =?UTF-8?q?refrac(mips):=20include=E8=B7=AF=E5=BE=84?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/demo_flow.mips | 3 ++- main/mips/cpu_test/situation2.mips | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/main/mips/cpu_test/demo_flow.mips b/main/mips/cpu_test/demo_flow.mips index 0609806..71557f9 100644 --- a/main/mips/cpu_test/demo_flow.mips +++ b/main/mips/cpu_test/demo_flow.mips @@ -46,4 +46,5 @@ case7: li $v0 500 jal sleep j while0 -.include "stdio_minisys.mips" +.include "../commons/std_io_minisys.mips" + diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index fd108d4..2ec95dc 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -47,4 +47,4 @@ case7: jal write_control j begin j begin -.include "stdio_minisys.mips" \ No newline at end of file +.include "../commons/std_io_minisys.mips" \ No newline at end of file -- Gitee From 64bd9e4706da78d17d6d11f32d24cf950ed97fac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 03:14:10 +0800 Subject: [PATCH 06/57] =?UTF-8?q?fix(mips):=20stdio=20read=20,=20=E4=BD=BF?= =?UTF-8?q?=E7=94=A8=E6=96=B0=E7=9A=84=E6=8E=A5=E5=8F=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.mips | 32 ++++++++++++++++++--------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/main/mips/commons/std_io_minisys.mips b/main/mips/commons/std_io_minisys.mips index 2dab38d..37e0d09 100644 --- a/main/mips/commons/std_io_minisys.mips +++ b/main/mips/commons/std_io_minisys.mips @@ -76,27 +76,37 @@ decode: #娴嬭瘯鐘舵侊細鍗遍櫓 # 鏍规嵁a1鐨別nter淇″彿鎺у埗锛岀瓑寰呰緭鍏ヤ竴涓暣鏁帮紙閫氳繃鍙冲紑鍏筹級锛岀粨鏋滀繚瀛樺埌a0銆 # a1鍜宎0閮戒細鏀瑰彉銆 +# note: 鐘舵侀攣瀹氾細闃诲璇诲彇鐘舵佷笅鏃犳硶淇敼妯″紡銆 read: save_ra() + write_control_set_true(4) jal decode - li $v0 4 - jal write_control_set #鎻愮ず鐢ㄦ埛绛夊緟enter淇″彿 bne $a1 $zero read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟enter鏄0 - li $v0 4 - li $v1 0 - jal write_control #鍙栨秷 + write_control_set_false(4) read_wait_for_enter: + li $t0 0 jal decode - li $v0 3 - li $v1 1 - jal write_control #鎻愮ず鐢ㄦ埛绛夊緟enter淇″彿 + addi $t0 $t0 1 + li $t1 0x15EF3C0 + blt $t0 $t1 end_if_wait_for_enter + sub $t0 $t0 $t1 + li $v0 4 + jal write_control_negate + end_if_wait_for_enter: beq $a1 $zero read_wait_for_enter # 绛夊埌enter鏄1銆 - li $v0 3 - li $v1 0 - jal write_control #鎻愮ず鐢ㄦ埛绛夊緟enter淇″彿 lw $a0 0x70($gp) load_ra() jr $ra +.macro write_control_set_true(%index) + li $v0 %index + li $v1 1 + jal write_control_set +.end_macro +.macro write_control_set_false(%index) + li $v0 %index + li $v1 0 + jal write_control_set +.end_macro # 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涙牴鎹畍1鐨勫肩殑鏈鍚庝竴浣嶆槸鍚︽槸1鏉ヤ慨鏀 write_control_set: lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 -- Gitee From 2b23e1d685843e12a4ff274a009834a4257180cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 04:03:48 +0800 Subject: [PATCH 07/57] =?UTF-8?q?fix(mips=20commons)=EF=BC=9A=E7=94=A8?= =?UTF-8?q?=E5=BB=B6=E6=97=B6=E8=A7=A3=E5=86=B3=E4=BA=86stdread=E9=97=AE?= =?UTF-8?q?=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.mips | 44 ++++++++++++++++----------- main/mips/cpu_test/situation2.mips | 14 +++++++-- 2 files changed, 38 insertions(+), 20 deletions(-) diff --git a/main/mips/commons/std_io_minisys.mips b/main/mips/commons/std_io_minisys.mips index 37e0d09..9ddc622 100644 --- a/main/mips/commons/std_io_minisys.mips +++ b/main/mips/commons/std_io_minisys.mips @@ -14,6 +14,16 @@ lw $ra 0($sp) addi $sp $sp +4 .end_macro +.macro write_control_set_true(%index) + li $v0 %index + li $v1 1 + jal write_control_set +.end_macro +.macro write_control_set_false(%index) + li $v0 %index + li $v1 0 + jal write_control_set +.end_macro #娴嬭瘯鐘舵侊細鍙俊 static_initialization: #MARS妯″紡涓嬭繖涓変釜鎸囬拡涓嶈璧嬪硷紙娉ㄩ噴鎺夛級 @@ -45,6 +55,8 @@ static_initialization: jal write_control li $a0 0 jal write_data + # 鏉ヤ釜寮鏈虹壒鏁 + load_ra() jr $ra #娴嬭瘯鐘舵侊細鍙俊 @@ -80,33 +92,31 @@ decode: read: save_ra() write_control_set_true(4) - jal decode + jal decode # 浼氳鐩朼0 a1鐨勫笺 + li $v0 100 + jal sleep bne $a1 $zero read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟enter鏄0 write_control_set_false(4) read_wait_for_enter: - li $t0 0 + li $v0 200 + jal sleep + #li $t0 0 jal decode - addi $t0 $t0 1 - li $t1 0x15EF3C0 - blt $t0 $t1 end_if_wait_for_enter - sub $t0 $t0 $t1 + #addi $t0 $t0 1 + #la $t1 0x015EF3C0 #0x015EF3C0= 23,000,000 + #blt $t0 $t1 end_if_wait_for_enter + # sub $t0 $t0 $t1 li $v0 4 jal write_control_negate - end_if_wait_for_enter: + #end_if_wait_for_enter: + lw $a0 0x70($gp) + jal write_data beq $a1 $zero read_wait_for_enter # 绛夊埌enter鏄1銆 lw $a0 0x70($gp) + jal write_data load_ra() jr $ra -.macro write_control_set_true(%index) - li $v0 %index - li $v1 1 - jal write_control_set -.end_macro -.macro write_control_set_false(%index) - li $v0 %index - li $v1 0 - jal write_control_set -.end_macro + # 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涙牴鎹畍1鐨勫肩殑鏈鍚庝竴浣嶆槸鍚︽槸1鏉ヤ慨鏀 write_control_set: lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 2ec95dc..d8dc199 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -2,7 +2,7 @@ .text jal static_initialization begin: - jal decode + jal decode # 浼氳鐩朼0 a1鐨勫笺 beq $a0 $zero case0 beq $a0 $s1 case1 beq $a0 $s2 case2 @@ -13,7 +13,15 @@ begin: beq $a0 $s7 case7 case0: jal read - jal write_data + # jal write_data + li $a0 0xFF + jal write_control + li $v0 1000 + jal sleep + li $a0 0x00 + jal write_control + li $v0 1000 + jal sleep j begin case1: li $a0 0 @@ -47,4 +55,4 @@ case7: jal write_control j begin j begin -.include "../commons/std_io_minisys.mips" \ No newline at end of file +.include "../commons/std_io_minisys.mips" -- Gitee From ffd218e2485f517c51d16651ba4b479328e2c819 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:30:19 +0800 Subject: [PATCH 08/57] =?UTF-8?q?feat(mips):=20=E5=88=86=E5=BC=80=E5=A4=B4?= =?UTF-8?q?=E6=96=87=E4=BB=B6=E5=92=8C=E5=AE=9E=E7=8E=B0=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 1 + ..._minisys.mips => std_io_minisys.impl.mips} | 118 +++++++++--------- main/mips/commons/std_io_minisys.macro.mips | 77 ++++++++++++ 3 files changed, 135 insertions(+), 61 deletions(-) rename main/mips/commons/{std_io_minisys.mips => std_io_minisys.impl.mips} (68%) create mode 100644 main/mips/commons/std_io_minisys.macro.mips diff --git a/.gitignore b/.gitignore index 16844cc..810f857 100644 --- a/.gitignore +++ b/.gitignore @@ -19,4 +19,5 @@ bin-release/ # ide specific vivado/ +vivado_impl/ .vscode/ \ No newline at end of file diff --git a/main/mips/commons/std_io_minisys.mips b/main/mips/commons/std_io_minisys.impl.mips similarity index 68% rename from main/mips/commons/std_io_minisys.mips rename to main/mips/commons/std_io_minisys.impl.mips index 9ddc622..ec027c2 100644 --- a/main/mips/commons/std_io_minisys.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -1,29 +1,4 @@ -#娴嬭瘯鐘舵侊細鍙俊 -# 浠庣紦瀛樺唴瀛樼殑鍊煎啓鍏ュ埌鐏腑銆傝繖鏄痯rivate鏂规硶锛屼笉瑕佽交鏄撹皟鐢ㄣ -.macro flush_lights() - lw $t0 4($k0) - sw $t0 0x62($gp) - lw $t0 0($k0) - sw $t0 0x60($gp) -.end_macro -.macro save_ra() - addi $sp $sp -4 - sw $ra 0($sp) -.end_macro -.macro load_ra() - lw $ra 0($sp) - addi $sp $sp +4 -.end_macro -.macro write_control_set_true(%index) - li $v0 %index - li $v1 1 - jal write_control_set -.end_macro -.macro write_control_set_false(%index) - li $v0 %index - li $v1 0 - jal write_control_set -.end_macro +.include "../commons/std_io_minisys.macro.mips" #娴嬭瘯鐘舵侊細鍙俊 static_initialization: #MARS妯″紡涓嬭繖涓変釜鎸囬拡涓嶈璧嬪硷紙娉ㄩ噴鎺夛級 @@ -32,30 +7,38 @@ static_initialization: la $fp 512 #base 鏁版嵁鐨勫熀纭鍦板潃 # 鏁版嵁闆嗛棿闅 li $s0 11 #space -# 甯告暟涓冨瓙 - li $s1 1 - li $s2 2 - li $s3 3 - li $s4 4 - li $s5 5 - li $s6 6 - li $s7 7 - #鐢宠缂撳瓨鐏殑鍊煎埌涓鍧楃湡瀹炲唴瀛樸 +#鐢宠缂撳瓨鐏殑鍊煎埌涓鍧楃湡瀹炲唴瀛樸 addi $sp $sp -16 # 鏀寔0, 4, 8, 12 鍥涗釜鍙橀噺 move $k0 $sp # k0鏄笓闂ㄧ殑鐏寚閽 save_ra() # 瑕佹兂jal鍏朵粬鏂规硶锛屽厛瑕佷繚瀛榬a - li $a0 0xFF - jal write_control - li $a0 0xFFFF - jal write_data - # 1s涔嬪悗瀹屾垚鎿嶄綔绯荤粺鐨勫惎鍔ㄣ - li $v0 1000 - jal sleep - li $a0 0 - jal write_control - li $a0 0 - jal write_data - # 鏉ヤ釜寮鏈虹壒鏁 +# 寮鏈虹壒鏁 鐐逛寒 + all_lights_off() + li $s0 0x80 + for_initialization0: + beq $s0 $zero end_for_initialization0 + lw $a0 4($k0) + add $a0 $a0 $s0 + jal write_control + srl $s0 $s0 1 + sleep(41) + j for_initialization0 + end_for_initialization0: + li $s0 0x8000 + for_initialization1: + beq $s0 $zero end_for_initialization1 + lw $a0 0($k0) + add $a0 $a0 $s0 + jal write_data + srl $s0 $s0 1 + sleep(41) + j for_initialization1 + end_for_initialization1: +# 鏉ヤ釜寮鏈虹壒鏁 闂竴闂 + all_lights_off() + sleep(100) + all_lights_on() + sleep(1000) + all_lights_off() load_ra() jr $ra @@ -88,32 +71,38 @@ decode: #娴嬭瘯鐘舵侊細鍗遍櫓 # 鏍规嵁a1鐨別nter淇″彿鎺у埗锛岀瓑寰呰緭鍏ヤ竴涓暣鏁帮紙閫氳繃鍙冲紑鍏筹級锛岀粨鏋滀繚瀛樺埌a0銆 # a1鍜宎0閮戒細鏀瑰彉銆 -# note: 鐘舵侀攣瀹氾細闃诲璇诲彇鐘舵佷笅鏃犳硶淇敼妯″紡銆 +# note: a2 涓簉ead涔嬪墠绯荤粺鐨刢ase鐘舵侊紝濡傛灉绛夊緟璇诲彇鐨勮繃绋嬪彂鐜板彉鍖栵紝浼氳繑鍥炲埌begin銆 read: save_ra() write_control_set_true(4) jal decode # 浼氳鐩朼0 a1鐨勫笺 - li $v0 100 - jal sleep + sleep(100) + bne $a0 $a2 begin bne $a1 $zero read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟enter鏄0 + # bne $a1 $zero begin # 鍏佽鍥炲埌begin閲嶆柊閫夋嫨鍔熻兘銆 write_control_set_false(4) read_wait_for_enter: - li $v0 200 - jal sleep + sleep(200) #li $t0 0 jal decode - #addi $t0 $t0 1 - #la $t1 0x015EF3C0 #0x015EF3C0= 23,000,000 - #blt $t0 $t1 end_if_wait_for_enter - # sub $t0 $t0 $t1 - li $v0 4 - jal write_control_negate - #end_if_wait_for_enter: + bne $a0 $a2 begin + write_control_negate(4) lw $a0 0x70($gp) + move $s0 $a0 jal write_data beq $a1 $zero read_wait_for_enter # 绛夊埌enter鏄1銆 - lw $a0 0x70($gp) - jal write_data + + li $a0 0 + jal write_data # 娓呯┖杈撳叆 + write_control_set_false(4) + write_control_negate(3) + write_control_negate(2) + sleep(400) + write_control_negate(3) + write_control_negate(2) + + # move $a0 $s0 + # jal write_data load_ra() jr $ra @@ -155,3 +144,10 @@ write_data: flush_lights() jr $ra + +exception_hint: + save_ra() + warn_data() + warn_data() + load_ra() + jr $ra diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips new file mode 100644 index 0000000..6aba668 --- /dev/null +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -0,0 +1,77 @@ +#娴嬭瘯鐘舵侊細鍙俊 +# 浠庣紦瀛樺唴瀛樼殑鍊煎啓鍏ュ埌鐏腑銆傝繖鏄痯rivate鏂规硶锛屼笉瑕佽交鏄撹皟鐢ㄣ +.macro flush_lights() + lw $t0 4($k0) + sw $t0 0x62($gp) + lw $t0 0($k0) + sw $t0 0x60($gp) +.end_macro +.macro save_ra() + # addi $sp $sp -4 + # sw $ra 0($sp) + move $k1 $ra +.end_macro +.macro load_ra() + # lw $ra 0($sp) + # addi $sp $sp 4 + move $ra $k1 # 鍔ㄧ敤k1 +.end_macro +.macro write_control_set_true(%index) + li $v0 %index + li $v1 1 + jal write_control_set +.end_macro +.macro write_control_set_false(%index) + li $v0 %index + li $v1 0 + jal write_control_set +.end_macro +.macro write_control_negate(%index) + li $v0 %index + jal write_control_negate +.end_macro +.macro set_s_to_be_seven_numbers() +# 甯告暟涓冨瓙 + li $s1 1 + li $s2 2 + li $s3 3 + li $s4 4 + li $s5 5 + li $s6 6 + li $s7 7 +.end_macro + +.macro warn_data() + lw $t7 0($k0) + li $a0 0xFFFF + jal write_data + write_control_set_true(2) + write_control_set_true(3) + li $v0 1000 + jal sleep + move $a0 $t7 + jal write_data + write_control_set_false(2) + write_control_set_false(3) + li $v0 500 + jal sleep +.end_macro + +.macro all_lights_on() + li $a0 0xFF + jal write_control + li $a0 0xFFFF + jal write_data +.end_macro + +.macro all_lights_off() + li $a0 0 + jal write_control + li $a0 0 + jal write_data +.end_macro + +.macro sleep(%msec) + la $v0 %msec + jal sleep +.end_macro \ No newline at end of file -- Gitee From 9cefa3a6e306a51d29d602ea1ddd8656fcf62369 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:31:02 +0800 Subject: [PATCH 09/57] =?UTF-8?q?feat(mips):=20=E5=9B=9E=E6=96=87=E6=95=B0?= =?UTF-8?q?=E5=BA=93?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_palindrome.impl.mips | 127 +++++++++++++++++++++ 1 file changed, 127 insertions(+) create mode 100644 main/mips/commons/std_palindrome.impl.mips diff --git a/main/mips/commons/std_palindrome.impl.mips b/main/mips/commons/std_palindrome.impl.mips new file mode 100644 index 0000000..fc68c02 --- /dev/null +++ b/main/mips/commons/std_palindrome.impl.mips @@ -0,0 +1,127 @@ +# developed by 鍙剁挩閾紝12011404@mail.sustech.edu.cn +# CC-BY license + +.text +#鍒ゆ柇a0鏄笉鏄簩杩涘埗鍥炴枃鏁帮紝杩斿洖鍊煎湪v0 +# 涓轰簡缁冧範锛屾垜浠娇鐢ㄩ掑綊瀹炵幇 +is_binary_palindrome: + li $a1 0 + move $t0 $a0 + while_binary_palindrome: + addi $a1 $a1 1 + srl $t0 $t0 1 + bne $t0 $zero while_binary_palindrome + addi $sp $sp -4 + sw $ra 0($sp) # 璋冪敤鍒汉鐨勬椂鍊欙紝闇瑕佷繚瀛樿嚜宸辩殑ra + jal is_binary_palindrome_impl #鏃╂湡浜虹被瀹炵幇閲嶈浇銆侀粯璁ゅ肩殑鐝嶈吹褰卞儚 + lw $ra 0($sp) + addi $sp $sp 4 + jr $ra +is_binary_palindrome_impl: + # 淇濆瓨鐢ㄥ埌鐨勫瘎瀛樺櫒锛氱幇鍦ㄤ綔涓篶allee锛岄渶瑕佷繚瀛榬a鍜宻 + # addi $sp $sp -4 + # sw $ra 0($sp) + bgt $a1 1 recursive_binary_palindrome + li $v0 1 #涓瀹氭槸鍥炴枃 + j end_if_binary_palindrome + recursive_binary_palindrome: + # 濡傛灉杩欎竴姝ヤ笉琛岋紝鐩存帴澶辫触 + addiu $t0 $a1 -1 # t0涓虹Щ浣嶇殑鏁伴噺 + srlv $t1 $a0 $t0 # t1 = a0>>>t0 绗竴浣 + andi $t0 $a0 1 # 鏈鍚庝竴浣 + bne $t1 $t0 fails_binary_palindrome + #杩欎竴姝ユ垚鍔熶簡锛岀湅鐪嬮掑綊鎴愪笉鎴 + addi $sp $sp -12 + sw $a0 0($sp) # 浣滀负璋冪敤鑰咃紝闇瑕佷繚瀛榓0锛宎1 + sw $a1 4($sp) + sw $ra 8($sp) + # 瑁佸壀a1 + addi $a1 $a1 -2 # a1-=2 + # 瑁佸壀a0 + # 鍏堢敓鎴愪竴涓猘1涓1鐨勬帺鐮 + li $t0 1 + sllv $t0 $t0 $a1 + addi $t0 $t0 -1 + sll $t0 $t0 1 + and $a0 $t0 $a0 + srl $a0 $a0 1 + #璋冪敤鍑芥暟 + jal is_binary_palindrome_impl + lw $a0 0($sp) # 浣滀负璋冪敤鑰咃紝闇瑕佹仮澶峚0锛宎1 + lw $a1 4($sp) + lw $ra 8($sp) + addi $sp $sp 12 + # 鐪嬬湅v0鎬庝箞鏍 + #li $v0 1 + #bne $v0 $zero end_if # 濡傛灉涓嶆槸false锛岄偅涔堝氨鏄痶rue # 閿欒浠ｇ爜锛屽簲璇ョ洿鎺ヤ互杩斿洖缁撴灉涓哄噯 + j end_if_binary_palindrome + fails_binary_palindrome: + li $v0 0 + end_if_binary_palindrome: + #鎭㈠鐢ㄥ埌鐨勫瘎瀛樺櫒锛氱幇鍦ㄤ綔涓篶allee锛岄渶瑕佹仮澶峳a鍜宻 + # lw $ra 0($sp) + # addi $sp $sp 4 + jr $ra + +is_hexadecimal_palindrome: + li $a1 0 + move $t0 $a0 + while_hexadecimal_palindrome: + addi $a1 $a1 1 + srl $t0 $t0 4 + bne $t0 $zero while_hexadecimal_palindrome + # a1 = a0鏈夊灏戜釜4浣 + addi $sp $sp -4 + sw $ra 0($sp) # 璋冪敤鍒汉鐨勬椂鍊欙紝闇瑕佷繚瀛樿嚜宸辩殑ra + jal is_hexadecimal_palindrome_impl #鏃╂湡浜虹被瀹炵幇閲嶈浇銆侀粯璁ゅ肩殑鐝嶈吹褰卞儚 + lw $ra 0($sp) + addi $sp $sp 4 + jr $ra +is_hexadecimal_palindrome_impl: + # 淇濆瓨鐢ㄥ埌鐨勫瘎瀛樺櫒锛氱幇鍦ㄤ綔涓篶allee锛岄渶瑕佷繚瀛榬a鍜宻 + # addi $sp $sp -4 + # sw $ra 0($sp) + bgt $a1 1 recursive_hexadecimal_palindrome + li $v0 1 #涓瀹氭槸鍥炴枃 + j end_if_hexadecimal_palindrome + recursive_hexadecimal_palindrome: + # 濡傛灉杩欎竴姝ヤ笉琛岋紝鐩存帴澶辫触 + addiu $t0 $a1 -1 # t0涓虹Щ浣嶇殑鏁伴噺 + sll $t0 $t0 2 # 姣斿锛宼0涓7锛岄偅涔堥渶瑕 28 浣 + srlv $t1 $a0 $t0 # t1 = a0>>>t0 鍓嶅洓浣 + andi $t0 $a0 15 # 鏈鍚庡洓浣 + bne $t1 $t0 fails_hexadecimal_palindrome + #杩欎竴姝ユ垚鍔熶簡锛岀湅鐪嬮掑綊鎴愪笉鎴 + addi $sp $sp -12 + sw $a0 0($sp) # 浣滀负璋冪敤鑰咃紝闇瑕佷繚瀛榓0锛宎1 + sw $a1 4($sp) + sw $ra 8($sp) + # 瑁佸壀a1 + addi $a1 $a1 -2 # a1-=2 + # 瑁佸壀a0 + sll $t0 $a1 2 # 姣斿锛宎1 = 5浣嶃傞渶瑕乼0=20浣嶇殑1 + # 鍏堢敓鎴愪竴涓猘1涓1鐨勬帺鐮 + li $t1 1 + sllv $t1 $t1 $t0 + addi $t1 $t1 -1 # t1寰楀埌浜20涓1. + sll $t1 $t1 4 # 涓嶈鏈浣庡洓浣 + and $a0 $t1 $a0 + srl $a0 $a0 4 #鎺ㄥ洖鍘 + #璋冪敤鍑芥暟 + jal is_hexadecimal_palindrome + lw $a0 0($sp) # 浣滀负璋冪敤鑰咃紝闇瑕佹仮澶峚0锛宎1 + lw $a1 4($sp) + lw $ra 8($sp) + addi $sp $sp 12 + # 鐪嬬湅v0鎬庝箞鏍 + #li $v0 1 + # bne $v0 $zero end_if2 # 濡傛灉涓嶆槸寰楀埌false锛岄偅涔堝氨鏄痶rue锛岃繑鍥瀟rue + # 鑽掕艾鍙瑧鐨勯昏緫-鈫 + j end_if_hexadecimal_palindrome + fails_hexadecimal_palindrome: + li $v0 0 + end_if_hexadecimal_palindrome: + #鎭㈠鐢ㄥ埌鐨勫瘎瀛樺櫒锛氱幇鍦ㄤ綔涓篶allee锛岄渶瑕佹仮澶峳a鍜宻 + # lw $ra 0($sp) + # addi $sp $sp 4 + jr $ra -- Gitee From 6b755290283796998f2fbbb86e5f25815bfe7366 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:31:40 +0800 Subject: [PATCH 10/57] =?UTF-8?q?feat(vivado):=20=E5=AF=BC=E5=85=A5xci?= =?UTF-8?q?=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/ip/RAM.xci | 267 ++++++++++++ main/verilog/ip/blk_mem_gen_0.xci | 266 ++++++++++++ main/verilog/ip/clk_wiz_0.xci | 677 +++++++++++++++++++++++++++++ main/verilog/ip/cpuclk.xci | 688 ++++++++++++++++++++++++++++++ main/verilog/ip/prgrom.xci | 267 ++++++++++++ main/verilog/ip/uart_bmpg_0.xci | 41 ++ 6 files changed, 2206 insertions(+) create mode 100644 main/verilog/ip/RAM.xci create mode 100644 main/verilog/ip/blk_mem_gen_0.xci create mode 100644 main/verilog/ip/clk_wiz_0.xci create mode 100644 main/verilog/ip/cpuclk.xci create mode 100644 main/verilog/ip/prgrom.xci create mode 100644 main/verilog/ip/uart_bmpg_0.xci diff --git a/main/verilog/ip/RAM.xci b/main/verilog/ip/RAM.xci new file mode 100644 index 0000000..5497222 --- /dev/null +++ b/main/verilog/ip/RAM.xci @@ -0,0 +1,267 @@ + + + xilinx.com + xci + unknown + 1.0 + + + RAM + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 14 + 14 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 14 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 13.776802 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + RAM.mem + RAM.mif + 0 + 1 + 0 + 0 + 1 + 16384 + 16384 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../../main/mips/coe/dmem32.coe + ALL + RAM + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16384 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + 1aa89aa0844684f9 + IP_Flow + 1 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/main/verilog/ip/blk_mem_gen_0.xci b/main/verilog/ip/blk_mem_gen_0.xci new file mode 100644 index 0000000..0874ea9 --- /dev/null +++ b/main/verilog/ip/blk_mem_gen_0.xci @@ -0,0 +1,266 @@ + + + xilinx.com + xci + unknown + 1.0 + + + blk_mem_gen_0 + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 14 + 14 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 14 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 13.776802 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + blk_mem_gen_0.mem + blk_mem_gen_0.mif + 0 + 1 + 0 + 0 + 1 + 16384 + 16384 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../../main/test_coe/dmem32.coe + ALL + blk_mem_gen_0 + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16384 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/main/verilog/ip/clk_wiz_0.xci b/main/verilog/ip/clk_wiz_0.xci new file mode 100644 index 0000000..7511ea8 --- /dev/null +++ b/main/verilog/ip/clk_wiz_0.xci @@ -0,0 +1,677 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0.000 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 23.000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 23.000 + 0.000 + 50.000 + 23 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.23 + 0.23 + 0.23 + 0.23 + 0.23 + 0.23 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 46.000 + 0.000 + FALSE + 10.000 + 10.000 + 40.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 5 + None + 0.010 + 0.010 + FALSE + 1 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1____23.000______0.000______50.0______342.117____303.235 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + PLL + AUTO + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 342.117 + false + 303.235 + 50.000 + 23 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_0 + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 46 + 0.000 + false + 10.000 + 10.000 + 40 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 1 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + PLL + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/main/verilog/ip/cpuclk.xci b/main/verilog/ip/cpuclk.xci new file mode 100644 index 0000000..037a865 --- /dev/null +++ b/main/verilog/ip/cpuclk.xci @@ -0,0 +1,688 @@ + + + xilinx.com + xci + unknown + 1.0 + + + cpuclk + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0.000 + + + + 100000000 + 0.000 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 23.000 + 0000 + 0000 + 10.000 + BUFG + 50.0 + false + 23.000 + 0.000 + 50.000 + 23 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 10.000 + 0.000 + 50.000 + 10 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 2.3 + 0.23 + 0.23 + 0.23 + 0.23 + 0.23 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 46.000 + 0.000 + FALSE + 10.000 + 10.000 + 40.000 + 0.500 + 0.000 + FALSE + 92 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 5 + None + 0.010 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1____23.000______0.000______50.0______342.117____303.235 + clk_out2____10.000______0.000______50.0______391.228____303.235 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + PLL + AUTO + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + cpuclk + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 342.117 + false + 303.235 + 50.000 + 23 + 0.000 + 1 + true + BUFG + 391.228 + false + 303.235 + 50.000 + 10 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + cpuclk + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 46 + 0.000 + false + 10.000 + 10.000 + 40 + 0.500 + 0.000 + false + 92 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + PLL + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/main/verilog/ip/prgrom.xci b/main/verilog/ip/prgrom.xci new file mode 100644 index 0000000..8a97daa --- /dev/null +++ b/main/verilog/ip/prgrom.xci @@ -0,0 +1,267 @@ + + + xilinx.com + xci + unknown + 1.0 + + + prgrom + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 14 + 14 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 14 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 13.776802 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + prgrom.mem + prgrom.mif + 0 + 1 + 0 + 0 + 1 + 16384 + 16384 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../../../main/mips/coe/prgmip32.coe + ALL + prgrom + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16384 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + a14d160ef830f38c + IP_Flow + 1 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + diff --git a/main/verilog/ip/uart_bmpg_0.xci b/main/verilog/ip/uart_bmpg_0.xci new file mode 100644 index 0000000..6d7acbc --- /dev/null +++ b/main/verilog/ip/uart_bmpg_0.xci @@ -0,0 +1,41 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_bmpg_0 + + + 128000 bps + uart_bmpg_0 + 8 bits + 10 MHz + No + Active High + 1 bit(s) + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + -- Gitee From f7ae527dfc908125221f87159d9b877086cbc477 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:32:20 +0800 Subject: [PATCH 11/57] =?UTF-8?q?feat(vivado):=20=E5=BC=95=E5=85=A5uart=20?= =?UTF-8?q?ip=E6=A0=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../component.xml | 345 + .../uart_bmpg.edif | 13965 ++++++++++++++++ .../uart_bmpg.v | 37 + .../ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v | 51 + .../xgui/uart_bmpg_v1_3.tcl | 71 + 5 files changed, 14469 insertions(+) create mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml create mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif create mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v create mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v create mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml new file mode 100644 index 0000000..8008995 --- /dev/null +++ b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml @@ -0,0 +1,345 @@ + + + SEU_CSE_507 + user + uart_bmpg + 1.3 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + upg + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 36acd76a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + upg + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6b59a370 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c3dd6d67 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + viewChecksum + 995a2cc2 + + + + + + + upg_clk_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_rst_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_clk_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_wen_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_adr_o + + out + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_dat_o + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_done_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_rx_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_tx_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + uart_bmpg.edif + edn + + + uart_bmpg.v + verilogSource + CHECKSUM_3f5e0c86 + + + upg.v + verilogSource + CHECKSUM_049fde7b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + uart_bmpg.v + verilogSource + + + upg.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/uart_bmpg_v1_3.tcl + tclSource + CHECKSUM_c3dd6d67 + XGUI_VERSION_2 + + + + xilinx_implementation_view_fileset + + uart_bmpg.edif + edn + + + + uart_bmpg_v1_3 + + + Component_Name + uart_bmpg_v1_3 + + + Input_Clock_Freqency + 10 MHz + + + + false + + + + + + Baud_Rate + 128000 bps + + + + false + + + + + + Data_Bits + 8 bits + + + + false + + + + + + Stop_Bits + Stop Bit(s) + 1 bit(s) + + + + false + + + + + + Parity + No + + + + false + + + + + + Reset + Active High + + + + false + + + + + + + + + artix7 + + + /UserIP + + uart_bmpg_v1_3 + package_project + 8 + 2018-07-14T12:11:51Z + + i:/uart_bmpg/uart_bmpg.srcs/sources_1/new + i:/uart_bmpg/uart_bmpg.srcs/sources_1/new + h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new + h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new + h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new + + + + 2017.4 + + + + + + diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif new file mode 100644 index 0000000..e53e627 --- /dev/null +++ b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif @@ -0,0 +1,13965 @@ +(edif uart_bmpg + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2018 07 14 20 08 21) + (program "Vivado" (version "2017.4")) + (comment "Built on 'Fri Dec 15 20:55:39 MST 2017'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell FDCE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port CLR (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell FDRE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell SRL16E (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port A0 (direction INPUT)) + (port A1 (direction INPUT)) + (port A2 (direction INPUT)) + (port A3 (direction INPUT)) + (port CE (direction INPUT)) + (port CLK (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell FDSE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell CARRY4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CI (direction INPUT)) + (port CYINIT (direction INPUT)) + (port (array (rename CO "CO[3:0]") 4) (direction OUTPUT)) + (port (array (rename O "O[3:0]") 4) (direction OUTPUT)) + (port (array (rename DI "DI[3:0]") 4) (direction INPUT)) + (port (array (rename S "S[3:0]") 4) (direction INPUT)) + ) + ) + ) + (cell BUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell FDPE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell OBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell IBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library work_library0_1 + (edifLevel 0) + (technology (numberDefinition )) + (cell axi_uart_pselect_f (celltype GENERIC) + (view pselect_f (viewtype NETLIST) + (interface + (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) + (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) + (port ce_expnd_i_3 (direction OUTPUT)) + ) + (contents + (instance CS (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined + (portref I0 (instanceref CS)) + (portref bus2ip_addr_i_reg_2_) + ) + ) + (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined + (portref I1 (instanceref CS)) + (portref bus2ip_addr_i_reg_3_) + ) + ) + (net ce_expnd_i_3 (joined + (portref O (instanceref CS)) + (portref ce_expnd_i_3) + ) + ) + ) + + (property ORIG_REF_NAME (string "pselect_f")) + ) + ) + (cell axi_uart_pselect_f__parameterized1 (celltype GENERIC) + (view pselect_f__parameterized1 (viewtype NETLIST) + (interface + (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) + (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) + (port ce_expnd_i_1 (direction OUTPUT)) + ) + (contents + (instance CS (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined + (portref I1 (instanceref CS)) + (portref bus2ip_addr_i_reg_2_) + ) + ) + (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined + (portref I0 (instanceref CS)) + (portref bus2ip_addr_i_reg_3_) + ) + ) + (net ce_expnd_i_1 (joined + (portref O (instanceref CS)) + (portref ce_expnd_i_1) + ) + ) + ) + + (property ORIG_REF_NAME (string "pselect_f")) + ) + ) + (cell axi_uart_address_decoder (celltype GENERIC) + (view address_decoder (viewtype NETLIST) + (interface + (port FIFO_Full_reg (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) + (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) + (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) + (port bus2ip_rnw_i (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port enable_interrupts_reg (direction OUTPUT)) + (port enable_interrupts_reg_0 (direction OUTPUT)) + (port fifo_wr (direction OUTPUT)) + (port ip2bus_error (direction OUTPUT)) + (port reset_RX_FIFO (direction OUTPUT)) + (port reset_TX_FIFO (direction OUTPUT)) + (port rx_Buffer_Full (direction INPUT)) + (port rx_Data_Present_Pre_reg (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_bready (direction INPUT)) + (port (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (direction OUTPUT)) + (port s_axi_bvalid_i_reg (direction OUTPUT)) + (port s_axi_bvalid_i_reg_0 (direction INPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid_i_reg (direction OUTPUT)) + (port s_axi_rvalid_i_reg_0 (direction INPUT)) + (port s_axi_wvalid (direction INPUT)) + (port start2 (direction INPUT)) + (port (rename state_reg_0_ "state_reg[0]") (direction INPUT)) + (port (rename state_reg_1_ "state_reg[1]") (direction INPUT)) + (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port (array (rename D "D[1:0]") 2) (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (direction INPUT)) + (port (array (rename Q "Q[1:0]") 2) (direction INPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction INPUT)) + (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction INPUT)) + (port (array (rename s_axi_rdata_i_reg_7_ "s_axi_rdata_i_reg[7][7:0]") 8) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance Bus_RNW_reg_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hB8")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance Bus_RNW_reg_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1 "GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_ "GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1 "GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFEFFFF")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2 "GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename INFERRED_GEN_cnt_i_3__i_2 "INFERRED_GEN.cnt_i[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF7")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_3 "INFERRED_GEN.cnt_i[4]_i_3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h7")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_5 "INFERRED_GEN.cnt_i[4]_i_5") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFD")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16_i_1 "INFERRED_GEN.data_reg[15][7]_srl16_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h10")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I "MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I") (viewref pselect_f (cellref axi_uart_pselect_f (libraryref work_library0_1)))) + (instance (rename MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I "MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I") (viewref pselect_f__parameterized1 (cellref axi_uart_pselect_f__parameterized1 (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance clr_Status_i_1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance enable_interrupts_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFB08")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance reset_RX_FIFO_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance reset_TX_FIFO_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance rx_Data_Present_Pre_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0444")) + ) + (instance s_axi_arready_INST_0 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hF0F0F0E0")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename s_axi_bresp_i_1__i_1 "s_axi_bresp_i[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFB08")) + ) + (instance s_axi_bvalid_i_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h40FF4040")) + ) + (instance (rename s_axi_rdata_i_0__i_1 "s_axi_rdata_i[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h5050C000")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename s_axi_rdata_i_1__i_1 "s_axi_rdata_i[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename s_axi_rdata_i_2__i_1 "s_axi_rdata_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename s_axi_rdata_i_3__i_1 "s_axi_rdata_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_4__i_1 "s_axi_rdata_i[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_5__i_1 "s_axi_rdata_i[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_6__i_1 "s_axi_rdata_i[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_7__i_2 "s_axi_rdata_i[7]_i_2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename s_axi_rresp_i_1__i_1 "s_axi_rresp_i[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hF0880088")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance s_axi_rvalid_i_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h40FF4040")) + ) + (instance s_axi_wready_INST_0 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0F0F0F0E")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename state_0__i_1 "state[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hCFEFCFEC")) + ) + (instance (rename state_1__i_1 "state[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hCFECCFECCFEFCFEC")) + ) + (instance tx_Buffer_Empty_Pre_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8808")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref Bus_RNW_reg_reg)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref Bus_RNW_reg_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg_i_1_n_0 (joined + (portref D (instanceref Bus_RNW_reg_reg)) + (portref O (instanceref Bus_RNW_reg_i_1)) + ) + ) + (net (rename D_0_ "D[0]") (joined + (portref O (instanceref state_0__i_1)) + (portref (member D 1)) + ) + ) + (net (rename D_1_ "D[1]") (joined + (portref O (instanceref state_1__i_1)) + (portref (member D 0)) + ) + ) + (net FIFO_Full_reg (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_3)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (joined + (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref I0 (instanceref s_axi_rresp_i_1__i_1)) + (portref I0 (instanceref s_axi_wready_INST_0)) + (portref I2 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref I2 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref I3 (instanceref s_axi_arready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_3)) + (portref I0 (instanceref s_axi_arready_INST_0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref I1 (instanceref s_axi_rdata_i_7__i_2)) + (portref I2 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I2 (instanceref s_axi_rresp_i_1__i_1)) + (portref I3 (instanceref rx_Data_Present_Pre_i_1)) + (portref I3 (instanceref s_axi_rdata_i_0__i_1)) + (portref I3 (instanceref s_axi_rdata_i_1__i_1)) + (portref I3 (instanceref s_axi_rdata_i_2__i_1)) + (portref I3 (instanceref s_axi_rdata_i_3__i_1)) + (portref I3 (instanceref s_axi_rdata_i_4__i_1)) + (portref I3 (instanceref s_axi_rdata_i_5__i_1)) + (portref I3 (instanceref s_axi_rdata_i_6__i_1)) + (portref I3 (instanceref s_axi_wready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg") (joined + (portref I0 (instanceref clr_Status_i_1)) + (portref I0 (instanceref s_axi_rdata_i_7__i_2)) + (portref I1 (instanceref s_axi_arready_INST_0)) + (portref I3 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I4 (instanceref s_axi_rdata_i_0__i_1)) + (portref I4 (instanceref s_axi_rdata_i_1__i_1)) + (portref I4 (instanceref s_axi_rdata_i_2__i_1)) + (portref I4 (instanceref s_axi_rdata_i_3__i_1)) + (portref I4 (instanceref s_axi_rdata_i_4__i_1)) + (portref I4 (instanceref s_axi_rdata_i_5__i_1)) + (portref I4 (instanceref s_axi_rdata_i_6__i_1)) + (portref I4 (instanceref s_axi_wready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg") (joined + (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I1 (instanceref enable_interrupts_i_1)) + (portref I1 (instanceref reset_RX_FIFO_i_1)) + (portref I1 (instanceref reset_TX_FIFO_i_1)) + (portref I1 (instanceref s_axi_wready_INST_0)) + (portref I4 (instanceref s_axi_arready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref INFERRED_GEN_cnt_i_reg_2_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref INFERRED_GEN_cnt_i_reg_2__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref I0 (instanceref rx_Data_Present_Pre_i_1)) + (portref I0 (instanceref s_axi_rdata_i_0__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref I4 (instanceref s_axi_rresp_i_1__i_1)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (joined + (portref I0 (instanceref s_axi_rdata_i_2__i_1)) + (portref I1 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref INFERRED_GEN_cnt_i_reg_4__0_0_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref I0 (instanceref s_axi_bvalid_i_i_1)) + (portref I1 (instanceref s_axi_rvalid_i_i_1)) + (portref I2 (instanceref s_axi_bresp_i_1__i_1)) + (portref I2 (instanceref state_1__i_1)) + (portref I3 (instanceref state_0__i_1)) + (portref (member Q 1)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref I0 (instanceref s_axi_rvalid_i_i_1)) + (portref I1 (instanceref s_axi_bresp_i_1__i_1)) + (portref I1 (instanceref s_axi_bvalid_i_i_1)) + (portref I2 (instanceref state_0__i_1)) + (portref I3 (instanceref state_1__i_1)) + (portref (member Q 0)) + ) + ) + (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined + (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) + (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) + (portref bus2ip_addr_i_reg_2_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_2_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_2_) + ) + ) + (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined + (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) + (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) + (portref bus2ip_addr_i_reg_3_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_3_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_3_) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref O (instanceref clr_Status_i_1)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_rnw_i (joined + (portref I0 (instanceref Bus_RNW_reg_i_1)) + (portref bus2ip_rnw_i) + ) + ) + (net ce_expnd_i_0 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + (portref O (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) + ) + ) + (net ce_expnd_i_1 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref ce_expnd_i_1 (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + ) + ) + (net ce_expnd_i_2 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref O (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) + ) + ) + (net ce_expnd_i_3 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref ce_expnd_i_3 (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + ) + ) + (net cs_ce_clr (joined + (portref O (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + ) + ) + (net enable_interrupts (joined + (portref I0 (instanceref s_axi_rdata_i_4__i_1)) + (portref I3 (instanceref enable_interrupts_i_1)) + (portref enable_interrupts) + ) + ) + (net enable_interrupts_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref I0 (instanceref reset_RX_FIFO_i_1)) + (portref I0 (instanceref reset_TX_FIFO_i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_3)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref I1 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref I1 (instanceref clr_Status_i_1)) + (portref I2 (instanceref Bus_RNW_reg_i_1)) + (portref I2 (instanceref enable_interrupts_i_1)) + (portref I2 (instanceref rx_Data_Present_Pre_i_1)) + (portref I2 (instanceref s_axi_arready_INST_0)) + (portref I2 (instanceref s_axi_rdata_i_0__i_1)) + (portref I2 (instanceref s_axi_rdata_i_1__i_1)) + (portref I2 (instanceref s_axi_rdata_i_2__i_1)) + (portref I2 (instanceref s_axi_rdata_i_3__i_1)) + (portref I2 (instanceref s_axi_rdata_i_4__i_1)) + (portref I2 (instanceref s_axi_rdata_i_5__i_1)) + (portref I2 (instanceref s_axi_rdata_i_6__i_1)) + (portref I2 (instanceref s_axi_rdata_i_7__i_2)) + (portref I2 (instanceref s_axi_wready_INST_0)) + (portref I3 (instanceref s_axi_rresp_i_1__i_1)) + (portref I3 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref Q (instanceref Bus_RNW_reg_reg)) + (portref enable_interrupts_reg) + ) + ) + (net enable_interrupts_reg_0 (joined + (portref O (instanceref enable_interrupts_i_1)) + (portref enable_interrupts_reg_0) + ) + ) + (net fifo_wr (joined + (portref O (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref fifo_wr) + ) + ) + (net ip2bus_error (joined + (portref I0 (instanceref s_axi_bresp_i_1__i_1)) + (portref O (instanceref s_axi_rresp_i_1__i_1)) + (portref ip2bus_error) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref I1 (instanceref s_axi_rdata_i_0__i_1)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref I1 (instanceref s_axi_rdata_i_1__i_1)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref I1 (instanceref s_axi_rdata_i_2__i_1)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref I1 (instanceref s_axi_rdata_i_3__i_1)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref I1 (instanceref s_axi_rdata_i_4__i_1)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref I1 (instanceref s_axi_rdata_i_5__i_1)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref I1 (instanceref s_axi_rdata_i_6__i_1)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref I3 (instanceref s_axi_rdata_i_7__i_2)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref O (instanceref reset_RX_FIFO_i_1)) + (portref reset_RX_FIFO) + ) + ) + (net reset_TX_FIFO (joined + (portref O (instanceref reset_TX_FIFO_i_1)) + (portref reset_TX_FIFO) + ) + ) + (net rx_Buffer_Full (joined + (portref I0 (instanceref s_axi_rdata_i_1__i_1)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre_reg (joined + (portref O (instanceref rx_Data_Present_Pre_i_1)) + (portref rx_Data_Present_Pre_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref Bus_RNW_reg_reg)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I0 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref I1 (instanceref rx_Data_Present_Pre_i_1)) + (portref I4 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref I0 (instanceref state_1__i_1)) + (portref I2 (instanceref s_axi_rvalid_i_i_1)) + (portref O (instanceref s_axi_arready_INST_0)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref I4 (instanceref state_0__i_1)) + (portref I5 (instanceref state_1__i_1)) + (portref s_axi_arvalid) + ) + ) + (net s_axi_awready (joined + (portref I0 (instanceref state_0__i_1)) + (portref I2 (instanceref s_axi_bvalid_i_i_1)) + (portref O (instanceref s_axi_wready_INST_0)) + (portref s_axi_awready) + ) + ) + (net s_axi_bready (joined + (portref I3 (instanceref s_axi_bvalid_i_i_1)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref I3 (instanceref s_axi_bresp_i_1__i_1)) + (portref s_axi_bresp_0_) + ) + ) + (net (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (joined + (portref O (instanceref s_axi_bresp_i_1__i_1)) + (portref s_axi_bresp_i_reg_1_) + ) + ) + (net s_axi_bvalid_i_reg (joined + (portref O (instanceref s_axi_bvalid_i_i_1)) + (portref s_axi_bvalid_i_reg) + ) + ) + (net s_axi_bvalid_i_reg_0 (joined + (portref I4 (instanceref s_axi_bvalid_i_i_1)) + (portref s_axi_bvalid_i_reg_0) + ) + ) + (net (rename s_axi_rdata_i_reg_7__0_ "s_axi_rdata_i_reg[7][0]") (joined + (portref O (instanceref s_axi_rdata_i_0__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 7)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__1_ "s_axi_rdata_i_reg[7][1]") (joined + (portref O (instanceref s_axi_rdata_i_1__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 6)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__2_ "s_axi_rdata_i_reg[7][2]") (joined + (portref O (instanceref s_axi_rdata_i_2__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 5)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__3_ "s_axi_rdata_i_reg[7][3]") (joined + (portref O (instanceref s_axi_rdata_i_3__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 4)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__4_ "s_axi_rdata_i_reg[7][4]") (joined + (portref O (instanceref s_axi_rdata_i_4__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 3)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__5_ "s_axi_rdata_i_reg[7][5]") (joined + (portref O (instanceref s_axi_rdata_i_5__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 2)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__6_ "s_axi_rdata_i_reg[7][6]") (joined + (portref O (instanceref s_axi_rdata_i_6__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 1)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__7_ "s_axi_rdata_i_reg[7][7]") (joined + (portref O (instanceref s_axi_rdata_i_7__i_2)) + (portref (member s_axi_rdata_i_reg_7_ 0)) + ) + ) + (net s_axi_rready (joined + (portref I3 (instanceref s_axi_rvalid_i_i_1)) + (portref s_axi_rready) + ) + ) + (net s_axi_rvalid_i_reg (joined + (portref O (instanceref s_axi_rvalid_i_i_1)) + (portref s_axi_rvalid_i_reg) + ) + ) + (net s_axi_rvalid_i_reg_0 (joined + (portref I4 (instanceref s_axi_rvalid_i_i_1)) + (portref s_axi_rvalid_i_reg_0) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref I2 (instanceref reset_TX_FIFO_i_1)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref I2 (instanceref reset_RX_FIFO_i_1)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref I0 (instanceref enable_interrupts_i_1)) + (portref (member s_axi_wdata 0)) + ) + ) + (net s_axi_wvalid (joined + (portref I4 (instanceref state_1__i_1)) + (portref s_axi_wvalid) + ) + ) + (net start2 (joined + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + (portref I1 (instanceref Bus_RNW_reg_i_1)) + (portref start2) + ) + ) + (net (rename state_reg_0_ "state_reg[0]") (joined + (portref I1 (instanceref state_0__i_1)) + (portref state_reg_0_) + ) + ) + (net (rename state_reg_1_ "state_reg[1]") (joined + (portref I1 (instanceref state_1__i_1)) + (portref state_reg_1_) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref I0 (instanceref s_axi_rdata_i_5__i_1)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref I0 (instanceref s_axi_rdata_i_6__i_1)) + (portref (member status_reg 0)) + ) + ) + (net tx_Buffer_Empty_Pre_reg (joined + (portref O (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref tx_Buffer_Empty_Pre_reg) + ) + ) + (net tx_Buffer_Full (joined + (portref I0 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref I0 (instanceref s_axi_rdata_i_3__i_1)) + (portref I1 (instanceref s_axi_rresp_i_1__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "address_decoder")) + ) + ) + (cell axi_uart_slave_attachment (celltype GENERIC) + (view slave_attachment (viewtype NETLIST) + (interface + (port FIFO_Full_reg (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) + (port bus2ip_reset (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port enable_interrupts_reg (direction OUTPUT)) + (port enable_interrupts_reg_0 (direction OUTPUT)) + (port fifo_wr (direction OUTPUT)) + (port reset_RX_FIFO (direction OUTPUT)) + (port reset_TX_FIFO (direction OUTPUT)) + (port rx_Buffer_Full (direction INPUT)) + (port rx_Data_Present_Pre_reg (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_awvalid (direction INPUT)) + (port s_axi_bready (direction INPUT)) + (port s_axi_bvalid (direction OUTPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid (direction OUTPUT)) + (port s_axi_wvalid (direction INPUT)) + (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction INPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction INPUT)) + (port (array (rename s_axi_araddr "s_axi_araddr[1:0]") 2) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[1:0]") 2) (direction INPUT)) + (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[7:0]") 8) (direction OUTPUT)) + (port (rename s_axi_rresp_0_ "s_axi_rresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance I_DECODER (viewref address_decoder (cellref axi_uart_address_decoder (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename bus2ip_addr_i_2__i_1 "bus2ip_addr_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hB8FFB800")) + ) + (instance (rename bus2ip_addr_i_3__i_1 "bus2ip_addr_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hB8FFB800")) + ) + (instance (rename bus2ip_addr_i_3__i_2 "bus2ip_addr_i[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hEF")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bus2ip_rnw_i_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFF7000000F0")) + ) + (instance bus2ip_rnw_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rst_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_bvalid_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_7__i_1 "s_axi_rdata_i[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename s_axi_rdata_i_reg_0_ "s_axi_rdata_i_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_1_ "s_axi_rdata_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_2_ "s_axi_rdata_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_3_ "s_axi_rdata_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_4_ "s_axi_rdata_i_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_5_ "s_axi_rdata_i_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_6_ "s_axi_rdata_i_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_7_ "s_axi_rdata_i_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rresp_i_reg_1_ "s_axi_rresp_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_rvalid_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance start2_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h000000F8")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance start2_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename state_0__i_2 "state[0]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h002A2A2A")) + ) + (instance (rename state_1__i_2 "state[1]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h002A2A2A")) + ) + (instance (rename state_1__i_3 "state[1]_i_3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + ) + (instance (rename state_reg_0_ "state_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename state_reg_1_ "state_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref rst_reg)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref bus2ip_addr_i_reg_2_)) + (portref CE (instanceref bus2ip_addr_i_reg_3_)) + (portref CE (instanceref bus2ip_rnw_i_reg)) + (portref CE (instanceref rst_reg)) + (portref CE (instanceref s_axi_bresp_i_reg_1_)) + (portref CE (instanceref s_axi_bvalid_i_reg)) + (portref CE (instanceref s_axi_rvalid_i_reg)) + (portref CE (instanceref start2_reg)) + (portref CE (instanceref state_reg_0_)) + (portref CE (instanceref state_reg_1_)) + (portref P (instanceref VCC)) + ) + ) + (net FIFO_Full_reg (joined + (portref FIFO_Full_reg (instanceref I_DECODER)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 (instanceref I_DECODER)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 (instanceref I_DECODER)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined + (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref I_DECODER)) + (portref INFERRED_GEN_cnt_i_reg_2_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined + (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref I_DECODER)) + (portref INFERRED_GEN_cnt_i_reg_2__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_0_ (instanceref I_DECODER)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net I_DECODER_n_26 (joined + (portref D (instanceref s_axi_rvalid_i_reg)) + (portref s_axi_rvalid_i_reg (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_27 (joined + (portref D (instanceref s_axi_bvalid_i_reg)) + (portref s_axi_bvalid_i_reg (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_28 (joined + (portref D (instanceref s_axi_bresp_i_reg_1_)) + (portref s_axi_bresp_i_reg_1_ (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_5 (joined + (portref D (instanceref state_reg_1_)) + (portref (member D 0) (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_6 (joined + (portref D (instanceref state_reg_0_)) + (portref (member D 1) (instanceref I_DECODER)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_DECODER)) + (portref Q_0_) + ) + ) + (net (rename SIn_DBus_0_ "SIn_DBus[0]") (joined + (portref D (instanceref s_axi_rdata_i_reg_7_)) + (portref (member s_axi_rdata_i_reg_7_ 0) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_1_ "SIn_DBus[1]") (joined + (portref D (instanceref s_axi_rdata_i_reg_6_)) + (portref (member s_axi_rdata_i_reg_7_ 1) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_2_ "SIn_DBus[2]") (joined + (portref D (instanceref s_axi_rdata_i_reg_5_)) + (portref (member s_axi_rdata_i_reg_7_ 2) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_3_ "SIn_DBus[3]") (joined + (portref D (instanceref s_axi_rdata_i_reg_4_)) + (portref (member s_axi_rdata_i_reg_7_ 3) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_4_ "SIn_DBus[4]") (joined + (portref D (instanceref s_axi_rdata_i_reg_3_)) + (portref (member s_axi_rdata_i_reg_7_ 4) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_5_ "SIn_DBus[5]") (joined + (portref D (instanceref s_axi_rdata_i_reg_2_)) + (portref (member s_axi_rdata_i_reg_7_ 5) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_6_ "SIn_DBus[6]") (joined + (portref D (instanceref s_axi_rdata_i_reg_1_)) + (portref (member s_axi_rdata_i_reg_7_ 6) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_7_ "SIn_DBus[7]") (joined + (portref D (instanceref s_axi_rdata_i_reg_0_)) + (portref (member s_axi_rdata_i_reg_7_ 7) (instanceref I_DECODER)) + ) + ) + (net (rename bus2ip_addr_i_2__i_1_n_0 "bus2ip_addr_i[2]_i_1_n_0") (joined + (portref D (instanceref bus2ip_addr_i_reg_2_)) + (portref O (instanceref bus2ip_addr_i_2__i_1)) + ) + ) + (net (rename bus2ip_addr_i_3__i_1_n_0 "bus2ip_addr_i[3]_i_1_n_0") (joined + (portref D (instanceref bus2ip_addr_i_reg_3_)) + (portref O (instanceref bus2ip_addr_i_3__i_1)) + ) + ) + (net (rename bus2ip_addr_i_3__i_2_n_0 "bus2ip_addr_i[3]_i_2_n_0") (joined + (portref I1 (instanceref bus2ip_addr_i_2__i_1)) + (portref I1 (instanceref bus2ip_addr_i_3__i_1)) + (portref O (instanceref bus2ip_addr_i_3__i_2)) + ) + ) + (net (rename bus2ip_addr_i_reg_n_0__2_ "bus2ip_addr_i_reg_n_0_[2]") (joined + (portref I4 (instanceref bus2ip_addr_i_2__i_1)) + (portref Q (instanceref bus2ip_addr_i_reg_2_)) + (portref bus2ip_addr_i_reg_2_ (instanceref I_DECODER)) + ) + ) + (net (rename bus2ip_addr_i_reg_n_0__3_ "bus2ip_addr_i_reg_n_0_[3]") (joined + (portref I4 (instanceref bus2ip_addr_i_3__i_1)) + (portref Q (instanceref bus2ip_addr_i_reg_3_)) + (portref bus2ip_addr_i_reg_3_ (instanceref I_DECODER)) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref bus2ip_rdce_0_ (instanceref I_DECODER)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_reset (joined + (portref D (instanceref rst_reg)) + (portref bus2ip_reset) + ) + ) + (net bus2ip_rnw_i (joined + (portref I5 (instanceref bus2ip_rnw_i_i_1)) + (portref Q (instanceref bus2ip_rnw_i_reg)) + (portref bus2ip_rnw_i (instanceref I_DECODER)) + ) + ) + (net bus2ip_rnw_i_i_1_n_0 (joined + (portref D (instanceref bus2ip_rnw_i_reg)) + (portref O (instanceref bus2ip_rnw_i_i_1)) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref I_DECODER)) + (portref enable_interrupts) + ) + ) + (net enable_interrupts_reg (joined + (portref enable_interrupts_reg (instanceref I_DECODER)) + (portref enable_interrupts_reg) + ) + ) + (net enable_interrupts_reg_0 (joined + (portref enable_interrupts_reg_0 (instanceref I_DECODER)) + (portref enable_interrupts_reg_0) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref I_DECODER)) + (portref fifo_wr) + ) + ) + (net ip2bus_error (joined + (portref D (instanceref s_axi_rresp_i_reg_1_)) + (portref ip2bus_error (instanceref I_DECODER)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref I_DECODER)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref I_DECODER)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref I_DECODER)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref I_DECODER)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref I_DECODER)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref I_DECODER)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref I_DECODER)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref I_DECODER)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref reset_RX_FIFO (instanceref I_DECODER)) + (portref reset_RX_FIFO) + ) + ) + (net reset_TX_FIFO (joined + (portref reset_TX_FIFO (instanceref I_DECODER)) + (portref reset_TX_FIFO) + ) + ) + (net rst (joined + (portref Q (instanceref rst_reg)) + (portref R (instanceref bus2ip_addr_i_reg_2_)) + (portref R (instanceref bus2ip_addr_i_reg_3_)) + (portref R (instanceref bus2ip_rnw_i_reg)) + (portref R (instanceref s_axi_bresp_i_reg_1_)) + (portref R (instanceref s_axi_bvalid_i_reg)) + (portref R (instanceref s_axi_rdata_i_reg_0_)) + (portref R (instanceref s_axi_rdata_i_reg_1_)) + (portref R (instanceref s_axi_rdata_i_reg_2_)) + (portref R (instanceref s_axi_rdata_i_reg_3_)) + (portref R (instanceref s_axi_rdata_i_reg_4_)) + (portref R (instanceref s_axi_rdata_i_reg_5_)) + (portref R (instanceref s_axi_rdata_i_reg_6_)) + (portref R (instanceref s_axi_rdata_i_reg_7_)) + (portref R (instanceref s_axi_rresp_i_reg_1_)) + (portref R (instanceref s_axi_rvalid_i_reg)) + (portref R (instanceref start2_reg)) + (portref R (instanceref state_reg_0_)) + (portref R (instanceref state_reg_1_)) + ) + ) + (net rx_Buffer_Full (joined + (portref rx_Buffer_Full (instanceref I_DECODER)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre_reg (joined + (portref rx_Data_Present_Pre_reg (instanceref I_DECODER)) + (portref rx_Data_Present_Pre_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref bus2ip_addr_i_reg_2_)) + (portref C (instanceref bus2ip_addr_i_reg_3_)) + (portref C (instanceref bus2ip_rnw_i_reg)) + (portref C (instanceref rst_reg)) + (portref C (instanceref s_axi_bresp_i_reg_1_)) + (portref C (instanceref s_axi_bvalid_i_reg)) + (portref C (instanceref s_axi_rdata_i_reg_0_)) + (portref C (instanceref s_axi_rdata_i_reg_1_)) + (portref C (instanceref s_axi_rdata_i_reg_2_)) + (portref C (instanceref s_axi_rdata_i_reg_3_)) + (portref C (instanceref s_axi_rdata_i_reg_4_)) + (portref C (instanceref s_axi_rdata_i_reg_5_)) + (portref C (instanceref s_axi_rdata_i_reg_6_)) + (portref C (instanceref s_axi_rdata_i_reg_7_)) + (portref C (instanceref s_axi_rresp_i_reg_1_)) + (portref C (instanceref s_axi_rvalid_i_reg)) + (portref C (instanceref start2_reg)) + (portref C (instanceref state_reg_0_)) + (portref C (instanceref state_reg_1_)) + (portref s_axi_aclk (instanceref I_DECODER)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined + (portref I2 (instanceref bus2ip_addr_i_2__i_1)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined + (portref I2 (instanceref bus2ip_addr_i_3__i_1)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_DECODER)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref I_DECODER)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref I2 (instanceref bus2ip_addr_i_3__i_2)) + (portref I2 (instanceref bus2ip_rnw_i_i_1)) + (portref I2 (instanceref start2_i_1)) + (portref s_axi_arvalid (instanceref I_DECODER)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined + (portref I0 (instanceref bus2ip_addr_i_2__i_1)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined + (portref I0 (instanceref bus2ip_addr_i_3__i_1)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref I_DECODER)) + (portref s_axi_awready) + ) + ) + (net s_axi_awvalid (joined + (portref I0 (instanceref bus2ip_rnw_i_i_1)) + (portref I0 (instanceref start2_i_1)) + (portref I0 (instanceref state_1__i_3)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref I3 (instanceref state_0__i_2)) + (portref I3 (instanceref state_1__i_2)) + (portref s_axi_bready (instanceref I_DECODER)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref Q (instanceref s_axi_bresp_i_reg_1_)) + (portref s_axi_bresp_0_ (instanceref I_DECODER)) + (portref s_axi_bresp_0_) + ) + ) + (net s_axi_bvalid (joined + (portref I4 (instanceref state_0__i_2)) + (portref I4 (instanceref state_1__i_2)) + (portref Q (instanceref s_axi_bvalid_i_reg)) + (portref s_axi_bvalid_i_reg_0 (instanceref I_DECODER)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_0_)) + (portref (member s_axi_rdata 7)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_1_)) + (portref (member s_axi_rdata 6)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_2_)) + (portref (member s_axi_rdata 5)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_3_)) + (portref (member s_axi_rdata 4)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_4_)) + (portref (member s_axi_rdata 3)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_5_)) + (portref (member s_axi_rdata 2)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_6_)) + (portref (member s_axi_rdata 1)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_7_)) + (portref (member s_axi_rdata 0)) + ) + ) + (net s_axi_rdata_i (joined + (portref CE (instanceref s_axi_rdata_i_reg_0_)) + (portref CE (instanceref s_axi_rdata_i_reg_1_)) + (portref CE (instanceref s_axi_rdata_i_reg_2_)) + (portref CE (instanceref s_axi_rdata_i_reg_3_)) + (portref CE (instanceref s_axi_rdata_i_reg_4_)) + (portref CE (instanceref s_axi_rdata_i_reg_5_)) + (portref CE (instanceref s_axi_rdata_i_reg_6_)) + (portref CE (instanceref s_axi_rdata_i_reg_7_)) + (portref CE (instanceref s_axi_rresp_i_reg_1_)) + (portref O (instanceref s_axi_rdata_i_7__i_1)) + ) + ) + (net s_axi_rready (joined + (portref I2 (instanceref state_0__i_2)) + (portref I2 (instanceref state_1__i_2)) + (portref s_axi_rready (instanceref I_DECODER)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined + (portref Q (instanceref s_axi_rresp_i_reg_1_)) + (portref s_axi_rresp_0_) + ) + ) + (net s_axi_rvalid (joined + (portref I1 (instanceref state_0__i_2)) + (portref I1 (instanceref state_1__i_2)) + (portref Q (instanceref s_axi_rvalid_i_reg)) + (portref s_axi_rvalid_i_reg_0 (instanceref I_DECODER)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 2) (instanceref I_DECODER)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 1) (instanceref I_DECODER)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 0) (instanceref I_DECODER)) + (portref (member s_axi_wdata 0)) + ) + ) + (net s_axi_wvalid (joined + (portref I1 (instanceref bus2ip_rnw_i_i_1)) + (portref I1 (instanceref start2_i_1)) + (portref I1 (instanceref state_1__i_3)) + (portref s_axi_wvalid) + ) + ) + (net start2 (joined + (portref Q (instanceref start2_reg)) + (portref start2 (instanceref I_DECODER)) + ) + ) + (net start2_i_1_n_0 (joined + (portref D (instanceref start2_reg)) + (portref I3 (instanceref bus2ip_addr_i_2__i_1)) + (portref I3 (instanceref bus2ip_addr_i_3__i_1)) + (portref O (instanceref start2_i_1)) + ) + ) + (net (rename state_0_ "state[0]") (joined + (portref I0 (instanceref s_axi_rdata_i_7__i_1)) + (portref I0 (instanceref state_0__i_2)) + (portref I1 (instanceref bus2ip_addr_i_3__i_2)) + (portref I3 (instanceref bus2ip_rnw_i_i_1)) + (portref I3 (instanceref start2_i_1)) + (portref Q (instanceref state_reg_0_)) + (portref (member Q 1) (instanceref I_DECODER)) + ) + ) + (net (rename state_0__i_2_n_0 "state[0]_i_2_n_0") (joined + (portref O (instanceref state_0__i_2)) + (portref state_reg_0_ (instanceref I_DECODER)) + ) + ) + (net (rename state_1_ "state[1]") (joined + (portref I0 (instanceref bus2ip_addr_i_3__i_2)) + (portref I0 (instanceref state_1__i_2)) + (portref I1 (instanceref s_axi_rdata_i_7__i_1)) + (portref I4 (instanceref bus2ip_rnw_i_i_1)) + (portref I4 (instanceref start2_i_1)) + (portref Q (instanceref state_reg_1_)) + (portref (member Q 0) (instanceref I_DECODER)) + ) + ) + (net (rename state_1__i_2_n_0 "state[1]_i_2_n_0") (joined + (portref O (instanceref state_1__i_2)) + (portref state_reg_1_ (instanceref I_DECODER)) + ) + ) + (net (rename state_1__i_3_n_0 "state[1]_i_3_n_0") (joined + (portref O (instanceref state_1__i_3)) + (portref s_axi_wvalid (instanceref I_DECODER)) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref (member status_reg 1) (instanceref I_DECODER)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref (member status_reg 0) (instanceref I_DECODER)) + (portref (member status_reg 0)) + ) + ) + (net tx_Buffer_Empty_Pre_reg (joined + (portref tx_Buffer_Empty_Pre_reg (instanceref I_DECODER)) + (portref tx_Buffer_Empty_Pre_reg) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref I_DECODER)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "slave_attachment")) + ) + ) + (cell axi_uart_axi_lite_ipif (celltype GENERIC) + (view axi_lite_ipif (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction OUTPUT)) + (port FIFO_Full_reg (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) + (port bus2ip_reset (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port enable_interrupts_reg (direction OUTPUT)) + (port fifo_wr (direction OUTPUT)) + (port reset_RX_FIFO (direction OUTPUT)) + (port reset_TX_FIFO (direction OUTPUT)) + (port rx_Buffer_Full (direction INPUT)) + (port rx_Data_Present_Pre_reg (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_awvalid (direction INPUT)) + (port s_axi_bready (direction INPUT)) + (port s_axi_bvalid (direction OUTPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid (direction OUTPUT)) + (port s_axi_wvalid (direction INPUT)) + (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction INPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction INPUT)) + (port (array (rename s_axi_araddr "s_axi_araddr[1:0]") 2) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[1:0]") 2) (direction INPUT)) + (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[7:0]") 8) (direction OUTPUT)) + (port (rename s_axi_rresp_0_ "s_axi_rresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance I_SLAVE_ATTACHMENT (viewref slave_attachment (cellref axi_uart_slave_attachment (libraryref work_library0_1)))) + (net Bus_RNW_reg (joined + (portref enable_interrupts_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref Bus_RNW_reg) + ) + ) + (net FIFO_Full_reg (joined + (portref FIFO_Full_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 (instanceref I_SLAVE_ATTACHMENT)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined + (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref I_SLAVE_ATTACHMENT)) + (portref INFERRED_GEN_cnt_i_reg_2_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined + (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref I_SLAVE_ATTACHMENT)) + (portref INFERRED_GEN_cnt_i_reg_2__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref Q_0_) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref bus2ip_rdce_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_reset (joined + (portref bus2ip_reset (instanceref I_SLAVE_ATTACHMENT)) + (portref bus2ip_reset) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref I_SLAVE_ATTACHMENT)) + (portref enable_interrupts) + ) + ) + (net enable_interrupts_reg (joined + (portref enable_interrupts_reg_0 (instanceref I_SLAVE_ATTACHMENT)) + (portref enable_interrupts_reg) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref I_SLAVE_ATTACHMENT)) + (portref fifo_wr) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref reset_RX_FIFO (instanceref I_SLAVE_ATTACHMENT)) + (portref reset_RX_FIFO) + ) + ) + (net reset_TX_FIFO (joined + (portref reset_TX_FIFO (instanceref I_SLAVE_ATTACHMENT)) + (portref reset_TX_FIFO) + ) + ) + (net rx_Buffer_Full (joined + (portref rx_Buffer_Full (instanceref I_SLAVE_ATTACHMENT)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre_reg (joined + (portref rx_Data_Present_Pre_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref rx_Data_Present_Pre_reg) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined + (portref (member s_axi_araddr 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined + (portref (member s_axi_araddr 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref s_axi_arvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined + (portref (member s_axi_awaddr 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined + (portref (member s_axi_awaddr 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_awready) + ) + ) + (net s_axi_awvalid (joined + (portref s_axi_awvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref s_axi_bready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref s_axi_bresp_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_bresp_0_) + ) + ) + (net s_axi_bvalid (joined + (portref s_axi_bvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref (member s_axi_rdata 7) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 7)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref (member s_axi_rdata 6) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 6)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref (member s_axi_rdata 5) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 5)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref (member s_axi_rdata 4) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 4)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref (member s_axi_rdata 3) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 3)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref (member s_axi_rdata 2) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 2)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref (member s_axi_rdata 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 1)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref (member s_axi_rdata 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 0)) + ) + ) + (net s_axi_rready (joined + (portref s_axi_rready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined + (portref s_axi_rresp_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_rresp_0_) + ) + ) + (net s_axi_rvalid (joined + (portref s_axi_rvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 2) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_wdata 0)) + ) + ) + (net s_axi_wvalid (joined + (portref s_axi_wvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_wvalid) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref (member status_reg 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref (member status_reg 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member status_reg 0)) + ) + ) + (net tx_Buffer_Empty_Pre_reg (joined + (portref tx_Buffer_Empty_Pre_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref tx_Buffer_Empty_Pre_reg) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref I_SLAVE_ATTACHMENT)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "axi_lite_ipif")) + ) + ) + (cell axi_uart_baudrate (celltype GENERIC) + (view baudrate (viewtype NETLIST) + (interface + (port en_16x_Baud (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port (rename SR_0_ "SR[0]") (direction INPUT)) + ) + (contents + (instance EN_16x_Baud_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance EN_16x_Baud_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename count_0__i_1 "count[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h32")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename count_1__i_1 "count[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hC2")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename count_2__i_1 "count[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA9")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename count_reg_0_ "count_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename count_reg_1_ "count_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename count_reg_2_ "count_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref EN_16x_Baud_reg)) + (portref CE (instanceref count_reg_0_)) + (portref CE (instanceref count_reg_1_)) + (portref CE (instanceref count_reg_2_)) + (portref P (instanceref VCC)) + ) + ) + (net EN_16x_Baud_i_1_n_0 (joined + (portref D (instanceref EN_16x_Baud_reg)) + (portref O (instanceref EN_16x_Baud_i_1)) + ) + ) + (net (rename SR_0_ "SR[0]") (joined + (portref R (instanceref EN_16x_Baud_reg)) + (portref R (instanceref count_reg_0_)) + (portref R (instanceref count_reg_1_)) + (portref R (instanceref count_reg_2_)) + (portref SR_0_) + ) + ) + (net (rename count_0_ "count[0]") (joined + (portref I1 (instanceref EN_16x_Baud_i_1)) + (portref I1 (instanceref count_0__i_1)) + (portref I1 (instanceref count_1__i_1)) + (portref I1 (instanceref count_2__i_1)) + (portref Q (instanceref count_reg_0_)) + ) + ) + (net (rename count_0__i_1_n_0 "count[0]_i_1_n_0") (joined + (portref D (instanceref count_reg_0_)) + (portref O (instanceref count_0__i_1)) + ) + ) + (net (rename count_1_ "count[1]") (joined + (portref I0 (instanceref EN_16x_Baud_i_1)) + (portref I2 (instanceref count_0__i_1)) + (portref I2 (instanceref count_1__i_1)) + (portref I2 (instanceref count_2__i_1)) + (portref Q (instanceref count_reg_1_)) + ) + ) + (net (rename count_1__i_1_n_0 "count[1]_i_1_n_0") (joined + (portref D (instanceref count_reg_1_)) + (portref O (instanceref count_1__i_1)) + ) + ) + (net (rename count_2_ "count[2]") (joined + (portref I0 (instanceref count_0__i_1)) + (portref I0 (instanceref count_1__i_1)) + (portref I0 (instanceref count_2__i_1)) + (portref I2 (instanceref EN_16x_Baud_i_1)) + (portref Q (instanceref count_reg_2_)) + ) + ) + (net (rename count_2__i_1_n_0 "count[2]_i_1_n_0") (joined + (portref D (instanceref count_reg_2_)) + (portref O (instanceref count_2__i_1)) + ) + ) + (net en_16x_Baud (joined + (portref Q (instanceref EN_16x_Baud_reg)) + (portref en_16x_Baud) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref EN_16x_Baud_reg)) + (portref C (instanceref count_reg_0_)) + (portref C (instanceref count_reg_1_)) + (portref C (instanceref count_reg_2_)) + (portref s_axi_aclk) + ) + ) + ) + + (property ORIG_REF_NAME (string "baudrate")) + ) + ) + (cell axi_uart_dynshreg_i_f (celltype GENERIC) + (view dynshreg_i_f (viewtype NETLIST) + (interface + (port (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port en_16x_Baud (direction INPUT)) + (port fifo_Write0 (direction OUTPUT)) + (port frame_err_ocrd (direction INPUT)) + (port frame_err_ocrd_reg (direction OUTPUT)) + (port p_11_out (direction OUTPUT)) + (port p_14_out (direction OUTPUT)) + (port p_17_out (direction OUTPUT)) + (port p_20_out (direction OUTPUT)) + (port p_2_out (direction OUTPUT)) + (port p_5_out (direction OUTPUT)) + (port p_8_out (direction OUTPUT)) + (port running_reg (direction OUTPUT)) + (port running_reg_0 (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port scndry_out (direction INPUT)) + (port start_Edge_Detected (direction INPUT)) + (port status_reg_reg0 (direction OUTPUT)) + (port stop_Bit_Position_reg (direction OUTPUT)) + (port stop_Bit_Position_reg_0 (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename INFERRED_GEN_data_reg_14__0__srl15 "INFERRED_GEN.data_reg[14][0]_srl15") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 ")) + ) + (instance (rename INFERRED_GEN_data_reg_14__0__srl15_i_1 "INFERRED_GEN.data_reg[14][0]_srl15_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4440")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename INFERRED_GEN_data_reg_15__0_ "INFERRED_GEN.data_reg[15][0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_2__fifo_din_2__i_1 "SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_3__fifo_din_3__i_1 "SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_4__fifo_din_4__i_1 "SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_5__fifo_din_5__i_1 "SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_6__fifo_din_6__i_1 "SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_7__fifo_din_7__i_1 "SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_8__i_1 "SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_8__i_2 "SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF7")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance fifo_Write_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8000")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance frame_err_ocrd_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00FF0080")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance running_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hBFFFA0A0")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename status_reg_1__i_1 "status_reg[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0000F200")) + ) + (instance (rename status_reg_1__i_2 "status_reg[1]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance stop_Bit_Position_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h2CCC")) + ) + (net (rename &_const0_ "") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref G (instanceref GND)) + (portref R (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net (rename &_const1_ "") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A2 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A3 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref P (instanceref VCC)) + ) + ) + (net (rename INFERRED_GEN_data_reg_14__0__srl15_n_0 "INFERRED_GEN.data_reg[14][0]_srl15_n_0") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref Q (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + ) + ) + (net (rename INFERRED_GEN_data_reg_15_ "INFERRED_GEN.data_reg[15]") (joined + (portref I0 (instanceref fifo_Write_i_1)) + (portref I0 (instanceref frame_err_ocrd_i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref I1 (instanceref running_i_1)) + (portref I2 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref I2 (instanceref status_reg_1__i_2)) + (portref I3 (instanceref stop_Bit_Position_i_1)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (joined + (portref I4 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref O (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_) + ) + ) + (net clr_Status (joined + (portref I4 (instanceref status_reg_1__i_1)) + (portref clr_Status) + ) + ) + (net en_16x_Baud (joined + (portref CE (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref I0 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref I1 (instanceref fifo_Write_i_1)) + (portref I1 (instanceref frame_err_ocrd_i_1)) + (portref I1 (instanceref status_reg_1__i_2)) + (portref I2 (instanceref running_i_1)) + (portref I2 (instanceref stop_Bit_Position_i_1)) + (portref en_16x_Baud) + ) + ) + (net fifo_Write0 (joined + (portref O (instanceref fifo_Write_i_1)) + (portref fifo_Write0) + ) + ) + (net frame_err_ocrd (joined + (portref I4 (instanceref frame_err_ocrd_i_1)) + (portref frame_err_ocrd) + ) + ) + (net frame_err_ocrd_reg (joined + (portref O (instanceref frame_err_ocrd_i_1)) + (portref frame_err_ocrd_reg) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref I1 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref I0 (instanceref stop_Bit_Position_i_1)) + (portref (member in 7)) + ) + ) + (net p_11_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref p_11_out) + ) + ) + (net p_14_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref p_14_out) + ) + ) + (net p_17_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref p_17_out) + ) + ) + (net p_20_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref p_20_out) + ) + ) + (net p_2_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref p_2_out) + ) + ) + (net p_5_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref p_5_out) + ) + ) + (net p_8_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref p_8_out) + ) + ) + (net recycle (joined + (portref D (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref O (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + ) + ) + (net running_reg (joined + (portref O (instanceref running_i_1)) + (portref running_reg) + ) + ) + (net running_reg_0 (joined + (portref I4 (instanceref running_i_1)) + (portref running_reg_0) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref CLK (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I3 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref I3 (instanceref status_reg_1__i_1)) + (portref s_axi_aresetn) + ) + ) + (net scndry_out (joined + (portref I1 (instanceref status_reg_1__i_1)) + (portref I3 (instanceref fifo_Write_i_1)) + (portref I3 (instanceref frame_err_ocrd_i_1)) + (portref scndry_out) + ) + ) + (net start_Edge_Detected (joined + (portref I0 (instanceref running_i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref I3 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref start_Edge_Detected) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref I2 (instanceref status_reg_1__i_1)) + (portref status_reg_0_) + ) + ) + (net (rename status_reg_1__i_2_n_0 "status_reg[1]_i_2_n_0") (joined + (portref I0 (instanceref status_reg_1__i_1)) + (portref O (instanceref status_reg_1__i_2)) + ) + ) + (net status_reg_reg0 (joined + (portref O (instanceref status_reg_1__i_1)) + (portref status_reg_reg0) + ) + ) + (net stop_Bit_Position_reg (joined + (portref O (instanceref stop_Bit_Position_i_1)) + (portref stop_Bit_Position_reg) + ) + ) + (net stop_Bit_Position_reg_0 (joined + (portref I0 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref I0 (instanceref status_reg_1__i_2)) + (portref I1 (instanceref stop_Bit_Position_i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref I2 (instanceref fifo_Write_i_1)) + (portref I2 (instanceref frame_err_ocrd_i_1)) + (portref I3 (instanceref running_i_1)) + (portref stop_Bit_Position_reg_0) + ) + ) + (net valid_rx (joined + (portref I1 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_i_f")) + ) + ) + (cell axi_uart_cdc_sync (celltype GENERIC) + (view cdc_sync (viewtype NETLIST) + (interface + (port EN_16x_Baud_reg (direction INPUT)) + (port p_26_out (direction OUTPUT)) + (port rx (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port scndry_out (direction OUTPUT)) + (port start_Edge_Detected (direction INPUT)) + (port (rename in_0_ "in[0]") (direction INPUT)) + ) + (contents + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename SERIAL_TO_PARALLEL_1__fifo_din_1__i_1 "SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFE00CE00")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + ) + ) + (net EN_16x_Baud_reg (joined + (portref I2 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref EN_16x_Baud_reg) + ) + ) + (net VCC_1 (joined + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref P (instanceref VCC)) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref I4 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref in_0_) + ) + ) + (net p_26_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref p_26_out) + ) + ) + (net rx (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref rx) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I3 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref s_axi_aresetn) + ) + ) + (net s_level_out_d1_cdc_to (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + ) + ) + (net s_level_out_d2 (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + ) + ) + (net s_level_out_d3 (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + ) + ) + (net scndry_out (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref scndry_out) + ) + ) + (net start_Edge_Detected (joined + (portref I1 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref start_Edge_Detected) + ) + ) + ) + + (property ORIG_REF_NAME (string "cdc_sync")) + ) + ) + (cell axi_uart_cntr_incr_decr_addn_f_2 (celltype GENERIC) + (view cntr_incr_decr_addn_f_2 (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port FIFO_Full_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port enable_interrupts (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port fifo_full_p1 (direction OUTPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (direction INPUT)) + (port (array (rename Q "Q[4:0]") 5) (direction OUTPUT)) + (port (rename SS_0_ "SS[0]") (direction OUTPUT)) + ) + (contents + (instance FIFO_Full_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000009040000")) + ) + (instance FIFO_Full_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h7")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename INFERRED_GEN_cnt_i_0__i_1 "INFERRED_GEN.cnt_i[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hF70808F7")) + ) + (instance (rename INFERRED_GEN_cnt_i_1__i_1 "INFERRED_GEN.cnt_i[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAAAA6A5595AAAA")) + ) + (instance (rename INFERRED_GEN_cnt_i_2__i_1 "INFERRED_GEN.cnt_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFE017F80")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename INFERRED_GEN_cnt_i_3__i_1 "INFERRED_GEN.cnt_i[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF0F0F0E178F0F0F0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_1 "INFERRED_GEN.cnt_i[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_2 "INFERRED_GEN.cnt_i[4]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF0F0F4F4F00AF0F0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_4 "INFERRED_GEN.cnt_i[4]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_5__0 "INFERRED_GEN.cnt_i[4]_i_5__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h7F")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_6 "INFERRED_GEN.cnt_i[4]_i_6") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hDF")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_0_ "INFERRED_GEN.cnt_i_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_1_ "INFERRED_GEN.cnt_i_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_3_ "INFERRED_GEN.cnt_i_reg[3]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance Interrupt_i_2 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h1010F010")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (net (rename &_const1_ "") (joined + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref Bus_RNW_reg_reg) + ) + ) + (net FIFO_Full_i_2_n_0 (joined + (portref I5 (instanceref FIFO_Full_i_1)) + (portref O (instanceref FIFO_Full_i_2)) + ) + ) + (net FIFO_Full_reg (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_6)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref I3 (instanceref FIFO_Full_i_1)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_4_n_0 "INFERRED_GEN.cnt_i[4]_i_4_n_0") (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_4)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_5__0_n_0 "INFERRED_GEN.cnt_i[4]_i_5__0_n_0") (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_6_n_0 "INFERRED_GEN.cnt_i[4]_i_6_n_0") (joined + (portref I0 (instanceref FIFO_Full_i_1)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_6)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (joined + (portref I3 (instanceref Interrupt_i_2)) + (portref INFERRED_GEN_cnt_i_reg_4__0_0_) + ) + ) + (net Interrupt0 (joined + (portref O (instanceref Interrupt_i_2)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref I1 (instanceref FIFO_Full_i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref (member Q 4)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref I0 (instanceref FIFO_Full_i_2)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_4)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref (member Q 3)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_4)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + (portref I1 (instanceref FIFO_Full_i_2)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref (member Q 2)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_4)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + (portref I4 (instanceref FIFO_Full_i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref (member Q 1)) + ) + ) + (net (rename Q_4_ "Q[4]") (joined + (portref I1 (instanceref Interrupt_i_2)) + (portref I2 (instanceref FIFO_Full_i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref (member Q 0)) + ) + ) + (net (rename SS_0_ "SS[0]") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_1)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref SS_0_) + ) + ) + (net (rename addr_i_p1_0_ "addr_i_p1[0]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref O (instanceref INFERRED_GEN_cnt_i_0__i_1)) + ) + ) + (net (rename addr_i_p1_1_ "addr_i_p1[1]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref O (instanceref INFERRED_GEN_cnt_i_1__i_1)) + ) + ) + (net (rename addr_i_p1_2_ "addr_i_p1[2]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref O (instanceref INFERRED_GEN_cnt_i_2__i_1)) + ) + ) + (net (rename addr_i_p1_3_ "addr_i_p1[3]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_1)) + ) + ) + (net (rename addr_i_p1_4_ "addr_i_p1[4]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_2)) + ) + ) + (net enable_interrupts (joined + (portref I2 (instanceref Interrupt_i_2)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_6)) + (portref fifo_Write) + ) + ) + (net fifo_full_p1 (joined + (portref O (instanceref FIFO_Full_i_1)) + (portref fifo_full_p1) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_1)) + (portref reset_RX_FIFO_reg) + ) + ) + (net rx_Data_Present_Pre (joined + (portref I0 (instanceref Interrupt_i_2)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_1)) + (portref s_axi_aresetn) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref I4 (instanceref Interrupt_i_2)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_6)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "cntr_incr_decr_addn_f")) + ) + ) + (cell axi_uart_dynshreg_f_3 (celltype GENERIC) + (view dynshreg_f_3 (viewtype NETLIST) + (interface + (port FIFO_Full_reg (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (array (rename Q "Q[3:0]") 4) (direction INPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + ) + (contents + (instance (rename INFERRED_GEN_data_reg_15__0__srl16 "INFERRED_GEN.data_reg[15][0]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__1__srl16 "INFERRED_GEN.data_reg[15][1]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__2__srl16 "INFERRED_GEN.data_reg[15][2]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__3__srl16 "INFERRED_GEN.data_reg[15][3]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__4__srl16 "INFERRED_GEN.data_reg[15][4]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__5__srl16 "INFERRED_GEN.data_reg[15][5]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__6__srl16 "INFERRED_GEN.data_reg[15][6]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16 "INFERRED_GEN.data_reg[15][7]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16_i_1__0 "INFERRED_GEN.data_reg[15][7]_srl16_i_1__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + ) + (net FIFO_Full_reg (joined + (portref I1 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + (portref FIFO_Full_reg) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 3)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 2)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref A2 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 1)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref A3 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 0)) + ) + ) + (net fifo_Write (joined + (portref I2 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + (portref fifo_Write) + ) + ) + (net fifo_wr (joined + (portref CE (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref O (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member in 7)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref (member out 0)) + ) + ) + (net s_axi_aclk (joined + (portref CLK (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref s_axi_aclk) + ) + ) + (net valid_rx (joined + (portref I0 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_f")) + ) + ) + (cell axi_uart_srl_fifo_rbu_f_1 (celltype GENERIC) + (view srl_fifo_rbu_f_1 (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) + (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) + ) + (contents + (instance CNTR_INCR_DECR_ADDN_F_I (viewref cntr_incr_decr_addn_f_2 (cellref axi_uart_cntr_incr_decr_addn_f_2 (libraryref work_library0_1)))) + (instance DYNSHREG_F_I (viewref dynshreg_f_3 (cellref axi_uart_dynshreg_f_3 (libraryref work_library0_1)))) + (instance FIFO_Full_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename status_reg_2__i_1 "status_reg[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00EA0000")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref FIFO_Full_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Bus_RNW_reg_reg) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_3 (joined + (portref (member Q 1) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 0) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_4 (joined + (portref (member Q 2) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 1) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_5 (joined + (portref (member Q 3) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 2) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_6 (joined + (portref (member Q 4) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 3) (instanceref DYNSHREG_F_I)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net Interrupt0 (joined + (portref Interrupt0 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref (member Q 0) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Q_0_) + ) + ) + (net RX_FIFO_Reset (joined + (portref R (instanceref FIFO_Full_reg)) + (portref SS_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net clr_Status (joined + (portref I3 (instanceref status_reg_2__i_1)) + (portref clr_Status) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref I1 (instanceref status_reg_2__i_1)) + (portref fifo_Write (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref fifo_Write (instanceref DYNSHREG_F_I)) + (portref fifo_Write) + ) + ) + (net fifo_full_p1 (joined + (portref D (instanceref FIFO_Full_reg)) + (portref fifo_full_p1 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref (member in 0) (instanceref DYNSHREG_F_I)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref (member in 1) (instanceref DYNSHREG_F_I)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref (member in 2) (instanceref DYNSHREG_F_I)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref (member in 3) (instanceref DYNSHREG_F_I)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref (member in 4) (instanceref DYNSHREG_F_I)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref (member in 5) (instanceref DYNSHREG_F_I)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref (member in 6) (instanceref DYNSHREG_F_I)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref (member in 7) (instanceref DYNSHREG_F_I)) + (portref (member in 7)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref DYNSHREG_F_I)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref DYNSHREG_F_I)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref DYNSHREG_F_I)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref DYNSHREG_F_I)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref DYNSHREG_F_I)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref DYNSHREG_F_I)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref DYNSHREG_F_I)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref DYNSHREG_F_I)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref reset_RX_FIFO_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref reset_RX_FIFO_reg) + ) + ) + (net rx_Data_Present_Pre (joined + (portref rx_Data_Present_Pre (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref FIFO_Full_reg)) + (portref s_axi_aclk (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aclk (instanceref DYNSHREG_F_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I4 (instanceref status_reg_2__i_1)) + (portref s_axi_aresetn (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref I0 (instanceref status_reg_2__i_1)) + (portref status_reg_0_) + ) + ) + (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined + (portref FIFO_Full_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref FIFO_Full_reg (instanceref DYNSHREG_F_I)) + (portref I2 (instanceref status_reg_2__i_1)) + (portref Q (instanceref FIFO_Full_reg)) + (portref status_reg_reg_2_) + ) + ) + (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined + (portref O (instanceref status_reg_2__i_1)) + (portref status_reg_reg_2__0) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref tx_Buffer_Empty_Pre (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref valid_rx (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref valid_rx (instanceref DYNSHREG_F_I)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_rbu_f")) + ) + ) + (cell axi_uart_srl_fifo_f_0 (celltype GENERIC) + (view srl_fifo_f_0 (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) + (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) + ) + (contents + (instance I_SRL_FIFO_RBU_F (viewref srl_fifo_rbu_f_1 (cellref axi_uart_srl_fifo_rbu_f_1 (libraryref work_library0_1)))) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref Bus_RNW_reg_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net Interrupt0 (joined + (portref Interrupt0 (instanceref I_SRL_FIFO_RBU_F)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref Q_0_) + ) + ) + (net clr_Status (joined + (portref clr_Status (instanceref I_SRL_FIFO_RBU_F)) + (portref clr_Status) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref I_SRL_FIFO_RBU_F)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref fifo_Write (instanceref I_SRL_FIFO_RBU_F)) + (portref fifo_Write) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref (member in 0) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref (member in 1) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref (member in 2) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref (member in 3) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref (member in 4) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref (member in 5) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref (member in 6) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref (member in 7) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 7)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref reset_RX_FIFO_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref reset_RX_FIFO_reg) + ) + ) + (net rx_Data_Present_Pre (joined + (portref rx_Data_Present_Pre (instanceref I_SRL_FIFO_RBU_F)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aresetn) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref status_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref status_reg_0_) + ) + ) + (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined + (portref status_reg_reg_2_ (instanceref I_SRL_FIFO_RBU_F)) + (portref status_reg_reg_2_) + ) + ) + (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined + (portref status_reg_reg_2__0 (instanceref I_SRL_FIFO_RBU_F)) + (portref status_reg_reg_2__0) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref tx_Buffer_Empty_Pre (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref valid_rx (instanceref I_SRL_FIFO_RBU_F)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_f")) + ) + ) + (cell axi_uart_uartlite_rx (celltype GENERIC) + (view uartlite_rx (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port en_16x_Baud (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port status_reg_reg0 (direction OUTPUT)) + (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) + (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (rename SR_0_ "SR[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance DELAY_16_I (viewref dynshreg_i_f (cellref axi_uart_dynshreg_i_f (libraryref work_library0_1)))) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance INPUT_DOUBLE_REGS3 (viewref cdc_sync (cellref axi_uart_cdc_sync (libraryref work_library0_1)))) + (instance Interrupt_i_1 (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename SERIAL_TO_PARALLEL_1__fifo_din_reg_1_ "SERIAL_TO_PARALLEL[1].fifo_din_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_3__fifo_din_reg_3_ "SERIAL_TO_PARALLEL[3].fifo_din_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_4__fifo_din_reg_4_ "SERIAL_TO_PARALLEL[4].fifo_din_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_5__fifo_din_reg_5_ "SERIAL_TO_PARALLEL[5].fifo_din_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_6__fifo_din_reg_6_ "SERIAL_TO_PARALLEL[6].fifo_din_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_7__fifo_din_reg_7_ "SERIAL_TO_PARALLEL[7].fifo_din_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_reg_8_ "SERIAL_TO_PARALLEL[8].fifo_din_reg[8]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance SRL_FIFO_I (viewref srl_fifo_f_0 (cellref axi_uart_srl_fifo_f_0 (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance fifo_Write_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance frame_err_ocrd_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance running_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_1_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_2_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_3_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_4_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_5_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_6_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_7_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_8_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_9_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance start_Edge_Detected_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000010")) + ) + (instance start_Edge_Detected_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000010")) + ) + (instance start_Edge_Detected_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance stop_Bit_Position_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance valid_rx_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hBA")) + ) + (instance valid_rx_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref R (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref R (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref R (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref R (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref R (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref R (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref R (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref CE (instanceref fifo_Write_reg)) + (portref CE (instanceref frame_err_ocrd_reg)) + (portref CE (instanceref running_reg)) + (portref CE (instanceref stop_Bit_Position_reg)) + (portref CE (instanceref valid_rx_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref SRL_FIFO_I)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref SRL_FIFO_I)) + (portref Bus_RNW_reg_reg) + ) + ) + (net DELAY_16_I_n_1 (joined + (portref EN_16x_Baud_reg (instanceref INPUT_DOUBLE_REGS3)) + (portref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ (instanceref DELAY_16_I)) + ) + ) + (net DELAY_16_I_n_10 (joined + (portref D (instanceref stop_Bit_Position_reg)) + (portref stop_Bit_Position_reg (instanceref DELAY_16_I)) + ) + ) + (net DELAY_16_I_n_11 (joined + (portref D (instanceref frame_err_ocrd_reg)) + (portref frame_err_ocrd_reg (instanceref DELAY_16_I)) + ) + ) + (net DELAY_16_I_n_12 (joined + (portref D (instanceref running_reg)) + (portref running_reg (instanceref DELAY_16_I)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref SRL_FIFO_I)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net Interrupt0 (joined + (portref Interrupt0 (instanceref SRL_FIFO_I)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref SRL_FIFO_I)) + (portref Q_0_) + ) + ) + (net RX_D2 (joined + (portref D (instanceref rx_1_reg)) + (portref scndry_out (instanceref DELAY_16_I)) + (portref scndry_out (instanceref INPUT_DOUBLE_REGS3)) + ) + ) + (net (rename SR_0_ "SR[0]") (joined + (portref O (instanceref Interrupt_i_1)) + (portref R (instanceref fifo_Write_reg)) + (portref R (instanceref frame_err_ocrd_reg)) + (portref R (instanceref running_reg)) + (portref R (instanceref rx_1_reg)) + (portref R (instanceref rx_2_reg)) + (portref R (instanceref rx_3_reg)) + (portref R (instanceref rx_4_reg)) + (portref R (instanceref rx_5_reg)) + (portref R (instanceref rx_6_reg)) + (portref R (instanceref rx_7_reg)) + (portref R (instanceref rx_8_reg)) + (portref R (instanceref rx_9_reg)) + (portref R (instanceref start_Edge_Detected_reg)) + (portref R (instanceref stop_Bit_Position_reg)) + (portref R (instanceref valid_rx_reg)) + (portref SR_0_) + ) + ) + (net clr_Status (joined + (portref clr_Status (instanceref DELAY_16_I)) + (portref clr_Status (instanceref SRL_FIFO_I)) + (portref clr_Status) + ) + ) + (net en_16x_Baud (joined + (portref CE (instanceref rx_1_reg)) + (portref CE (instanceref rx_2_reg)) + (portref CE (instanceref rx_3_reg)) + (portref CE (instanceref rx_4_reg)) + (portref CE (instanceref rx_5_reg)) + (portref CE (instanceref rx_6_reg)) + (portref CE (instanceref rx_7_reg)) + (portref CE (instanceref rx_8_reg)) + (portref CE (instanceref rx_9_reg)) + (portref CE (instanceref start_Edge_Detected_reg)) + (portref en_16x_Baud (instanceref DELAY_16_I)) + (portref en_16x_Baud) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref SRL_FIFO_I)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref I1 (instanceref valid_rx_i_1)) + (portref Q (instanceref fifo_Write_reg)) + (portref fifo_Write (instanceref SRL_FIFO_I)) + ) + ) + (net fifo_Write0 (joined + (portref D (instanceref fifo_Write_reg)) + (portref fifo_Write0 (instanceref DELAY_16_I)) + ) + ) + (net (rename fifo_din_1_ "fifo_din[1]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref (member in 0) (instanceref DELAY_16_I)) + (portref in_0_ (instanceref INPUT_DOUBLE_REGS3)) + (portref (member in 0) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_2_ "fifo_din[2]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref (member in 1) (instanceref DELAY_16_I)) + (portref (member in 1) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_3_ "fifo_din[3]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref (member in 2) (instanceref DELAY_16_I)) + (portref (member in 2) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_4_ "fifo_din[4]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref (member in 3) (instanceref DELAY_16_I)) + (portref (member in 3) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_5_ "fifo_din[5]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref (member in 4) (instanceref DELAY_16_I)) + (portref (member in 4) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_6_ "fifo_din[6]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref (member in 5) (instanceref DELAY_16_I)) + (portref (member in 5) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_7_ "fifo_din[7]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref (member in 6) (instanceref DELAY_16_I)) + (portref (member in 6) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_8_ "fifo_din[8]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref (member in 7) (instanceref DELAY_16_I)) + (portref (member in 7) (instanceref SRL_FIFO_I)) + ) + ) + (net frame_err_ocrd (joined + (portref I5 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref frame_err_ocrd_reg)) + (portref frame_err_ocrd (instanceref DELAY_16_I)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref SRL_FIFO_I)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref SRL_FIFO_I)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref SRL_FIFO_I)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref SRL_FIFO_I)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref SRL_FIFO_I)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref SRL_FIFO_I)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref SRL_FIFO_I)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref SRL_FIFO_I)) + (portref (member out 0)) + ) + ) + (net p_11_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref p_11_out (instanceref DELAY_16_I)) + ) + ) + (net p_14_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref p_14_out (instanceref DELAY_16_I)) + ) + ) + (net p_17_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref p_17_out (instanceref DELAY_16_I)) + ) + ) + (net p_20_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref p_20_out (instanceref DELAY_16_I)) + ) + ) + (net p_26_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref p_26_out (instanceref INPUT_DOUBLE_REGS3)) + ) + ) + (net p_2_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref p_2_out (instanceref DELAY_16_I)) + ) + ) + (net p_5_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref p_5_out (instanceref DELAY_16_I)) + ) + ) + (net p_8_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref p_8_out (instanceref DELAY_16_I)) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref reset_RX_FIFO_reg (instanceref SRL_FIFO_I)) + (portref reset_RX_FIFO_reg) + ) + ) + (net running_reg_n_0 (joined + (portref I3 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref running_reg)) + (portref running_reg_0 (instanceref DELAY_16_I)) + ) + ) + (net rx (joined + (portref rx (instanceref INPUT_DOUBLE_REGS3)) + (portref rx) + ) + ) + (net rx_1 (joined + (portref D (instanceref rx_2_reg)) + (portref I4 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_1_reg)) + ) + ) + (net rx_2 (joined + (portref D (instanceref rx_3_reg)) + (portref I1 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_2_reg)) + ) + ) + (net rx_3 (joined + (portref D (instanceref rx_4_reg)) + (portref I3 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_3_reg)) + ) + ) + (net rx_4 (joined + (portref D (instanceref rx_5_reg)) + (portref I5 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_4_reg)) + ) + ) + (net rx_5 (joined + (portref D (instanceref rx_6_reg)) + (portref I0 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_5_reg)) + ) + ) + (net rx_6 (joined + (portref D (instanceref rx_7_reg)) + (portref I4 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_6_reg)) + ) + ) + (net rx_7 (joined + (portref D (instanceref rx_8_reg)) + (portref I1 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_7_reg)) + ) + ) + (net rx_8 (joined + (portref D (instanceref rx_9_reg)) + (portref I0 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_8_reg)) + ) + ) + (net rx_9 (joined + (portref I2 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_9_reg)) + ) + ) + (net rx_Data_Present_Pre (joined + (portref rx_Data_Present_Pre (instanceref SRL_FIFO_I)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref C (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref C (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref C (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref C (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref C (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref C (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref C (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref C (instanceref fifo_Write_reg)) + (portref C (instanceref frame_err_ocrd_reg)) + (portref C (instanceref running_reg)) + (portref C (instanceref rx_1_reg)) + (portref C (instanceref rx_2_reg)) + (portref C (instanceref rx_3_reg)) + (portref C (instanceref rx_4_reg)) + (portref C (instanceref rx_5_reg)) + (portref C (instanceref rx_6_reg)) + (portref C (instanceref rx_7_reg)) + (portref C (instanceref rx_8_reg)) + (portref C (instanceref rx_9_reg)) + (portref C (instanceref start_Edge_Detected_reg)) + (portref C (instanceref stop_Bit_Position_reg)) + (portref C (instanceref valid_rx_reg)) + (portref s_axi_aclk (instanceref DELAY_16_I)) + (portref s_axi_aclk (instanceref INPUT_DOUBLE_REGS3)) + (portref s_axi_aclk (instanceref SRL_FIFO_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I0 (instanceref Interrupt_i_1)) + (portref s_axi_aresetn (instanceref DELAY_16_I)) + (portref s_axi_aresetn (instanceref INPUT_DOUBLE_REGS3)) + (portref s_axi_aresetn (instanceref SRL_FIFO_I)) + (portref s_axi_aresetn) + ) + ) + (net start_Edge_Detected (joined + (portref I0 (instanceref valid_rx_i_1)) + (portref Q (instanceref start_Edge_Detected_reg)) + (portref start_Edge_Detected (instanceref DELAY_16_I)) + (portref start_Edge_Detected (instanceref INPUT_DOUBLE_REGS3)) + ) + ) + (net start_Edge_Detected0 (joined + (portref D (instanceref start_Edge_Detected_reg)) + (portref O (instanceref start_Edge_Detected_i_1)) + ) + ) + (net start_Edge_Detected_i_2_n_0 (joined + (portref I2 (instanceref start_Edge_Detected_i_1)) + (portref O (instanceref start_Edge_Detected_i_2)) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref status_reg_0_ (instanceref SRL_FIFO_I)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref status_reg_0_ (instanceref DELAY_16_I)) + (portref (member status_reg 0)) + ) + ) + (net status_reg_reg0 (joined + (portref status_reg_reg0 (instanceref DELAY_16_I)) + (portref status_reg_reg0) + ) + ) + (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined + (portref status_reg_reg_2_ (instanceref SRL_FIFO_I)) + (portref status_reg_reg_2_) + ) + ) + (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined + (portref status_reg_reg_2__0 (instanceref SRL_FIFO_I)) + (portref status_reg_reg_2__0) + ) + ) + (net stop_Bit_Position_reg_n_0 (joined + (portref Q (instanceref stop_Bit_Position_reg)) + (portref stop_Bit_Position_reg_0 (instanceref DELAY_16_I)) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref tx_Buffer_Empty_Pre (instanceref SRL_FIFO_I)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref I2 (instanceref valid_rx_i_1)) + (portref Q (instanceref valid_rx_reg)) + (portref valid_rx (instanceref DELAY_16_I)) + (portref valid_rx (instanceref SRL_FIFO_I)) + ) + ) + (net valid_rx_i_1_n_0 (joined + (portref D (instanceref valid_rx_reg)) + (portref O (instanceref valid_rx_i_1)) + ) + ) + ) + + (property ORIG_REF_NAME (string "uartlite_rx")) + ) + ) + (cell axi_uart_dynshreg_i_f__parameterized0 (celltype GENERIC) + (view dynshreg_i_f__parameterized0 (viewtype NETLIST) + (interface + (port en_16x_Baud (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port tx_Data_Enable_reg (direction OUTPUT)) + (port tx_Data_Enable_reg_0 (direction INPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename INFERRED_GEN_data_reg_14__0__srl15 "INFERRED_GEN.data_reg[14][0]_srl15") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__0_ "INFERRED_GEN.data_reg[15][0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance tx_Data_Enable_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + ) + (net (rename &_const0_ "") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref G (instanceref GND)) + (portref R (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net (rename &_const1_ "") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A2 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A3 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref P (instanceref VCC)) + ) + ) + (net (rename INFERRED_GEN_data_reg_14__0__srl15_n_0 "INFERRED_GEN.data_reg[14][0]_srl15_n_0") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref Q (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + ) + ) + (net (rename INFERRED_GEN_data_reg_n_0__15__0_ "INFERRED_GEN.data_reg_n_0_[15][0]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref I0 (instanceref tx_Data_Enable_i_1)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net en_16x_Baud (joined + (portref CE (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref I2 (instanceref tx_Data_Enable_i_1)) + (portref en_16x_Baud) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref CLK (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref s_axi_aclk) + ) + ) + (net tx_Data_Enable_reg (joined + (portref O (instanceref tx_Data_Enable_i_1)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Data_Enable_reg_0 (joined + (portref I1 (instanceref tx_Data_Enable_i_1)) + (portref tx_Data_Enable_reg_0) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_i_f")) + ) + ) + (cell axi_uart_cntr_incr_decr_addn_f (celltype GENERIC) + (view cntr_incr_decr_addn_f (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port fifo_Read (direction INPUT)) + (port fifo_full_p1 (direction OUTPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port tx_DataBits (direction INPUT)) + (port tx_Data_Enable_reg (direction INPUT)) + (port tx_Start (direction INPUT)) + (port tx_Start0 (direction OUTPUT)) + (port (array (rename Q "Q[4:0]") 5) (direction OUTPUT)) + (port (rename SS_0_ "SS[0]") (direction OUTPUT)) + ) + (contents + (instance FIFO_Full_i_1__0 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000004090000")) + ) + (instance FIFO_Full_i_2__0 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h7")) + ) + (instance (rename INFERRED_GEN_cnt_i_0__i_1__0 "INFERRED_GEN.cnt_i[0]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hBBB4BBBB444B4444")) + ) + (instance (rename INFERRED_GEN_cnt_i_1__i_1__0 "INFERRED_GEN.cnt_i[1]_i_1__0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hAA9A65AA")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename INFERRED_GEN_cnt_i_2__i_1__0 "INFERRED_GEN.cnt_i[2]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF4FF0B00FFBF0040")) + ) + (instance (rename INFERRED_GEN_cnt_i_3__i_1__0 "INFERRED_GEN.cnt_i[3]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAA6AAAAAA9AAAA")) + ) + (instance (rename INFERRED_GEN_cnt_i_3__i_2__0 "INFERRED_GEN.cnt_i[3]_i_2__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_1__0 "INFERRED_GEN.cnt_i[4]_i_1__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_2__0 "INFERRED_GEN.cnt_i[4]_i_2__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF0F0FAFAF003F0F0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_3__0 "INFERRED_GEN.cnt_i[4]_i_3__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0004")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_4__0 "INFERRED_GEN.cnt_i[4]_i_4__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h7F")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_0_ "INFERRED_GEN.cnt_i_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_1_ "INFERRED_GEN.cnt_i_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_3_ "INFERRED_GEN.cnt_i_reg[3]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance tx_Start_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0F02")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref Bus_RNW_reg) + ) + ) + (net FIFO_Full_i_2__0_n_0 (joined + (portref I5 (instanceref FIFO_Full_i_1__0)) + (portref O (instanceref FIFO_Full_i_2__0)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref I4 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref I0 (instanceref FIFO_Full_i_1__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_3__i_2__0_n_0 "INFERRED_GEN.cnt_i[3]_i_2__0_n_0") (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_3__0_n_0 "INFERRED_GEN.cnt_i[4]_i_3__0_n_0") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_4__0_n_0 "INFERRED_GEN.cnt_i[4]_i_4__0_n_0") (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref I1 (instanceref FIFO_Full_i_1__0)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref (member Q 4)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref I0 (instanceref FIFO_Full_i_2__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref (member Q 3)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + (portref I1 (instanceref FIFO_Full_i_2__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref (member Q 2)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + (portref I4 (instanceref FIFO_Full_i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref (member Q 1)) + ) + ) + (net (rename Q_4_ "Q[4]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I1 (instanceref tx_Start_i_1)) + (portref I2 (instanceref FIFO_Full_i_1__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref (member Q 0)) + ) + ) + (net (rename SS_0_ "SS[0]") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref SS_0_) + ) + ) + (net (rename addr_i_p1_0_ "addr_i_p1[0]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref O (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + ) + ) + (net (rename addr_i_p1_1_ "addr_i_p1[1]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref O (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + ) + ) + (net (rename addr_i_p1_2_ "addr_i_p1[2]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref O (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + ) + ) + (net (rename addr_i_p1_3_ "addr_i_p1[3]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + ) + ) + (net (rename addr_i_p1_4_ "addr_i_p1[4]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + ) + ) + (net fifo_Read (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I3 (instanceref FIFO_Full_i_1__0)) + (portref fifo_Read) + ) + ) + (net fifo_full_p1 (joined + (portref O (instanceref FIFO_Full_i_1__0)) + (portref fifo_full_p1) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) + (portref s_axi_aresetn) + ) + ) + (net tx_Buffer_Full (joined + (portref I2 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref I2 (instanceref tx_Start_i_1)) + (portref tx_DataBits) + ) + ) + (net tx_Data_Enable_reg (joined + (portref I0 (instanceref tx_Start_i_1)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Start (joined + (portref I3 (instanceref tx_Start_i_1)) + (portref tx_Start) + ) + ) + (net tx_Start0 (joined + (portref O (instanceref tx_Start_i_1)) + (portref tx_Start0) + ) + ) + ) + + (property ORIG_REF_NAME (string "cntr_incr_decr_addn_f")) + ) + ) + (cell axi_uart_dynshreg_f (celltype GENERIC) + (view dynshreg_f (viewtype NETLIST) + (interface + (port fifo_wr (direction INPUT)) + (port mux_Out (direction OUTPUT)) + (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) + (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) + (port p_4_in (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port (array (rename Q "Q[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance (rename INFERRED_GEN_data_reg_15__0__srl16 "INFERRED_GEN.data_reg[15][0]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__1__srl16 "INFERRED_GEN.data_reg[15][1]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__2__srl16 "INFERRED_GEN.data_reg[15][2]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__3__srl16 "INFERRED_GEN.data_reg[15][3]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__4__srl16 "INFERRED_GEN.data_reg[15][4]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__5__srl16 "INFERRED_GEN.data_reg[15][5]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__6__srl16 "INFERRED_GEN.data_reg[15][6]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16 "INFERRED_GEN.data_reg[15][7]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ")) + ) + (instance serial_Data_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance serial_Data_i_2 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h44400040")) + ) + (instance serial_Data_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h88800080")) + ) + (instance serial_Data_i_4 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h44400040")) + ) + (instance serial_Data_i_5 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h000A000C")) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 3)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 2)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref A2 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 1)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref A3 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 0)) + ) + ) + (net (rename fifo_DOut_0_ "fifo_DOut[0]") (joined + (portref I1 (instanceref serial_Data_i_5)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + ) + ) + (net (rename fifo_DOut_1_ "fifo_DOut[1]") (joined + (portref I2 (instanceref serial_Data_i_4)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + ) + ) + (net (rename fifo_DOut_2_ "fifo_DOut[2]") (joined + (portref I2 (instanceref serial_Data_i_2)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + ) + ) + (net (rename fifo_DOut_3_ "fifo_DOut[3]") (joined + (portref I4 (instanceref serial_Data_i_4)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + ) + ) + (net (rename fifo_DOut_4_ "fifo_DOut[4]") (joined + (portref I0 (instanceref serial_Data_i_5)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + ) + ) + (net (rename fifo_DOut_5_ "fifo_DOut[5]") (joined + (portref I2 (instanceref serial_Data_i_3)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + ) + ) + (net (rename fifo_DOut_6_ "fifo_DOut[6]") (joined + (portref I4 (instanceref serial_Data_i_2)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + ) + ) + (net (rename fifo_DOut_7_ "fifo_DOut[7]") (joined + (portref I4 (instanceref serial_Data_i_3)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + ) + ) + (net fifo_wr (joined + (portref CE (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref O (instanceref serial_Data_i_1)) + (portref mux_Out) + ) + ) + (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined + (portref I0 (instanceref serial_Data_i_3)) + (portref I0 (instanceref serial_Data_i_4)) + (portref I3 (instanceref serial_Data_i_2)) + (portref I4 (instanceref serial_Data_i_5)) + (portref mux_sel_reg_0_) + ) + ) + (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined + (portref I0 (instanceref serial_Data_i_2)) + (portref I1 (instanceref serial_Data_i_3)) + (portref I1 (instanceref serial_Data_i_4)) + (portref I3 (instanceref serial_Data_i_5)) + (portref mux_sel_reg_2_) + ) + ) + (net p_4_in (joined + (portref I1 (instanceref serial_Data_i_2)) + (portref I2 (instanceref serial_Data_i_5)) + (portref I3 (instanceref serial_Data_i_3)) + (portref I3 (instanceref serial_Data_i_4)) + (portref p_4_in) + ) + ) + (net s_axi_aclk (joined + (portref CLK (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref (member s_axi_wdata 0)) + ) + ) + (net serial_Data_i_2_n_0 (joined + (portref I0 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_2)) + ) + ) + (net serial_Data_i_3_n_0 (joined + (portref I1 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_3)) + ) + ) + (net serial_Data_i_4_n_0 (joined + (portref I2 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_4)) + ) + ) + (net serial_Data_i_5_n_0 (joined + (portref I3 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_5)) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_f")) + ) + ) + (cell axi_uart_srl_fifo_rbu_f (celltype GENERIC) + (view srl_fifo_rbu_f (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port fifo_Read (direction INPUT)) + (port fifo_wr (direction INPUT)) + (port mux_Out (direction OUTPUT)) + (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) + (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) + (port p_4_in (direction INPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port tx_DataBits (direction INPUT)) + (port tx_Data_Enable_reg (direction INPUT)) + (port tx_Start (direction INPUT)) + (port tx_Start0 (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance CNTR_INCR_DECR_ADDN_F_I (viewref cntr_incr_decr_addn_f (cellref axi_uart_cntr_incr_decr_addn_f (libraryref work_library0_1)))) + (instance DYNSHREG_F_I (viewref dynshreg_f (cellref axi_uart_dynshreg_f (libraryref work_library0_1)))) + (instance FIFO_Full_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (net (rename &_const1_ "") (joined + (portref CE (instanceref FIFO_Full_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Bus_RNW_reg) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_2 (joined + (portref (member Q 1) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 0) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_3 (joined + (portref (member Q 2) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 1) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_4 (joined + (portref (member Q 3) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 2) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_5 (joined + (portref (member Q 4) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 3) (instanceref DYNSHREG_F_I)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref (member Q 0) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Q_0_) + ) + ) + (net TX_FIFO_Reset (joined + (portref R (instanceref FIFO_Full_reg)) + (portref SS_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net fifo_Read (joined + (portref fifo_Read (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref fifo_Read) + ) + ) + (net fifo_full_p1 (joined + (portref D (instanceref FIFO_Full_reg)) + (portref fifo_full_p1 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref DYNSHREG_F_I)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref mux_Out (instanceref DYNSHREG_F_I)) + (portref mux_Out) + ) + ) + (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined + (portref mux_sel_reg_0_ (instanceref DYNSHREG_F_I)) + (portref mux_sel_reg_0_) + ) + ) + (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined + (portref mux_sel_reg_2_ (instanceref DYNSHREG_F_I)) + (portref mux_sel_reg_2_) + ) + ) + (net p_4_in (joined + (portref p_4_in (instanceref DYNSHREG_F_I)) + (portref p_4_in) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref reset_TX_FIFO_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref FIFO_Full_reg)) + (portref s_axi_aclk (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aclk (instanceref DYNSHREG_F_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 0)) + ) + ) + (net tx_Buffer_Full (joined + (portref Q (instanceref FIFO_Full_reg)) + (portref tx_Buffer_Full (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref tx_DataBits (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_DataBits) + ) + ) + (net tx_Data_Enable_reg (joined + (portref tx_Data_Enable_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Start (joined + (portref tx_Start (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Start) + ) + ) + (net tx_Start0 (joined + (portref tx_Start0 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Start0) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_rbu_f")) + ) + ) + (cell axi_uart_srl_fifo_f (celltype GENERIC) + (view srl_fifo_f (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port fifo_Read (direction INPUT)) + (port fifo_wr (direction INPUT)) + (port mux_Out (direction OUTPUT)) + (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) + (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) + (port p_4_in (direction INPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port tx_DataBits (direction INPUT)) + (port tx_Data_Enable_reg (direction INPUT)) + (port tx_Start (direction INPUT)) + (port tx_Start0 (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance I_SRL_FIFO_RBU_F (viewref srl_fifo_rbu_f (cellref axi_uart_srl_fifo_rbu_f (libraryref work_library0_1)))) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref Bus_RNW_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref Q_0_) + ) + ) + (net fifo_Read (joined + (portref fifo_Read (instanceref I_SRL_FIFO_RBU_F)) + (portref fifo_Read) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref I_SRL_FIFO_RBU_F)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref mux_Out (instanceref I_SRL_FIFO_RBU_F)) + (portref mux_Out) + ) + ) + (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined + (portref mux_sel_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref mux_sel_reg_0_) + ) + ) + (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined + (portref mux_sel_reg_2_ (instanceref I_SRL_FIFO_RBU_F)) + (portref mux_sel_reg_2_) + ) + ) + (net p_4_in (joined + (portref p_4_in (instanceref I_SRL_FIFO_RBU_F)) + (portref p_4_in) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref reset_TX_FIFO_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 0)) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref tx_DataBits (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_DataBits) + ) + ) + (net tx_Data_Enable_reg (joined + (portref tx_Data_Enable_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Start (joined + (portref tx_Start (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Start) + ) + ) + (net tx_Start0 (joined + (portref tx_Start0 (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Start0) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_f")) + ) + ) + (cell axi_uart_uartlite_tx (celltype GENERIC) + (view uartlite_tx (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port en_16x_Baud (direction INPUT)) + (port fifo_wr (direction INPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx (direction OUTPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (rename SR_0_ "SR[0]") (direction INPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance MID_START_BIT_SRL16_I (viewref dynshreg_i_f__parameterized0 (cellref axi_uart_dynshreg_i_f__parameterized0 (libraryref work_library0_1)))) + (instance SRL_FIFO_I (viewref srl_fifo_f (cellref axi_uart_srl_fifo_f (libraryref work_library0_1)))) + (instance TX_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h31")) + ) + (instance TX_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance fifo_Read_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0100")) + ) + (instance fifo_Read_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename mux_sel_0__i_1 "mux_sel[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hE1F0F1F0")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename mux_sel_1__i_1 "mux_sel[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h99AAABAA")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename mux_sel_2__i_1 "mux_sel[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h7777888C")) + ) + (instance (rename mux_sel_reg_0_ "mux_sel_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename mux_sel_reg_1_ "mux_sel_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename mux_sel_reg_2_ "mux_sel_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance serial_Data_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_DataBits_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0F08")) + ) + (instance tx_DataBits_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_Data_Enable_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_Start_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref TX_reg)) + (portref CE (instanceref fifo_Read_reg)) + (portref CE (instanceref mux_sel_reg_0_)) + (portref CE (instanceref mux_sel_reg_1_)) + (portref CE (instanceref mux_sel_reg_2_)) + (portref CE (instanceref serial_Data_reg)) + (portref CE (instanceref tx_DataBits_reg)) + (portref CE (instanceref tx_Data_Enable_reg)) + (portref CE (instanceref tx_Start_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref SRL_FIFO_I)) + (portref Bus_RNW_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net MID_START_BIT_SRL16_I_n_0 (joined + (portref D (instanceref tx_Data_Enable_reg)) + (portref tx_Data_Enable_reg (instanceref MID_START_BIT_SRL16_I)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref SRL_FIFO_I)) + (portref Q_0_) + ) + ) + (net (rename SR_0_ "SR[0]") (joined + (portref R (instanceref fifo_Read_reg)) + (portref R (instanceref serial_Data_reg)) + (portref R (instanceref tx_DataBits_reg)) + (portref R (instanceref tx_Data_Enable_reg)) + (portref R (instanceref tx_Start_reg)) + (portref S (instanceref TX_reg)) + (portref S (instanceref mux_sel_reg_0_)) + (portref S (instanceref mux_sel_reg_1_)) + (portref S (instanceref mux_sel_reg_2_)) + (portref SR_0_) + ) + ) + (net TX0 (joined + (portref D (instanceref TX_reg)) + (portref O (instanceref TX_i_1)) + ) + ) + (net en_16x_Baud (joined + (portref en_16x_Baud (instanceref MID_START_BIT_SRL16_I)) + (portref en_16x_Baud) + ) + ) + (net fifo_Read (joined + (portref I2 (instanceref tx_DataBits_i_1)) + (portref Q (instanceref fifo_Read_reg)) + (portref fifo_Read (instanceref SRL_FIFO_I)) + ) + ) + (net fifo_Read0 (joined + (portref D (instanceref fifo_Read_reg)) + (portref O (instanceref fifo_Read_i_1)) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref SRL_FIFO_I)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref D (instanceref serial_Data_reg)) + (portref mux_Out (instanceref SRL_FIFO_I)) + ) + ) + (net (rename mux_sel_0__i_1_n_0 "mux_sel[0]_i_1_n_0") (joined + (portref D (instanceref mux_sel_reg_0_)) + (portref O (instanceref mux_sel_0__i_1)) + ) + ) + (net (rename mux_sel_1__i_1_n_0 "mux_sel[1]_i_1_n_0") (joined + (portref D (instanceref mux_sel_reg_1_)) + (portref O (instanceref mux_sel_1__i_1)) + ) + ) + (net (rename mux_sel_2__i_1_n_0 "mux_sel[2]_i_1_n_0") (joined + (portref D (instanceref mux_sel_reg_2_)) + (portref O (instanceref mux_sel_2__i_1)) + ) + ) + (net (rename mux_sel_reg_n_0__0_ "mux_sel_reg_n_0_[0]") (joined + (portref I0 (instanceref fifo_Read_i_1)) + (portref I2 (instanceref mux_sel_0__i_1)) + (portref I2 (instanceref mux_sel_1__i_1)) + (portref I2 (instanceref mux_sel_2__i_1)) + (portref Q (instanceref mux_sel_reg_0_)) + (portref mux_sel_reg_0_ (instanceref SRL_FIFO_I)) + ) + ) + (net (rename mux_sel_reg_n_0__2_ "mux_sel_reg_n_0_[2]") (joined + (portref I1 (instanceref fifo_Read_i_1)) + (portref I1 (instanceref mux_sel_0__i_1)) + (portref I1 (instanceref mux_sel_1__i_1)) + (portref I4 (instanceref mux_sel_2__i_1)) + (portref Q (instanceref mux_sel_reg_2_)) + (portref mux_sel_reg_2_ (instanceref SRL_FIFO_I)) + ) + ) + (net p_4_in (joined + (portref I0 (instanceref mux_sel_0__i_1)) + (portref I0 (instanceref mux_sel_1__i_1)) + (portref I2 (instanceref fifo_Read_i_1)) + (portref I3 (instanceref mux_sel_2__i_1)) + (portref Q (instanceref mux_sel_reg_1_)) + (portref p_4_in (instanceref SRL_FIFO_I)) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref reset_TX_FIFO_reg (instanceref SRL_FIFO_I)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref TX_reg)) + (portref C (instanceref fifo_Read_reg)) + (portref C (instanceref mux_sel_reg_0_)) + (portref C (instanceref mux_sel_reg_1_)) + (portref C (instanceref mux_sel_reg_2_)) + (portref C (instanceref serial_Data_reg)) + (portref C (instanceref tx_DataBits_reg)) + (portref C (instanceref tx_Data_Enable_reg)) + (portref C (instanceref tx_Start_reg)) + (portref s_axi_aclk (instanceref MID_START_BIT_SRL16_I)) + (portref s_axi_aclk (instanceref SRL_FIFO_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref SRL_FIFO_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 0)) + ) + ) + (net serial_Data (joined + (portref I2 (instanceref TX_i_1)) + (portref Q (instanceref serial_Data_reg)) + ) + ) + (net tx (joined + (portref Q (instanceref TX_reg)) + (portref tx) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref SRL_FIFO_I)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref I0 (instanceref TX_i_1)) + (portref I0 (instanceref mux_sel_2__i_1)) + (portref I3 (instanceref tx_DataBits_i_1)) + (portref I4 (instanceref mux_sel_0__i_1)) + (portref I4 (instanceref mux_sel_1__i_1)) + (portref Q (instanceref tx_DataBits_reg)) + (portref tx_DataBits (instanceref SRL_FIFO_I)) + ) + ) + (net tx_DataBits0 (joined + (portref D (instanceref tx_DataBits_reg)) + (portref O (instanceref tx_DataBits_i_1)) + ) + ) + (net tx_Data_Enable_reg_n_0 (joined + (portref I1 (instanceref mux_sel_2__i_1)) + (portref I1 (instanceref tx_DataBits_i_1)) + (portref I3 (instanceref fifo_Read_i_1)) + (portref I3 (instanceref mux_sel_0__i_1)) + (portref I3 (instanceref mux_sel_1__i_1)) + (portref Q (instanceref tx_Data_Enable_reg)) + (portref tx_Data_Enable_reg (instanceref SRL_FIFO_I)) + (portref tx_Data_Enable_reg_0 (instanceref MID_START_BIT_SRL16_I)) + ) + ) + (net tx_Start (joined + (portref I0 (instanceref tx_DataBits_i_1)) + (portref I1 (instanceref TX_i_1)) + (portref Q (instanceref tx_Start_reg)) + (portref tx_Start (instanceref SRL_FIFO_I)) + ) + ) + (net tx_Start0 (joined + (portref D (instanceref tx_Start_reg)) + (portref tx_Start0 (instanceref SRL_FIFO_I)) + ) + ) + ) + + (property ORIG_REF_NAME (string "uartlite_tx")) + ) + ) + (cell axi_uart_uartlite_core (celltype GENERIC) + (view uartlite_core (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0 "INFERRED_GEN.cnt_i_reg[4]_0") (direction INPUT)) + (port bus2ip_reset (direction OUTPUT)) + (port enable_interrupts (direction OUTPUT)) + (port fifo_wr (direction INPUT)) + (port interrupt (direction OUTPUT)) + (port reset_RX_FIFO (direction INPUT)) + (port reset_TX_FIFO (direction INPUT)) + (port rx (direction INPUT)) + (port rx_Buffer_Full (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx (direction OUTPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0_ "INFERRED_GEN.cnt_i_reg[2][0]") (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction OUTPUT)) + ) + (contents + (instance BAUD_RATE_I (viewref baudrate (cellref axi_uart_baudrate (libraryref work_library0_1)))) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance Interrupt_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance UARTLITE_RX_I (viewref uartlite_rx (cellref axi_uart_uartlite_rx (libraryref work_library0_1)))) + (instance UARTLITE_TX_I (viewref uartlite_tx (cellref axi_uart_uartlite_tx (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance clr_Status_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance enable_interrupts_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance reset_RX_FIFO_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance reset_TX_FIFO_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance rx_Data_Present_Pre_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename status_reg_reg_1_ "status_reg_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename status_reg_reg_2_ "status_reg_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_Buffer_Empty_Pre_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref rx_Data_Present_Pre_reg)) + (portref R (instanceref status_reg_reg_1_)) + (portref R (instanceref status_reg_reg_2_)) + (portref R (instanceref tx_Buffer_Empty_Pre_reg)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref Interrupt_reg)) + (portref CE (instanceref clr_Status_reg)) + (portref CE (instanceref enable_interrupts_reg)) + (portref CE (instanceref reset_RX_FIFO_reg)) + (portref CE (instanceref reset_TX_FIFO_reg)) + (portref CE (instanceref rx_Data_Present_Pre_reg)) + (portref CE (instanceref status_reg_reg_1_)) + (portref CE (instanceref status_reg_reg_2_)) + (portref CE (instanceref tx_Buffer_Empty_Pre_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref UARTLITE_RX_I)) + (portref Bus_RNW_reg (instanceref UARTLITE_TX_I)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref UARTLITE_RX_I)) + (portref Bus_RNW_reg_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref UARTLITE_RX_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref UARTLITE_RX_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref UARTLITE_TX_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref UARTLITE_TX_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (joined + (portref D (instanceref enable_interrupts_reg)) + (portref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0_ "INFERRED_GEN.cnt_i_reg[2][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref UARTLITE_RX_I)) + (portref Q_0_ (instanceref UARTLITE_TX_I)) + (portref INFERRED_GEN_cnt_i_reg_2__0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (joined + (portref D (instanceref tx_Buffer_Empty_Pre_reg)) + (portref INFERRED_GEN_cnt_i_reg_4_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0 "INFERRED_GEN.cnt_i_reg[4]_0") (joined + (portref D (instanceref rx_Data_Present_Pre_reg)) + (portref INFERRED_GEN_cnt_i_reg_4__0) + ) + ) + (net Interrupt0 (joined + (portref D (instanceref Interrupt_reg)) + (portref Interrupt0 (instanceref UARTLITE_RX_I)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref UARTLITE_RX_I)) + (portref Q_0_) + ) + ) + (net UARTLITE_RX_I_n_4 (joined + (portref D (instanceref status_reg_reg_2_)) + (portref status_reg_reg_2__0 (instanceref UARTLITE_RX_I)) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref D (instanceref clr_Status_reg)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_reset (joined + (portref R (instanceref Interrupt_reg)) + (portref R (instanceref clr_Status_reg)) + (portref R (instanceref enable_interrupts_reg)) + (portref S (instanceref reset_RX_FIFO_reg)) + (portref S (instanceref reset_TX_FIFO_reg)) + (portref SR_0_ (instanceref BAUD_RATE_I)) + (portref SR_0_ (instanceref UARTLITE_RX_I)) + (portref SR_0_ (instanceref UARTLITE_TX_I)) + (portref bus2ip_reset) + ) + ) + (net clr_Status (joined + (portref Q (instanceref clr_Status_reg)) + (portref clr_Status (instanceref UARTLITE_RX_I)) + ) + ) + (net en_16x_Baud (joined + (portref en_16x_Baud (instanceref BAUD_RATE_I)) + (portref en_16x_Baud (instanceref UARTLITE_RX_I)) + (portref en_16x_Baud (instanceref UARTLITE_TX_I)) + ) + ) + (net enable_interrupts (joined + (portref Q (instanceref enable_interrupts_reg)) + (portref enable_interrupts (instanceref UARTLITE_RX_I)) + (portref enable_interrupts) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref UARTLITE_TX_I)) + (portref fifo_wr) + ) + ) + (net interrupt (joined + (portref Q (instanceref Interrupt_reg)) + (portref interrupt) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref UARTLITE_RX_I)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref UARTLITE_RX_I)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref UARTLITE_RX_I)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref UARTLITE_RX_I)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref UARTLITE_RX_I)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref UARTLITE_RX_I)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref UARTLITE_RX_I)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref UARTLITE_RX_I)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref D (instanceref reset_RX_FIFO_reg)) + (portref reset_RX_FIFO) + ) + ) + (net reset_RX_FIFO_reg_n_0 (joined + (portref Q (instanceref reset_RX_FIFO_reg)) + (portref reset_RX_FIFO_reg (instanceref UARTLITE_RX_I)) + ) + ) + (net reset_TX_FIFO (joined + (portref D (instanceref reset_TX_FIFO_reg)) + (portref reset_TX_FIFO) + ) + ) + (net reset_TX_FIFO_reg_n_0 (joined + (portref Q (instanceref reset_TX_FIFO_reg)) + (portref reset_TX_FIFO_reg (instanceref UARTLITE_TX_I)) + ) + ) + (net rx (joined + (portref rx (instanceref UARTLITE_RX_I)) + (portref rx) + ) + ) + (net rx_Buffer_Full (joined + (portref status_reg_reg_2_ (instanceref UARTLITE_RX_I)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre (joined + (portref Q (instanceref rx_Data_Present_Pre_reg)) + (portref rx_Data_Present_Pre (instanceref UARTLITE_RX_I)) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref Interrupt_reg)) + (portref C (instanceref clr_Status_reg)) + (portref C (instanceref enable_interrupts_reg)) + (portref C (instanceref reset_RX_FIFO_reg)) + (portref C (instanceref reset_TX_FIFO_reg)) + (portref C (instanceref rx_Data_Present_Pre_reg)) + (portref C (instanceref status_reg_reg_1_)) + (portref C (instanceref status_reg_reg_2_)) + (portref C (instanceref tx_Buffer_Empty_Pre_reg)) + (portref s_axi_aclk (instanceref BAUD_RATE_I)) + (portref s_axi_aclk (instanceref UARTLITE_RX_I)) + (portref s_axi_aclk (instanceref UARTLITE_TX_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref UARTLITE_RX_I)) + (portref s_axi_aresetn (instanceref UARTLITE_TX_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 0)) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref Q (instanceref status_reg_reg_2_)) + (portref (member status_reg 1) (instanceref UARTLITE_RX_I)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref Q (instanceref status_reg_reg_1_)) + (portref (member status_reg 0) (instanceref UARTLITE_RX_I)) + (portref (member status_reg 0)) + ) + ) + (net status_reg_reg0 (joined + (portref D (instanceref status_reg_reg_1_)) + (portref status_reg_reg0 (instanceref UARTLITE_RX_I)) + ) + ) + (net tx (joined + (portref tx (instanceref UARTLITE_TX_I)) + (portref tx) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref Q (instanceref tx_Buffer_Empty_Pre_reg)) + (portref tx_Buffer_Empty_Pre (instanceref UARTLITE_RX_I)) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref UARTLITE_TX_I)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "uartlite_core")) + ) + ) + (cell axi_uart_axi_uartlite (celltype GENERIC) + (view axi_uartlite (viewtype NETLIST) + (interface + (port interrupt (direction OUTPUT)) + (port rx (direction INPUT)) + (port s_axi_aclk (direction INPUT) + (property max_fanout (string "10000")) + ) + (port s_axi_aresetn (direction INPUT) + (property max_fanout (string "10000")) + ) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_awvalid (direction INPUT)) + (port s_axi_bready (direction INPUT)) + (port s_axi_bvalid (direction OUTPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid (direction OUTPUT)) + (port s_axi_wready (direction OUTPUT)) + (port s_axi_wvalid (direction INPUT)) + (port tx (direction OUTPUT)) + (port (array (rename s_axi_araddr "s_axi_araddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_bresp "s_axi_bresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[31:0]") 32) (direction OUTPUT)) + (port (array (rename s_axi_rresp "s_axi_rresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[31:0]") 32) (direction INPUT)) + (port (array (rename s_axi_wstrb "s_axi_wstrb[3:0]") 4) (direction INPUT)) + ) + (contents + (instance AXI_LITE_IPIF_I (viewref axi_lite_ipif (cellref axi_uart_axi_lite_ipif (libraryref work_library0_1)))) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance UARTLITE_CORE_I (viewref uartlite_core (cellref axi_uart_uartlite_core (libraryref work_library0_1)))) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref (member s_axi_bresp 1)) + (portref (member s_axi_rdata 21)) + (portref (member s_axi_rdata 20)) + (portref (member s_axi_rdata 19)) + (portref (member s_axi_rdata 18)) + (portref (member s_axi_rdata 17)) + (portref (member s_axi_rdata 16)) + (portref (member s_axi_rdata 15)) + (portref (member s_axi_rdata 14)) + (portref (member s_axi_rdata 13)) + (portref (member s_axi_rdata 12)) + (portref (member s_axi_rdata 11)) + (portref (member s_axi_rdata 10)) + (portref (member s_axi_rdata 9)) + (portref (member s_axi_rdata 8)) + (portref (member s_axi_rdata 7)) + (portref (member s_axi_rdata 6)) + (portref (member s_axi_rdata 5)) + (portref (member s_axi_rdata 4)) + (portref (member s_axi_rdata 3)) + (portref (member s_axi_rdata 2)) + (portref (member s_axi_rdata 1)) + (portref (member s_axi_rdata 0)) + (portref (member s_axi_rdata 23)) + (portref (member s_axi_rdata 22)) + (portref (member s_axi_rresp 1)) + ) + ) + (net AXI_LITE_IPIF_I_n_11 (joined + (portref Bus_RNW_reg_reg (instanceref UARTLITE_CORE_I)) + (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_12 (joined + (portref INFERRED_GEN_cnt_i_reg_4__0 (instanceref UARTLITE_CORE_I)) + (portref rx_Data_Present_Pre_reg (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_13 (joined + (portref FIFO_Full_reg (instanceref AXI_LITE_IPIF_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref UARTLITE_CORE_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_16 (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref UARTLITE_CORE_I)) + (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_17 (joined + (portref INFERRED_GEN_cnt_i_reg_4_ (instanceref UARTLITE_CORE_I)) + (portref tx_Buffer_Empty_Pre_reg (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_18 (joined + (portref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ (instanceref UARTLITE_CORE_I)) + (portref enable_interrupts_reg (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net (rename I_SLAVE_ATTACHMENT_I_DECODER_Bus_RNW_reg "I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg") (joined + (portref Bus_RNW_reg (instanceref AXI_LITE_IPIF_I)) + (portref Bus_RNW_reg (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename I_SLAVE_ATTACHMENT_I_DECODER_GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref AXI_LITE_IPIF_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename I_SLAVE_ATTACHMENT_I_DECODER_GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref AXI_LITE_IPIF_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename UARTLITE_RX_I_rx_Data_Empty "UARTLITE_RX_I/rx_Data_Empty") (joined + (portref Q_0_ (instanceref AXI_LITE_IPIF_I)) + (portref Q_0_ (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename UARTLITE_TX_I_fifo_wr "UARTLITE_TX_I/fifo_wr") (joined + (portref fifo_wr (instanceref AXI_LITE_IPIF_I)) + (portref fifo_wr (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename bus2ip_rdce_1_ "bus2ip_rdce[1]") (joined + (portref bus2ip_rdce_0_ (instanceref AXI_LITE_IPIF_I)) + (portref bus2ip_rdce_0_ (instanceref UARTLITE_CORE_I)) + ) + ) + (net bus2ip_reset (joined + (portref bus2ip_reset (instanceref AXI_LITE_IPIF_I)) + (portref bus2ip_reset (instanceref UARTLITE_CORE_I)) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref AXI_LITE_IPIF_I)) + (portref enable_interrupts (instanceref UARTLITE_CORE_I)) + ) + ) + (net interrupt (joined + (portref interrupt (instanceref UARTLITE_CORE_I)) + (portref interrupt) + ) + ) + (net reset_RX_FIFO (joined + (portref reset_RX_FIFO (instanceref AXI_LITE_IPIF_I)) + (portref reset_RX_FIFO (instanceref UARTLITE_CORE_I)) + ) + ) + (net reset_TX_FIFO (joined + (portref reset_TX_FIFO (instanceref AXI_LITE_IPIF_I)) + (portref reset_TX_FIFO (instanceref UARTLITE_CORE_I)) + ) + ) + (net rx (joined + (portref rx (instanceref UARTLITE_CORE_I)) + (portref rx) + ) + ) + (net rx_Buffer_Full (joined + (portref rx_Buffer_Full (instanceref AXI_LITE_IPIF_I)) + (portref rx_Buffer_Full (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_0_ "rx_Data[0]") (joined + (portref (member out 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 0) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_1_ "rx_Data[1]") (joined + (portref (member out 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 1) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_2_ "rx_Data[2]") (joined + (portref (member out 2) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 2) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_3_ "rx_Data[3]") (joined + (portref (member out 3) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 3) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_4_ "rx_Data[4]") (joined + (portref (member out 4) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 4) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_5_ "rx_Data[5]") (joined + (portref (member out 5) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 5) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_6_ "rx_Data[6]") (joined + (portref (member out 6) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 6) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_7_ "rx_Data[7]") (joined + (portref (member out 7) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 7) (instanceref UARTLITE_CORE_I)) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_aclk (instanceref UARTLITE_CORE_I)) + (portref s_axi_aclk) + ) + + (property RTL_MAX_FANOUT (string "found")) + (property MAX_FANOUT (string "10000")) + ) + (net (rename s_axi_araddr_2_ "s_axi_araddr[2]") (joined + (portref (member s_axi_araddr 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_3_ "s_axi_araddr[3]") (joined + (portref (member s_axi_araddr 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_aresetn (instanceref UARTLITE_CORE_I)) + (portref s_axi_aresetn) + ) + + (property RTL_MAX_FANOUT (string "found")) + (property MAX_FANOUT (string "10000")) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref s_axi_arvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_2_ "s_axi_awaddr[2]") (joined + (portref (member s_axi_awaddr 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_3_ "s_axi_awaddr[3]") (joined + (portref (member s_axi_awaddr 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_awready) + (portref s_axi_wready) + ) + ) + (net s_axi_awvalid (joined + (portref s_axi_awvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref s_axi_bready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_1_ "s_axi_bresp[1]") (joined + (portref s_axi_bresp_0_ (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_bresp 0)) + ) + ) + (net s_axi_bvalid (joined + (portref s_axi_bvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref (member s_axi_rdata 7) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 31)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref (member s_axi_rdata 6) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 30)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref (member s_axi_rdata 5) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 29)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref (member s_axi_rdata 4) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 28)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref (member s_axi_rdata 3) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 27)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref (member s_axi_rdata 2) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 26)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref (member s_axi_rdata 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 25)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref (member s_axi_rdata 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 24)) + ) + ) + (net s_axi_rready (joined + (portref s_axi_rready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_1_ "s_axi_rresp[1]") (joined + (portref s_axi_rresp_0_ (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rresp 0)) + ) + ) + (net s_axi_rvalid (joined + (portref s_axi_rvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 2) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_wdata 7) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 31)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_wdata 6) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 30)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 29)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 28)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_wdata 3) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 27)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 26)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 25)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 24)) + ) + ) + (net s_axi_wvalid (joined + (portref s_axi_wvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_wvalid) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref (member status_reg 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member status_reg 0) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename status_reg_2_ "status_reg[2]") (joined + (portref (member status_reg 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member status_reg 1) (instanceref UARTLITE_CORE_I)) + ) + ) + (net tx (joined + (portref tx (instanceref UARTLITE_CORE_I)) + (portref tx) + ) + ) + (net tx_Buffer_Empty (joined + (portref INFERRED_GEN_cnt_i_reg_2__0_ (instanceref UARTLITE_CORE_I)) + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref AXI_LITE_IPIF_I)) + (portref tx_Buffer_Full (instanceref UARTLITE_CORE_I)) + ) + ) + ) + + (property C_FAMILY (string "artix7")) + (property C_S_AXI_ACLK_FREQ_HZ (integer 10000000)) + (property C_S_AXI_ADDR_WIDTH (integer 4)) + (property C_S_AXI_DATA_WIDTH (integer 32)) + (property C_BAUDRATE (integer 128000)) + (property C_DATA_BITS (integer 8)) + (property C_USE_PARITY (integer 0)) + (property C_ODD_PARITY (integer 0)) + (property downgradeipidentifiedwarnings (string "yes")) + (property ORIG_REF_NAME (string "axi_uartlite")) + ) + ) + (cell axi_uart (celltype GENERIC) + (view axi_uart (viewtype NETLIST) + (interface + (port interrupt (direction OUTPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME INTERRUPT, SENSITIVITY EDGE_RISING, PortWidth 1")) + (property x_interface_info (string "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT")) + ) + (port rx (direction INPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UARTLITE_BOARD_INTERFACE")) + (property x_interface_info (string "xilinx.com:interface:uart:1.0 UART RxD")) + ) + (port s_axi_aclk (direction INPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000")) + (property x_interface_info (string "xilinx.com:signal:clock:1.0 ACLK CLK")) + ) + (port s_axi_aresetn (direction INPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW")) + (property x_interface_info (string "xilinx.com:signal:reset:1.0 ARESETN RST")) + ) + (port s_axi_arready (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI ARREADY")) + ) + (port s_axi_arvalid (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI ARVALID")) + ) + (port s_axi_awready (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI AWREADY")) + ) + (port s_axi_awvalid (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI AWVALID")) + ) + (port s_axi_bready (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI BREADY")) + ) + (port s_axi_bvalid (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI BVALID")) + ) + (port s_axi_rready (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI RREADY")) + ) + (port s_axi_rvalid (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI RVALID")) + ) + (port s_axi_wready (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI WREADY")) + ) + (port s_axi_wvalid (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI WVALID")) + ) + (port tx (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:uart:1.0 UART TxD")) + ) + (port (array (rename s_axi_araddr "s_axi_araddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_bresp "s_axi_bresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[31:0]") 32) (direction OUTPUT)) + (port (array (rename s_axi_rresp "s_axi_rresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[31:0]") 32) (direction INPUT)) + (port (array (rename s_axi_wstrb "s_axi_wstrb[3:0]") 4) (direction INPUT)) + ) + (contents + (instance U0 (viewref axi_uartlite (cellref axi_uart_axi_uartlite (libraryref work_library0_1))) + (property C_BAUDRATE (integer 128000)) + (property C_DATA_BITS (integer 8)) + (property C_FAMILY (string "artix7")) + (property C_ODD_PARITY (integer 0)) + (property C_S_AXI_ACLK_FREQ_HZ (integer 10000000)) + (property C_S_AXI_ADDR_WIDTH (integer 4)) + (property C_S_AXI_DATA_WIDTH (integer 32)) + (property C_USE_PARITY (integer 0)) + (property downgradeipidentifiedwarnings (string "yes")) + ) + (net interrupt (joined + (portref interrupt (instanceref U0)) + (portref interrupt) + ) + ) + (net rx (joined + (portref rx (instanceref U0)) + (portref rx) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref U0)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined + (portref (member s_axi_araddr 3) (instanceref U0)) + (portref (member s_axi_araddr 3)) + ) + ) + (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined + (portref (member s_axi_araddr 2) (instanceref U0)) + (portref (member s_axi_araddr 2)) + ) + ) + (net (rename s_axi_araddr_2_ "s_axi_araddr[2]") (joined + (portref (member s_axi_araddr 1) (instanceref U0)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_3_ "s_axi_araddr[3]") (joined + (portref (member s_axi_araddr 0) (instanceref U0)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref U0)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref U0)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref s_axi_arvalid (instanceref U0)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined + (portref (member s_axi_awaddr 3) (instanceref U0)) + (portref (member s_axi_awaddr 3)) + ) + ) + (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined + (portref (member s_axi_awaddr 2) (instanceref U0)) + (portref (member s_axi_awaddr 2)) + ) + ) + (net (rename s_axi_awaddr_2_ "s_axi_awaddr[2]") (joined + (portref (member s_axi_awaddr 1) (instanceref U0)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_3_ "s_axi_awaddr[3]") (joined + (portref (member s_axi_awaddr 0) (instanceref U0)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref U0)) + (portref s_axi_awready) + ) + ) + (net s_axi_awvalid (joined + (portref s_axi_awvalid (instanceref U0)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref s_axi_bready (instanceref U0)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref (member s_axi_bresp 1) (instanceref U0)) + (portref (member s_axi_bresp 1)) + ) + ) + (net (rename s_axi_bresp_1_ "s_axi_bresp[1]") (joined + (portref (member s_axi_bresp 0) (instanceref U0)) + (portref (member s_axi_bresp 0)) + ) + ) + (net s_axi_bvalid (joined + (portref s_axi_bvalid (instanceref U0)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref (member s_axi_rdata 31) (instanceref U0)) + (portref (member s_axi_rdata 31)) + ) + ) + (net (rename s_axi_rdata_10_ "s_axi_rdata[10]") (joined + (portref (member s_axi_rdata 21) (instanceref U0)) + (portref (member s_axi_rdata 21)) + ) + ) + (net (rename s_axi_rdata_11_ "s_axi_rdata[11]") (joined + (portref (member s_axi_rdata 20) (instanceref U0)) + (portref (member s_axi_rdata 20)) + ) + ) + (net (rename s_axi_rdata_12_ "s_axi_rdata[12]") (joined + (portref (member s_axi_rdata 19) (instanceref U0)) + (portref (member s_axi_rdata 19)) + ) + ) + (net (rename s_axi_rdata_13_ "s_axi_rdata[13]") (joined + (portref (member s_axi_rdata 18) (instanceref U0)) + (portref (member s_axi_rdata 18)) + ) + ) + (net (rename s_axi_rdata_14_ "s_axi_rdata[14]") (joined + (portref (member s_axi_rdata 17) (instanceref U0)) + (portref (member s_axi_rdata 17)) + ) + ) + (net (rename s_axi_rdata_15_ "s_axi_rdata[15]") (joined + (portref (member s_axi_rdata 16) (instanceref U0)) + (portref (member s_axi_rdata 16)) + ) + ) + (net (rename s_axi_rdata_16_ "s_axi_rdata[16]") (joined + (portref (member s_axi_rdata 15) (instanceref U0)) + (portref (member s_axi_rdata 15)) + ) + ) + (net (rename s_axi_rdata_17_ "s_axi_rdata[17]") (joined + (portref (member s_axi_rdata 14) (instanceref U0)) + (portref (member s_axi_rdata 14)) + ) + ) + (net (rename s_axi_rdata_18_ "s_axi_rdata[18]") (joined + (portref (member s_axi_rdata 13) (instanceref U0)) + (portref (member s_axi_rdata 13)) + ) + ) + (net (rename s_axi_rdata_19_ "s_axi_rdata[19]") (joined + (portref (member s_axi_rdata 12) (instanceref U0)) + (portref (member s_axi_rdata 12)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref (member s_axi_rdata 30) (instanceref U0)) + (portref (member s_axi_rdata 30)) + ) + ) + (net (rename s_axi_rdata_20_ "s_axi_rdata[20]") (joined + (portref (member s_axi_rdata 11) (instanceref U0)) + (portref (member s_axi_rdata 11)) + ) + ) + (net (rename s_axi_rdata_21_ "s_axi_rdata[21]") (joined + (portref (member s_axi_rdata 10) (instanceref U0)) + (portref (member s_axi_rdata 10)) + ) + ) + (net (rename s_axi_rdata_22_ "s_axi_rdata[22]") (joined + (portref (member s_axi_rdata 9) (instanceref U0)) + (portref (member s_axi_rdata 9)) + ) + ) + (net (rename s_axi_rdata_23_ "s_axi_rdata[23]") (joined + (portref (member s_axi_rdata 8) (instanceref U0)) + (portref (member s_axi_rdata 8)) + ) + ) + (net (rename s_axi_rdata_24_ "s_axi_rdata[24]") (joined + (portref (member s_axi_rdata 7) (instanceref U0)) + (portref (member s_axi_rdata 7)) + ) + ) + (net (rename s_axi_rdata_25_ "s_axi_rdata[25]") (joined + (portref (member s_axi_rdata 6) (instanceref U0)) + (portref (member s_axi_rdata 6)) + ) + ) + (net (rename s_axi_rdata_26_ "s_axi_rdata[26]") (joined + (portref (member s_axi_rdata 5) (instanceref U0)) + (portref (member s_axi_rdata 5)) + ) + ) + (net (rename s_axi_rdata_27_ "s_axi_rdata[27]") (joined + (portref (member s_axi_rdata 4) (instanceref U0)) + (portref (member s_axi_rdata 4)) + ) + ) + (net (rename s_axi_rdata_28_ "s_axi_rdata[28]") (joined + (portref (member s_axi_rdata 3) (instanceref U0)) + (portref (member s_axi_rdata 3)) + ) + ) + (net (rename s_axi_rdata_29_ "s_axi_rdata[29]") (joined + (portref (member s_axi_rdata 2) (instanceref U0)) + (portref (member s_axi_rdata 2)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref (member s_axi_rdata 29) (instanceref U0)) + (portref (member s_axi_rdata 29)) + ) + ) + (net (rename s_axi_rdata_30_ "s_axi_rdata[30]") (joined + (portref (member s_axi_rdata 1) (instanceref U0)) + (portref (member s_axi_rdata 1)) + ) + ) + (net (rename s_axi_rdata_31_ "s_axi_rdata[31]") (joined + (portref (member s_axi_rdata 0) (instanceref U0)) + (portref (member s_axi_rdata 0)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref (member s_axi_rdata 28) (instanceref U0)) + (portref (member s_axi_rdata 28)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref (member s_axi_rdata 27) (instanceref U0)) + (portref (member s_axi_rdata 27)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref (member s_axi_rdata 26) (instanceref U0)) + (portref (member s_axi_rdata 26)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref (member s_axi_rdata 25) (instanceref U0)) + (portref (member s_axi_rdata 25)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref (member s_axi_rdata 24) (instanceref U0)) + (portref (member s_axi_rdata 24)) + ) + ) + (net (rename s_axi_rdata_8_ "s_axi_rdata[8]") (joined + (portref (member s_axi_rdata 23) (instanceref U0)) + (portref (member s_axi_rdata 23)) + ) + ) + (net (rename s_axi_rdata_9_ "s_axi_rdata[9]") (joined + (portref (member s_axi_rdata 22) (instanceref U0)) + (portref (member s_axi_rdata 22)) + ) + ) + (net s_axi_rready (joined + (portref s_axi_rready (instanceref U0)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined + (portref (member s_axi_rresp 1) (instanceref U0)) + (portref (member s_axi_rresp 1)) + ) + ) + (net (rename s_axi_rresp_1_ "s_axi_rresp[1]") (joined + (portref (member s_axi_rresp 0) (instanceref U0)) + (portref (member s_axi_rresp 0)) + ) + ) + (net s_axi_rvalid (joined + (portref s_axi_rvalid (instanceref U0)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 31) (instanceref U0)) + (portref (member s_axi_wdata 31)) + ) + ) + (net (rename s_axi_wdata_10_ "s_axi_wdata[10]") (joined + (portref (member s_axi_wdata 21) (instanceref U0)) + (portref (member s_axi_wdata 21)) + ) + ) + (net (rename s_axi_wdata_11_ "s_axi_wdata[11]") (joined + (portref (member s_axi_wdata 20) (instanceref U0)) + (portref (member s_axi_wdata 20)) + ) + ) + (net (rename s_axi_wdata_12_ "s_axi_wdata[12]") (joined + (portref (member s_axi_wdata 19) (instanceref U0)) + (portref (member s_axi_wdata 19)) + ) + ) + (net (rename s_axi_wdata_13_ "s_axi_wdata[13]") (joined + (portref (member s_axi_wdata 18) (instanceref U0)) + (portref (member s_axi_wdata 18)) + ) + ) + (net (rename s_axi_wdata_14_ "s_axi_wdata[14]") (joined + (portref (member s_axi_wdata 17) (instanceref U0)) + (portref (member s_axi_wdata 17)) + ) + ) + (net (rename s_axi_wdata_15_ "s_axi_wdata[15]") (joined + (portref (member s_axi_wdata 16) (instanceref U0)) + (portref (member s_axi_wdata 16)) + ) + ) + (net (rename s_axi_wdata_16_ "s_axi_wdata[16]") (joined + (portref (member s_axi_wdata 15) (instanceref U0)) + (portref (member s_axi_wdata 15)) + ) + ) + (net (rename s_axi_wdata_17_ "s_axi_wdata[17]") (joined + (portref (member s_axi_wdata 14) (instanceref U0)) + (portref (member s_axi_wdata 14)) + ) + ) + (net (rename s_axi_wdata_18_ "s_axi_wdata[18]") (joined + (portref (member s_axi_wdata 13) (instanceref U0)) + (portref (member s_axi_wdata 13)) + ) + ) + (net (rename s_axi_wdata_19_ "s_axi_wdata[19]") (joined + (portref (member s_axi_wdata 12) (instanceref U0)) + (portref (member s_axi_wdata 12)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 30) (instanceref U0)) + (portref (member s_axi_wdata 30)) + ) + ) + (net (rename s_axi_wdata_20_ "s_axi_wdata[20]") (joined + (portref (member s_axi_wdata 11) (instanceref U0)) + (portref (member s_axi_wdata 11)) + ) + ) + (net (rename s_axi_wdata_21_ "s_axi_wdata[21]") (joined + (portref (member s_axi_wdata 10) (instanceref U0)) + (portref (member s_axi_wdata 10)) + ) + ) + (net (rename s_axi_wdata_22_ "s_axi_wdata[22]") (joined + (portref (member s_axi_wdata 9) (instanceref U0)) + (portref (member s_axi_wdata 9)) + ) + ) + (net (rename s_axi_wdata_23_ "s_axi_wdata[23]") (joined + (portref (member s_axi_wdata 8) (instanceref U0)) + (portref (member s_axi_wdata 8)) + ) + ) + (net (rename s_axi_wdata_24_ "s_axi_wdata[24]") (joined + (portref (member s_axi_wdata 7) (instanceref U0)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_25_ "s_axi_wdata[25]") (joined + (portref (member s_axi_wdata 6) (instanceref U0)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_26_ "s_axi_wdata[26]") (joined + (portref (member s_axi_wdata 5) (instanceref U0)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_27_ "s_axi_wdata[27]") (joined + (portref (member s_axi_wdata 4) (instanceref U0)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_28_ "s_axi_wdata[28]") (joined + (portref (member s_axi_wdata 3) (instanceref U0)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_29_ "s_axi_wdata[29]") (joined + (portref (member s_axi_wdata 2) (instanceref U0)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 29) (instanceref U0)) + (portref (member s_axi_wdata 29)) + ) + ) + (net (rename s_axi_wdata_30_ "s_axi_wdata[30]") (joined + (portref (member s_axi_wdata 1) (instanceref U0)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_31_ "s_axi_wdata[31]") (joined + (portref (member s_axi_wdata 0) (instanceref U0)) + (portref (member s_axi_wdata 0)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 28) (instanceref U0)) + (portref (member s_axi_wdata 28)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 27) (instanceref U0)) + (portref (member s_axi_wdata 27)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 26) (instanceref U0)) + (portref (member s_axi_wdata 26)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 25) (instanceref U0)) + (portref (member s_axi_wdata 25)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 24) (instanceref U0)) + (portref (member s_axi_wdata 24)) + ) + ) + (net (rename s_axi_wdata_8_ "s_axi_wdata[8]") (joined + (portref (member s_axi_wdata 23) (instanceref U0)) + (portref (member s_axi_wdata 23)) + ) + ) + (net (rename s_axi_wdata_9_ "s_axi_wdata[9]") (joined + (portref (member s_axi_wdata 22) (instanceref U0)) + (portref (member s_axi_wdata 22)) + ) + ) + (net s_axi_wready (joined + (portref s_axi_wready (instanceref U0)) + (portref s_axi_wready) + ) + ) + (net (rename s_axi_wstrb_0_ "s_axi_wstrb[0]") (joined + (portref (member s_axi_wstrb 3) (instanceref U0)) + (portref (member s_axi_wstrb 3)) + ) + ) + (net (rename s_axi_wstrb_1_ "s_axi_wstrb[1]") (joined + (portref (member s_axi_wstrb 2) (instanceref U0)) + (portref (member s_axi_wstrb 2)) + ) + ) + (net (rename s_axi_wstrb_2_ "s_axi_wstrb[2]") (joined + (portref (member s_axi_wstrb 1) (instanceref U0)) + (portref (member s_axi_wstrb 1)) + ) + ) + (net (rename s_axi_wstrb_3_ "s_axi_wstrb[3]") (joined + (portref (member s_axi_wstrb 0) (instanceref U0)) + (portref (member s_axi_wstrb 0)) + ) + ) + (net s_axi_wvalid (joined + (portref s_axi_wvalid (instanceref U0)) + (portref s_axi_wvalid) + ) + ) + (net tx (joined + (portref tx (instanceref U0)) + (portref tx) + ) + ) + ) + + (property downgradeipidentifiedwarnings (string "yes")) + (property x_core_info (string "axi_uartlite,Vivado 2017.4")) + (property CHECK_LICENSE_TYPE (string "axi_uart,axi_uartlite,{}")) + (property core_generation_info (string "axi_uart,axi_uartlite,{x_ipProduct=Vivado 2017.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=10000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=128000,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}")) + ) + ) + ) + (Library work + (edifLevel 0) + (technology (numberDefinition )) + (cell uart_bmpg (celltype GENERIC) + (view uart_bmpg (viewtype NETLIST) + (interface + (port upg_clk_i (direction INPUT)) + (port upg_clk_o (direction OUTPUT)) + (port upg_done_o (direction OUTPUT)) + (port upg_rst_i (direction INPUT)) + (port upg_rx_i (direction INPUT)) + (port upg_tx_o (direction OUTPUT)) + (port upg_wen_o (direction OUTPUT)) + (port (array (rename upg_adr_o "upg_adr_o[14:0]") 15) (direction OUTPUT)) + (port (array (rename upg_dat_o "upg_dat_o[31:0]") 32) (direction OUTPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename RCS_0__i_1 "RCS[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFF0050CF")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename RCS_1__i_1 "RCS[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF00FF0055FCFF00")) + ) + (instance (rename RCS_2__i_1 "RCS[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFF5C000")) + ) + (instance (rename RCS_reg_0_ "RCS_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RCS_reg_1_ "RCS_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RCS_reg_2_ "RCS_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename WCS_0__i_1 "WCS[0]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF0000FF0F080F")) + ) + (instance (rename WCS_0__i_2 "WCS[0]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename WCS_1__i_1 "WCS[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFF7700F0F0F0")) + ) + (instance (rename WCS_2__i_1 "WCS[2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF00FF88FF000F00")) + ) + (instance (rename WCS_2__i_2 "WCS[2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename WCS_2__i_3 "WCS[2]_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hEFFF")) + ) + (instance (rename WCS_2__i_4 "WCS[2]_i_4") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF7FFF")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename WCS_2__i_5 "WCS[2]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hEFFF")) + ) + (instance (rename WCS_reg_0_ "WCS_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename WCS_reg_1_ "WCS_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename WCS_reg_2_ "WCS_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance axi_uart_inst (viewref axi_uart (cellref axi_uart (libraryref work_library0_1))) + (property x_core_info (string "axi_uartlite,Vivado 2017.4")) + ) + (instance axi_uart_inst_i_1 (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename bn_ascii_0__i_1 "bn_ascii[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bn_ascii_10__i_1 "bn_ascii[10]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bn_ascii_11__i_1 "bn_ascii[11]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance (rename bn_ascii_13__i_1 "bn_ascii[13]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename bn_ascii_14__i_1 "bn_ascii[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + ) + (instance (rename bn_ascii_16__i_1 "bn_ascii[16]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename bn_ascii_17__i_1 "bn_ascii[17]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename bn_ascii_18__i_1 "bn_ascii[18]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bn_ascii_19__i_1 "bn_ascii[19]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bn_ascii_1__i_1 "bn_ascii[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bn_ascii_21__i_1 "bn_ascii[21]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bn_ascii_22__i_1 "bn_ascii[22]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bn_ascii_24__i_1 "bn_ascii[24]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bn_ascii_25__i_1 "bn_ascii[25]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bn_ascii_26__i_1 "bn_ascii[26]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bn_ascii_27__i_1 "bn_ascii[27]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bn_ascii_29__i_1 "bn_ascii[29]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bn_ascii_2__i_1 "bn_ascii[2]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bn_ascii_30__i_1 "bn_ascii[30]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bn_ascii_32__i_1 "bn_ascii[32]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bn_ascii_33__i_1 "bn_ascii[33]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bn_ascii_34__i_1 "bn_ascii[34]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bn_ascii_35__i_1 "bn_ascii[35]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bn_ascii_37__i_1 "bn_ascii[37]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bn_ascii_38__i_1 "bn_ascii[38]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bn_ascii_3__i_1 "bn_ascii[3]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bn_ascii_40__i_1 "bn_ascii[40]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bn_ascii_41__i_1 "bn_ascii[41]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bn_ascii_42__i_1 "bn_ascii[42]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bn_ascii_43__i_1 "bn_ascii[43]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bn_ascii_45__i_1 "bn_ascii[45]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bn_ascii_46__i_1 "bn_ascii[46]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bn_ascii_48__i_1 "bn_ascii[48]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bn_ascii_49__i_1 "bn_ascii[49]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bn_ascii_50__i_1 "bn_ascii[50]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bn_ascii_51__i_1 "bn_ascii[51]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bn_ascii_53__i_1 "bn_ascii[53]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bn_ascii_54__i_1 "bn_ascii[54]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bn_ascii_56__i_1 "bn_ascii[56]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bn_ascii_57__i_1 "bn_ascii[57]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bn_ascii_58__i_1 "bn_ascii[58]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bn_ascii_59__i_1 "bn_ascii[59]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bn_ascii_5__i_1 "bn_ascii[5]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bn_ascii_61__i_1 "bn_ascii[61]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bn_ascii_62__i_1 "bn_ascii[62]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename bn_ascii_62__i_2 "bn_ascii[62]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bn_ascii_6__i_1 "bn_ascii[6]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bn_ascii_8__i_1 "bn_ascii[8]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename bn_ascii_9__i_1 "bn_ascii[9]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bn_ascii_reg_0_ "bn_ascii_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_10_ "bn_ascii_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_11_ "bn_ascii_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_13_ "bn_ascii_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_14_ "bn_ascii_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_16_ "bn_ascii_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_17_ "bn_ascii_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_18_ "bn_ascii_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_19_ "bn_ascii_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_1_ "bn_ascii_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_21_ "bn_ascii_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_22_ "bn_ascii_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_24_ "bn_ascii_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_25_ "bn_ascii_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_26_ "bn_ascii_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_27_ "bn_ascii_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_29_ "bn_ascii_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_2_ "bn_ascii_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_30_ "bn_ascii_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_32_ "bn_ascii_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_33_ "bn_ascii_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_34_ "bn_ascii_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_35_ "bn_ascii_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_37_ "bn_ascii_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_38_ "bn_ascii_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_3_ "bn_ascii_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_40_ "bn_ascii_reg[40]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_41_ "bn_ascii_reg[41]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_42_ "bn_ascii_reg[42]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_43_ "bn_ascii_reg[43]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_45_ "bn_ascii_reg[45]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_46_ "bn_ascii_reg[46]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_48_ "bn_ascii_reg[48]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_49_ "bn_ascii_reg[49]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_50_ "bn_ascii_reg[50]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_51_ "bn_ascii_reg[51]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_53_ "bn_ascii_reg[53]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_54_ "bn_ascii_reg[54]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_56_ "bn_ascii_reg[56]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_57_ "bn_ascii_reg[57]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_58_ "bn_ascii_reg[58]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_59_ "bn_ascii_reg[59]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_5_ "bn_ascii_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_61_ "bn_ascii_reg[61]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_62_ "bn_ascii_reg[62]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_6_ "bn_ascii_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_8_ "bn_ascii_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_9_ "bn_ascii_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_0__i_1 "byte_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename byte_cnt_31__i_1 "byte_cnt[31]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0040")) + ) + (instance (rename byte_cnt_reg_0_ "byte_cnt_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_10_ "byte_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_11_ "byte_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_12_ "byte_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_12__i_1 "byte_cnt_reg[12]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_13_ "byte_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_14_ "byte_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_15_ "byte_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_16_ "byte_cnt_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_16__i_1 "byte_cnt_reg[16]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_17_ "byte_cnt_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_18_ "byte_cnt_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_19_ "byte_cnt_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_1_ "byte_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_20_ "byte_cnt_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_20__i_1 "byte_cnt_reg[20]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_21_ "byte_cnt_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_22_ "byte_cnt_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_23_ "byte_cnt_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_24_ "byte_cnt_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_24__i_1 "byte_cnt_reg[24]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_25_ "byte_cnt_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_26_ "byte_cnt_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_27_ "byte_cnt_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_28_ "byte_cnt_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_28__i_1 "byte_cnt_reg[28]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_29_ "byte_cnt_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_2_ "byte_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_30_ "byte_cnt_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_31_ "byte_cnt_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_31__i_2 "byte_cnt_reg[31]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_3_ "byte_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_4_ "byte_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_4__i_1 "byte_cnt_reg[4]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_5_ "byte_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_6_ "byte_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_7_ "byte_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_8_ "byte_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_8__i_1 "byte_cnt_reg[8]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_9_ "byte_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_7__i_1 "byte_len[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + ) + (instance (rename byte_len_reg_0_ "byte_len_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_1_ "byte_len_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_2_ "byte_len_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_3_ "byte_len_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_4_ "byte_len_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_5_ "byte_len_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_6_ "byte_len_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_7_ "byte_len_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_31__i_1 "byte_num[31]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h08")) + ) + (instance (rename byte_num_reg_0_ "byte_num_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_10_ "byte_num_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_11_ "byte_num_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_12_ "byte_num_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_13_ "byte_num_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_14_ "byte_num_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_15_ "byte_num_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_16_ "byte_num_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_17_ "byte_num_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_18_ "byte_num_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_19_ "byte_num_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_1_ "byte_num_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_20_ "byte_num_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_21_ "byte_num_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_22_ "byte_num_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_23_ "byte_num_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_24_ "byte_num_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_25_ "byte_num_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_26_ "byte_num_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_27_ "byte_num_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_28_ "byte_num_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_29_ "byte_num_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_2_ "byte_num_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_30_ "byte_num_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_31_ "byte_num_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_3_ "byte_num_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_4_ "byte_num_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_5_ "byte_num_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_6_ "byte_num_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_7_ "byte_num_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_8_ "byte_num_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_9_ "byte_num_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_0_ "dbuf_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_10_ "dbuf_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_11_ "dbuf_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_12_ "dbuf_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_13_ "dbuf_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_14_ "dbuf_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_15_ "dbuf_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_16_ "dbuf_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_17_ "dbuf_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_18_ "dbuf_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_19_ "dbuf_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_1_ "dbuf_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_20_ "dbuf_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_21_ "dbuf_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_22_ "dbuf_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_23_ "dbuf_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_2_ "dbuf_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_3_ "dbuf_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_4_ "dbuf_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_5_ "dbuf_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_6_ "dbuf_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_7_ "dbuf_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_8_ "dbuf_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_9_ "dbuf_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_0__i_1 "disp[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h5595")) + ) + (instance (rename disp_1__i_1 "disp[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h55556555")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename disp_1__i_2 "disp[1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFEFF0000EFFFFFFF")) + ) + (instance (rename disp_1__i_3 "disp[1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000FF00FFFFEFFF")) + ) + (instance (rename disp_2__i_1 "disp[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h82882222")) + ) + (instance (rename disp_2__i_2 "disp[2]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFEFFF")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename disp_3__i_1 "disp[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF0000007F807F80")) + ) + (instance (rename disp_3__i_2 "disp[3]_i_2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h00A2")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename disp_4__i_1 "disp[4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF0000007F807F80")) + ) + (instance (rename disp_5__i_1 "disp[5]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00000000BFFF4000")) + ) + (instance (rename disp_5__i_2 "disp[5]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename disp_5__i_3 "disp[5]_i_3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h20220000")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename disp_5__i_4 "disp[5]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename disp_6__i_1 "disp[6]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hB000B00000F0B000")) + ) + (instance (rename disp_6__i_2 "disp[6]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFDFFFF")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename disp_6__i_3 "disp[6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF7F7F7F7F7F7D7F7")) + ) + (instance (rename disp_7__i_1 "disp[7]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hD02FD0D0D0D0D0D0")) + ) + (instance (rename disp_7__i_2 "disp[7]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFDFFFFFFFFFFFFFF")) + ) + (instance (rename disp_7__i_3 "disp[7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFAAEFFFFFFFFFFF")) + ) + (instance (rename disp_7__i_4 "disp[7]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename disp_reg_0_ "disp_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_1_ "disp_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_2_ "disp_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_3_ "disp_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_4_ "disp_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_5_ "disp_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_6_ "disp_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_7_ "disp_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance initFlag_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hAAAE")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance initFlag_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_0__i_1 "len_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename len_cnt_1__i_1 "len_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename len_cnt_2__i_1 "len_cnt[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h6A")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename len_cnt_3__i_1 "len_cnt[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h6AAA")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename len_cnt_reg_0_ "len_cnt_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_reg_1_ "len_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_reg_2_ "len_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_reg_3_ "len_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_0__i_1 "msg_indx[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename msg_indx_1__i_1 "msg_indx[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename msg_indx_2__i_1 "msg_indx[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h6A")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename msg_indx_3__i_1 "msg_indx[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h6AAA")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename msg_indx_4__i_1 "msg_indx[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h6AAAAAAA")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename msg_indx_5__i_1 "msg_indx[5]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h6AAAAAAAAAAAAAAA")) + ) + (instance (rename msg_indx_6__i_1 "msg_indx[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename msg_indx_7__i_1 "msg_indx[7]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + ) + (instance (rename msg_indx_7__i_2 "msg_indx[7]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h6A")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename msg_indx_7__i_3 "msg_indx[7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h8000000000000000")) + ) + (instance (rename msg_indx_reg_0_ "msg_indx_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_1_ "msg_indx_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_2_ "msg_indx_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_3_ "msg_indx_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_4_ "msg_indx_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_5_ "msg_indx_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_6_ "msg_indx_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_7_ "msg_indx_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance oldInitF_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF0200")) + ) + (instance oldInitF_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rdStat_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives)))) + (instance rdStat_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF708F708FF00FF0A")) + ) + (instance rdStat_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance recv_done_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF2000")) + ) + (instance recv_done_i_10 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_11 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_13 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_14 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_15 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_16 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_17 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_18 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_19 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_20 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_22 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_23 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_24 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_25 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_26 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_27 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_28 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_29 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_30 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_31 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_32 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_33 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h222B")) + ) + (instance recv_done_i_34 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_35 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_36 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_37 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h6006")) + ) + (instance recv_done_i_4 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_5 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_6 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_7 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_8 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_9 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance recv_done_reg_i_12 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance recv_done_reg_i_2 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance recv_done_reg_i_21 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance recv_done_reg_i_3 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_0__i_1 "rwait_cnt[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance (rename rwait_cnt_10__i_1 "rwait_cnt[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename rwait_cnt_11__i_1 "rwait_cnt[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename rwait_cnt_12__i_1 "rwait_cnt[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename rwait_cnt_13__i_1 "rwait_cnt[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename rwait_cnt_14__i_1 "rwait_cnt[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename rwait_cnt_15__i_1 "rwait_cnt[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h10")) + ) + (instance (rename rwait_cnt_15__i_2 "rwait_cnt[15]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename rwait_cnt_15__i_4 "rwait_cnt[15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000004000")) + ) + (instance (rename rwait_cnt_15__i_5 "rwait_cnt[15]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFD")) + ) + (instance (rename rwait_cnt_15__i_6 "rwait_cnt[15]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFBFF")) + ) + (instance (rename rwait_cnt_15__i_7 "rwait_cnt[15]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFEF")) + ) + (instance (rename rwait_cnt_1__i_1 "rwait_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename rwait_cnt_2__i_1 "rwait_cnt[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename rwait_cnt_3__i_1 "rwait_cnt[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename rwait_cnt_4__i_1 "rwait_cnt[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename rwait_cnt_5__i_1 "rwait_cnt[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename rwait_cnt_6__i_1 "rwait_cnt[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename rwait_cnt_7__i_1 "rwait_cnt[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename rwait_cnt_8__i_1 "rwait_cnt[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename rwait_cnt_9__i_1 "rwait_cnt[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename rwait_cnt_reg_0_ "rwait_cnt_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename rwait_cnt_reg_10_ "rwait_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_11_ "rwait_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_12_ "rwait_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_12__i_2 "rwait_cnt_reg[12]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_13_ "rwait_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_14_ "rwait_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_15_ "rwait_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_15__i_3 "rwait_cnt_reg[15]_i_3") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_1_ "rwait_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_2_ "rwait_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_3_ "rwait_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_4_ "rwait_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_4__i_2 "rwait_cnt_reg[4]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_5_ "rwait_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_6_ "rwait_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_7_ "rwait_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_8_ "rwait_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_8__i_2 "rwait_cnt_reg[8]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_9_ "rwait_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_done_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h38")) + ) + (instance rx_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_araddr_3__i_1 "s_axi_araddr[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFE00000002")) + ) + (instance (rename s_axi_araddr_reg_3_ "s_axi_araddr_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_arvalid_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF7373000C4040")) + ) + (instance s_axi_arvalid_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance s_axi_arvalid_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance s_axi_arvalid_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_awaddr_3__i_1 "s_axi_awaddr[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFD00000001")) + ) + (instance (rename s_axi_awaddr_reg_3_ "s_axi_awaddr_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_awvalid_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFF558A00")) + ) + (instance s_axi_awvalid_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000F0008000F")) + ) + (instance s_axi_awvalid_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_0__i_1 "s_axi_wdata[0]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h20AA2020AAAAAAAA")) + ) + (instance (rename s_axi_wdata_0__i_2 "s_axi_wdata[0]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000004B560AB000")) + ) + (instance (rename s_axi_wdata_0__i_3 "s_axi_wdata[0]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hABEFABEFABEF0000")) + ) + (instance (rename s_axi_wdata_0__i_4 "s_axi_wdata[0]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000037F7FFFF37F7")) + ) + (instance (rename s_axi_wdata_0__i_5 "s_axi_wdata[0]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAFA0CFCFAFA0C0C0")) + ) + (instance (rename s_axi_wdata_1__i_1 "s_axi_wdata[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h20AA2020AAAAAAAA")) + ) + (instance (rename s_axi_wdata_1__i_2 "s_axi_wdata[1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000F008800441500")) + ) + (instance (rename s_axi_wdata_1__i_3 "s_axi_wdata[1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hABEFABEFABEF0000")) + ) + (instance (rename s_axi_wdata_1__i_4 "s_axi_wdata[1]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename s_axi_wdata_1__i_5 "s_axi_wdata[1]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF000057F757F7")) + ) + (instance (rename s_axi_wdata_1__i_6 "s_axi_wdata[1]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h05F5030305F5F3F3")) + ) + (instance (rename s_axi_wdata_2__i_1 "s_axi_wdata[2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h4F4F4FFF44444444")) + ) + (instance (rename s_axi_wdata_2__i_2 "s_axi_wdata[2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00000047C6526000")) + ) + (instance (rename s_axi_wdata_2__i_3 "s_axi_wdata[2]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFF4FFF7FFFFFFFF")) + ) + (instance (rename s_axi_wdata_2__i_4 "s_axi_wdata[2]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000037F7FFFF37F7")) + ) + (instance (rename s_axi_wdata_2__i_5 "s_axi_wdata[2]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAFA0CFCFAFA0C0C0")) + ) + (instance (rename s_axi_wdata_3__i_1 "s_axi_wdata[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h4F4F4FFF44444444")) + ) + (instance (rename s_axi_wdata_3__i_2 "s_axi_wdata[3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000046431202")) + ) + (instance (rename s_axi_wdata_3__i_3 "s_axi_wdata[3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFF35FFFFFFFF")) + ) + (instance (rename s_axi_wdata_3__i_4 "s_axi_wdata[3]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000037F7FFFF37F7")) + ) + (instance (rename s_axi_wdata_3__i_5 "s_axi_wdata[3]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAFA0CFCFAFA0C0C0")) + ) + (instance (rename s_axi_wdata_4__i_1 "s_axi_wdata[4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0100010101010101")) + ) + (instance (rename s_axi_wdata_4__i_2 "s_axi_wdata[4]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hAA20AAAA")) + ) + (instance (rename s_axi_wdata_4__i_3 "s_axi_wdata[4]_i_3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h54")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename s_axi_wdata_4__i_4 "s_axi_wdata[4]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h02A8")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename s_axi_wdata_4__i_5 "s_axi_wdata[4]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000009D584FF")) + ) + (instance (rename s_axi_wdata_4__i_6 "s_axi_wdata[4]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88888888AAA888A8")) + ) + (instance (rename s_axi_wdata_4__i_7 "s_axi_wdata[4]_i_7") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h45")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename s_axi_wdata_4__i_8 "s_axi_wdata[4]_i_8") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFD")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename s_axi_wdata_5__i_1 "s_axi_wdata[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFF4F4444")) + ) + (instance (rename s_axi_wdata_5__i_2 "s_axi_wdata[5]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000FFF7FFFFF")) + ) + (instance (rename s_axi_wdata_5__i_3 "s_axi_wdata[5]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFF35FFFFFFFF")) + ) + (instance (rename s_axi_wdata_5__i_4 "s_axi_wdata[5]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0455")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename s_axi_wdata_5__i_5 "s_axi_wdata[5]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h05F5030305F5F3F3")) + ) + (instance (rename s_axi_wdata_5__i_6 "s_axi_wdata[5]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF47FF")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename s_axi_wdata_6__i_1 "s_axi_wdata[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00010101")) + ) + (instance (rename s_axi_wdata_6__i_2 "s_axi_wdata[6]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h3A3A3A0A")) + ) + (instance (rename s_axi_wdata_6__i_3 "s_axi_wdata[6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00DF00F8009E0704")) + ) + (instance (rename s_axi_wdata_6__i_4 "s_axi_wdata[6]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000005300000000")) + ) + (instance (rename s_axi_wdata_6__i_5 "s_axi_wdata[6]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00000000AAAAFEAE")) + ) + (instance (rename s_axi_wdata_6__i_6 "s_axi_wdata[6]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h8A80FFFF")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename s_axi_wdata_6__i_7 "s_axi_wdata[6]_i_7") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00103010")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename s_axi_wdata_reg_0_ "s_axi_wdata_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_1_ "s_axi_wdata_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_2_ "s_axi_wdata_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_3_ "s_axi_wdata_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_4_ "s_axi_wdata_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_5_ "s_axi_wdata_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_6_ "s_axi_wdata_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wstrb_3__i_1 "s_axi_wstrb[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h2220AAAA")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename s_axi_wstrb_reg_3_ "s_axi_wstrb_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename statReg_0__i_1 "statReg[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFBF0080")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename statReg_0__i_2 "statReg[0]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename statReg_reg_0_ "statReg_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_7__i_1 "uart_rdat[7]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000080")) + ) + (instance (rename uart_rdat_reg_0_ "uart_rdat_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_1_ "uart_rdat_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_2_ "uart_rdat_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_3_ "uart_rdat_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_4_ "uart_rdat_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_5_ "uart_rdat_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_6_ "uart_rdat_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_7_ "uart_rdat_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance uart_wen_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFEF00000020")) + ) + (instance uart_wen_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_14__i_1 "upg_adr_o[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + ) + (instance (rename upg_adr_o_OBUF_0__inst "upg_adr_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_10__inst "upg_adr_o_OBUF[10]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_11__inst "upg_adr_o_OBUF[11]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_12__inst "upg_adr_o_OBUF[12]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_13__inst "upg_adr_o_OBUF[13]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_14__inst "upg_adr_o_OBUF[14]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_1__inst "upg_adr_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_2__inst "upg_adr_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_3__inst "upg_adr_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_4__inst "upg_adr_o_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_5__inst "upg_adr_o_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_6__inst "upg_adr_o_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_7__inst "upg_adr_o_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_8__inst "upg_adr_o_OBUF[8]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_9__inst "upg_adr_o_OBUF[9]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_reg_0_ "upg_adr_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_10_ "upg_adr_o_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_11_ "upg_adr_o_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_12_ "upg_adr_o_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_13_ "upg_adr_o_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_14_ "upg_adr_o_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_1_ "upg_adr_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_2_ "upg_adr_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_3_ "upg_adr_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_4_ "upg_adr_o_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_5_ "upg_adr_o_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_6_ "upg_adr_o_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_7_ "upg_adr_o_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_8_ "upg_adr_o_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_9_ "upg_adr_o_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance upg_clk_i_IBUF_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives)))) + (instance upg_clk_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) + (instance upg_clk_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_clk_o_OBUF_inst_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFB")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance upg_clk_o_OBUF_inst_i_2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance (rename upg_dat_o_OBUF_0__inst "upg_dat_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_10__inst "upg_dat_o_OBUF[10]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_11__inst "upg_dat_o_OBUF[11]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_12__inst "upg_dat_o_OBUF[12]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_13__inst "upg_dat_o_OBUF[13]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_14__inst "upg_dat_o_OBUF[14]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_15__inst "upg_dat_o_OBUF[15]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_16__inst "upg_dat_o_OBUF[16]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_17__inst "upg_dat_o_OBUF[17]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_18__inst "upg_dat_o_OBUF[18]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_19__inst "upg_dat_o_OBUF[19]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_1__inst "upg_dat_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_20__inst "upg_dat_o_OBUF[20]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_21__inst "upg_dat_o_OBUF[21]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_22__inst "upg_dat_o_OBUF[22]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_23__inst "upg_dat_o_OBUF[23]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_24__inst "upg_dat_o_OBUF[24]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_25__inst "upg_dat_o_OBUF[25]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_26__inst "upg_dat_o_OBUF[26]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_27__inst "upg_dat_o_OBUF[27]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_28__inst "upg_dat_o_OBUF[28]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_29__inst "upg_dat_o_OBUF[29]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_2__inst "upg_dat_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_30__inst "upg_dat_o_OBUF[30]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_31__inst "upg_dat_o_OBUF[31]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_3__inst "upg_dat_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_4__inst "upg_dat_o_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_5__inst "upg_dat_o_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_6__inst "upg_dat_o_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_7__inst "upg_dat_o_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_8__inst "upg_dat_o_OBUF[8]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_9__inst "upg_dat_o_OBUF[9]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_reg_0_ "upg_dat_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_10_ "upg_dat_o_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_11_ "upg_dat_o_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_12_ "upg_dat_o_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_13_ "upg_dat_o_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_14_ "upg_dat_o_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_15_ "upg_dat_o_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_16_ "upg_dat_o_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_17_ "upg_dat_o_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_18_ "upg_dat_o_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_19_ "upg_dat_o_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_1_ "upg_dat_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_20_ "upg_dat_o_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_21_ "upg_dat_o_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_22_ "upg_dat_o_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_23_ "upg_dat_o_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_24_ "upg_dat_o_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_25_ "upg_dat_o_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_26_ "upg_dat_o_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_27_ "upg_dat_o_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_28_ "upg_dat_o_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_29_ "upg_dat_o_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_2_ "upg_dat_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_30_ "upg_dat_o_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_31_ "upg_dat_o_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_3_ "upg_dat_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_4_ "upg_dat_o_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_5_ "upg_dat_o_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_6_ "upg_dat_o_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_7_ "upg_dat_o_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_8_ "upg_dat_o_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_9_ "upg_dat_o_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance upg_done_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_done_o_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + ) + (instance upg_done_o_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFEFEFEFEFEEEEEEE")) + ) + (instance upg_done_o_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance upg_done_o_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance upg_rst_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) + (instance upg_rx_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) + (instance upg_tx_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_wen_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_wen_o_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hAAAB")) + ) + (instance upg_wen_o_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance upg_wen_o_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0000AAA8")) + ) + (instance upg_wen_o_i_4 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFBBB0")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance upg_wen_o_i_5 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000002800000000")) + ) + (instance upg_wen_o_i_6 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF00FFFFFE00FEFE")) + ) + (instance upg_wen_o_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance wr_byte_len_done_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h5555555555555554")) + ) + (instance wr_byte_len_done_i_2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance wr_byte_len_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance wr_byte_num_done_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000000006AAA9555")) + ) + (instance wr_byte_num_done_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFF96F6FF6")) + ) + (instance wr_byte_num_done_i_3 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFEFFFEFFFF")) + ) + (instance wr_byte_num_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_0__i_1 "wwait_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename wwait_cnt_10__i_1 "wwait_cnt[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename wwait_cnt_11__i_1 "wwait_cnt[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename wwait_cnt_12__i_1 "wwait_cnt[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename wwait_cnt_13__i_1 "wwait_cnt[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename wwait_cnt_14__i_1 "wwait_cnt[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename wwait_cnt_15__i_1 "wwait_cnt[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h10")) + ) + (instance (rename wwait_cnt_15__i_2 "wwait_cnt[15]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename wwait_cnt_15__i_4 "wwait_cnt[15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000040000000")) + ) + (instance (rename wwait_cnt_15__i_5 "wwait_cnt[15]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h7FFF")) + ) + (instance (rename wwait_cnt_15__i_6 "wwait_cnt[15]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename wwait_cnt_15__i_7 "wwait_cnt[15]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename wwait_cnt_1__i_1 "wwait_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename wwait_cnt_2__i_1 "wwait_cnt[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename wwait_cnt_3__i_1 "wwait_cnt[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename wwait_cnt_4__i_1 "wwait_cnt[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename wwait_cnt_5__i_1 "wwait_cnt[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename wwait_cnt_6__i_1 "wwait_cnt[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename wwait_cnt_7__i_1 "wwait_cnt[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename wwait_cnt_8__i_1 "wwait_cnt[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename wwait_cnt_9__i_1 "wwait_cnt[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename wwait_cnt_reg_0_ "wwait_cnt_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename wwait_cnt_reg_10_ "wwait_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_11_ "wwait_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_12_ "wwait_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_12__i_2 "wwait_cnt_reg[12]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_13_ "wwait_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_14_ "wwait_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_15_ "wwait_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_15__i_3 "wwait_cnt_reg[15]_i_3") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_1_ "wwait_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_2_ "wwait_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_3_ "wwait_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_4_ "wwait_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_4__i_2 "wwait_cnt_reg[4]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_5_ "wwait_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_6_ "wwait_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_7_ "wwait_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_8_ "wwait_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_8__i_2 "wwait_cnt_reg[8]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_9_ "wwait_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref CI (instanceref byte_cnt_reg_4__i_1)) + (portref CI (instanceref recv_done_reg_i_21)) + (portref CI (instanceref rwait_cnt_reg_4__i_2)) + (portref CI (instanceref wwait_cnt_reg_4__i_2)) + (portref CYINIT (instanceref byte_cnt_reg_12__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_16__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_20__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_24__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_28__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_31__i_2)) + (portref CYINIT (instanceref byte_cnt_reg_8__i_1)) + (portref CYINIT (instanceref recv_done_reg_i_12)) + (portref CYINIT (instanceref recv_done_reg_i_2)) + (portref CYINIT (instanceref recv_done_reg_i_3)) + (portref CYINIT (instanceref rwait_cnt_reg_12__i_2)) + (portref CYINIT (instanceref rwait_cnt_reg_15__i_3)) + (portref CYINIT (instanceref rwait_cnt_reg_8__i_2)) + (portref CYINIT (instanceref wwait_cnt_reg_12__i_2)) + (portref CYINIT (instanceref wwait_cnt_reg_15__i_3)) + (portref CYINIT (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 3) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 3) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 3) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 3) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 3) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 3) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 3) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 3) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 3) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 3) (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 2) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 2) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 2) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 2) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 2) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 2) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 2) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 2) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 2) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 2) (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 1) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 1) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 1) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 1) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 1) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 1) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 1) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 1) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 1) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 1) (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 0) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 0) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 0) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 0) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 0) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 0) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 0) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 0) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 0) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 0) (instanceref wwait_cnt_reg_8__i_2)) + (portref G (instanceref GND)) + (portref R (instanceref s_axi_araddr_reg_3_)) + (portref R (instanceref s_axi_arvalid_reg)) + (portref R (instanceref s_axi_awaddr_reg_3_)) + (portref R (instanceref s_axi_awvalid_reg)) + (portref R (instanceref s_axi_wdata_reg_0_)) + (portref R (instanceref s_axi_wdata_reg_1_)) + (portref R (instanceref s_axi_wdata_reg_4_)) + (portref R (instanceref s_axi_wstrb_reg_3_)) + (portref R (instanceref uart_rdat_reg_0_)) + (portref R (instanceref uart_rdat_reg_1_)) + (portref R (instanceref uart_rdat_reg_2_)) + (portref R (instanceref uart_rdat_reg_3_)) + (portref R (instanceref uart_rdat_reg_4_)) + (portref R (instanceref uart_rdat_reg_5_)) + (portref R (instanceref uart_rdat_reg_6_)) + (portref R (instanceref uart_rdat_reg_7_)) + (portref (member S 0) (instanceref byte_cnt_reg_31__i_2)) + (portref (member S 0) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member S 0) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member s_axi_araddr 3) (instanceref axi_uart_inst)) + (portref (member s_axi_araddr 2) (instanceref axi_uart_inst)) + (portref (member s_axi_araddr 1) (instanceref axi_uart_inst)) + (portref (member s_axi_awaddr 3) (instanceref axi_uart_inst)) + (portref (member s_axi_awaddr 2) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 21) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 20) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 19) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 18) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 17) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 16) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 15) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 14) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 13) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 12) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 11) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 10) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 9) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 8) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 7) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 6) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 5) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 4) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 3) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 2) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 1) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 0) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 24) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 23) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 22) (instanceref axi_uart_inst)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref RCS_reg_0_)) + (portref CE (instanceref RCS_reg_1_)) + (portref CE (instanceref RCS_reg_2_)) + (portref CE (instanceref WCS_reg_0_)) + (portref CE (instanceref WCS_reg_1_)) + (portref CE (instanceref WCS_reg_2_)) + (portref CE (instanceref initFlag_reg)) + (portref CE (instanceref oldInitF_reg)) + (portref CE (instanceref rdStat_reg)) + (portref CE (instanceref recv_done_reg)) + (portref CE (instanceref rx_done_reg)) + (portref CE (instanceref s_axi_araddr_reg_3_)) + (portref CE (instanceref s_axi_arvalid_reg)) + (portref CE (instanceref s_axi_awaddr_reg_3_)) + (portref CE (instanceref s_axi_awvalid_reg)) + (portref CE (instanceref statReg_reg_0_)) + (portref CE (instanceref uart_wen_reg)) + (portref CYINIT (instanceref recv_done_reg_i_21)) + (portref P (instanceref VCC)) + (portref (member s_axi_awaddr 1) (instanceref axi_uart_inst)) + (portref s_axi_bready (instanceref axi_uart_inst)) + (portref s_axi_rready (instanceref axi_uart_inst)) + ) + ) + (net (rename RCS_0__i_1_n_0 "RCS[0]_i_1_n_0") (joined + (portref D (instanceref RCS_reg_0_)) + (portref O (instanceref RCS_0__i_1)) + ) + ) + (net (rename RCS_1__i_1_n_0 "RCS[1]_i_1_n_0") (joined + (portref D (instanceref RCS_reg_1_)) + (portref O (instanceref RCS_1__i_1)) + ) + ) + (net (rename RCS_2__i_1_n_0 "RCS[2]_i_1_n_0") (joined + (portref D (instanceref RCS_reg_2_)) + (portref O (instanceref RCS_2__i_1)) + ) + ) + (net (rename RCS_reg_n_0__0_ "RCS_reg_n_0_[0]") (joined + (portref I0 (instanceref rdStat_i_1)) + (portref I0 (instanceref statReg_0__i_2)) + (portref I1 (instanceref rwait_cnt_15__i_1)) + (portref I2 (instanceref uart_rdat_7__i_1)) + (portref I3 (instanceref RCS_0__i_1)) + (portref I3 (instanceref RCS_2__i_1)) + (portref I4 (instanceref RCS_1__i_1)) + (portref I4 (instanceref s_axi_araddr_3__i_1)) + (portref I4 (instanceref s_axi_arvalid_i_1)) + (portref Q (instanceref RCS_reg_0_)) + ) + ) + (net (rename RCS_reg_n_0__1_ "RCS_reg_n_0_[1]") (joined + (portref I0 (instanceref rwait_cnt_15__i_1)) + (portref I1 (instanceref statReg_0__i_2)) + (portref I1 (instanceref uart_rdat_7__i_1)) + (portref I2 (instanceref RCS_0__i_1)) + (portref I2 (instanceref RCS_2__i_1)) + (portref I2 (instanceref s_axi_arvalid_i_1)) + (portref I3 (instanceref RCS_1__i_1)) + (portref I3 (instanceref s_axi_araddr_3__i_1)) + (portref I5 (instanceref rdStat_i_1)) + (portref Q (instanceref RCS_reg_1_)) + ) + ) + (net (rename RCS_reg_n_0__2_ "RCS_reg_n_0_[2]") (joined + (portref I1 (instanceref s_axi_araddr_3__i_1)) + (portref I1 (instanceref s_axi_arvalid_i_2)) + (portref I2 (instanceref rdStat_i_1)) + (portref I2 (instanceref rwait_cnt_15__i_1)) + (portref I3 (instanceref statReg_0__i_1)) + (portref I4 (instanceref RCS_0__i_1)) + (portref I4 (instanceref RCS_2__i_1)) + (portref I4 (instanceref uart_rdat_7__i_1)) + (portref I5 (instanceref RCS_1__i_1)) + (portref Q (instanceref RCS_reg_2_)) + ) + ) + (net (rename WCS_0__i_1_n_0 "WCS[0]_i_1_n_0") (joined + (portref D (instanceref WCS_reg_0_)) + (portref O (instanceref WCS_0__i_1)) + ) + ) + (net (rename WCS_0__i_2_n_0 "WCS[0]_i_2_n_0") (joined + (portref I0 (instanceref WCS_0__i_1)) + (portref O (instanceref WCS_0__i_2)) + ) + ) + (net (rename WCS_1__i_1_n_0 "WCS[1]_i_1_n_0") (joined + (portref D (instanceref WCS_reg_1_)) + (portref O (instanceref WCS_1__i_1)) + ) + ) + (net (rename WCS_2__i_1_n_0 "WCS[2]_i_1_n_0") (joined + (portref D (instanceref WCS_reg_2_)) + (portref O (instanceref WCS_2__i_1)) + ) + ) + (net (rename WCS_2__i_2_n_0 "WCS[2]_i_2_n_0") (joined + (portref I1 (instanceref WCS_0__i_1)) + (portref I2 (instanceref WCS_2__i_1)) + (portref I3 (instanceref oldInitF_i_1)) + (portref O (instanceref WCS_2__i_2)) + ) + ) + (net (rename WCS_2__i_3_n_0 "WCS[2]_i_3_n_0") (joined + (portref I0 (instanceref WCS_2__i_2)) + (portref O (instanceref WCS_2__i_3)) + ) + ) + (net (rename WCS_2__i_4_n_0 "WCS[2]_i_4_n_0") (joined + (portref I5 (instanceref WCS_2__i_2)) + (portref O (instanceref WCS_2__i_4)) + ) + ) + (net (rename WCS_2__i_5_n_0 "WCS[2]_i_5_n_0") (joined + (portref I4 (instanceref WCS_2__i_4)) + (portref O (instanceref WCS_2__i_5)) + ) + ) + (net (rename WCS_reg_n_0__0_ "WCS_reg_n_0_[0]") (joined + (portref I0 (instanceref s_axi_wdata_0__i_1)) + (portref I0 (instanceref s_axi_wdata_1__i_1)) + (portref I0 (instanceref s_axi_wdata_4__i_2)) + (portref I0 (instanceref s_axi_wstrb_3__i_1)) + (portref I0 (instanceref wwait_cnt_15__i_1)) + (portref I1 (instanceref initFlag_i_1)) + (portref I1 (instanceref msg_indx_7__i_1)) + (portref I1 (instanceref upg_done_o_i_1)) + (portref I2 (instanceref oldInitF_i_1)) + (portref I2 (instanceref uart_wen_i_1)) + (portref I3 (instanceref s_axi_awaddr_3__i_1)) + (portref I3 (instanceref s_axi_awvalid_i_1)) + (portref I3 (instanceref s_axi_wdata_6__i_1)) + (portref I4 (instanceref WCS_0__i_1)) + (portref I4 (instanceref WCS_1__i_1)) + (portref I4 (instanceref WCS_2__i_1)) + (portref I5 (instanceref s_axi_awvalid_i_2)) + (portref I5 (instanceref s_axi_wdata_4__i_1)) + (portref Q (instanceref WCS_reg_0_)) + ) + ) + (net (rename WCS_reg_n_0__1_ "WCS_reg_n_0_[1]") (joined + (portref I0 (instanceref s_axi_wdata_4__i_1)) + (portref I1 (instanceref oldInitF_i_1)) + (portref I1 (instanceref wwait_cnt_15__i_1)) + (portref I2 (instanceref initFlag_i_1)) + (portref I2 (instanceref msg_indx_7__i_1)) + (portref I2 (instanceref s_axi_wdata_6__i_1)) + (portref I2 (instanceref upg_done_o_i_1)) + (portref I3 (instanceref uart_wen_i_1)) + (portref I4 (instanceref s_axi_awaddr_3__i_1)) + (portref I4 (instanceref s_axi_awvalid_i_2)) + (portref I5 (instanceref WCS_0__i_1)) + (portref I5 (instanceref WCS_1__i_1)) + (portref I5 (instanceref WCS_2__i_1)) + (portref Q (instanceref WCS_reg_1_)) + ) + ) + (net (rename WCS_reg_n_0__2_ "WCS_reg_n_0_[2]") (joined + (portref I0 (instanceref oldInitF_i_1)) + (portref I0 (instanceref s_axi_wdata_6__i_1)) + (portref I1 (instanceref s_axi_awaddr_3__i_1)) + (portref I2 (instanceref s_axi_wdata_4__i_1)) + (portref I2 (instanceref wwait_cnt_15__i_1)) + (portref I3 (instanceref WCS_0__i_1)) + (portref I3 (instanceref WCS_1__i_1)) + (portref I3 (instanceref WCS_2__i_1)) + (portref I3 (instanceref initFlag_i_1)) + (portref I3 (instanceref msg_indx_7__i_1)) + (portref I3 (instanceref s_axi_awvalid_i_2)) + (portref I3 (instanceref upg_done_o_i_1)) + (portref I4 (instanceref uart_wen_i_1)) + (portref Q (instanceref WCS_reg_2_)) + ) + ) + (net (rename bn_ascii_reg_n_0__0_ "bn_ascii_reg_n_0_[0]") (joined + (portref I2 (instanceref s_axi_wdata_0__i_3)) + (portref Q (instanceref bn_ascii_reg_0_)) + ) + ) + (net (rename bn_ascii_reg_n_0__1_ "bn_ascii_reg_n_0_[1]") (joined + (portref I2 (instanceref s_axi_wdata_1__i_3)) + (portref Q (instanceref bn_ascii_reg_1_)) + ) + ) + (net (rename bn_ascii_reg_n_0__2_ "bn_ascii_reg_n_0_[2]") (joined + (portref I0 (instanceref s_axi_wdata_2__i_3)) + (portref Q (instanceref bn_ascii_reg_2_)) + ) + ) + (net (rename bn_ascii_reg_n_0__3_ "bn_ascii_reg_n_0_[3]") (joined + (portref I1 (instanceref s_axi_wdata_3__i_3)) + (portref Q (instanceref bn_ascii_reg_3_)) + ) + ) + (net (rename bn_ascii_reg_n_0__48_ "bn_ascii_reg_n_0_[48]") (joined + (portref I3 (instanceref s_axi_wdata_0__i_4)) + (portref Q (instanceref bn_ascii_reg_48_)) + ) + ) + (net (rename bn_ascii_reg_n_0__49_ "bn_ascii_reg_n_0_[49]") (joined + (portref I3 (instanceref s_axi_wdata_1__i_5)) + (portref Q (instanceref bn_ascii_reg_49_)) + ) + ) + (net (rename bn_ascii_reg_n_0__50_ "bn_ascii_reg_n_0_[50]") (joined + (portref I3 (instanceref s_axi_wdata_2__i_4)) + (portref Q (instanceref bn_ascii_reg_50_)) + ) + ) + (net (rename bn_ascii_reg_n_0__51_ "bn_ascii_reg_n_0_[51]") (joined + (portref I3 (instanceref s_axi_wdata_3__i_4)) + (portref Q (instanceref bn_ascii_reg_51_)) + ) + ) + (net (rename bn_ascii_reg_n_0__53_ "bn_ascii_reg_n_0_[53]") (joined + (portref I0 (instanceref s_axi_wdata_5__i_6)) + (portref Q (instanceref bn_ascii_reg_53_)) + ) + ) + (net (rename bn_ascii_reg_n_0__54_ "bn_ascii_reg_n_0_[54]") (joined + (portref I4 (instanceref s_axi_wdata_6__i_7)) + (portref Q (instanceref bn_ascii_reg_54_)) + ) + ) + (net (rename bn_ascii_reg_n_0__56_ "bn_ascii_reg_n_0_[56]") (joined + (portref I0 (instanceref s_axi_wdata_0__i_4)) + (portref Q (instanceref bn_ascii_reg_56_)) + ) + ) + (net (rename bn_ascii_reg_n_0__57_ "bn_ascii_reg_n_0_[57]") (joined + (portref I1 (instanceref s_axi_wdata_1__i_5)) + (portref Q (instanceref bn_ascii_reg_57_)) + ) + ) + (net (rename bn_ascii_reg_n_0__58_ "bn_ascii_reg_n_0_[58]") (joined + (portref I0 (instanceref s_axi_wdata_2__i_4)) + (portref Q (instanceref bn_ascii_reg_58_)) + ) + ) + (net (rename bn_ascii_reg_n_0__59_ "bn_ascii_reg_n_0_[59]") (joined + (portref I0 (instanceref s_axi_wdata_3__i_4)) + (portref Q (instanceref bn_ascii_reg_59_)) + ) + ) + (net (rename bn_ascii_reg_n_0__5_ "bn_ascii_reg_n_0_[5]") (joined + (portref I1 (instanceref s_axi_wdata_5__i_3)) + (portref I2 (instanceref s_axi_wdata_4__i_6)) + (portref Q (instanceref bn_ascii_reg_5_)) + ) + ) + (net (rename bn_ascii_reg_n_0__61_ "bn_ascii_reg_n_0_[61]") (joined + (portref I2 (instanceref s_axi_wdata_5__i_6)) + (portref Q (instanceref bn_ascii_reg_61_)) + ) + ) + (net (rename bn_ascii_reg_n_0__62_ "bn_ascii_reg_n_0_[62]") (joined + (portref I0 (instanceref s_axi_wdata_6__i_7)) + (portref Q (instanceref bn_ascii_reg_62_)) + ) + ) + (net (rename bn_ascii_reg_n_0__6_ "bn_ascii_reg_n_0_[6]") (joined + (portref I0 (instanceref s_axi_wdata_6__i_4)) + (portref Q (instanceref bn_ascii_reg_6_)) + ) + ) + (net byte_cnt (joined + (portref CE (instanceref byte_cnt_reg_0_)) + (portref CE (instanceref byte_cnt_reg_10_)) + (portref CE (instanceref byte_cnt_reg_11_)) + (portref CE (instanceref byte_cnt_reg_12_)) + (portref CE (instanceref byte_cnt_reg_13_)) + (portref CE (instanceref byte_cnt_reg_14_)) + (portref CE (instanceref byte_cnt_reg_15_)) + (portref CE (instanceref byte_cnt_reg_16_)) + (portref CE (instanceref byte_cnt_reg_17_)) + (portref CE (instanceref byte_cnt_reg_18_)) + (portref CE (instanceref byte_cnt_reg_19_)) + (portref CE (instanceref byte_cnt_reg_1_)) + (portref CE (instanceref byte_cnt_reg_20_)) + (portref CE (instanceref byte_cnt_reg_21_)) + (portref CE (instanceref byte_cnt_reg_22_)) + (portref CE (instanceref byte_cnt_reg_23_)) + (portref CE (instanceref byte_cnt_reg_24_)) + (portref CE (instanceref byte_cnt_reg_25_)) + (portref CE (instanceref byte_cnt_reg_26_)) + (portref CE (instanceref byte_cnt_reg_27_)) + (portref CE (instanceref byte_cnt_reg_28_)) + (portref CE (instanceref byte_cnt_reg_29_)) + (portref CE (instanceref byte_cnt_reg_2_)) + (portref CE (instanceref byte_cnt_reg_30_)) + (portref CE (instanceref byte_cnt_reg_31_)) + (portref CE (instanceref byte_cnt_reg_3_)) + (portref CE (instanceref byte_cnt_reg_4_)) + (portref CE (instanceref byte_cnt_reg_5_)) + (portref CE (instanceref byte_cnt_reg_6_)) + (portref CE (instanceref byte_cnt_reg_7_)) + (portref CE (instanceref byte_cnt_reg_8_)) + (portref CE (instanceref byte_cnt_reg_9_)) + (portref CE (instanceref dbuf_reg_0_)) + (portref CE (instanceref dbuf_reg_10_)) + (portref CE (instanceref dbuf_reg_11_)) + (portref CE (instanceref dbuf_reg_12_)) + (portref CE (instanceref dbuf_reg_13_)) + (portref CE (instanceref dbuf_reg_14_)) + (portref CE (instanceref dbuf_reg_15_)) + (portref CE (instanceref dbuf_reg_16_)) + (portref CE (instanceref dbuf_reg_17_)) + (portref CE (instanceref dbuf_reg_18_)) + (portref CE (instanceref dbuf_reg_19_)) + (portref CE (instanceref dbuf_reg_1_)) + (portref CE (instanceref dbuf_reg_20_)) + (portref CE (instanceref dbuf_reg_21_)) + (portref CE (instanceref dbuf_reg_22_)) + (portref CE (instanceref dbuf_reg_23_)) + (portref CE (instanceref dbuf_reg_2_)) + (portref CE (instanceref dbuf_reg_3_)) + (portref CE (instanceref dbuf_reg_4_)) + (portref CE (instanceref dbuf_reg_5_)) + (portref CE (instanceref dbuf_reg_6_)) + (portref CE (instanceref dbuf_reg_7_)) + (portref CE (instanceref dbuf_reg_8_)) + (portref CE (instanceref dbuf_reg_9_)) + (portref O (instanceref byte_cnt_31__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_0 "byte_cnt_reg[12]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_16__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_1 "byte_cnt_reg[12]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_2 "byte_cnt_reg[12]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_3 "byte_cnt_reg[12]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_0 "byte_cnt_reg[16]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_20__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_1 "byte_cnt_reg[16]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_2 "byte_cnt_reg[16]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_3 "byte_cnt_reg[16]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_0 "byte_cnt_reg[20]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_24__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_1 "byte_cnt_reg[20]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_2 "byte_cnt_reg[20]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_3 "byte_cnt_reg[20]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_0 "byte_cnt_reg[24]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_28__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_1 "byte_cnt_reg[24]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_2 "byte_cnt_reg[24]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_3 "byte_cnt_reg[24]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_0 "byte_cnt_reg[28]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_31__i_2)) + (portref (member CO 0) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_1 "byte_cnt_reg[28]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_2 "byte_cnt_reg[28]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_3 "byte_cnt_reg[28]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_31__i_2_n_2 "byte_cnt_reg[31]_i_2_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_31__i_2_n_3 "byte_cnt_reg[31]_i_2_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_0 "byte_cnt_reg[4]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_8__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_1 "byte_cnt_reg[4]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_2 "byte_cnt_reg[4]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_3 "byte_cnt_reg[4]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_0 "byte_cnt_reg[8]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_12__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_1 "byte_cnt_reg[8]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_2 "byte_cnt_reg[8]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_3 "byte_cnt_reg[8]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__0_ "byte_cnt_reg_n_0_[0]") (joined + (portref CYINIT (instanceref byte_cnt_reg_4__i_1)) + (portref I0 (instanceref byte_cnt_0__i_1)) + (portref I1 (instanceref recv_done_i_37)) + (portref I2 (instanceref recv_done_i_33)) + (portref Q (instanceref byte_cnt_reg_0_)) + ) + ) + (net (rename byte_cnt_reg_n_0__17_ "byte_cnt_reg_n_0_[17]") (joined + (portref Q (instanceref byte_cnt_reg_17_)) + (portref (member S 3) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__18_ "byte_cnt_reg_n_0_[18]") (joined + (portref Q (instanceref byte_cnt_reg_18_)) + (portref (member S 2) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__19_ "byte_cnt_reg_n_0_[19]") (joined + (portref Q (instanceref byte_cnt_reg_19_)) + (portref (member S 1) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__1_ "byte_cnt_reg_n_0_[1]") (joined + (portref Q (instanceref byte_cnt_reg_1_)) + (portref (member S 3) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__20_ "byte_cnt_reg_n_0_[20]") (joined + (portref Q (instanceref byte_cnt_reg_20_)) + (portref (member S 0) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__21_ "byte_cnt_reg_n_0_[21]") (joined + (portref Q (instanceref byte_cnt_reg_21_)) + (portref (member S 3) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__22_ "byte_cnt_reg_n_0_[22]") (joined + (portref Q (instanceref byte_cnt_reg_22_)) + (portref (member S 2) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__23_ "byte_cnt_reg_n_0_[23]") (joined + (portref Q (instanceref byte_cnt_reg_23_)) + (portref (member S 1) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__24_ "byte_cnt_reg_n_0_[24]") (joined + (portref Q (instanceref byte_cnt_reg_24_)) + (portref (member S 0) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__25_ "byte_cnt_reg_n_0_[25]") (joined + (portref Q (instanceref byte_cnt_reg_25_)) + (portref (member S 3) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__26_ "byte_cnt_reg_n_0_[26]") (joined + (portref Q (instanceref byte_cnt_reg_26_)) + (portref (member S 2) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__27_ "byte_cnt_reg_n_0_[27]") (joined + (portref Q (instanceref byte_cnt_reg_27_)) + (portref (member S 1) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__28_ "byte_cnt_reg_n_0_[28]") (joined + (portref Q (instanceref byte_cnt_reg_28_)) + (portref (member S 0) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__29_ "byte_cnt_reg_n_0_[29]") (joined + (portref Q (instanceref byte_cnt_reg_29_)) + (portref (member S 3) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_n_0__30_ "byte_cnt_reg_n_0_[30]") (joined + (portref Q (instanceref byte_cnt_reg_30_)) + (portref (member S 2) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_n_0__31_ "byte_cnt_reg_n_0_[31]") (joined + (portref Q (instanceref byte_cnt_reg_31_)) + (portref (member S 1) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_len_7__i_1_n_0 "byte_len[7]_i_1_n_0") (joined + (portref CE (instanceref byte_len_reg_0_)) + (portref CE (instanceref byte_len_reg_1_)) + (portref CE (instanceref byte_len_reg_2_)) + (portref CE (instanceref byte_len_reg_3_)) + (portref CE (instanceref byte_len_reg_4_)) + (portref CE (instanceref byte_len_reg_5_)) + (portref CE (instanceref byte_len_reg_6_)) + (portref CE (instanceref byte_len_reg_7_)) + (portref CE (instanceref wr_byte_len_done_reg)) + (portref O (instanceref byte_len_7__i_1)) + ) + ) + (net (rename byte_len_reg_n_0__0_ "byte_len_reg_n_0_[0]") (joined + (portref I4 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_0_)) + ) + ) + (net (rename byte_len_reg_n_0__1_ "byte_len_reg_n_0_[1]") (joined + (portref I2 (instanceref wr_byte_num_done_i_2)) + (portref Q (instanceref byte_len_reg_1_)) + ) + ) + (net (rename byte_len_reg_n_0__2_ "byte_len_reg_n_0_[2]") (joined + (portref I1 (instanceref wr_byte_num_done_i_2)) + (portref Q (instanceref byte_len_reg_2_)) + ) + ) + (net (rename byte_len_reg_n_0__3_ "byte_len_reg_n_0_[3]") (joined + (portref I4 (instanceref wr_byte_num_done_i_1)) + (portref Q (instanceref byte_len_reg_3_)) + ) + ) + (net (rename byte_len_reg_n_0__4_ "byte_len_reg_n_0_[4]") (joined + (portref I1 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_4_)) + ) + ) + (net (rename byte_len_reg_n_0__5_ "byte_len_reg_n_0_[5]") (joined + (portref I0 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_5_)) + ) + ) + (net (rename byte_len_reg_n_0__6_ "byte_len_reg_n_0_[6]") (joined + (portref I3 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_6_)) + ) + ) + (net (rename byte_len_reg_n_0__7_ "byte_len_reg_n_0_[7]") (joined + (portref I2 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_7_)) + ) + ) + (net byte_num (joined + (portref CE (instanceref byte_num_reg_0_)) + (portref CE (instanceref byte_num_reg_10_)) + (portref CE (instanceref byte_num_reg_11_)) + (portref CE (instanceref byte_num_reg_12_)) + (portref CE (instanceref byte_num_reg_13_)) + (portref CE (instanceref byte_num_reg_14_)) + (portref CE (instanceref byte_num_reg_15_)) + (portref CE (instanceref byte_num_reg_16_)) + (portref CE (instanceref byte_num_reg_17_)) + (portref CE (instanceref byte_num_reg_18_)) + (portref CE (instanceref byte_num_reg_19_)) + (portref CE (instanceref byte_num_reg_1_)) + (portref CE (instanceref byte_num_reg_20_)) + (portref CE (instanceref byte_num_reg_21_)) + (portref CE (instanceref byte_num_reg_22_)) + (portref CE (instanceref byte_num_reg_23_)) + (portref CE (instanceref byte_num_reg_24_)) + (portref CE (instanceref byte_num_reg_25_)) + (portref CE (instanceref byte_num_reg_26_)) + (portref CE (instanceref byte_num_reg_27_)) + (portref CE (instanceref byte_num_reg_28_)) + (portref CE (instanceref byte_num_reg_29_)) + (portref CE (instanceref byte_num_reg_2_)) + (portref CE (instanceref byte_num_reg_30_)) + (portref CE (instanceref byte_num_reg_31_)) + (portref CE (instanceref byte_num_reg_3_)) + (portref CE (instanceref byte_num_reg_4_)) + (portref CE (instanceref byte_num_reg_5_)) + (portref CE (instanceref byte_num_reg_6_)) + (portref CE (instanceref byte_num_reg_7_)) + (portref CE (instanceref byte_num_reg_8_)) + (portref CE (instanceref byte_num_reg_9_)) + (portref CE (instanceref len_cnt_reg_0_)) + (portref CE (instanceref len_cnt_reg_1_)) + (portref CE (instanceref len_cnt_reg_2_)) + (portref CE (instanceref len_cnt_reg_3_)) + (portref O (instanceref byte_num_31__i_1)) + ) + ) + (net (rename byte_num_reg_n_0__24_ "byte_num_reg_n_0_[24]") (joined + (portref I2 (instanceref recv_done_i_11)) + (portref I3 (instanceref recv_done_i_7)) + (portref Q (instanceref byte_num_reg_24_)) + ) + ) + (net (rename byte_num_reg_n_0__25_ "byte_num_reg_n_0_[25]") (joined + (portref I0 (instanceref recv_done_i_11)) + (portref I1 (instanceref recv_done_i_7)) + (portref Q (instanceref byte_num_reg_25_)) + ) + ) + (net (rename byte_num_reg_n_0__26_ "byte_num_reg_n_0_[26]") (joined + (portref I2 (instanceref recv_done_i_10)) + (portref I3 (instanceref recv_done_i_6)) + (portref Q (instanceref byte_num_reg_26_)) + ) + ) + (net (rename byte_num_reg_n_0__27_ "byte_num_reg_n_0_[27]") (joined + (portref I0 (instanceref recv_done_i_10)) + (portref I1 (instanceref recv_done_i_6)) + (portref Q (instanceref byte_num_reg_27_)) + ) + ) + (net (rename byte_num_reg_n_0__28_ "byte_num_reg_n_0_[28]") (joined + (portref I2 (instanceref recv_done_i_9)) + (portref I3 (instanceref recv_done_i_5)) + (portref Q (instanceref byte_num_reg_28_)) + ) + ) + (net (rename byte_num_reg_n_0__29_ "byte_num_reg_n_0_[29]") (joined + (portref I0 (instanceref recv_done_i_9)) + (portref I1 (instanceref recv_done_i_5)) + (portref Q (instanceref byte_num_reg_29_)) + ) + ) + (net (rename byte_num_reg_n_0__30_ "byte_num_reg_n_0_[30]") (joined + (portref I2 (instanceref recv_done_i_8)) + (portref I3 (instanceref recv_done_i_4)) + (portref Q (instanceref byte_num_reg_30_)) + ) + ) + (net (rename byte_num_reg_n_0__31_ "byte_num_reg_n_0_[31]") (joined + (portref I0 (instanceref recv_done_i_8)) + (portref I1 (instanceref recv_done_i_4)) + (portref Q (instanceref byte_num_reg_31_)) + ) + ) + (net (rename data2_0_ "data2[0]") (joined + (portref I5 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_40_)) + ) + ) + (net (rename data2_1_ "data2[1]") (joined + (portref I1 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_41_)) + ) + ) + (net (rename data2_2_ "data2[2]") (joined + (portref I5 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_42_)) + ) + ) + (net (rename data2_3_ "data2[3]") (joined + (portref I5 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_43_)) + ) + ) + (net (rename data2_5_ "data2[5]") (joined + (portref I1 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_45_)) + ) + ) + (net (rename data2_6_ "data2[6]") (joined + (portref I1 (instanceref s_axi_wdata_6__i_5)) + (portref Q (instanceref bn_ascii_reg_46_)) + ) + ) + (net (rename data3_0_ "data3[0]") (joined + (portref I3 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_32_)) + ) + ) + (net (rename data3_1_ "data3[1]") (joined + (portref I0 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_33_)) + ) + ) + (net (rename data3_2_ "data3[2]") (joined + (portref I3 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_34_)) + ) + ) + (net (rename data3_3_ "data3[3]") (joined + (portref I3 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_35_)) + ) + ) + (net (rename data3_5_ "data3[5]") (joined + (portref I0 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_37_)) + ) + ) + (net (rename data3_6_ "data3[6]") (joined + (portref I3 (instanceref s_axi_wdata_6__i_5)) + (portref Q (instanceref bn_ascii_reg_38_)) + ) + ) + (net (rename data4_0_ "data4[0]") (joined + (portref I1 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_24_)) + ) + ) + (net (rename data4_1_ "data4[1]") (joined + (portref I5 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_25_)) + ) + ) + (net (rename data4_2_ "data4[2]") (joined + (portref I1 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_26_)) + ) + ) + (net (rename data4_3_ "data4[3]") (joined + (portref I1 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_27_)) + ) + ) + (net (rename data4_5_ "data4[5]") (joined + (portref I5 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_29_)) + ) + ) + (net (rename data4_6_ "data4[6]") (joined + (portref I3 (instanceref s_axi_wdata_6__i_6)) + (portref Q (instanceref bn_ascii_reg_30_)) + ) + ) + (net (rename data5_0_ "data5[0]") (joined + (portref I0 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_16_)) + ) + ) + (net (rename data5_1_ "data5[1]") (joined + (portref I3 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_17_)) + ) + ) + (net (rename data5_2_ "data5[2]") (joined + (portref I0 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_18_)) + ) + ) + (net (rename data5_3_ "data5[3]") (joined + (portref I0 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_19_)) + ) + ) + (net (rename data5_5_ "data5[5]") (joined + (portref I3 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_21_)) + ) + ) + (net (rename data5_6_ "data5[6]") (joined + (portref I1 (instanceref s_axi_wdata_6__i_6)) + (portref Q (instanceref bn_ascii_reg_22_)) + ) + ) + (net (rename data6_0_ "data6[0]") (joined + (portref I3 (instanceref s_axi_wdata_0__i_3)) + (portref Q (instanceref bn_ascii_reg_8_)) + ) + ) + (net (rename data6_1_ "data6[1]") (joined + (portref I3 (instanceref s_axi_wdata_1__i_3)) + (portref Q (instanceref bn_ascii_reg_9_)) + ) + ) + (net (rename data6_2_ "data6[2]") (joined + (portref I4 (instanceref s_axi_wdata_2__i_3)) + (portref Q (instanceref bn_ascii_reg_10_)) + ) + ) + (net (rename data6_3_ "data6[3]") (joined + (portref I0 (instanceref s_axi_wdata_3__i_3)) + (portref Q (instanceref bn_ascii_reg_11_)) + ) + ) + (net (rename data6_5_ "data6[5]") (joined + (portref I0 (instanceref s_axi_wdata_5__i_3)) + (portref I4 (instanceref s_axi_wdata_4__i_6)) + (portref Q (instanceref bn_ascii_reg_13_)) + ) + ) + (net (rename data6_6_ "data6[6]") (joined + (portref I1 (instanceref s_axi_wdata_6__i_4)) + (portref Q (instanceref bn_ascii_reg_14_)) + ) + ) + (net (rename dbuf_0_ "dbuf[0]") (joined + (portref D (instanceref dbuf_reg_8_)) + (portref D (instanceref upg_dat_o_reg_8_)) + (portref Q (instanceref dbuf_reg_0_)) + ) + ) + (net (rename dbuf_10_ "dbuf[10]") (joined + (portref D (instanceref dbuf_reg_18_)) + (portref D (instanceref upg_dat_o_reg_18_)) + (portref Q (instanceref dbuf_reg_10_)) + ) + ) + (net (rename dbuf_11_ "dbuf[11]") (joined + (portref D (instanceref dbuf_reg_19_)) + (portref D (instanceref upg_dat_o_reg_19_)) + (portref Q (instanceref dbuf_reg_11_)) + ) + ) + (net (rename dbuf_12_ "dbuf[12]") (joined + (portref D (instanceref dbuf_reg_20_)) + (portref D (instanceref upg_dat_o_reg_20_)) + (portref Q (instanceref dbuf_reg_12_)) + ) + ) + (net (rename dbuf_13_ "dbuf[13]") (joined + (portref D (instanceref dbuf_reg_21_)) + (portref D (instanceref upg_dat_o_reg_21_)) + (portref Q (instanceref dbuf_reg_13_)) + ) + ) + (net (rename dbuf_14_ "dbuf[14]") (joined + (portref D (instanceref dbuf_reg_22_)) + (portref D (instanceref upg_dat_o_reg_22_)) + (portref Q (instanceref dbuf_reg_14_)) + ) + ) + (net (rename dbuf_15_ "dbuf[15]") (joined + (portref D (instanceref dbuf_reg_23_)) + (portref D (instanceref upg_dat_o_reg_23_)) + (portref Q (instanceref dbuf_reg_15_)) + ) + ) + (net (rename dbuf_16_ "dbuf[16]") (joined + (portref D (instanceref upg_dat_o_reg_24_)) + (portref Q (instanceref dbuf_reg_16_)) + ) + ) + (net (rename dbuf_17_ "dbuf[17]") (joined + (portref D (instanceref upg_dat_o_reg_25_)) + (portref Q (instanceref dbuf_reg_17_)) + ) + ) + (net (rename dbuf_18_ "dbuf[18]") (joined + (portref D (instanceref upg_dat_o_reg_26_)) + (portref Q (instanceref dbuf_reg_18_)) + ) + ) + (net (rename dbuf_19_ "dbuf[19]") (joined + (portref D (instanceref upg_dat_o_reg_27_)) + (portref Q (instanceref dbuf_reg_19_)) + ) + ) + (net (rename dbuf_1_ "dbuf[1]") (joined + (portref D (instanceref dbuf_reg_9_)) + (portref D (instanceref upg_dat_o_reg_9_)) + (portref Q (instanceref dbuf_reg_1_)) + ) + ) + (net (rename dbuf_20_ "dbuf[20]") (joined + (portref D (instanceref upg_dat_o_reg_28_)) + (portref Q (instanceref dbuf_reg_20_)) + ) + ) + (net (rename dbuf_21_ "dbuf[21]") (joined + (portref D (instanceref upg_dat_o_reg_29_)) + (portref Q (instanceref dbuf_reg_21_)) + ) + ) + (net (rename dbuf_22_ "dbuf[22]") (joined + (portref D (instanceref upg_dat_o_reg_30_)) + (portref Q (instanceref dbuf_reg_22_)) + ) + ) + (net (rename dbuf_23_ "dbuf[23]") (joined + (portref D (instanceref upg_dat_o_reg_31_)) + (portref Q (instanceref dbuf_reg_23_)) + ) + ) + (net (rename dbuf_2_ "dbuf[2]") (joined + (portref D (instanceref dbuf_reg_10_)) + (portref D (instanceref upg_dat_o_reg_10_)) + (portref Q (instanceref dbuf_reg_2_)) + ) + ) + (net (rename dbuf_3_ "dbuf[3]") (joined + (portref D (instanceref dbuf_reg_11_)) + (portref D (instanceref upg_dat_o_reg_11_)) + (portref Q (instanceref dbuf_reg_3_)) + ) + ) + (net (rename dbuf_4_ "dbuf[4]") (joined + (portref D (instanceref dbuf_reg_12_)) + (portref D (instanceref upg_dat_o_reg_12_)) + (portref Q (instanceref dbuf_reg_4_)) + ) + ) + (net (rename dbuf_5_ "dbuf[5]") (joined + (portref D (instanceref dbuf_reg_13_)) + (portref D (instanceref upg_dat_o_reg_13_)) + (portref Q (instanceref dbuf_reg_5_)) + ) + ) + (net (rename dbuf_6_ "dbuf[6]") (joined + (portref D (instanceref dbuf_reg_14_)) + (portref D (instanceref upg_dat_o_reg_14_)) + (portref Q (instanceref dbuf_reg_6_)) + ) + ) + (net (rename dbuf_7_ "dbuf[7]") (joined + (portref D (instanceref dbuf_reg_15_)) + (portref D (instanceref upg_dat_o_reg_15_)) + (portref Q (instanceref dbuf_reg_7_)) + ) + ) + (net (rename dbuf_8_ "dbuf[8]") (joined + (portref D (instanceref dbuf_reg_16_)) + (portref D (instanceref upg_dat_o_reg_16_)) + (portref Q (instanceref dbuf_reg_8_)) + ) + ) + (net (rename dbuf_9_ "dbuf[9]") (joined + (portref D (instanceref dbuf_reg_17_)) + (portref D (instanceref upg_dat_o_reg_17_)) + (portref Q (instanceref dbuf_reg_9_)) + ) + ) + (net disp1 (joined + (portref I2 (instanceref disp_6__i_3)) + (portref I2 (instanceref disp_7__i_2)) + (portref I3 (instanceref disp_7__i_3)) + (portref I4 (instanceref disp_1__i_2)) + (portref I5 (instanceref disp_5__i_1)) + (portref I5 (instanceref upg_wen_o_i_5)) + (portref O (instanceref disp_5__i_4)) + ) + ) + (net (rename disp_0__i_1_n_0 "disp[0]_i_1_n_0") (joined + (portref D (instanceref disp_reg_0_)) + (portref O (instanceref disp_0__i_1)) + ) + ) + (net (rename disp_1__i_1_n_0 "disp[1]_i_1_n_0") (joined + (portref D (instanceref disp_reg_1_)) + (portref O (instanceref disp_1__i_1)) + ) + ) + (net (rename disp_1__i_2_n_0 "disp[1]_i_2_n_0") (joined + (portref I0 (instanceref disp_1__i_1)) + (portref I0 (instanceref disp_2__i_2)) + (portref O (instanceref disp_1__i_2)) + ) + ) + (net (rename disp_1__i_3_n_0 "disp[1]_i_3_n_0") (joined + (portref I0 (instanceref disp_0__i_1)) + (portref I1 (instanceref disp_1__i_1)) + (portref I1 (instanceref disp_2__i_2)) + (portref O (instanceref disp_1__i_3)) + ) + ) + (net (rename disp_2__i_1_n_0 "disp[2]_i_1_n_0") (joined + (portref D (instanceref disp_reg_2_)) + (portref O (instanceref disp_2__i_1)) + ) + ) + (net (rename disp_2__i_2_n_0 "disp[2]_i_2_n_0") (joined + (portref I0 (instanceref upg_adr_o_14__i_1)) + (portref I1 (instanceref disp_2__i_1)) + (portref I1 (instanceref upg_wen_o_i_2)) + (portref I3 (instanceref upg_wen_o_i_1)) + (portref O (instanceref disp_2__i_2)) + ) + ) + (net (rename disp_3__i_1_n_0 "disp[3]_i_1_n_0") (joined + (portref D (instanceref disp_reg_3_)) + (portref O (instanceref disp_3__i_1)) + ) + ) + (net (rename disp_3__i_2_n_0 "disp[3]_i_2_n_0") (joined + (portref I1 (instanceref disp_3__i_1)) + (portref O (instanceref disp_3__i_2)) + ) + ) + (net (rename disp_4__i_1_n_0 "disp[4]_i_1_n_0") (joined + (portref D (instanceref disp_reg_4_)) + (portref O (instanceref disp_4__i_1)) + ) + ) + (net (rename disp_5__i_1_n_0 "disp[5]_i_1_n_0") (joined + (portref D (instanceref disp_reg_5_)) + (portref O (instanceref disp_5__i_1)) + ) + ) + (net (rename disp_5__i_2_n_0 "disp[5]_i_2_n_0") (joined + (portref I0 (instanceref disp_5__i_1)) + (portref I0 (instanceref disp_7__i_3)) + (portref O (instanceref disp_5__i_2)) + ) + ) + (net (rename disp_5__i_3_n_0 "disp[5]_i_3_n_0") (joined + (portref I1 (instanceref disp_4__i_1)) + (portref I1 (instanceref disp_5__i_1)) + (portref O (instanceref disp_5__i_3)) + ) + ) + (net (rename disp_6__i_1_n_0 "disp[6]_i_1_n_0") (joined + (portref D (instanceref disp_reg_6_)) + (portref O (instanceref disp_6__i_1)) + ) + ) + (net (rename disp_6__i_2_n_0 "disp[6]_i_2_n_0") (joined + (portref I0 (instanceref disp_2__i_1)) + (portref I2 (instanceref disp_6__i_1)) + (portref O (instanceref disp_6__i_2)) + ) + ) + (net (rename disp_6__i_3_n_0 "disp[6]_i_3_n_0") (joined + (portref I1 (instanceref disp_5__i_3)) + (portref I2 (instanceref disp_6__i_2)) + (portref I3 (instanceref disp_3__i_2)) + (portref O (instanceref disp_6__i_3)) + ) + ) + (net (rename disp_7__i_1_n_0 "disp[7]_i_1_n_0") (joined + (portref D (instanceref disp_reg_7_)) + (portref O (instanceref disp_7__i_1)) + ) + ) + (net (rename disp_7__i_2_n_0 "disp[7]_i_2_n_0") (joined + (portref I3 (instanceref disp_7__i_1)) + (portref I5 (instanceref disp_6__i_1)) + (portref O (instanceref disp_7__i_2)) + ) + ) + (net (rename disp_7__i_3_n_0 "disp[7]_i_3_n_0") (joined + (portref I1 (instanceref disp_7__i_2)) + (portref O (instanceref disp_7__i_3)) + ) + ) + (net (rename disp_7__i_4_n_0 "disp[7]_i_4_n_0") (joined + (portref I1 (instanceref disp_7__i_3)) + (portref O (instanceref disp_7__i_4)) + ) + ) + (net (rename disp_reg_n_0__0_ "disp_reg_n_0_[0]") (joined + (portref I1 (instanceref disp_6__i_3)) + (portref I1 (instanceref upg_wen_o_i_3)) + (portref I1 (instanceref upg_wen_o_i_5)) + (portref I2 (instanceref disp_1__i_2)) + (portref I2 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I4 (instanceref disp_7__i_3)) + (portref I5 (instanceref disp_1__i_3)) + (portref Q (instanceref disp_reg_0_)) + ) + ) + (net (rename disp_reg_n_0__1_ "disp_reg_n_0_[1]") (joined + (portref I0 (instanceref disp_6__i_3)) + (portref I0 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I2 (instanceref upg_wen_o_i_5)) + (portref I5 (instanceref disp_1__i_2)) + (portref I5 (instanceref disp_7__i_3)) + (portref Q (instanceref disp_reg_1_)) + ) + ) + (net (rename disp_reg_n_0__2_ "disp_reg_n_0_[2]") (joined + (portref I0 (instanceref disp_3__i_2)) + (portref I1 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I2 (instanceref upg_wen_o_i_4)) + (portref I3 (instanceref disp_7__i_2)) + (portref I4 (instanceref disp_2__i_1)) + (portref I4 (instanceref disp_5__i_3)) + (portref Q (instanceref disp_reg_2_)) + ) + ) + (net (rename disp_reg_n_0__3_ "disp_reg_n_0_[3]") (joined + (portref I0 (instanceref disp_5__i_3)) + (portref I0 (instanceref disp_7__i_2)) + (portref I3 (instanceref disp_3__i_1)) + (portref I3 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I3 (instanceref upg_wen_o_i_4)) + (portref Q (instanceref disp_reg_3_)) + ) + ) + (net (rename disp_reg_n_0__4_ "disp_reg_n_0_[4]") (joined + (portref I1 (instanceref upg_wen_o_i_6)) + (portref I2 (instanceref disp_5__i_1)) + (portref I2 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I3 (instanceref disp_4__i_1)) + (portref I4 (instanceref disp_7__i_2)) + (portref Q (instanceref disp_reg_4_)) + ) + ) + (net (rename disp_reg_n_0__5_ "disp_reg_n_0_[5]") (joined + (portref I0 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I4 (instanceref disp_5__i_1)) + (portref I5 (instanceref disp_7__i_2)) + (portref I5 (instanceref upg_wen_o_i_6)) + (portref Q (instanceref disp_reg_5_)) + ) + ) + (net (rename disp_reg_n_0__6_ "disp_reg_n_0_[6]") (joined + (portref I0 (instanceref disp_1__i_2)) + (portref I0 (instanceref disp_1__i_3)) + (portref I0 (instanceref disp_7__i_4)) + (portref I2 (instanceref upg_wen_o_i_6)) + (portref I3 (instanceref disp_6__i_1)) + (portref I3 (instanceref upg_wen_o_i_3)) + (portref I4 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I4 (instanceref upg_wen_o_i_5)) + (portref I5 (instanceref disp_6__i_3)) + (portref I5 (instanceref disp_7__i_1)) + (portref Q (instanceref disp_reg_6_)) + ) + ) + (net (rename disp_reg_n_0__7_ "disp_reg_n_0_[7]") (joined + (portref I0 (instanceref upg_wen_o_i_6)) + (portref I1 (instanceref disp_1__i_2)) + (portref I1 (instanceref disp_1__i_3)) + (portref I1 (instanceref disp_7__i_4)) + (portref I2 (instanceref disp_7__i_1)) + (portref I2 (instanceref upg_wen_o_i_3)) + (portref I3 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I3 (instanceref upg_wen_o_i_5)) + (portref I4 (instanceref disp_6__i_3)) + (portref Q (instanceref disp_reg_7_)) + ) + ) + (net (rename hex0_10_ "hex0[10]") (joined + (portref D (instanceref byte_num_reg_10_)) + (portref I1 (instanceref bn_ascii_18__i_1)) + (portref I1 (instanceref bn_ascii_19__i_1)) + (portref I1 (instanceref bn_ascii_21__i_1)) + (portref I1 (instanceref bn_ascii_22__i_1)) + (portref I2 (instanceref bn_ascii_16__i_1)) + (portref I2 (instanceref bn_ascii_17__i_1)) + (portref I2 (instanceref recv_done_i_36)) + (portref I3 (instanceref recv_done_i_32)) + (portref Q (instanceref byte_num_reg_2_)) + ) + ) + (net (rename hex0_11_ "hex0[11]") (joined + (portref D (instanceref byte_num_reg_11_)) + (portref I0 (instanceref bn_ascii_19__i_1)) + (portref I0 (instanceref bn_ascii_22__i_1)) + (portref I0 (instanceref recv_done_i_36)) + (portref I1 (instanceref bn_ascii_17__i_1)) + (portref I1 (instanceref recv_done_i_32)) + (portref I2 (instanceref bn_ascii_18__i_1)) + (portref I2 (instanceref bn_ascii_21__i_1)) + (portref I3 (instanceref bn_ascii_16__i_1)) + (portref Q (instanceref byte_num_reg_3_)) + ) + ) + (net (rename hex0_12_ "hex0[12]") (joined + (portref D (instanceref byte_num_reg_12_)) + (portref I0 (instanceref bn_ascii_24__i_1)) + (portref I0 (instanceref bn_ascii_25__i_1)) + (portref I2 (instanceref recv_done_i_35)) + (portref I3 (instanceref bn_ascii_26__i_1)) + (portref I3 (instanceref recv_done_i_31)) + (portref Q (instanceref byte_num_reg_4_)) + ) + ) + (net (rename hex0_13_ "hex0[13]") (joined + (portref D (instanceref byte_num_reg_13_)) + (portref I0 (instanceref bn_ascii_26__i_1)) + (portref I0 (instanceref bn_ascii_29__i_1)) + (portref I0 (instanceref recv_done_i_35)) + (portref I1 (instanceref bn_ascii_24__i_1)) + (portref I1 (instanceref recv_done_i_31)) + (portref I2 (instanceref bn_ascii_27__i_1)) + (portref I2 (instanceref bn_ascii_30__i_1)) + (portref I3 (instanceref bn_ascii_25__i_1)) + (portref Q (instanceref byte_num_reg_5_)) + ) + ) + (net (rename hex0_14_ "hex0[14]") (joined + (portref D (instanceref byte_num_reg_14_)) + (portref I1 (instanceref bn_ascii_26__i_1)) + (portref I1 (instanceref bn_ascii_27__i_1)) + (portref I1 (instanceref bn_ascii_29__i_1)) + (portref I1 (instanceref bn_ascii_30__i_1)) + (portref I2 (instanceref bn_ascii_24__i_1)) + (portref I2 (instanceref bn_ascii_25__i_1)) + (portref I2 (instanceref recv_done_i_34)) + (portref I3 (instanceref recv_done_i_30)) + (portref Q (instanceref byte_num_reg_6_)) + ) + ) + (net (rename hex0_15_ "hex0[15]") (joined + (portref D (instanceref byte_num_reg_15_)) + (portref I0 (instanceref bn_ascii_27__i_1)) + (portref I0 (instanceref bn_ascii_30__i_1)) + (portref I0 (instanceref recv_done_i_34)) + (portref I1 (instanceref bn_ascii_25__i_1)) + (portref I1 (instanceref recv_done_i_30)) + (portref I2 (instanceref bn_ascii_26__i_1)) + (portref I2 (instanceref bn_ascii_29__i_1)) + (portref I3 (instanceref bn_ascii_24__i_1)) + (portref Q (instanceref byte_num_reg_7_)) + ) + ) + (net (rename hex0_16_ "hex0[16]") (joined + (portref D (instanceref byte_num_reg_16_)) + (portref I0 (instanceref bn_ascii_32__i_1)) + (portref I0 (instanceref bn_ascii_33__i_1)) + (portref I2 (instanceref recv_done_i_29)) + (portref I3 (instanceref bn_ascii_34__i_1)) + (portref I3 (instanceref recv_done_i_25)) + (portref Q (instanceref byte_num_reg_8_)) + ) + ) + (net (rename hex0_17_ "hex0[17]") (joined + (portref D (instanceref byte_num_reg_17_)) + (portref I0 (instanceref bn_ascii_34__i_1)) + (portref I0 (instanceref bn_ascii_37__i_1)) + (portref I0 (instanceref recv_done_i_29)) + (portref I1 (instanceref bn_ascii_32__i_1)) + (portref I1 (instanceref recv_done_i_25)) + (portref I2 (instanceref bn_ascii_35__i_1)) + (portref I2 (instanceref bn_ascii_38__i_1)) + (portref I3 (instanceref bn_ascii_33__i_1)) + (portref Q (instanceref byte_num_reg_9_)) + ) + ) + (net (rename hex0_18_ "hex0[18]") (joined + (portref D (instanceref byte_num_reg_18_)) + (portref I1 (instanceref bn_ascii_34__i_1)) + (portref I1 (instanceref bn_ascii_35__i_1)) + (portref I1 (instanceref bn_ascii_37__i_1)) + (portref I1 (instanceref bn_ascii_38__i_1)) + (portref I2 (instanceref bn_ascii_32__i_1)) + (portref I2 (instanceref bn_ascii_33__i_1)) + (portref I2 (instanceref recv_done_i_28)) + (portref I3 (instanceref recv_done_i_24)) + (portref Q (instanceref byte_num_reg_10_)) + ) + ) + (net (rename hex0_19_ "hex0[19]") (joined + (portref D (instanceref byte_num_reg_19_)) + (portref I0 (instanceref bn_ascii_35__i_1)) + (portref I0 (instanceref bn_ascii_38__i_1)) + (portref I0 (instanceref recv_done_i_28)) + (portref I1 (instanceref bn_ascii_33__i_1)) + (portref I1 (instanceref recv_done_i_24)) + (portref I2 (instanceref bn_ascii_34__i_1)) + (portref I2 (instanceref bn_ascii_37__i_1)) + (portref I3 (instanceref bn_ascii_32__i_1)) + (portref Q (instanceref byte_num_reg_11_)) + ) + ) + (net (rename hex0_20_ "hex0[20]") (joined + (portref D (instanceref byte_num_reg_20_)) + (portref I0 (instanceref bn_ascii_40__i_1)) + (portref I0 (instanceref bn_ascii_41__i_1)) + (portref I2 (instanceref recv_done_i_27)) + (portref I3 (instanceref bn_ascii_42__i_1)) + (portref I3 (instanceref recv_done_i_23)) + (portref Q (instanceref byte_num_reg_12_)) + ) + ) + (net (rename hex0_21_ "hex0[21]") (joined + (portref D (instanceref byte_num_reg_21_)) + (portref I0 (instanceref bn_ascii_42__i_1)) + (portref I0 (instanceref bn_ascii_45__i_1)) + (portref I0 (instanceref recv_done_i_27)) + (portref I1 (instanceref bn_ascii_40__i_1)) + (portref I1 (instanceref recv_done_i_23)) + (portref I2 (instanceref bn_ascii_43__i_1)) + (portref I2 (instanceref bn_ascii_46__i_1)) + (portref I3 (instanceref bn_ascii_41__i_1)) + (portref Q (instanceref byte_num_reg_13_)) + ) + ) + (net (rename hex0_22_ "hex0[22]") (joined + (portref D (instanceref byte_num_reg_22_)) + (portref I1 (instanceref bn_ascii_42__i_1)) + (portref I1 (instanceref bn_ascii_43__i_1)) + (portref I1 (instanceref bn_ascii_45__i_1)) + (portref I1 (instanceref bn_ascii_46__i_1)) + (portref I2 (instanceref bn_ascii_40__i_1)) + (portref I2 (instanceref bn_ascii_41__i_1)) + (portref I2 (instanceref recv_done_i_26)) + (portref I3 (instanceref recv_done_i_22)) + (portref Q (instanceref byte_num_reg_14_)) + ) + ) + (net (rename hex0_23_ "hex0[23]") (joined + (portref D (instanceref byte_num_reg_23_)) + (portref I0 (instanceref bn_ascii_43__i_1)) + (portref I0 (instanceref bn_ascii_46__i_1)) + (portref I0 (instanceref recv_done_i_26)) + (portref I1 (instanceref bn_ascii_41__i_1)) + (portref I1 (instanceref recv_done_i_22)) + (portref I2 (instanceref bn_ascii_42__i_1)) + (portref I2 (instanceref bn_ascii_45__i_1)) + (portref I3 (instanceref bn_ascii_40__i_1)) + (portref Q (instanceref byte_num_reg_15_)) + ) + ) + (net (rename hex0_24_ "hex0[24]") (joined + (portref D (instanceref byte_num_reg_24_)) + (portref I0 (instanceref bn_ascii_48__i_1)) + (portref I0 (instanceref bn_ascii_49__i_1)) + (portref I2 (instanceref recv_done_i_20)) + (portref I3 (instanceref bn_ascii_50__i_1)) + (portref I3 (instanceref recv_done_i_16)) + (portref Q (instanceref byte_num_reg_16_)) + ) + ) + (net (rename hex0_25_ "hex0[25]") (joined + (portref D (instanceref byte_num_reg_25_)) + (portref I0 (instanceref bn_ascii_50__i_1)) + (portref I0 (instanceref bn_ascii_53__i_1)) + (portref I0 (instanceref recv_done_i_20)) + (portref I1 (instanceref bn_ascii_48__i_1)) + (portref I1 (instanceref recv_done_i_16)) + (portref I2 (instanceref bn_ascii_51__i_1)) + (portref I2 (instanceref bn_ascii_54__i_1)) + (portref I3 (instanceref bn_ascii_49__i_1)) + (portref Q (instanceref byte_num_reg_17_)) + ) + ) + (net (rename hex0_26_ "hex0[26]") (joined + (portref D (instanceref byte_num_reg_26_)) + (portref I1 (instanceref bn_ascii_50__i_1)) + (portref I1 (instanceref bn_ascii_51__i_1)) + (portref I1 (instanceref bn_ascii_53__i_1)) + (portref I1 (instanceref bn_ascii_54__i_1)) + (portref I2 (instanceref bn_ascii_48__i_1)) + (portref I2 (instanceref bn_ascii_49__i_1)) + (portref I2 (instanceref recv_done_i_19)) + (portref I3 (instanceref recv_done_i_15)) + (portref Q (instanceref byte_num_reg_18_)) + ) + ) + (net (rename hex0_27_ "hex0[27]") (joined + (portref D (instanceref byte_num_reg_27_)) + (portref I0 (instanceref bn_ascii_51__i_1)) + (portref I0 (instanceref bn_ascii_54__i_1)) + (portref I0 (instanceref recv_done_i_19)) + (portref I1 (instanceref bn_ascii_49__i_1)) + (portref I1 (instanceref recv_done_i_15)) + (portref I2 (instanceref bn_ascii_50__i_1)) + (portref I2 (instanceref bn_ascii_53__i_1)) + (portref I3 (instanceref bn_ascii_48__i_1)) + (portref Q (instanceref byte_num_reg_19_)) + ) + ) + (net (rename hex0_28_ "hex0[28]") (joined + (portref D (instanceref byte_num_reg_28_)) + (portref I0 (instanceref bn_ascii_56__i_1)) + (portref I0 (instanceref bn_ascii_57__i_1)) + (portref I2 (instanceref recv_done_i_18)) + (portref I3 (instanceref bn_ascii_58__i_1)) + (portref I3 (instanceref recv_done_i_14)) + (portref Q (instanceref byte_num_reg_20_)) + ) + ) + (net (rename hex0_29_ "hex0[29]") (joined + (portref D (instanceref byte_num_reg_29_)) + (portref I0 (instanceref bn_ascii_58__i_1)) + (portref I0 (instanceref bn_ascii_61__i_1)) + (portref I0 (instanceref recv_done_i_18)) + (portref I1 (instanceref bn_ascii_56__i_1)) + (portref I1 (instanceref recv_done_i_14)) + (portref I2 (instanceref bn_ascii_59__i_1)) + (portref I2 (instanceref bn_ascii_62__i_2)) + (portref I3 (instanceref bn_ascii_57__i_1)) + (portref Q (instanceref byte_num_reg_21_)) + ) + ) + (net (rename hex0_30_ "hex0[30]") (joined + (portref D (instanceref byte_num_reg_30_)) + (portref I1 (instanceref bn_ascii_58__i_1)) + (portref I1 (instanceref bn_ascii_59__i_1)) + (portref I1 (instanceref bn_ascii_61__i_1)) + (portref I1 (instanceref bn_ascii_62__i_2)) + (portref I2 (instanceref bn_ascii_56__i_1)) + (portref I2 (instanceref bn_ascii_57__i_1)) + (portref I2 (instanceref recv_done_i_17)) + (portref I3 (instanceref recv_done_i_13)) + (portref Q (instanceref byte_num_reg_22_)) + ) + ) + (net (rename hex0_31_ "hex0[31]") (joined + (portref D (instanceref byte_num_reg_31_)) + (portref I0 (instanceref bn_ascii_59__i_1)) + (portref I0 (instanceref bn_ascii_62__i_2)) + (portref I0 (instanceref recv_done_i_17)) + (portref I1 (instanceref bn_ascii_57__i_1)) + (portref I1 (instanceref recv_done_i_13)) + (portref I2 (instanceref bn_ascii_58__i_1)) + (portref I2 (instanceref bn_ascii_61__i_1)) + (portref I3 (instanceref bn_ascii_56__i_1)) + (portref Q (instanceref byte_num_reg_23_)) + ) + ) + (net (rename hex0_8_ "hex0[8]") (joined + (portref D (instanceref byte_num_reg_8_)) + (portref I0 (instanceref bn_ascii_16__i_1)) + (portref I0 (instanceref bn_ascii_17__i_1)) + (portref I0 (instanceref recv_done_i_37)) + (portref I3 (instanceref bn_ascii_18__i_1)) + (portref I3 (instanceref recv_done_i_33)) + (portref Q (instanceref byte_num_reg_0_)) + ) + ) + (net (rename hex0_9_ "hex0[9]") (joined + (portref D (instanceref byte_num_reg_9_)) + (portref I0 (instanceref bn_ascii_18__i_1)) + (portref I0 (instanceref bn_ascii_21__i_1)) + (portref I1 (instanceref bn_ascii_16__i_1)) + (portref I1 (instanceref recv_done_i_33)) + (portref I2 (instanceref bn_ascii_19__i_1)) + (portref I2 (instanceref bn_ascii_22__i_1)) + (portref I2 (instanceref recv_done_i_37)) + (portref I3 (instanceref bn_ascii_17__i_1)) + (portref Q (instanceref byte_num_reg_1_)) + ) + ) + (net (rename hex2ascii_return0_0_ "hex2ascii_return0[0]") (joined + (portref D (instanceref bn_ascii_reg_56_)) + (portref O (instanceref bn_ascii_56__i_1)) + ) + ) + (net (rename hex2ascii_return0_1_ "hex2ascii_return0[1]") (joined + (portref D (instanceref bn_ascii_reg_57_)) + (portref O (instanceref bn_ascii_57__i_1)) + ) + ) + (net (rename hex2ascii_return0_2_ "hex2ascii_return0[2]") (joined + (portref D (instanceref bn_ascii_reg_58_)) + (portref O (instanceref bn_ascii_58__i_1)) + ) + ) + (net (rename hex2ascii_return0_3_ "hex2ascii_return0[3]") (joined + (portref D (instanceref bn_ascii_reg_59_)) + (portref O (instanceref bn_ascii_59__i_1)) + ) + ) + (net (rename hex2ascii_return0_5_ "hex2ascii_return0[5]") (joined + (portref D (instanceref bn_ascii_reg_61_)) + (portref O (instanceref bn_ascii_61__i_1)) + ) + ) + (net (rename hex2ascii_return0_6_ "hex2ascii_return0[6]") (joined + (portref D (instanceref bn_ascii_reg_62_)) + (portref O (instanceref bn_ascii_62__i_2)) + ) + ) + (net (rename hex2ascii_return_0_ "hex2ascii_return[0]") (joined + (portref D (instanceref bn_ascii_reg_0_)) + (portref O (instanceref bn_ascii_0__i_1)) + ) + ) + (net (rename hex2ascii_return_10_ "hex2ascii_return[10]") (joined + (portref D (instanceref bn_ascii_reg_10_)) + (portref O (instanceref bn_ascii_10__i_1)) + ) + ) + (net (rename hex2ascii_return_11_ "hex2ascii_return[11]") (joined + (portref D (instanceref bn_ascii_reg_11_)) + (portref O (instanceref bn_ascii_11__i_1)) + ) + ) + (net (rename hex2ascii_return_13_ "hex2ascii_return[13]") (joined + (portref D (instanceref bn_ascii_reg_13_)) + (portref O (instanceref bn_ascii_13__i_1)) + ) + ) + (net (rename hex2ascii_return_14_ "hex2ascii_return[14]") (joined + (portref D (instanceref bn_ascii_reg_14_)) + (portref O (instanceref bn_ascii_14__i_1)) + ) + ) + (net (rename hex2ascii_return_16_ "hex2ascii_return[16]") (joined + (portref D (instanceref bn_ascii_reg_16_)) + (portref O (instanceref bn_ascii_16__i_1)) + ) + ) + (net (rename hex2ascii_return_17_ "hex2ascii_return[17]") (joined + (portref D (instanceref bn_ascii_reg_17_)) + (portref O (instanceref bn_ascii_17__i_1)) + ) + ) + (net (rename hex2ascii_return_18_ "hex2ascii_return[18]") (joined + (portref D (instanceref bn_ascii_reg_18_)) + (portref O (instanceref bn_ascii_18__i_1)) + ) + ) + (net (rename hex2ascii_return_19_ "hex2ascii_return[19]") (joined + (portref D (instanceref bn_ascii_reg_19_)) + (portref O (instanceref bn_ascii_19__i_1)) + ) + ) + (net (rename hex2ascii_return_1_ "hex2ascii_return[1]") (joined + (portref D (instanceref bn_ascii_reg_1_)) + (portref O (instanceref bn_ascii_1__i_1)) + ) + ) + (net (rename hex2ascii_return_21_ "hex2ascii_return[21]") (joined + (portref D (instanceref bn_ascii_reg_21_)) + (portref O (instanceref bn_ascii_21__i_1)) + ) + ) + (net (rename hex2ascii_return_22_ "hex2ascii_return[22]") (joined + (portref D (instanceref bn_ascii_reg_22_)) + (portref O (instanceref bn_ascii_22__i_1)) + ) + ) + (net (rename hex2ascii_return_24_ "hex2ascii_return[24]") (joined + (portref D (instanceref bn_ascii_reg_24_)) + (portref O (instanceref bn_ascii_24__i_1)) + ) + ) + (net (rename hex2ascii_return_25_ "hex2ascii_return[25]") (joined + (portref D (instanceref bn_ascii_reg_25_)) + (portref O (instanceref bn_ascii_25__i_1)) + ) + ) + (net (rename hex2ascii_return_26_ "hex2ascii_return[26]") (joined + (portref D (instanceref bn_ascii_reg_26_)) + (portref O (instanceref bn_ascii_26__i_1)) + ) + ) + (net (rename hex2ascii_return_27_ "hex2ascii_return[27]") (joined + (portref D (instanceref bn_ascii_reg_27_)) + (portref O (instanceref bn_ascii_27__i_1)) + ) + ) + (net (rename hex2ascii_return_29_ "hex2ascii_return[29]") (joined + (portref D (instanceref bn_ascii_reg_29_)) + (portref O (instanceref bn_ascii_29__i_1)) + ) + ) + (net (rename hex2ascii_return_2_ "hex2ascii_return[2]") (joined + (portref D (instanceref bn_ascii_reg_2_)) + (portref O (instanceref bn_ascii_2__i_1)) + ) + ) + (net (rename hex2ascii_return_30_ "hex2ascii_return[30]") (joined + (portref D (instanceref bn_ascii_reg_30_)) + (portref O (instanceref bn_ascii_30__i_1)) + ) + ) + (net (rename hex2ascii_return_32_ "hex2ascii_return[32]") (joined + (portref D (instanceref bn_ascii_reg_32_)) + (portref O (instanceref bn_ascii_32__i_1)) + ) + ) + (net (rename hex2ascii_return_33_ "hex2ascii_return[33]") (joined + (portref D (instanceref bn_ascii_reg_33_)) + (portref O (instanceref bn_ascii_33__i_1)) + ) + ) + (net (rename hex2ascii_return_34_ "hex2ascii_return[34]") (joined + (portref D (instanceref bn_ascii_reg_34_)) + (portref O (instanceref bn_ascii_34__i_1)) + ) + ) + (net (rename hex2ascii_return_35_ "hex2ascii_return[35]") (joined + (portref D (instanceref bn_ascii_reg_35_)) + (portref O (instanceref bn_ascii_35__i_1)) + ) + ) + (net (rename hex2ascii_return_37_ "hex2ascii_return[37]") (joined + (portref D (instanceref bn_ascii_reg_37_)) + (portref O (instanceref bn_ascii_37__i_1)) + ) + ) + (net (rename hex2ascii_return_38_ "hex2ascii_return[38]") (joined + (portref D (instanceref bn_ascii_reg_38_)) + (portref O (instanceref bn_ascii_38__i_1)) + ) + ) + (net (rename hex2ascii_return_3_ "hex2ascii_return[3]") (joined + (portref D (instanceref bn_ascii_reg_3_)) + (portref O (instanceref bn_ascii_3__i_1)) + ) + ) + (net (rename hex2ascii_return_40_ "hex2ascii_return[40]") (joined + (portref D (instanceref bn_ascii_reg_40_)) + (portref O (instanceref bn_ascii_40__i_1)) + ) + ) + (net (rename hex2ascii_return_41_ "hex2ascii_return[41]") (joined + (portref D (instanceref bn_ascii_reg_41_)) + (portref O (instanceref bn_ascii_41__i_1)) + ) + ) + (net (rename hex2ascii_return_42_ "hex2ascii_return[42]") (joined + (portref D (instanceref bn_ascii_reg_42_)) + (portref O (instanceref bn_ascii_42__i_1)) + ) + ) + (net (rename hex2ascii_return_43_ "hex2ascii_return[43]") (joined + (portref D (instanceref bn_ascii_reg_43_)) + (portref O (instanceref bn_ascii_43__i_1)) + ) + ) + (net (rename hex2ascii_return_45_ "hex2ascii_return[45]") (joined + (portref D (instanceref bn_ascii_reg_45_)) + (portref O (instanceref bn_ascii_45__i_1)) + ) + ) + (net (rename hex2ascii_return_46_ "hex2ascii_return[46]") (joined + (portref D (instanceref bn_ascii_reg_46_)) + (portref O (instanceref bn_ascii_46__i_1)) + ) + ) + (net (rename hex2ascii_return_48_ "hex2ascii_return[48]") (joined + (portref D (instanceref bn_ascii_reg_48_)) + (portref O (instanceref bn_ascii_48__i_1)) + ) + ) + (net (rename hex2ascii_return_49_ "hex2ascii_return[49]") (joined + (portref D (instanceref bn_ascii_reg_49_)) + (portref O (instanceref bn_ascii_49__i_1)) + ) + ) + (net (rename hex2ascii_return_50_ "hex2ascii_return[50]") (joined + (portref D (instanceref bn_ascii_reg_50_)) + (portref O (instanceref bn_ascii_50__i_1)) + ) + ) + (net (rename hex2ascii_return_51_ "hex2ascii_return[51]") (joined + (portref D (instanceref bn_ascii_reg_51_)) + (portref O (instanceref bn_ascii_51__i_1)) + ) + ) + (net (rename hex2ascii_return_53_ "hex2ascii_return[53]") (joined + (portref D (instanceref bn_ascii_reg_53_)) + (portref O (instanceref bn_ascii_53__i_1)) + ) + ) + (net (rename hex2ascii_return_54_ "hex2ascii_return[54]") (joined + (portref D (instanceref bn_ascii_reg_54_)) + (portref O (instanceref bn_ascii_54__i_1)) + ) + ) + (net (rename hex2ascii_return_5_ "hex2ascii_return[5]") (joined + (portref D (instanceref bn_ascii_reg_5_)) + (portref O (instanceref bn_ascii_5__i_1)) + ) + ) + (net (rename hex2ascii_return_6_ "hex2ascii_return[6]") (joined + (portref D (instanceref bn_ascii_reg_6_)) + (portref O (instanceref bn_ascii_6__i_1)) + ) + ) + (net (rename hex2ascii_return_8_ "hex2ascii_return[8]") (joined + (portref D (instanceref bn_ascii_reg_8_)) + (portref O (instanceref bn_ascii_8__i_1)) + ) + ) + (net (rename hex2ascii_return_9_ "hex2ascii_return[9]") (joined + (portref D (instanceref bn_ascii_reg_9_)) + (portref O (instanceref bn_ascii_9__i_1)) + ) + ) + (net initFlag (joined + (portref I0 (instanceref WCS_0__i_2)) + (portref I0 (instanceref initFlag_i_1)) + (portref I0 (instanceref s_axi_awaddr_3__i_1)) + (portref I2 (instanceref s_axi_awvalid_i_1)) + (portref I4 (instanceref s_axi_wdata_4__i_1)) + (portref I4 (instanceref s_axi_wdata_4__i_2)) + (portref I4 (instanceref s_axi_wdata_6__i_1)) + (portref I4 (instanceref s_axi_wstrb_3__i_1)) + (portref I5 (instanceref s_axi_wdata_0__i_1)) + (portref I5 (instanceref s_axi_wdata_1__i_1)) + (portref Q (instanceref initFlag_reg)) + ) + ) + (net initFlag_i_1_n_0 (joined + (portref D (instanceref initFlag_reg)) + (portref O (instanceref initFlag_i_1)) + ) + ) + (net (rename len_cnt_0__i_1_n_0 "len_cnt[0]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_0_)) + (portref O (instanceref len_cnt_0__i_1)) + ) + ) + (net (rename len_cnt_1__i_1_n_0 "len_cnt[1]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_1_)) + (portref O (instanceref len_cnt_1__i_1)) + ) + ) + (net (rename len_cnt_2__i_1_n_0 "len_cnt[2]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_2_)) + (portref O (instanceref len_cnt_2__i_1)) + ) + ) + (net (rename len_cnt_3__i_1_n_0 "len_cnt[3]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_3_)) + (portref O (instanceref len_cnt_3__i_1)) + ) + ) + (net (rename len_cnt_reg__0_0_ "len_cnt_reg__0[0]") (joined + (portref I0 (instanceref len_cnt_0__i_1)) + (portref I0 (instanceref len_cnt_1__i_1)) + (portref I1 (instanceref len_cnt_3__i_1)) + (portref I1 (instanceref wr_byte_num_done_i_1)) + (portref I2 (instanceref len_cnt_2__i_1)) + (portref I4 (instanceref wr_byte_num_done_i_2)) + (portref I5 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref len_cnt_reg_0_)) + ) + ) + (net (rename len_cnt_reg__0_1_ "len_cnt_reg__0[1]") (joined + (portref I1 (instanceref len_cnt_1__i_1)) + (portref I1 (instanceref len_cnt_2__i_1)) + (portref I2 (instanceref len_cnt_3__i_1)) + (portref I2 (instanceref wr_byte_num_done_i_1)) + (portref I3 (instanceref wr_byte_num_done_i_2)) + (portref Q (instanceref len_cnt_reg_1_)) + ) + ) + (net (rename len_cnt_reg__0_2_ "len_cnt_reg__0[2]") (joined + (portref I0 (instanceref len_cnt_2__i_1)) + (portref I0 (instanceref wr_byte_num_done_i_2)) + (portref I3 (instanceref len_cnt_3__i_1)) + (portref I3 (instanceref wr_byte_num_done_i_1)) + (portref Q (instanceref len_cnt_reg_2_)) + ) + ) + (net (rename len_cnt_reg__0_3_ "len_cnt_reg__0[3]") (joined + (portref I0 (instanceref len_cnt_3__i_1)) + (portref I0 (instanceref wr_byte_num_done_i_1)) + (portref Q (instanceref len_cnt_reg_3_)) + ) + ) + (net (rename msg_indx_7__i_1_n_0 "msg_indx[7]_i_1_n_0") (joined + (portref CE (instanceref msg_indx_reg_0_)) + (portref CE (instanceref msg_indx_reg_1_)) + (portref CE (instanceref msg_indx_reg_2_)) + (portref CE (instanceref msg_indx_reg_3_)) + (portref CE (instanceref msg_indx_reg_4_)) + (portref CE (instanceref msg_indx_reg_5_)) + (portref CE (instanceref msg_indx_reg_6_)) + (portref CE (instanceref msg_indx_reg_7_)) + (portref O (instanceref msg_indx_7__i_1)) + ) + ) + (net (rename msg_indx_7__i_3_n_0 "msg_indx[7]_i_3_n_0") (joined + (portref I1 (instanceref msg_indx_6__i_1)) + (portref I1 (instanceref msg_indx_7__i_2)) + (portref O (instanceref msg_indx_7__i_3)) + ) + ) + (net (rename msg_indx_reg__0_0_ "msg_indx_reg__0[0]") (joined + (portref I0 (instanceref msg_indx_0__i_1)) + (portref I0 (instanceref msg_indx_1__i_1)) + (portref I0 (instanceref s_axi_wdata_5__i_2)) + (portref I1 (instanceref s_axi_wdata_0__i_2)) + (portref I1 (instanceref s_axi_wdata_1__i_2)) + (portref I1 (instanceref s_axi_wdata_2__i_2)) + (portref I1 (instanceref s_axi_wdata_2__i_3)) + (portref I1 (instanceref s_axi_wdata_4__i_5)) + (portref I1 (instanceref s_axi_wdata_5__i_6)) + (portref I1 (instanceref s_axi_wdata_6__i_3)) + (portref I2 (instanceref msg_indx_2__i_1)) + (portref I2 (instanceref msg_indx_4__i_1)) + (portref I2 (instanceref msg_indx_7__i_3)) + (portref I2 (instanceref s_axi_wdata_0__i_4)) + (portref I2 (instanceref s_axi_wdata_1__i_5)) + (portref I2 (instanceref s_axi_wdata_2__i_4)) + (portref I2 (instanceref s_axi_wdata_3__i_3)) + (portref I2 (instanceref s_axi_wdata_3__i_4)) + (portref I2 (instanceref s_axi_wdata_4__i_7)) + (portref I2 (instanceref s_axi_wdata_5__i_3)) + (portref I2 (instanceref s_axi_wdata_6__i_4)) + (portref I2 (instanceref s_axi_wdata_6__i_5)) + (portref I2 (instanceref s_axi_wdata_6__i_6)) + (portref I3 (instanceref msg_indx_3__i_1)) + (portref I3 (instanceref msg_indx_5__i_1)) + (portref I3 (instanceref s_axi_wdata_6__i_7)) + (portref I4 (instanceref s_axi_wdata_0__i_5)) + (portref I4 (instanceref s_axi_wdata_1__i_6)) + (portref I4 (instanceref s_axi_wdata_2__i_5)) + (portref I4 (instanceref s_axi_wdata_3__i_2)) + (portref I4 (instanceref s_axi_wdata_3__i_5)) + (portref I4 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref msg_indx_reg_0_)) + ) + ) + (net (rename msg_indx_reg__0_1_ "msg_indx_reg__0[1]") (joined + (portref I0 (instanceref msg_indx_7__i_3)) + (portref I0 (instanceref s_axi_wdata_0__i_2)) + (portref I0 (instanceref s_axi_wdata_1__i_2)) + (portref I0 (instanceref s_axi_wdata_1__i_5)) + (portref I0 (instanceref s_axi_wdata_2__i_2)) + (portref I0 (instanceref s_axi_wdata_4__i_5)) + (portref I0 (instanceref s_axi_wdata_6__i_3)) + (portref I0 (instanceref s_axi_wdata_6__i_6)) + (portref I1 (instanceref msg_indx_1__i_1)) + (portref I1 (instanceref msg_indx_2__i_1)) + (portref I1 (instanceref msg_indx_3__i_1)) + (portref I1 (instanceref msg_indx_5__i_1)) + (portref I1 (instanceref s_axi_wdata_0__i_4)) + (portref I1 (instanceref s_axi_wdata_2__i_4)) + (portref I1 (instanceref s_axi_wdata_3__i_4)) + (portref I1 (instanceref s_axi_wdata_4__i_4)) + (portref I1 (instanceref s_axi_wdata_4__i_7)) + (portref I1 (instanceref s_axi_wdata_5__i_2)) + (portref I2 (instanceref s_axi_wdata_0__i_5)) + (portref I2 (instanceref s_axi_wdata_1__i_6)) + (portref I2 (instanceref s_axi_wdata_2__i_3)) + (portref I2 (instanceref s_axi_wdata_2__i_5)) + (portref I2 (instanceref s_axi_wdata_3__i_5)) + (portref I2 (instanceref s_axi_wdata_4__i_8)) + (portref I2 (instanceref s_axi_wdata_5__i_5)) + (portref I2 (instanceref s_axi_wdata_6__i_7)) + (portref I3 (instanceref s_axi_wdata_3__i_3)) + (portref I3 (instanceref s_axi_wdata_5__i_3)) + (portref I3 (instanceref s_axi_wdata_5__i_6)) + (portref I3 (instanceref s_axi_wdata_6__i_4)) + (portref I4 (instanceref msg_indx_4__i_1)) + (portref I4 (instanceref s_axi_wdata_6__i_5)) + (portref I4 (instanceref upg_done_o_i_2)) + (portref I5 (instanceref s_axi_wdata_3__i_2)) + (portref Q (instanceref msg_indx_reg_1_)) + ) + ) + (net (rename msg_indx_reg__0_2_ "msg_indx_reg__0[2]") (joined + (portref I0 (instanceref msg_indx_2__i_1)) + (portref I0 (instanceref s_axi_wdata_4__i_7)) + (portref I1 (instanceref msg_indx_7__i_3)) + (portref I1 (instanceref s_axi_wdata_4__i_8)) + (portref I1 (instanceref s_axi_wdata_5__i_4)) + (portref I1 (instanceref s_axi_wdata_6__i_7)) + (portref I2 (instanceref msg_indx_3__i_1)) + (portref I2 (instanceref msg_indx_5__i_1)) + (portref I2 (instanceref s_axi_wdata_0__i_2)) + (portref I2 (instanceref s_axi_wdata_1__i_2)) + (portref I2 (instanceref s_axi_wdata_2__i_2)) + (portref I2 (instanceref s_axi_wdata_4__i_4)) + (portref I2 (instanceref s_axi_wdata_4__i_5)) + (portref I2 (instanceref s_axi_wdata_5__i_2)) + (portref I2 (instanceref s_axi_wdata_6__i_3)) + (portref I3 (instanceref msg_indx_4__i_1)) + (portref I3 (instanceref s_axi_wdata_2__i_3)) + (portref I3 (instanceref s_axi_wdata_3__i_2)) + (portref I3 (instanceref upg_done_o_i_2)) + (portref I4 (instanceref s_axi_wdata_0__i_4)) + (portref I4 (instanceref s_axi_wdata_2__i_4)) + (portref I4 (instanceref s_axi_wdata_3__i_3)) + (portref I4 (instanceref s_axi_wdata_3__i_4)) + (portref I4 (instanceref s_axi_wdata_5__i_3)) + (portref I4 (instanceref s_axi_wdata_5__i_6)) + (portref I4 (instanceref s_axi_wdata_6__i_4)) + (portref I4 (instanceref s_axi_wdata_6__i_6)) + (portref I5 (instanceref s_axi_wdata_1__i_5)) + (portref Q (instanceref msg_indx_reg_2_)) + ) + ) + (net (rename msg_indx_reg__0_3_ "msg_indx_reg__0[3]") (joined + (portref I0 (instanceref msg_indx_3__i_1)) + (portref I0 (instanceref s_axi_wdata_4__i_8)) + (portref I0 (instanceref s_axi_wdata_5__i_4)) + (portref I0 (instanceref upg_done_o_i_3)) + (portref I1 (instanceref msg_indx_4__i_1)) + (portref I2 (instanceref s_axi_wdata_3__i_2)) + (portref I3 (instanceref msg_indx_7__i_3)) + (portref I3 (instanceref s_axi_wdata_0__i_2)) + (portref I3 (instanceref s_axi_wdata_2__i_2)) + (portref I3 (instanceref s_axi_wdata_4__i_4)) + (portref I3 (instanceref s_axi_wdata_5__i_2)) + (portref I3 (instanceref s_axi_wdata_6__i_2)) + (portref I4 (instanceref msg_indx_5__i_1)) + (portref I4 (instanceref s_axi_wdata_2__i_1)) + (portref I4 (instanceref s_axi_wdata_3__i_1)) + (portref I4 (instanceref s_axi_wdata_4__i_5)) + (portref I5 (instanceref s_axi_wdata_0__i_3)) + (portref I5 (instanceref s_axi_wdata_1__i_2)) + (portref I5 (instanceref s_axi_wdata_1__i_3)) + (portref I5 (instanceref s_axi_wdata_2__i_3)) + (portref I5 (instanceref s_axi_wdata_3__i_3)) + (portref I5 (instanceref s_axi_wdata_5__i_3)) + (portref I5 (instanceref s_axi_wdata_6__i_3)) + (portref I5 (instanceref s_axi_wdata_6__i_4)) + (portref Q (instanceref msg_indx_reg_3_)) + ) + ) + (net (rename msg_indx_reg__0_4_ "msg_indx_reg__0[4]") (joined + (portref I0 (instanceref msg_indx_4__i_1)) + (portref I1 (instanceref s_axi_wdata_3__i_2)) + (portref I1 (instanceref upg_done_o_i_3)) + (portref I3 (instanceref s_axi_wdata_1__i_4)) + (portref I3 (instanceref s_axi_wdata_4__i_5)) + (portref I4 (instanceref msg_indx_7__i_3)) + (portref I4 (instanceref s_axi_wdata_0__i_2)) + (portref I4 (instanceref s_axi_wdata_1__i_2)) + (portref I4 (instanceref s_axi_wdata_2__i_2)) + (portref I4 (instanceref s_axi_wdata_5__i_2)) + (portref I4 (instanceref s_axi_wdata_6__i_3)) + (portref I5 (instanceref msg_indx_5__i_1)) + (portref Q (instanceref msg_indx_reg_4_)) + ) + ) + (net (rename msg_indx_reg__0_5_ "msg_indx_reg__0[5]") (joined + (portref I0 (instanceref msg_indx_5__i_1)) + (portref I0 (instanceref s_axi_wdata_3__i_2)) + (portref I2 (instanceref s_axi_wdata_1__i_4)) + (portref I2 (instanceref upg_done_o_i_2)) + (portref I3 (instanceref s_axi_wdata_1__i_2)) + (portref I3 (instanceref s_axi_wdata_6__i_3)) + (portref I5 (instanceref msg_indx_7__i_3)) + (portref I5 (instanceref s_axi_wdata_0__i_2)) + (portref I5 (instanceref s_axi_wdata_2__i_2)) + (portref I5 (instanceref s_axi_wdata_4__i_5)) + (portref I5 (instanceref s_axi_wdata_5__i_2)) + (portref Q (instanceref msg_indx_reg_5_)) + ) + ) + (net (rename msg_indx_reg__1_6_ "msg_indx_reg__1[6]") (joined + (portref I0 (instanceref msg_indx_6__i_1)) + (portref I1 (instanceref s_axi_wdata_1__i_4)) + (portref I1 (instanceref upg_done_o_i_2)) + (portref I2 (instanceref msg_indx_7__i_2)) + (portref Q (instanceref msg_indx_reg_6_)) + ) + ) + (net (rename msg_indx_reg__1_7_ "msg_indx_reg__1[7]") (joined + (portref I0 (instanceref msg_indx_7__i_2)) + (portref I0 (instanceref s_axi_wdata_1__i_4)) + (portref I0 (instanceref upg_done_o_i_2)) + (portref Q (instanceref msg_indx_reg_7_)) + ) + ) + (net oldInitF_i_1_n_0 (joined + (portref D (instanceref oldInitF_reg)) + (portref O (instanceref oldInitF_i_1)) + ) + ) + (net oldInitF_reg_n_0 (joined + (portref I1 (instanceref WCS_0__i_2)) + (portref I4 (instanceref oldInitF_i_1)) + (portref Q (instanceref oldInitF_reg)) + ) + ) + (net (rename p_0_in_0_ "p_0_in[0]") (joined + (portref D (instanceref upg_adr_o_reg_0_)) + (portref Q (instanceref byte_cnt_reg_2_)) + (portref (member S 2) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename p_0_in_10_ "p_0_in[10]") (joined + (portref D (instanceref upg_adr_o_reg_10_)) + (portref Q (instanceref byte_cnt_reg_12_)) + (portref (member S 0) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in_11_ "p_0_in[11]") (joined + (portref D (instanceref upg_adr_o_reg_11_)) + (portref Q (instanceref byte_cnt_reg_13_)) + (portref (member S 3) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_12_ "p_0_in[12]") (joined + (portref D (instanceref upg_adr_o_reg_12_)) + (portref Q (instanceref byte_cnt_reg_14_)) + (portref (member S 2) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_13_ "p_0_in[13]") (joined + (portref D (instanceref upg_adr_o_reg_13_)) + (portref Q (instanceref byte_cnt_reg_15_)) + (portref (member S 1) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_14_ "p_0_in[14]") (joined + (portref D (instanceref upg_adr_o_reg_14_)) + (portref Q (instanceref byte_cnt_reg_16_)) + (portref (member S 0) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_1_ "p_0_in[1]") (joined + (portref D (instanceref upg_adr_o_reg_1_)) + (portref Q (instanceref byte_cnt_reg_3_)) + (portref (member S 1) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename p_0_in_2_ "p_0_in[2]") (joined + (portref D (instanceref upg_adr_o_reg_2_)) + (portref Q (instanceref byte_cnt_reg_4_)) + (portref (member S 0) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename p_0_in_3_ "p_0_in[3]") (joined + (portref D (instanceref upg_adr_o_reg_3_)) + (portref Q (instanceref byte_cnt_reg_5_)) + (portref (member S 3) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_4_ "p_0_in[4]") (joined + (portref D (instanceref upg_adr_o_reg_4_)) + (portref Q (instanceref byte_cnt_reg_6_)) + (portref (member S 2) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_5_ "p_0_in[5]") (joined + (portref D (instanceref upg_adr_o_reg_5_)) + (portref Q (instanceref byte_cnt_reg_7_)) + (portref (member S 1) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_6_ "p_0_in[6]") (joined + (portref D (instanceref upg_adr_o_reg_6_)) + (portref Q (instanceref byte_cnt_reg_8_)) + (portref (member S 0) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_7_ "p_0_in[7]") (joined + (portref D (instanceref upg_adr_o_reg_7_)) + (portref Q (instanceref byte_cnt_reg_9_)) + (portref (member S 3) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in_8_ "p_0_in[8]") (joined + (portref D (instanceref upg_adr_o_reg_8_)) + (portref Q (instanceref byte_cnt_reg_10_)) + (portref (member S 2) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in_9_ "p_0_in[9]") (joined + (portref D (instanceref upg_adr_o_reg_9_)) + (portref Q (instanceref byte_cnt_reg_11_)) + (portref (member S 1) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in__0_0_ "p_0_in__0[0]") (joined + (portref D (instanceref msg_indx_reg_0_)) + (portref O (instanceref msg_indx_0__i_1)) + ) + ) + (net (rename p_0_in__0_1_ "p_0_in__0[1]") (joined + (portref D (instanceref msg_indx_reg_1_)) + (portref O (instanceref msg_indx_1__i_1)) + ) + ) + (net (rename p_0_in__0_2_ "p_0_in__0[2]") (joined + (portref D (instanceref msg_indx_reg_2_)) + (portref O (instanceref msg_indx_2__i_1)) + ) + ) + (net (rename p_0_in__0_3_ "p_0_in__0[3]") (joined + (portref D (instanceref msg_indx_reg_3_)) + (portref O (instanceref msg_indx_3__i_1)) + ) + ) + (net (rename p_0_in__0_4_ "p_0_in__0[4]") (joined + (portref D (instanceref msg_indx_reg_4_)) + (portref O (instanceref msg_indx_4__i_1)) + ) + ) + (net (rename p_0_in__0_5_ "p_0_in__0[5]") (joined + (portref D (instanceref msg_indx_reg_5_)) + (portref O (instanceref msg_indx_5__i_1)) + ) + ) + (net (rename p_0_in__0_6_ "p_0_in__0[6]") (joined + (portref D (instanceref msg_indx_reg_6_)) + (portref O (instanceref msg_indx_6__i_1)) + ) + ) + (net (rename p_0_in__0_7_ "p_0_in__0[7]") (joined + (portref D (instanceref msg_indx_reg_7_)) + (portref O (instanceref msg_indx_7__i_2)) + ) + ) + (net rdStat (joined + (portref I (instanceref rdStat_BUFG_inst)) + (portref I0 (instanceref s_axi_araddr_3__i_1)) + (portref I0 (instanceref s_axi_arvalid_i_3)) + (portref I2 (instanceref RCS_1__i_1)) + (portref I2 (instanceref statReg_0__i_1)) + (portref I3 (instanceref rdStat_i_1)) + (portref I5 (instanceref uart_rdat_7__i_1)) + (portref Q (instanceref rdStat_reg)) + ) + ) + (net rdStat_BUFG (joined + (portref C (instanceref bn_ascii_reg_0_)) + (portref C (instanceref bn_ascii_reg_10_)) + (portref C (instanceref bn_ascii_reg_11_)) + (portref C (instanceref bn_ascii_reg_13_)) + (portref C (instanceref bn_ascii_reg_14_)) + (portref C (instanceref bn_ascii_reg_16_)) + (portref C (instanceref bn_ascii_reg_17_)) + (portref C (instanceref bn_ascii_reg_18_)) + (portref C (instanceref bn_ascii_reg_19_)) + (portref C (instanceref bn_ascii_reg_1_)) + (portref C (instanceref bn_ascii_reg_21_)) + (portref C (instanceref bn_ascii_reg_22_)) + (portref C (instanceref bn_ascii_reg_24_)) + (portref C (instanceref bn_ascii_reg_25_)) + (portref C (instanceref bn_ascii_reg_26_)) + (portref C (instanceref bn_ascii_reg_27_)) + (portref C (instanceref bn_ascii_reg_29_)) + (portref C (instanceref bn_ascii_reg_2_)) + (portref C (instanceref bn_ascii_reg_30_)) + (portref C (instanceref bn_ascii_reg_32_)) + (portref C (instanceref bn_ascii_reg_33_)) + (portref C (instanceref bn_ascii_reg_34_)) + (portref C (instanceref bn_ascii_reg_35_)) + (portref C (instanceref bn_ascii_reg_37_)) + (portref C (instanceref bn_ascii_reg_38_)) + (portref C (instanceref bn_ascii_reg_3_)) + (portref C (instanceref bn_ascii_reg_40_)) + (portref C (instanceref bn_ascii_reg_41_)) + (portref C (instanceref bn_ascii_reg_42_)) + (portref C (instanceref bn_ascii_reg_43_)) + (portref C (instanceref bn_ascii_reg_45_)) + (portref C (instanceref bn_ascii_reg_46_)) + (portref C (instanceref bn_ascii_reg_48_)) + (portref C (instanceref bn_ascii_reg_49_)) + (portref C (instanceref bn_ascii_reg_50_)) + (portref C (instanceref bn_ascii_reg_51_)) + (portref C (instanceref bn_ascii_reg_53_)) + (portref C (instanceref bn_ascii_reg_54_)) + (portref C (instanceref bn_ascii_reg_56_)) + (portref C (instanceref bn_ascii_reg_57_)) + (portref C (instanceref bn_ascii_reg_58_)) + (portref C (instanceref bn_ascii_reg_59_)) + (portref C (instanceref bn_ascii_reg_5_)) + (portref C (instanceref bn_ascii_reg_61_)) + (portref C (instanceref bn_ascii_reg_62_)) + (portref C (instanceref bn_ascii_reg_6_)) + (portref C (instanceref bn_ascii_reg_8_)) + (portref C (instanceref bn_ascii_reg_9_)) + (portref C (instanceref byte_cnt_reg_0_)) + (portref C (instanceref byte_cnt_reg_10_)) + (portref C (instanceref byte_cnt_reg_11_)) + (portref C (instanceref byte_cnt_reg_12_)) + (portref C (instanceref byte_cnt_reg_13_)) + (portref C (instanceref byte_cnt_reg_14_)) + (portref C (instanceref byte_cnt_reg_15_)) + (portref C (instanceref byte_cnt_reg_16_)) + (portref C (instanceref byte_cnt_reg_17_)) + (portref C (instanceref byte_cnt_reg_18_)) + (portref C (instanceref byte_cnt_reg_19_)) + (portref C (instanceref byte_cnt_reg_1_)) + (portref C (instanceref byte_cnt_reg_20_)) + (portref C (instanceref byte_cnt_reg_21_)) + (portref C (instanceref byte_cnt_reg_22_)) + (portref C (instanceref byte_cnt_reg_23_)) + (portref C (instanceref byte_cnt_reg_24_)) + (portref C (instanceref byte_cnt_reg_25_)) + (portref C (instanceref byte_cnt_reg_26_)) + (portref C (instanceref byte_cnt_reg_27_)) + (portref C (instanceref byte_cnt_reg_28_)) + (portref C (instanceref byte_cnt_reg_29_)) + (portref C (instanceref byte_cnt_reg_2_)) + (portref C (instanceref byte_cnt_reg_30_)) + (portref C (instanceref byte_cnt_reg_31_)) + (portref C (instanceref byte_cnt_reg_3_)) + (portref C (instanceref byte_cnt_reg_4_)) + (portref C (instanceref byte_cnt_reg_5_)) + (portref C (instanceref byte_cnt_reg_6_)) + (portref C (instanceref byte_cnt_reg_7_)) + (portref C (instanceref byte_cnt_reg_8_)) + (portref C (instanceref byte_cnt_reg_9_)) + (portref C (instanceref byte_len_reg_0_)) + (portref C (instanceref byte_len_reg_1_)) + (portref C (instanceref byte_len_reg_2_)) + (portref C (instanceref byte_len_reg_3_)) + (portref C (instanceref byte_len_reg_4_)) + (portref C (instanceref byte_len_reg_5_)) + (portref C (instanceref byte_len_reg_6_)) + (portref C (instanceref byte_len_reg_7_)) + (portref C (instanceref byte_num_reg_0_)) + (portref C (instanceref byte_num_reg_10_)) + (portref C (instanceref byte_num_reg_11_)) + (portref C (instanceref byte_num_reg_12_)) + (portref C (instanceref byte_num_reg_13_)) + (portref C (instanceref byte_num_reg_14_)) + (portref C (instanceref byte_num_reg_15_)) + (portref C (instanceref byte_num_reg_16_)) + (portref C (instanceref byte_num_reg_17_)) + (portref C (instanceref byte_num_reg_18_)) + (portref C (instanceref byte_num_reg_19_)) + (portref C (instanceref byte_num_reg_1_)) + (portref C (instanceref byte_num_reg_20_)) + (portref C (instanceref byte_num_reg_21_)) + (portref C (instanceref byte_num_reg_22_)) + (portref C (instanceref byte_num_reg_23_)) + (portref C (instanceref byte_num_reg_24_)) + (portref C (instanceref byte_num_reg_25_)) + (portref C (instanceref byte_num_reg_26_)) + (portref C (instanceref byte_num_reg_27_)) + (portref C (instanceref byte_num_reg_28_)) + (portref C (instanceref byte_num_reg_29_)) + (portref C (instanceref byte_num_reg_2_)) + (portref C (instanceref byte_num_reg_30_)) + (portref C (instanceref byte_num_reg_31_)) + (portref C (instanceref byte_num_reg_3_)) + (portref C (instanceref byte_num_reg_4_)) + (portref C (instanceref byte_num_reg_5_)) + (portref C (instanceref byte_num_reg_6_)) + (portref C (instanceref byte_num_reg_7_)) + (portref C (instanceref byte_num_reg_8_)) + (portref C (instanceref byte_num_reg_9_)) + (portref C (instanceref dbuf_reg_0_)) + (portref C (instanceref dbuf_reg_10_)) + (portref C (instanceref dbuf_reg_11_)) + (portref C (instanceref dbuf_reg_12_)) + (portref C (instanceref dbuf_reg_13_)) + (portref C (instanceref dbuf_reg_14_)) + (portref C (instanceref dbuf_reg_15_)) + (portref C (instanceref dbuf_reg_16_)) + (portref C (instanceref dbuf_reg_17_)) + (portref C (instanceref dbuf_reg_18_)) + (portref C (instanceref dbuf_reg_19_)) + (portref C (instanceref dbuf_reg_1_)) + (portref C (instanceref dbuf_reg_20_)) + (portref C (instanceref dbuf_reg_21_)) + (portref C (instanceref dbuf_reg_22_)) + (portref C (instanceref dbuf_reg_23_)) + (portref C (instanceref dbuf_reg_2_)) + (portref C (instanceref dbuf_reg_3_)) + (portref C (instanceref dbuf_reg_4_)) + (portref C (instanceref dbuf_reg_5_)) + (portref C (instanceref dbuf_reg_6_)) + (portref C (instanceref dbuf_reg_7_)) + (portref C (instanceref dbuf_reg_8_)) + (portref C (instanceref dbuf_reg_9_)) + (portref C (instanceref disp_reg_0_)) + (portref C (instanceref disp_reg_1_)) + (portref C (instanceref disp_reg_2_)) + (portref C (instanceref disp_reg_3_)) + (portref C (instanceref disp_reg_4_)) + (portref C (instanceref disp_reg_5_)) + (portref C (instanceref disp_reg_6_)) + (portref C (instanceref disp_reg_7_)) + (portref C (instanceref len_cnt_reg_0_)) + (portref C (instanceref len_cnt_reg_1_)) + (portref C (instanceref len_cnt_reg_2_)) + (portref C (instanceref len_cnt_reg_3_)) + (portref C (instanceref recv_done_reg)) + (portref C (instanceref rx_done_reg)) + (portref C (instanceref upg_adr_o_reg_0_)) + (portref C (instanceref upg_adr_o_reg_10_)) + (portref C (instanceref upg_adr_o_reg_11_)) + (portref C (instanceref upg_adr_o_reg_12_)) + (portref C (instanceref upg_adr_o_reg_13_)) + (portref C (instanceref upg_adr_o_reg_14_)) + (portref C (instanceref upg_adr_o_reg_1_)) + (portref C (instanceref upg_adr_o_reg_2_)) + (portref C (instanceref upg_adr_o_reg_3_)) + (portref C (instanceref upg_adr_o_reg_4_)) + (portref C (instanceref upg_adr_o_reg_5_)) + (portref C (instanceref upg_adr_o_reg_6_)) + (portref C (instanceref upg_adr_o_reg_7_)) + (portref C (instanceref upg_adr_o_reg_8_)) + (portref C (instanceref upg_adr_o_reg_9_)) + (portref C (instanceref upg_dat_o_reg_0_)) + (portref C (instanceref upg_dat_o_reg_10_)) + (portref C (instanceref upg_dat_o_reg_11_)) + (portref C (instanceref upg_dat_o_reg_12_)) + (portref C (instanceref upg_dat_o_reg_13_)) + (portref C (instanceref upg_dat_o_reg_14_)) + (portref C (instanceref upg_dat_o_reg_15_)) + (portref C (instanceref upg_dat_o_reg_16_)) + (portref C (instanceref upg_dat_o_reg_17_)) + (portref C (instanceref upg_dat_o_reg_18_)) + (portref C (instanceref upg_dat_o_reg_19_)) + (portref C (instanceref upg_dat_o_reg_1_)) + (portref C (instanceref upg_dat_o_reg_20_)) + (portref C (instanceref upg_dat_o_reg_21_)) + (portref C (instanceref upg_dat_o_reg_22_)) + (portref C (instanceref upg_dat_o_reg_23_)) + (portref C (instanceref upg_dat_o_reg_24_)) + (portref C (instanceref upg_dat_o_reg_25_)) + (portref C (instanceref upg_dat_o_reg_26_)) + (portref C (instanceref upg_dat_o_reg_27_)) + (portref C (instanceref upg_dat_o_reg_28_)) + (portref C (instanceref upg_dat_o_reg_29_)) + (portref C (instanceref upg_dat_o_reg_2_)) + (portref C (instanceref upg_dat_o_reg_30_)) + (portref C (instanceref upg_dat_o_reg_31_)) + (portref C (instanceref upg_dat_o_reg_3_)) + (portref C (instanceref upg_dat_o_reg_4_)) + (portref C (instanceref upg_dat_o_reg_5_)) + (portref C (instanceref upg_dat_o_reg_6_)) + (portref C (instanceref upg_dat_o_reg_7_)) + (portref C (instanceref upg_dat_o_reg_8_)) + (portref C (instanceref upg_dat_o_reg_9_)) + (portref C (instanceref upg_wen_o_reg)) + (portref C (instanceref wr_byte_len_done_reg)) + (portref C (instanceref wr_byte_num_done_reg)) + (portref O (instanceref rdStat_BUFG_inst)) + ) + ) + (net rdStat_i_1_n_0 (joined + (portref D (instanceref rdStat_reg)) + (portref O (instanceref rdStat_i_1)) + ) + ) + (net recv_done0 (joined + (portref (member CO 0) (instanceref recv_done_reg_i_2)) + (portref I0 (instanceref recv_done_i_1)) + ) + ) + (net (rename recv_done1_0_ "recv_done1[0]") (joined + (portref D (instanceref byte_cnt_reg_0_)) + (portref O (instanceref byte_cnt_0__i_1)) + ) + ) + (net (rename recv_done1_10_ "recv_done1[10]") (joined + (portref D (instanceref byte_cnt_reg_10_)) + (portref I2 (instanceref recv_done_i_24)) + (portref I3 (instanceref recv_done_i_28)) + (portref (member O 2) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename recv_done1_11_ "recv_done1[11]") (joined + (portref D (instanceref byte_cnt_reg_11_)) + (portref I0 (instanceref recv_done_i_24)) + (portref I1 (instanceref recv_done_i_28)) + (portref (member O 1) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename recv_done1_12_ "recv_done1[12]") (joined + (portref D (instanceref byte_cnt_reg_12_)) + (portref I2 (instanceref recv_done_i_23)) + (portref I3 (instanceref recv_done_i_27)) + (portref (member O 0) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename recv_done1_13_ "recv_done1[13]") (joined + (portref D (instanceref byte_cnt_reg_13_)) + (portref I0 (instanceref recv_done_i_23)) + (portref I1 (instanceref recv_done_i_27)) + (portref (member O 3) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_14_ "recv_done1[14]") (joined + (portref D (instanceref byte_cnt_reg_14_)) + (portref I2 (instanceref recv_done_i_22)) + (portref I3 (instanceref recv_done_i_26)) + (portref (member O 2) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_15_ "recv_done1[15]") (joined + (portref D (instanceref byte_cnt_reg_15_)) + (portref I0 (instanceref recv_done_i_22)) + (portref I1 (instanceref recv_done_i_26)) + (portref (member O 1) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_16_ "recv_done1[16]") (joined + (portref D (instanceref byte_cnt_reg_16_)) + (portref I2 (instanceref recv_done_i_16)) + (portref I3 (instanceref recv_done_i_20)) + (portref (member O 0) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_17_ "recv_done1[17]") (joined + (portref D (instanceref byte_cnt_reg_17_)) + (portref I0 (instanceref recv_done_i_16)) + (portref I1 (instanceref recv_done_i_20)) + (portref (member O 3) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_18_ "recv_done1[18]") (joined + (portref D (instanceref byte_cnt_reg_18_)) + (portref I2 (instanceref recv_done_i_15)) + (portref I3 (instanceref recv_done_i_19)) + (portref (member O 2) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_19_ "recv_done1[19]") (joined + (portref D (instanceref byte_cnt_reg_19_)) + (portref I0 (instanceref recv_done_i_15)) + (portref I1 (instanceref recv_done_i_19)) + (portref (member O 1) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_1_ "recv_done1[1]") (joined + (portref D (instanceref byte_cnt_reg_1_)) + (portref I0 (instanceref recv_done_i_33)) + (portref I3 (instanceref recv_done_i_37)) + (portref (member O 3) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_20_ "recv_done1[20]") (joined + (portref D (instanceref byte_cnt_reg_20_)) + (portref I2 (instanceref recv_done_i_14)) + (portref I3 (instanceref recv_done_i_18)) + (portref (member O 0) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_21_ "recv_done1[21]") (joined + (portref D (instanceref byte_cnt_reg_21_)) + (portref I0 (instanceref recv_done_i_14)) + (portref I1 (instanceref recv_done_i_18)) + (portref (member O 3) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_22_ "recv_done1[22]") (joined + (portref D (instanceref byte_cnt_reg_22_)) + (portref I2 (instanceref recv_done_i_13)) + (portref I3 (instanceref recv_done_i_17)) + (portref (member O 2) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_23_ "recv_done1[23]") (joined + (portref D (instanceref byte_cnt_reg_23_)) + (portref I0 (instanceref recv_done_i_13)) + (portref I1 (instanceref recv_done_i_17)) + (portref (member O 1) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_24_ "recv_done1[24]") (joined + (portref D (instanceref byte_cnt_reg_24_)) + (portref I2 (instanceref recv_done_i_7)) + (portref I3 (instanceref recv_done_i_11)) + (portref (member O 0) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_25_ "recv_done1[25]") (joined + (portref D (instanceref byte_cnt_reg_25_)) + (portref I0 (instanceref recv_done_i_7)) + (portref I1 (instanceref recv_done_i_11)) + (portref (member O 3) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_26_ "recv_done1[26]") (joined + (portref D (instanceref byte_cnt_reg_26_)) + (portref I2 (instanceref recv_done_i_6)) + (portref I3 (instanceref recv_done_i_10)) + (portref (member O 2) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_27_ "recv_done1[27]") (joined + (portref D (instanceref byte_cnt_reg_27_)) + (portref I0 (instanceref recv_done_i_6)) + (portref I1 (instanceref recv_done_i_10)) + (portref (member O 1) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_28_ "recv_done1[28]") (joined + (portref D (instanceref byte_cnt_reg_28_)) + (portref I2 (instanceref recv_done_i_5)) + (portref I3 (instanceref recv_done_i_9)) + (portref (member O 0) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_29_ "recv_done1[29]") (joined + (portref D (instanceref byte_cnt_reg_29_)) + (portref I0 (instanceref recv_done_i_5)) + (portref I1 (instanceref recv_done_i_9)) + (portref (member O 3) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename recv_done1_2_ "recv_done1[2]") (joined + (portref D (instanceref byte_cnt_reg_2_)) + (portref I2 (instanceref recv_done_i_32)) + (portref I3 (instanceref recv_done_i_36)) + (portref (member O 2) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_30_ "recv_done1[30]") (joined + (portref D (instanceref byte_cnt_reg_30_)) + (portref I2 (instanceref recv_done_i_4)) + (portref I3 (instanceref recv_done_i_8)) + (portref (member O 2) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename recv_done1_31_ "recv_done1[31]") (joined + (portref D (instanceref byte_cnt_reg_31_)) + (portref I0 (instanceref recv_done_i_4)) + (portref I1 (instanceref recv_done_i_8)) + (portref (member O 1) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename recv_done1_3_ "recv_done1[3]") (joined + (portref D (instanceref byte_cnt_reg_3_)) + (portref I0 (instanceref recv_done_i_32)) + (portref I1 (instanceref recv_done_i_36)) + (portref (member O 1) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_4_ "recv_done1[4]") (joined + (portref D (instanceref byte_cnt_reg_4_)) + (portref I2 (instanceref recv_done_i_31)) + (portref I3 (instanceref recv_done_i_35)) + (portref (member O 0) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_5_ "recv_done1[5]") (joined + (portref D (instanceref byte_cnt_reg_5_)) + (portref I0 (instanceref recv_done_i_31)) + (portref I1 (instanceref recv_done_i_35)) + (portref (member O 3) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_6_ "recv_done1[6]") (joined + (portref D (instanceref byte_cnt_reg_6_)) + (portref I2 (instanceref recv_done_i_30)) + (portref I3 (instanceref recv_done_i_34)) + (portref (member O 2) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_7_ "recv_done1[7]") (joined + (portref D (instanceref byte_cnt_reg_7_)) + (portref I0 (instanceref recv_done_i_30)) + (portref I1 (instanceref recv_done_i_34)) + (portref (member O 1) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_8_ "recv_done1[8]") (joined + (portref D (instanceref byte_cnt_reg_8_)) + (portref I2 (instanceref recv_done_i_25)) + (portref I3 (instanceref recv_done_i_29)) + (portref (member O 0) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_9_ "recv_done1[9]") (joined + (portref D (instanceref byte_cnt_reg_9_)) + (portref I0 (instanceref recv_done_i_25)) + (portref I1 (instanceref recv_done_i_29)) + (portref (member O 3) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net recv_done_i_10_n_0 (joined + (portref O (instanceref recv_done_i_10)) + (portref (member S 2) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_i_11_n_0 (joined + (portref O (instanceref recv_done_i_11)) + (portref (member S 3) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_i_13_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_13)) + ) + ) + (net recv_done_i_14_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_14)) + ) + ) + (net recv_done_i_15_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_15)) + ) + ) + (net recv_done_i_16_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_16)) + ) + ) + (net recv_done_i_17_n_0 (joined + (portref O (instanceref recv_done_i_17)) + (portref (member S 0) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_18_n_0 (joined + (portref O (instanceref recv_done_i_18)) + (portref (member S 1) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_19_n_0 (joined + (portref O (instanceref recv_done_i_19)) + (portref (member S 2) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_1_n_0 (joined + (portref D (instanceref recv_done_reg)) + (portref O (instanceref recv_done_i_1)) + ) + ) + (net recv_done_i_20_n_0 (joined + (portref O (instanceref recv_done_i_20)) + (portref (member S 3) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_22_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_22)) + ) + ) + (net recv_done_i_23_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_23)) + ) + ) + (net recv_done_i_24_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_24)) + ) + ) + (net recv_done_i_25_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_25)) + ) + ) + (net recv_done_i_26_n_0 (joined + (portref O (instanceref recv_done_i_26)) + (portref (member S 0) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_27_n_0 (joined + (portref O (instanceref recv_done_i_27)) + (portref (member S 1) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_28_n_0 (joined + (portref O (instanceref recv_done_i_28)) + (portref (member S 2) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_29_n_0 (joined + (portref O (instanceref recv_done_i_29)) + (portref (member S 3) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_30_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_30)) + ) + ) + (net recv_done_i_31_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_31)) + ) + ) + (net recv_done_i_32_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_32)) + ) + ) + (net recv_done_i_33_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_33)) + ) + ) + (net recv_done_i_34_n_0 (joined + (portref O (instanceref recv_done_i_34)) + (portref (member S 0) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_35_n_0 (joined + (portref O (instanceref recv_done_i_35)) + (portref (member S 1) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_36_n_0 (joined + (portref O (instanceref recv_done_i_36)) + (portref (member S 2) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_37_n_0 (joined + (portref O (instanceref recv_done_i_37)) + (portref (member S 3) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_4_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_4)) + ) + ) + (net recv_done_i_5_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_5)) + ) + ) + (net recv_done_i_6_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_6)) + ) + ) + (net recv_done_i_7_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_7)) + ) + ) + (net recv_done_i_8_n_0 (joined + (portref O (instanceref recv_done_i_8)) + (portref (member S 0) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_i_9_n_0 (joined + (portref O (instanceref recv_done_i_9)) + (portref (member S 1) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_12_n_0 (joined + (portref CI (instanceref recv_done_reg_i_3)) + (portref (member CO 0) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_12_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_12_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_12_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_21_n_0 (joined + (portref CI (instanceref recv_done_reg_i_12)) + (portref (member CO 0) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_21_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_21_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_21_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_2_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_2_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_2_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_3_n_0 (joined + (portref CI (instanceref recv_done_reg_i_2)) + (portref (member CO 0) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_i_3_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_i_3_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_i_3_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_n_0 (joined + (portref I0 (instanceref byte_cnt_31__i_1)) + (portref I0 (instanceref disp_5__i_2)) + (portref I0 (instanceref disp_5__i_4)) + (portref I0 (instanceref disp_7__i_1)) + (portref I0 (instanceref rx_done_i_1)) + (portref I1 (instanceref disp_3__i_2)) + (portref I1 (instanceref disp_6__i_1)) + (portref I1 (instanceref disp_6__i_2)) + (portref I1 (instanceref upg_wen_o_i_4)) + (portref I3 (instanceref disp_0__i_1)) + (portref I3 (instanceref disp_1__i_3)) + (portref I3 (instanceref disp_2__i_1)) + (portref I3 (instanceref disp_5__i_3)) + (portref I4 (instanceref disp_1__i_1)) + (portref I4 (instanceref disp_2__i_2)) + (portref I4 (instanceref recv_done_i_1)) + (portref I4 (instanceref upg_wen_o_i_6)) + (portref I5 (instanceref disp_3__i_1)) + (portref I5 (instanceref disp_4__i_1)) + (portref Q (instanceref recv_done_reg)) + ) + ) + (net (rename rwait_cnt_0_ "rwait_cnt[0]") (joined + (portref D (instanceref rwait_cnt_reg_0_)) + (portref O (instanceref rwait_cnt_0__i_1)) + ) + ) + (net (rename rwait_cnt_10_ "rwait_cnt[10]") (joined + (portref D (instanceref rwait_cnt_reg_10_)) + (portref O (instanceref rwait_cnt_10__i_1)) + ) + ) + (net (rename rwait_cnt_11_ "rwait_cnt[11]") (joined + (portref D (instanceref rwait_cnt_reg_11_)) + (portref O (instanceref rwait_cnt_11__i_1)) + ) + ) + (net (rename rwait_cnt_12_ "rwait_cnt[12]") (joined + (portref D (instanceref rwait_cnt_reg_12_)) + (portref O (instanceref rwait_cnt_12__i_1)) + ) + ) + (net (rename rwait_cnt_13_ "rwait_cnt[13]") (joined + (portref D (instanceref rwait_cnt_reg_13_)) + (portref O (instanceref rwait_cnt_13__i_1)) + ) + ) + (net (rename rwait_cnt_14_ "rwait_cnt[14]") (joined + (portref D (instanceref rwait_cnt_reg_14_)) + (portref O (instanceref rwait_cnt_14__i_1)) + ) + ) + (net (rename rwait_cnt_15_ "rwait_cnt[15]") (joined + (portref D (instanceref rwait_cnt_reg_15_)) + (portref O (instanceref rwait_cnt_15__i_2)) + ) + ) + (net (rename rwait_cnt_15__i_1_n_0 "rwait_cnt[15]_i_1_n_0") (joined + (portref CE (instanceref rwait_cnt_reg_0_)) + (portref CE (instanceref rwait_cnt_reg_10_)) + (portref CE (instanceref rwait_cnt_reg_11_)) + (portref CE (instanceref rwait_cnt_reg_12_)) + (portref CE (instanceref rwait_cnt_reg_13_)) + (portref CE (instanceref rwait_cnt_reg_14_)) + (portref CE (instanceref rwait_cnt_reg_15_)) + (portref CE (instanceref rwait_cnt_reg_1_)) + (portref CE (instanceref rwait_cnt_reg_2_)) + (portref CE (instanceref rwait_cnt_reg_3_)) + (portref CE (instanceref rwait_cnt_reg_4_)) + (portref CE (instanceref rwait_cnt_reg_5_)) + (portref CE (instanceref rwait_cnt_reg_6_)) + (portref CE (instanceref rwait_cnt_reg_7_)) + (portref CE (instanceref rwait_cnt_reg_8_)) + (portref CE (instanceref rwait_cnt_reg_9_)) + (portref O (instanceref rwait_cnt_15__i_1)) + ) + ) + (net (rename rwait_cnt_15__i_4_n_0 "rwait_cnt[15]_i_4_n_0") (joined + (portref I0 (instanceref RCS_2__i_1)) + (portref I1 (instanceref rwait_cnt_0__i_1)) + (portref I1 (instanceref rwait_cnt_10__i_1)) + (portref I1 (instanceref rwait_cnt_11__i_1)) + (portref I1 (instanceref rwait_cnt_12__i_1)) + (portref I1 (instanceref rwait_cnt_13__i_1)) + (portref I1 (instanceref rwait_cnt_14__i_1)) + (portref I1 (instanceref rwait_cnt_15__i_2)) + (portref I1 (instanceref rwait_cnt_1__i_1)) + (portref I1 (instanceref rwait_cnt_2__i_1)) + (portref I1 (instanceref rwait_cnt_3__i_1)) + (portref I1 (instanceref rwait_cnt_4__i_1)) + (portref I1 (instanceref rwait_cnt_5__i_1)) + (portref I1 (instanceref rwait_cnt_6__i_1)) + (portref I1 (instanceref rwait_cnt_7__i_1)) + (portref I1 (instanceref rwait_cnt_8__i_1)) + (portref I1 (instanceref rwait_cnt_9__i_1)) + (portref O (instanceref rwait_cnt_15__i_4)) + ) + ) + (net (rename rwait_cnt_15__i_5_n_0 "rwait_cnt[15]_i_5_n_0") (joined + (portref I0 (instanceref rwait_cnt_15__i_4)) + (portref O (instanceref rwait_cnt_15__i_5)) + ) + ) + (net (rename rwait_cnt_15__i_6_n_0 "rwait_cnt[15]_i_6_n_0") (joined + (portref I5 (instanceref rwait_cnt_15__i_4)) + (portref O (instanceref rwait_cnt_15__i_6)) + ) + ) + (net (rename rwait_cnt_15__i_7_n_0 "rwait_cnt[15]_i_7_n_0") (joined + (portref I4 (instanceref rwait_cnt_15__i_6)) + (portref O (instanceref rwait_cnt_15__i_7)) + ) + ) + (net (rename rwait_cnt_1_ "rwait_cnt[1]") (joined + (portref D (instanceref rwait_cnt_reg_1_)) + (portref O (instanceref rwait_cnt_1__i_1)) + ) + ) + (net (rename rwait_cnt_2_ "rwait_cnt[2]") (joined + (portref D (instanceref rwait_cnt_reg_2_)) + (portref O (instanceref rwait_cnt_2__i_1)) + ) + ) + (net (rename rwait_cnt_3_ "rwait_cnt[3]") (joined + (portref D (instanceref rwait_cnt_reg_3_)) + (portref O (instanceref rwait_cnt_3__i_1)) + ) + ) + (net (rename rwait_cnt_4_ "rwait_cnt[4]") (joined + (portref D (instanceref rwait_cnt_reg_4_)) + (portref O (instanceref rwait_cnt_4__i_1)) + ) + ) + (net (rename rwait_cnt_5_ "rwait_cnt[5]") (joined + (portref D (instanceref rwait_cnt_reg_5_)) + (portref O (instanceref rwait_cnt_5__i_1)) + ) + ) + (net (rename rwait_cnt_6_ "rwait_cnt[6]") (joined + (portref D (instanceref rwait_cnt_reg_6_)) + (portref O (instanceref rwait_cnt_6__i_1)) + ) + ) + (net (rename rwait_cnt_7_ "rwait_cnt[7]") (joined + (portref D (instanceref rwait_cnt_reg_7_)) + (portref O (instanceref rwait_cnt_7__i_1)) + ) + ) + (net (rename rwait_cnt_8_ "rwait_cnt[8]") (joined + (portref D (instanceref rwait_cnt_reg_8_)) + (portref O (instanceref rwait_cnt_8__i_1)) + ) + ) + (net (rename rwait_cnt_9_ "rwait_cnt[9]") (joined + (portref D (instanceref rwait_cnt_reg_9_)) + (portref O (instanceref rwait_cnt_9__i_1)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_0 "rwait_cnt_reg[12]_i_2_n_0") (joined + (portref CI (instanceref rwait_cnt_reg_15__i_3)) + (portref (member CO 0) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_1 "rwait_cnt_reg[12]_i_2_n_1") (joined + (portref (member CO 1) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_2 "rwait_cnt_reg[12]_i_2_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_3 "rwait_cnt_reg[12]_i_2_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_4 "rwait_cnt_reg[12]_i_2_n_4") (joined + (portref I0 (instanceref rwait_cnt_12__i_1)) + (portref (member O 0) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_5 "rwait_cnt_reg[12]_i_2_n_5") (joined + (portref I0 (instanceref rwait_cnt_11__i_1)) + (portref (member O 1) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_6 "rwait_cnt_reg[12]_i_2_n_6") (joined + (portref I0 (instanceref rwait_cnt_10__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_7 "rwait_cnt_reg[12]_i_2_n_7") (joined + (portref I0 (instanceref rwait_cnt_9__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_2 "rwait_cnt_reg[15]_i_3_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_3 "rwait_cnt_reg[15]_i_3_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_5 "rwait_cnt_reg[15]_i_3_n_5") (joined + (portref I0 (instanceref rwait_cnt_15__i_2)) + (portref (member O 1) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_6 "rwait_cnt_reg[15]_i_3_n_6") (joined + (portref I0 (instanceref rwait_cnt_14__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_7 "rwait_cnt_reg[15]_i_3_n_7") (joined + (portref I0 (instanceref rwait_cnt_13__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_0 "rwait_cnt_reg[4]_i_2_n_0") (joined + (portref CI (instanceref rwait_cnt_reg_8__i_2)) + (portref (member CO 0) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_1 "rwait_cnt_reg[4]_i_2_n_1") (joined + (portref (member CO 1) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_2 "rwait_cnt_reg[4]_i_2_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_3 "rwait_cnt_reg[4]_i_2_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_4 "rwait_cnt_reg[4]_i_2_n_4") (joined + (portref I0 (instanceref rwait_cnt_4__i_1)) + (portref (member O 0) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_5 "rwait_cnt_reg[4]_i_2_n_5") (joined + (portref I0 (instanceref rwait_cnt_3__i_1)) + (portref (member O 1) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_6 "rwait_cnt_reg[4]_i_2_n_6") (joined + (portref I0 (instanceref rwait_cnt_2__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_7 "rwait_cnt_reg[4]_i_2_n_7") (joined + (portref I0 (instanceref rwait_cnt_1__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_0 "rwait_cnt_reg[8]_i_2_n_0") (joined + (portref CI (instanceref rwait_cnt_reg_12__i_2)) + (portref (member CO 0) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_1 "rwait_cnt_reg[8]_i_2_n_1") (joined + (portref (member CO 1) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_2 "rwait_cnt_reg[8]_i_2_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_3 "rwait_cnt_reg[8]_i_2_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_4 "rwait_cnt_reg[8]_i_2_n_4") (joined + (portref I0 (instanceref rwait_cnt_8__i_1)) + (portref (member O 0) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_5 "rwait_cnt_reg[8]_i_2_n_5") (joined + (portref I0 (instanceref rwait_cnt_7__i_1)) + (portref (member O 1) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_6 "rwait_cnt_reg[8]_i_2_n_6") (joined + (portref I0 (instanceref rwait_cnt_6__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_7 "rwait_cnt_reg[8]_i_2_n_7") (joined + (portref I0 (instanceref rwait_cnt_5__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__0_ "rwait_cnt_reg_n_0_[0]") (joined + (portref CYINIT (instanceref rwait_cnt_reg_4__i_2)) + (portref I0 (instanceref rwait_cnt_0__i_1)) + (portref I2 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_0_)) + ) + ) + (net (rename rwait_cnt_reg_n_0__10_ "rwait_cnt_reg_n_0_[10]") (joined + (portref I1 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_10_)) + (portref (member S 2) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__11_ "rwait_cnt_reg_n_0_[11]") (joined + (portref I4 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_11_)) + (portref (member S 1) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__12_ "rwait_cnt_reg_n_0_[12]") (joined + (portref I0 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_12_)) + (portref (member S 0) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__13_ "rwait_cnt_reg_n_0_[13]") (joined + (portref I1 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_13_)) + (portref (member S 3) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_n_0__14_ "rwait_cnt_reg_n_0_[14]") (joined + (portref I0 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_14_)) + (portref (member S 2) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_n_0__15_ "rwait_cnt_reg_n_0_[15]") (joined + (portref I3 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_15_)) + (portref (member S 1) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_n_0__1_ "rwait_cnt_reg_n_0_[1]") (joined + (portref I1 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_1_)) + (portref (member S 3) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__2_ "rwait_cnt_reg_n_0_[2]") (joined + (portref I1 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_2_)) + (portref (member S 2) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__3_ "rwait_cnt_reg_n_0_[3]") (joined + (portref I2 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_3_)) + (portref (member S 1) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__4_ "rwait_cnt_reg_n_0_[4]") (joined + (portref I0 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_4_)) + (portref (member S 0) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__5_ "rwait_cnt_reg_n_0_[5]") (joined + (portref I2 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_5_)) + (portref (member S 3) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__6_ "rwait_cnt_reg_n_0_[6]") (joined + (portref I3 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_6_)) + (portref (member S 2) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__7_ "rwait_cnt_reg_n_0_[7]") (joined + (portref I2 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_7_)) + (portref (member S 1) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__8_ "rwait_cnt_reg_n_0_[8]") (joined + (portref I3 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_8_)) + (portref (member S 0) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__9_ "rwait_cnt_reg_n_0_[9]") (joined + (portref I3 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_9_)) + (portref (member S 3) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net rx_done (joined + (portref I0 (instanceref upg_wen_o_i_1)) + (portref I1 (instanceref rx_done_i_1)) + (portref O (instanceref upg_wen_o_i_3)) + ) + ) + (net rx_done_i_1_n_0 (joined + (portref D (instanceref rx_done_reg)) + (portref O (instanceref rx_done_i_1)) + ) + ) + (net rx_done_reg_n_0 (joined + (portref I0 (instanceref disp_6__i_1)) + (portref I0 (instanceref upg_wen_o_i_4)) + (portref I1 (instanceref disp_5__i_4)) + (portref I1 (instanceref disp_7__i_1)) + (portref I2 (instanceref disp_2__i_1)) + (portref I2 (instanceref disp_3__i_2)) + (portref I2 (instanceref disp_5__i_3)) + (portref I2 (instanceref rx_done_i_1)) + (portref I2 (instanceref s_axi_wdata_4__i_3)) + (portref I3 (instanceref s_axi_wstrb_3__i_1)) + (portref I3 (instanceref upg_wen_o_i_6)) + (portref I4 (instanceref disp_1__i_3)) + (portref I4 (instanceref disp_3__i_1)) + (portref I4 (instanceref disp_4__i_1)) + (portref Q (instanceref rx_done_reg)) + ) + ) + (net (rename s_axi_araddr_3__i_1_n_0 "s_axi_araddr[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_araddr_reg_3_)) + (portref O (instanceref s_axi_araddr_3__i_1)) + ) + ) + (net (rename s_axi_araddr_reg_n_0__3_ "s_axi_araddr_reg_n_0_[3]") (joined + (portref I5 (instanceref s_axi_araddr_3__i_1)) + (portref Q (instanceref s_axi_araddr_reg_3_)) + (portref (member s_axi_araddr 0) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_aresetn0 (joined + (portref CE (instanceref disp_reg_0_)) + (portref CE (instanceref disp_reg_1_)) + (portref CE (instanceref disp_reg_2_)) + (portref CE (instanceref disp_reg_3_)) + (portref CE (instanceref disp_reg_4_)) + (portref CE (instanceref disp_reg_5_)) + (portref CE (instanceref disp_reg_6_)) + (portref CE (instanceref disp_reg_7_)) + (portref O (instanceref axi_uart_inst_i_1)) + (portref s_axi_aresetn (instanceref axi_uart_inst)) + ) + ) + (net s_axi_arready (joined + (portref I0 (instanceref s_axi_arvalid_i_1)) + (portref I1 (instanceref RCS_0__i_1)) + (portref s_axi_arready (instanceref axi_uart_inst)) + ) + ) + (net s_axi_arvalid (joined + (portref I5 (instanceref s_axi_arvalid_i_1)) + (portref Q (instanceref s_axi_arvalid_reg)) + (portref s_axi_arvalid (instanceref axi_uart_inst)) + ) + ) + (net s_axi_arvalid_i_1_n_0 (joined + (portref D (instanceref s_axi_arvalid_reg)) + (portref O (instanceref s_axi_arvalid_i_1)) + ) + ) + (net s_axi_arvalid_i_2_n_0 (joined + (portref I1 (instanceref s_axi_arvalid_i_1)) + (portref O (instanceref s_axi_arvalid_i_2)) + ) + ) + (net s_axi_arvalid_i_3_n_0 (joined + (portref I3 (instanceref s_axi_arvalid_i_1)) + (portref O (instanceref s_axi_arvalid_i_3)) + ) + ) + (net (rename s_axi_awaddr_3__i_1_n_0 "s_axi_awaddr[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_awaddr_reg_3_)) + (portref O (instanceref s_axi_awaddr_3__i_1)) + ) + ) + (net (rename s_axi_awaddr_reg_n_0__3_ "s_axi_awaddr_reg_n_0_[3]") (joined + (portref I5 (instanceref s_axi_awaddr_3__i_1)) + (portref Q (instanceref s_axi_awaddr_reg_3_)) + (portref (member s_axi_awaddr 0) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_awready (joined + (portref I0 (instanceref WCS_1__i_1)) + (portref I0 (instanceref s_axi_awvalid_i_2)) + (portref I1 (instanceref WCS_2__i_1)) + (portref s_axi_awready (instanceref axi_uart_inst)) + ) + ) + (net s_axi_awvalid_i_1_n_0 (joined + (portref D (instanceref s_axi_awvalid_reg)) + (portref O (instanceref s_axi_awvalid_i_1)) + ) + ) + (net s_axi_awvalid_i_2_n_0 (joined + (portref I0 (instanceref s_axi_awvalid_i_1)) + (portref O (instanceref s_axi_awvalid_i_2)) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref D (instanceref uart_rdat_reg_0_)) + (portref I0 (instanceref statReg_0__i_1)) + (portref (member s_axi_rdata 31) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref D (instanceref uart_rdat_reg_1_)) + (portref (member s_axi_rdata 30) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref D (instanceref uart_rdat_reg_2_)) + (portref (member s_axi_rdata 29) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref D (instanceref uart_rdat_reg_3_)) + (portref (member s_axi_rdata 28) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref D (instanceref uart_rdat_reg_4_)) + (portref (member s_axi_rdata 27) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref D (instanceref uart_rdat_reg_5_)) + (portref (member s_axi_rdata 26) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref D (instanceref uart_rdat_reg_6_)) + (portref (member s_axi_rdata 25) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref D (instanceref uart_rdat_reg_7_)) + (portref (member s_axi_rdata 24) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_rvalid (joined + (portref I0 (instanceref RCS_0__i_1)) + (portref I0 (instanceref RCS_1__i_1)) + (portref I0 (instanceref uart_rdat_7__i_1)) + (portref I1 (instanceref RCS_2__i_1)) + (portref I1 (instanceref rdStat_i_1)) + (portref I2 (instanceref statReg_0__i_2)) + (portref s_axi_rvalid (instanceref axi_uart_inst)) + ) + ) + (net s_axi_wdata (joined + (portref CE (instanceref s_axi_wdata_reg_0_)) + (portref CE (instanceref s_axi_wdata_reg_1_)) + (portref CE (instanceref s_axi_wdata_reg_2_)) + (portref CE (instanceref s_axi_wdata_reg_3_)) + (portref CE (instanceref s_axi_wdata_reg_4_)) + (portref CE (instanceref s_axi_wdata_reg_5_)) + (portref CE (instanceref s_axi_wdata_reg_6_)) + (portref CE (instanceref s_axi_wstrb_reg_3_)) + (portref O (instanceref s_axi_wdata_4__i_1)) + ) + ) + (net (rename s_axi_wdata_0__i_1_n_0 "s_axi_wdata[0]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_0_)) + (portref O (instanceref s_axi_wdata_0__i_1)) + ) + ) + (net (rename s_axi_wdata_0__i_2_n_0 "s_axi_wdata[0]_i_2_n_0") (joined + (portref I2 (instanceref s_axi_wdata_0__i_1)) + (portref O (instanceref s_axi_wdata_0__i_2)) + ) + ) + (net (rename s_axi_wdata_0__i_3_n_0 "s_axi_wdata[0]_i_3_n_0") (joined + (portref I3 (instanceref s_axi_wdata_0__i_1)) + (portref O (instanceref s_axi_wdata_0__i_3)) + ) + ) + (net (rename s_axi_wdata_0__i_4_n_0 "s_axi_wdata[0]_i_4_n_0") (joined + (portref I4 (instanceref s_axi_wdata_0__i_3)) + (portref O (instanceref s_axi_wdata_0__i_4)) + ) + ) + (net (rename s_axi_wdata_0__i_5_n_0 "s_axi_wdata[0]_i_5_n_0") (joined + (portref I5 (instanceref s_axi_wdata_0__i_4)) + (portref O (instanceref s_axi_wdata_0__i_5)) + ) + ) + (net (rename s_axi_wdata_1__i_1_n_0 "s_axi_wdata[1]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_1_)) + (portref O (instanceref s_axi_wdata_1__i_1)) + ) + ) + (net (rename s_axi_wdata_1__i_2_n_0 "s_axi_wdata[1]_i_2_n_0") (joined + (portref I2 (instanceref s_axi_wdata_1__i_1)) + (portref O (instanceref s_axi_wdata_1__i_2)) + ) + ) + (net (rename s_axi_wdata_1__i_3_n_0 "s_axi_wdata[1]_i_3_n_0") (joined + (portref I3 (instanceref s_axi_wdata_1__i_1)) + (portref O (instanceref s_axi_wdata_1__i_3)) + ) + ) + (net (rename s_axi_wdata_1__i_4_n_0 "s_axi_wdata[1]_i_4_n_0") (joined + (portref I0 (instanceref s_axi_wdata_4__i_4)) + (portref I0 (instanceref s_axi_wdata_4__i_6)) + (portref I4 (instanceref s_axi_wdata_0__i_1)) + (portref I4 (instanceref s_axi_wdata_1__i_1)) + (portref I4 (instanceref s_axi_wdata_5__i_1)) + (portref I5 (instanceref s_axi_wdata_2__i_1)) + (portref I5 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_1__i_4)) + ) + ) + (net (rename s_axi_wdata_1__i_5_n_0 "s_axi_wdata[1]_i_5_n_0") (joined + (portref I4 (instanceref s_axi_wdata_1__i_3)) + (portref O (instanceref s_axi_wdata_1__i_5)) + ) + ) + (net (rename s_axi_wdata_1__i_6_n_0 "s_axi_wdata[1]_i_6_n_0") (joined + (portref I4 (instanceref s_axi_wdata_1__i_5)) + (portref O (instanceref s_axi_wdata_1__i_6)) + ) + ) + (net (rename s_axi_wdata_2__i_1_n_0 "s_axi_wdata[2]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_2_)) + (portref O (instanceref s_axi_wdata_2__i_1)) + ) + ) + (net (rename s_axi_wdata_2__i_2_n_0 "s_axi_wdata[2]_i_2_n_0") (joined + (portref I1 (instanceref s_axi_wdata_2__i_1)) + (portref O (instanceref s_axi_wdata_2__i_2)) + ) + ) + (net (rename s_axi_wdata_2__i_3_n_0 "s_axi_wdata[2]_i_3_n_0") (joined + (portref I2 (instanceref s_axi_wdata_2__i_1)) + (portref O (instanceref s_axi_wdata_2__i_3)) + ) + ) + (net (rename s_axi_wdata_2__i_4_n_0 "s_axi_wdata[2]_i_4_n_0") (joined + (portref I3 (instanceref s_axi_wdata_2__i_1)) + (portref O (instanceref s_axi_wdata_2__i_4)) + ) + ) + (net (rename s_axi_wdata_2__i_5_n_0 "s_axi_wdata[2]_i_5_n_0") (joined + (portref I5 (instanceref s_axi_wdata_2__i_4)) + (portref O (instanceref s_axi_wdata_2__i_5)) + ) + ) + (net (rename s_axi_wdata_3__i_1_n_0 "s_axi_wdata[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_3_)) + (portref O (instanceref s_axi_wdata_3__i_1)) + ) + ) + (net (rename s_axi_wdata_3__i_2_n_0 "s_axi_wdata[3]_i_2_n_0") (joined + (portref I1 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_3__i_2)) + ) + ) + (net (rename s_axi_wdata_3__i_3_n_0 "s_axi_wdata[3]_i_3_n_0") (joined + (portref I2 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_3__i_3)) + ) + ) + (net (rename s_axi_wdata_3__i_4_n_0 "s_axi_wdata[3]_i_4_n_0") (joined + (portref I3 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_3__i_4)) + ) + ) + (net (rename s_axi_wdata_3__i_5_n_0 "s_axi_wdata[3]_i_5_n_0") (joined + (portref I5 (instanceref s_axi_wdata_3__i_4)) + (portref O (instanceref s_axi_wdata_3__i_5)) + ) + ) + (net (rename s_axi_wdata_4__i_2_n_0 "s_axi_wdata[4]_i_2_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_4_)) + (portref O (instanceref s_axi_wdata_4__i_2)) + ) + ) + (net (rename s_axi_wdata_4__i_4_n_0 "s_axi_wdata[4]_i_4_n_0") (joined + (portref I0 (instanceref s_axi_wdata_2__i_1)) + (portref I0 (instanceref s_axi_wdata_3__i_1)) + (portref I0 (instanceref s_axi_wdata_5__i_1)) + (portref I1 (instanceref s_axi_wdata_0__i_1)) + (portref I1 (instanceref s_axi_wdata_1__i_1)) + (portref I1 (instanceref s_axi_wdata_4__i_2)) + (portref I2 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_4__i_4)) + ) + ) + (net (rename s_axi_wdata_4__i_5_n_0 "s_axi_wdata[4]_i_5_n_0") (joined + (portref I2 (instanceref s_axi_wdata_4__i_2)) + (portref O (instanceref s_axi_wdata_4__i_5)) + ) + ) + (net (rename s_axi_wdata_4__i_6_n_0 "s_axi_wdata[4]_i_6_n_0") (joined + (portref I3 (instanceref s_axi_wdata_4__i_2)) + (portref O (instanceref s_axi_wdata_4__i_6)) + ) + ) + (net (rename s_axi_wdata_4__i_7_n_0 "s_axi_wdata[4]_i_7_n_0") (joined + (portref I1 (instanceref s_axi_wdata_0__i_3)) + (portref I1 (instanceref s_axi_wdata_1__i_3)) + (portref I3 (instanceref s_axi_wdata_4__i_6)) + (portref O (instanceref s_axi_wdata_4__i_7)) + ) + ) + (net (rename s_axi_wdata_4__i_8_n_0 "s_axi_wdata[4]_i_8_n_0") (joined + (portref I0 (instanceref s_axi_wdata_0__i_3)) + (portref I0 (instanceref s_axi_wdata_1__i_3)) + (portref I5 (instanceref s_axi_wdata_4__i_6)) + (portref O (instanceref s_axi_wdata_4__i_8)) + ) + ) + (net (rename s_axi_wdata_5__i_1_n_0 "s_axi_wdata[5]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_5_)) + (portref O (instanceref s_axi_wdata_5__i_1)) + ) + ) + (net (rename s_axi_wdata_5__i_2_n_0 "s_axi_wdata[5]_i_2_n_0") (joined + (portref I1 (instanceref s_axi_wdata_5__i_1)) + (portref O (instanceref s_axi_wdata_5__i_2)) + ) + ) + (net (rename s_axi_wdata_5__i_3_n_0 "s_axi_wdata[5]_i_3_n_0") (joined + (portref I2 (instanceref s_axi_wdata_5__i_1)) + (portref O (instanceref s_axi_wdata_5__i_3)) + ) + ) + (net (rename s_axi_wdata_5__i_4_n_0 "s_axi_wdata[5]_i_4_n_0") (joined + (portref I1 (instanceref s_axi_wdata_4__i_6)) + (portref I3 (instanceref s_axi_wdata_5__i_1)) + (portref O (instanceref s_axi_wdata_5__i_4)) + ) + ) + (net (rename s_axi_wdata_5__i_5_n_0 "s_axi_wdata[5]_i_5_n_0") (joined + (portref I2 (instanceref s_axi_wdata_5__i_4)) + (portref O (instanceref s_axi_wdata_5__i_5)) + ) + ) + (net (rename s_axi_wdata_5__i_6_n_0 "s_axi_wdata[5]_i_6_n_0") (joined + (portref I3 (instanceref s_axi_wdata_5__i_4)) + (portref O (instanceref s_axi_wdata_5__i_6)) + ) + ) + (net (rename s_axi_wdata_6__i_1_n_0 "s_axi_wdata[6]_i_1_n_0") (joined + (portref O (instanceref s_axi_wdata_6__i_1)) + (portref R (instanceref s_axi_wdata_reg_2_)) + (portref R (instanceref s_axi_wdata_reg_3_)) + (portref R (instanceref s_axi_wdata_reg_5_)) + (portref R (instanceref s_axi_wdata_reg_6_)) + ) + ) + (net (rename s_axi_wdata_6__i_2_n_0 "s_axi_wdata[6]_i_2_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_6_)) + (portref O (instanceref s_axi_wdata_6__i_2)) + ) + ) + (net (rename s_axi_wdata_6__i_3_n_0 "s_axi_wdata[6]_i_3_n_0") (joined + (portref I0 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_6__i_3)) + ) + ) + (net (rename s_axi_wdata_6__i_4_n_0 "s_axi_wdata[6]_i_4_n_0") (joined + (portref I1 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_6__i_4)) + ) + ) + (net (rename s_axi_wdata_6__i_5_n_0 "s_axi_wdata[6]_i_5_n_0") (joined + (portref I4 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_6__i_5)) + ) + ) + (net (rename s_axi_wdata_6__i_6_n_0 "s_axi_wdata[6]_i_6_n_0") (joined + (portref I0 (instanceref s_axi_wdata_6__i_5)) + (portref O (instanceref s_axi_wdata_6__i_6)) + ) + ) + (net (rename s_axi_wdata_6__i_7_n_0 "s_axi_wdata[6]_i_7_n_0") (joined + (portref I5 (instanceref s_axi_wdata_6__i_5)) + (portref O (instanceref s_axi_wdata_6__i_7)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__0_ "s_axi_wdata_reg_n_0_[0]") (joined + (portref Q (instanceref s_axi_wdata_reg_0_)) + (portref (member s_axi_wdata 31) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__1_ "s_axi_wdata_reg_n_0_[1]") (joined + (portref Q (instanceref s_axi_wdata_reg_1_)) + (portref (member s_axi_wdata 30) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__2_ "s_axi_wdata_reg_n_0_[2]") (joined + (portref Q (instanceref s_axi_wdata_reg_2_)) + (portref (member s_axi_wdata 29) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__3_ "s_axi_wdata_reg_n_0_[3]") (joined + (portref Q (instanceref s_axi_wdata_reg_3_)) + (portref (member s_axi_wdata 28) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__4_ "s_axi_wdata_reg_n_0_[4]") (joined + (portref Q (instanceref s_axi_wdata_reg_4_)) + (portref (member s_axi_wdata 27) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__5_ "s_axi_wdata_reg_n_0_[5]") (joined + (portref Q (instanceref s_axi_wdata_reg_5_)) + (portref (member s_axi_wdata 26) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__6_ "s_axi_wdata_reg_n_0_[6]") (joined + (portref Q (instanceref s_axi_wdata_reg_6_)) + (portref (member s_axi_wdata 25) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_wready (joined + (portref I0 (instanceref WCS_2__i_1)) + (portref I1 (instanceref WCS_1__i_1)) + (portref I1 (instanceref s_axi_awvalid_i_2)) + (portref s_axi_wready (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wstrb_3_ "s_axi_wstrb[3]") (joined + (portref Q (instanceref s_axi_wstrb_reg_3_)) + (portref (member s_axi_wstrb 3) (instanceref axi_uart_inst)) + (portref (member s_axi_wstrb 2) (instanceref axi_uart_inst)) + (portref (member s_axi_wstrb 1) (instanceref axi_uart_inst)) + (portref (member s_axi_wstrb 0) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wstrb_3__i_1_n_0 "s_axi_wstrb[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_wstrb_reg_3_)) + (portref I2 (instanceref WCS_0__i_1)) + (portref I2 (instanceref WCS_1__i_1)) + (portref O (instanceref s_axi_wstrb_3__i_1)) + ) + ) + (net s_axi_wvalid (joined + (portref I4 (instanceref s_axi_awvalid_i_1)) + (portref Q (instanceref s_axi_awvalid_reg)) + (portref s_axi_awvalid (instanceref axi_uart_inst)) + (portref s_axi_wvalid (instanceref axi_uart_inst)) + ) + ) + (net (rename statReg_0__i_1_n_0 "statReg[0]_i_1_n_0") (joined + (portref D (instanceref statReg_reg_0_)) + (portref O (instanceref statReg_0__i_1)) + ) + ) + (net (rename statReg_0__i_2_n_0 "statReg[0]_i_2_n_0") (joined + (portref I1 (instanceref statReg_0__i_1)) + (portref O (instanceref statReg_0__i_2)) + ) + ) + (net (rename statReg_reg_n_0__0_ "statReg_reg_n_0_[0]") (joined + (portref I1 (instanceref RCS_1__i_1)) + (portref I1 (instanceref bn_ascii_62__i_1)) + (portref I1 (instanceref byte_len_7__i_1)) + (portref I1 (instanceref byte_num_31__i_1)) + (portref I1 (instanceref disp_0__i_1)) + (portref I1 (instanceref s_axi_arvalid_i_3)) + (portref I2 (instanceref byte_cnt_31__i_1)) + (portref I2 (instanceref disp_1__i_1)) + (portref I2 (instanceref disp_2__i_2)) + (portref I2 (instanceref disp_3__i_1)) + (portref I2 (instanceref disp_4__i_1)) + (portref I2 (instanceref recv_done_i_1)) + (portref I3 (instanceref disp_5__i_1)) + (portref I4 (instanceref disp_6__i_1)) + (portref I4 (instanceref disp_6__i_2)) + (portref I4 (instanceref disp_7__i_1)) + (portref I4 (instanceref rdStat_i_1)) + (portref I4 (instanceref statReg_0__i_1)) + (portref Q (instanceref statReg_reg_0_)) + ) + ) + (net uart_rdat (joined + (portref CE (instanceref uart_rdat_reg_0_)) + (portref CE (instanceref uart_rdat_reg_1_)) + (portref CE (instanceref uart_rdat_reg_2_)) + (portref CE (instanceref uart_rdat_reg_3_)) + (portref CE (instanceref uart_rdat_reg_4_)) + (portref CE (instanceref uart_rdat_reg_5_)) + (portref CE (instanceref uart_rdat_reg_6_)) + (portref CE (instanceref uart_rdat_reg_7_)) + (portref O (instanceref uart_rdat_7__i_1)) + ) + ) + (net (rename uart_rdat_reg_n_0__0_ "uart_rdat_reg_n_0_[0]") (joined + (portref D (instanceref byte_len_reg_0_)) + (portref D (instanceref byte_num_reg_0_)) + (portref D (instanceref dbuf_reg_0_)) + (portref D (instanceref upg_dat_o_reg_0_)) + (portref I0 (instanceref bn_ascii_0__i_1)) + (portref I0 (instanceref bn_ascii_1__i_1)) + (portref I3 (instanceref bn_ascii_2__i_1)) + (portref I5 (instanceref wr_byte_len_done_i_1)) + (portref Q (instanceref uart_rdat_reg_0_)) + ) + ) + (net (rename uart_rdat_reg_n_0__1_ "uart_rdat_reg_n_0_[1]") (joined + (portref D (instanceref byte_len_reg_1_)) + (portref D (instanceref byte_num_reg_1_)) + (portref D (instanceref dbuf_reg_1_)) + (portref D (instanceref upg_dat_o_reg_1_)) + (portref I0 (instanceref bn_ascii_2__i_1)) + (portref I0 (instanceref bn_ascii_5__i_1)) + (portref I1 (instanceref bn_ascii_0__i_1)) + (portref I2 (instanceref bn_ascii_3__i_1)) + (portref I2 (instanceref bn_ascii_6__i_1)) + (portref I3 (instanceref bn_ascii_1__i_1)) + (portref I3 (instanceref wr_byte_len_done_i_2)) + (portref Q (instanceref uart_rdat_reg_1_)) + ) + ) + (net (rename uart_rdat_reg_n_0__2_ "uart_rdat_reg_n_0_[2]") (joined + (portref D (instanceref byte_len_reg_2_)) + (portref D (instanceref byte_num_reg_2_)) + (portref D (instanceref dbuf_reg_2_)) + (portref D (instanceref upg_dat_o_reg_2_)) + (portref I1 (instanceref bn_ascii_2__i_1)) + (portref I1 (instanceref bn_ascii_3__i_1)) + (portref I1 (instanceref bn_ascii_5__i_1)) + (portref I1 (instanceref bn_ascii_6__i_1)) + (portref I2 (instanceref bn_ascii_0__i_1)) + (portref I2 (instanceref bn_ascii_1__i_1)) + (portref I2 (instanceref wr_byte_len_done_i_2)) + (portref Q (instanceref uart_rdat_reg_2_)) + ) + ) + (net (rename uart_rdat_reg_n_0__3_ "uart_rdat_reg_n_0_[3]") (joined + (portref D (instanceref byte_len_reg_3_)) + (portref D (instanceref byte_num_reg_3_)) + (portref D (instanceref dbuf_reg_3_)) + (portref D (instanceref upg_dat_o_reg_3_)) + (portref I0 (instanceref bn_ascii_3__i_1)) + (portref I0 (instanceref bn_ascii_6__i_1)) + (portref I1 (instanceref bn_ascii_1__i_1)) + (portref I2 (instanceref bn_ascii_2__i_1)) + (portref I2 (instanceref bn_ascii_5__i_1)) + (portref I3 (instanceref bn_ascii_0__i_1)) + (portref I3 (instanceref wr_byte_len_done_i_1)) + (portref Q (instanceref uart_rdat_reg_3_)) + ) + ) + (net (rename uart_rdat_reg_n_0__4_ "uart_rdat_reg_n_0_[4]") (joined + (portref D (instanceref byte_len_reg_4_)) + (portref D (instanceref byte_num_reg_4_)) + (portref D (instanceref dbuf_reg_4_)) + (portref D (instanceref upg_dat_o_reg_4_)) + (portref I0 (instanceref bn_ascii_8__i_1)) + (portref I0 (instanceref bn_ascii_9__i_1)) + (portref I2 (instanceref wr_byte_len_done_i_1)) + (portref I3 (instanceref bn_ascii_10__i_1)) + (portref Q (instanceref uart_rdat_reg_4_)) + ) + ) + (net (rename uart_rdat_reg_n_0__5_ "uart_rdat_reg_n_0_[5]") (joined + (portref D (instanceref byte_len_reg_5_)) + (portref D (instanceref byte_num_reg_5_)) + (portref D (instanceref dbuf_reg_5_)) + (portref D (instanceref upg_dat_o_reg_5_)) + (portref I0 (instanceref bn_ascii_10__i_1)) + (portref I0 (instanceref bn_ascii_13__i_1)) + (portref I1 (instanceref bn_ascii_8__i_1)) + (portref I1 (instanceref wr_byte_len_done_i_2)) + (portref I2 (instanceref bn_ascii_11__i_1)) + (portref I2 (instanceref bn_ascii_14__i_1)) + (portref I3 (instanceref bn_ascii_9__i_1)) + (portref Q (instanceref uart_rdat_reg_5_)) + ) + ) + (net (rename uart_rdat_reg_n_0__6_ "uart_rdat_reg_n_0_[6]") (joined + (portref D (instanceref byte_len_reg_6_)) + (portref D (instanceref byte_num_reg_6_)) + (portref D (instanceref dbuf_reg_6_)) + (portref D (instanceref upg_dat_o_reg_6_)) + (portref I0 (instanceref wr_byte_len_done_i_2)) + (portref I1 (instanceref bn_ascii_10__i_1)) + (portref I1 (instanceref bn_ascii_11__i_1)) + (portref I1 (instanceref bn_ascii_13__i_1)) + (portref I1 (instanceref bn_ascii_14__i_1)) + (portref I2 (instanceref bn_ascii_8__i_1)) + (portref I2 (instanceref bn_ascii_9__i_1)) + (portref Q (instanceref uart_rdat_reg_6_)) + ) + ) + (net (rename uart_rdat_reg_n_0__7_ "uart_rdat_reg_n_0_[7]") (joined + (portref D (instanceref byte_len_reg_7_)) + (portref D (instanceref byte_num_reg_7_)) + (portref D (instanceref dbuf_reg_7_)) + (portref D (instanceref upg_dat_o_reg_7_)) + (portref I0 (instanceref bn_ascii_11__i_1)) + (portref I0 (instanceref bn_ascii_14__i_1)) + (portref I1 (instanceref bn_ascii_9__i_1)) + (portref I2 (instanceref bn_ascii_10__i_1)) + (portref I2 (instanceref bn_ascii_13__i_1)) + (portref I3 (instanceref bn_ascii_8__i_1)) + (portref I4 (instanceref wr_byte_len_done_i_1)) + (portref Q (instanceref uart_rdat_reg_7_)) + ) + ) + (net uart_wen5_out (joined + (portref I0 (instanceref msg_indx_7__i_1)) + (portref I0 (instanceref uart_wen_i_1)) + (portref I1 (instanceref s_axi_awvalid_i_1)) + (portref I3 (instanceref s_axi_wdata_4__i_1)) + (portref O (instanceref s_axi_wdata_4__i_3)) + ) + ) + (net uart_wen_i_1_n_0 (joined + (portref D (instanceref uart_wen_reg)) + (portref O (instanceref uart_wen_i_1)) + ) + ) + (net uart_wen_reg_n_0 (joined + (portref I1 (instanceref s_axi_wdata_4__i_3)) + (portref I2 (instanceref s_axi_wstrb_3__i_1)) + (portref I5 (instanceref uart_wen_i_1)) + (portref Q (instanceref uart_wen_reg)) + ) + ) + (net (rename upg_adr_o_0_ "upg_adr_o[0]") (joined + (portref O (instanceref upg_adr_o_OBUF_0__inst)) + (portref (member upg_adr_o 14)) + ) + ) + (net (rename upg_adr_o_10_ "upg_adr_o[10]") (joined + (portref O (instanceref upg_adr_o_OBUF_10__inst)) + (portref (member upg_adr_o 4)) + ) + ) + (net (rename upg_adr_o_11_ "upg_adr_o[11]") (joined + (portref O (instanceref upg_adr_o_OBUF_11__inst)) + (portref (member upg_adr_o 3)) + ) + ) + (net (rename upg_adr_o_12_ "upg_adr_o[12]") (joined + (portref O (instanceref upg_adr_o_OBUF_12__inst)) + (portref (member upg_adr_o 2)) + ) + ) + (net (rename upg_adr_o_13_ "upg_adr_o[13]") (joined + (portref O (instanceref upg_adr_o_OBUF_13__inst)) + (portref (member upg_adr_o 1)) + ) + ) + (net (rename upg_adr_o_14_ "upg_adr_o[14]") (joined + (portref O (instanceref upg_adr_o_OBUF_14__inst)) + (portref (member upg_adr_o 0)) + ) + ) + (net (rename upg_adr_o_14__i_1_n_0 "upg_adr_o[14]_i_1_n_0") (joined + (portref CE (instanceref upg_adr_o_reg_0_)) + (portref CE (instanceref upg_adr_o_reg_10_)) + (portref CE (instanceref upg_adr_o_reg_11_)) + (portref CE (instanceref upg_adr_o_reg_12_)) + (portref CE (instanceref upg_adr_o_reg_13_)) + (portref CE (instanceref upg_adr_o_reg_14_)) + (portref CE (instanceref upg_adr_o_reg_1_)) + (portref CE (instanceref upg_adr_o_reg_2_)) + (portref CE (instanceref upg_adr_o_reg_3_)) + (portref CE (instanceref upg_adr_o_reg_4_)) + (portref CE (instanceref upg_adr_o_reg_5_)) + (portref CE (instanceref upg_adr_o_reg_6_)) + (portref CE (instanceref upg_adr_o_reg_7_)) + (portref CE (instanceref upg_adr_o_reg_8_)) + (portref CE (instanceref upg_adr_o_reg_9_)) + (portref CE (instanceref upg_dat_o_reg_0_)) + (portref CE (instanceref upg_dat_o_reg_10_)) + (portref CE (instanceref upg_dat_o_reg_11_)) + (portref CE (instanceref upg_dat_o_reg_12_)) + (portref CE (instanceref upg_dat_o_reg_13_)) + (portref CE (instanceref upg_dat_o_reg_14_)) + (portref CE (instanceref upg_dat_o_reg_15_)) + (portref CE (instanceref upg_dat_o_reg_16_)) + (portref CE (instanceref upg_dat_o_reg_17_)) + (portref CE (instanceref upg_dat_o_reg_18_)) + (portref CE (instanceref upg_dat_o_reg_19_)) + (portref CE (instanceref upg_dat_o_reg_1_)) + (portref CE (instanceref upg_dat_o_reg_20_)) + (portref CE (instanceref upg_dat_o_reg_21_)) + (portref CE (instanceref upg_dat_o_reg_22_)) + (portref CE (instanceref upg_dat_o_reg_23_)) + (portref CE (instanceref upg_dat_o_reg_24_)) + (portref CE (instanceref upg_dat_o_reg_25_)) + (portref CE (instanceref upg_dat_o_reg_26_)) + (portref CE (instanceref upg_dat_o_reg_27_)) + (portref CE (instanceref upg_dat_o_reg_28_)) + (portref CE (instanceref upg_dat_o_reg_29_)) + (portref CE (instanceref upg_dat_o_reg_2_)) + (portref CE (instanceref upg_dat_o_reg_30_)) + (portref CE (instanceref upg_dat_o_reg_31_)) + (portref CE (instanceref upg_dat_o_reg_3_)) + (portref CE (instanceref upg_dat_o_reg_4_)) + (portref CE (instanceref upg_dat_o_reg_5_)) + (portref CE (instanceref upg_dat_o_reg_6_)) + (portref CE (instanceref upg_dat_o_reg_7_)) + (portref CE (instanceref upg_dat_o_reg_8_)) + (portref CE (instanceref upg_dat_o_reg_9_)) + (portref O (instanceref upg_adr_o_14__i_1)) + ) + ) + (net (rename upg_adr_o_1_ "upg_adr_o[1]") (joined + (portref O (instanceref upg_adr_o_OBUF_1__inst)) + (portref (member upg_adr_o 13)) + ) + ) + (net (rename upg_adr_o_2_ "upg_adr_o[2]") (joined + (portref O (instanceref upg_adr_o_OBUF_2__inst)) + (portref (member upg_adr_o 12)) + ) + ) + (net (rename upg_adr_o_3_ "upg_adr_o[3]") (joined + (portref O (instanceref upg_adr_o_OBUF_3__inst)) + (portref (member upg_adr_o 11)) + ) + ) + (net (rename upg_adr_o_4_ "upg_adr_o[4]") (joined + (portref O (instanceref upg_adr_o_OBUF_4__inst)) + (portref (member upg_adr_o 10)) + ) + ) + (net (rename upg_adr_o_5_ "upg_adr_o[5]") (joined + (portref O (instanceref upg_adr_o_OBUF_5__inst)) + (portref (member upg_adr_o 9)) + ) + ) + (net (rename upg_adr_o_6_ "upg_adr_o[6]") (joined + (portref O (instanceref upg_adr_o_OBUF_6__inst)) + (portref (member upg_adr_o 8)) + ) + ) + (net (rename upg_adr_o_7_ "upg_adr_o[7]") (joined + (portref O (instanceref upg_adr_o_OBUF_7__inst)) + (portref (member upg_adr_o 7)) + ) + ) + (net (rename upg_adr_o_8_ "upg_adr_o[8]") (joined + (portref O (instanceref upg_adr_o_OBUF_8__inst)) + (portref (member upg_adr_o 6)) + ) + ) + (net (rename upg_adr_o_9_ "upg_adr_o[9]") (joined + (portref O (instanceref upg_adr_o_OBUF_9__inst)) + (portref (member upg_adr_o 5)) + ) + ) + (net (rename upg_adr_o_OBUF_0_ "upg_adr_o_OBUF[0]") (joined + (portref I (instanceref upg_adr_o_OBUF_0__inst)) + (portref Q (instanceref upg_adr_o_reg_0_)) + ) + ) + (net (rename upg_adr_o_OBUF_10_ "upg_adr_o_OBUF[10]") (joined + (portref I (instanceref upg_adr_o_OBUF_10__inst)) + (portref Q (instanceref upg_adr_o_reg_10_)) + ) + ) + (net (rename upg_adr_o_OBUF_11_ "upg_adr_o_OBUF[11]") (joined + (portref I (instanceref upg_adr_o_OBUF_11__inst)) + (portref Q (instanceref upg_adr_o_reg_11_)) + ) + ) + (net (rename upg_adr_o_OBUF_12_ "upg_adr_o_OBUF[12]") (joined + (portref I (instanceref upg_adr_o_OBUF_12__inst)) + (portref Q (instanceref upg_adr_o_reg_12_)) + ) + ) + (net (rename upg_adr_o_OBUF_13_ "upg_adr_o_OBUF[13]") (joined + (portref I (instanceref upg_adr_o_OBUF_13__inst)) + (portref Q (instanceref upg_adr_o_reg_13_)) + ) + ) + (net (rename upg_adr_o_OBUF_14_ "upg_adr_o_OBUF[14]") (joined + (portref I (instanceref upg_adr_o_OBUF_14__inst)) + (portref Q (instanceref upg_adr_o_reg_14_)) + ) + ) + (net (rename upg_adr_o_OBUF_1_ "upg_adr_o_OBUF[1]") (joined + (portref I (instanceref upg_adr_o_OBUF_1__inst)) + (portref Q (instanceref upg_adr_o_reg_1_)) + ) + ) + (net (rename upg_adr_o_OBUF_2_ "upg_adr_o_OBUF[2]") (joined + (portref I (instanceref upg_adr_o_OBUF_2__inst)) + (portref Q (instanceref upg_adr_o_reg_2_)) + ) + ) + (net (rename upg_adr_o_OBUF_3_ "upg_adr_o_OBUF[3]") (joined + (portref I (instanceref upg_adr_o_OBUF_3__inst)) + (portref Q (instanceref upg_adr_o_reg_3_)) + ) + ) + (net (rename upg_adr_o_OBUF_4_ "upg_adr_o_OBUF[4]") (joined + (portref I (instanceref upg_adr_o_OBUF_4__inst)) + (portref Q (instanceref upg_adr_o_reg_4_)) + ) + ) + (net (rename upg_adr_o_OBUF_5_ "upg_adr_o_OBUF[5]") (joined + (portref I (instanceref upg_adr_o_OBUF_5__inst)) + (portref Q (instanceref upg_adr_o_reg_5_)) + ) + ) + (net (rename upg_adr_o_OBUF_6_ "upg_adr_o_OBUF[6]") (joined + (portref I (instanceref upg_adr_o_OBUF_6__inst)) + (portref Q (instanceref upg_adr_o_reg_6_)) + ) + ) + (net (rename upg_adr_o_OBUF_7_ "upg_adr_o_OBUF[7]") (joined + (portref I (instanceref upg_adr_o_OBUF_7__inst)) + (portref Q (instanceref upg_adr_o_reg_7_)) + ) + ) + (net (rename upg_adr_o_OBUF_8_ "upg_adr_o_OBUF[8]") (joined + (portref I (instanceref upg_adr_o_OBUF_8__inst)) + (portref Q (instanceref upg_adr_o_reg_8_)) + ) + ) + (net (rename upg_adr_o_OBUF_9_ "upg_adr_o_OBUF[9]") (joined + (portref I (instanceref upg_adr_o_OBUF_9__inst)) + (portref Q (instanceref upg_adr_o_reg_9_)) + ) + ) + (net upg_clk_i (joined + (portref I (instanceref upg_clk_i_IBUF_inst)) + (portref upg_clk_i) + ) + ) + (net upg_clk_i_IBUF (joined + (portref I (instanceref upg_clk_i_IBUF_BUFG_inst)) + (portref O (instanceref upg_clk_i_IBUF_inst)) + ) + ) + (net upg_clk_i_IBUF_BUFG (joined + (portref C (instanceref RCS_reg_0_)) + (portref C (instanceref RCS_reg_1_)) + (portref C (instanceref RCS_reg_2_)) + (portref C (instanceref WCS_reg_0_)) + (portref C (instanceref WCS_reg_1_)) + (portref C (instanceref WCS_reg_2_)) + (portref C (instanceref initFlag_reg)) + (portref C (instanceref msg_indx_reg_0_)) + (portref C (instanceref msg_indx_reg_1_)) + (portref C (instanceref msg_indx_reg_2_)) + (portref C (instanceref msg_indx_reg_3_)) + (portref C (instanceref msg_indx_reg_4_)) + (portref C (instanceref msg_indx_reg_5_)) + (portref C (instanceref msg_indx_reg_6_)) + (portref C (instanceref msg_indx_reg_7_)) + (portref C (instanceref oldInitF_reg)) + (portref C (instanceref rdStat_reg)) + (portref C (instanceref rwait_cnt_reg_0_)) + (portref C (instanceref rwait_cnt_reg_10_)) + (portref C (instanceref rwait_cnt_reg_11_)) + (portref C (instanceref rwait_cnt_reg_12_)) + (portref C (instanceref rwait_cnt_reg_13_)) + (portref C (instanceref rwait_cnt_reg_14_)) + (portref C (instanceref rwait_cnt_reg_15_)) + (portref C (instanceref rwait_cnt_reg_1_)) + (portref C (instanceref rwait_cnt_reg_2_)) + (portref C (instanceref rwait_cnt_reg_3_)) + (portref C (instanceref rwait_cnt_reg_4_)) + (portref C (instanceref rwait_cnt_reg_5_)) + (portref C (instanceref rwait_cnt_reg_6_)) + (portref C (instanceref rwait_cnt_reg_7_)) + (portref C (instanceref rwait_cnt_reg_8_)) + (portref C (instanceref rwait_cnt_reg_9_)) + (portref C (instanceref s_axi_araddr_reg_3_)) + (portref C (instanceref s_axi_arvalid_reg)) + (portref C (instanceref s_axi_awaddr_reg_3_)) + (portref C (instanceref s_axi_awvalid_reg)) + (portref C (instanceref s_axi_wdata_reg_0_)) + (portref C (instanceref s_axi_wdata_reg_1_)) + (portref C (instanceref s_axi_wdata_reg_2_)) + (portref C (instanceref s_axi_wdata_reg_3_)) + (portref C (instanceref s_axi_wdata_reg_4_)) + (portref C (instanceref s_axi_wdata_reg_5_)) + (portref C (instanceref s_axi_wdata_reg_6_)) + (portref C (instanceref s_axi_wstrb_reg_3_)) + (portref C (instanceref statReg_reg_0_)) + (portref C (instanceref uart_rdat_reg_0_)) + (portref C (instanceref uart_rdat_reg_1_)) + (portref C (instanceref uart_rdat_reg_2_)) + (portref C (instanceref uart_rdat_reg_3_)) + (portref C (instanceref uart_rdat_reg_4_)) + (portref C (instanceref uart_rdat_reg_5_)) + (portref C (instanceref uart_rdat_reg_6_)) + (portref C (instanceref uart_rdat_reg_7_)) + (portref C (instanceref uart_wen_reg)) + (portref C (instanceref upg_done_o_reg)) + (portref C (instanceref wwait_cnt_reg_0_)) + (portref C (instanceref wwait_cnt_reg_10_)) + (portref C (instanceref wwait_cnt_reg_11_)) + (portref C (instanceref wwait_cnt_reg_12_)) + (portref C (instanceref wwait_cnt_reg_13_)) + (portref C (instanceref wwait_cnt_reg_14_)) + (portref C (instanceref wwait_cnt_reg_15_)) + (portref C (instanceref wwait_cnt_reg_1_)) + (portref C (instanceref wwait_cnt_reg_2_)) + (portref C (instanceref wwait_cnt_reg_3_)) + (portref C (instanceref wwait_cnt_reg_4_)) + (portref C (instanceref wwait_cnt_reg_5_)) + (portref C (instanceref wwait_cnt_reg_6_)) + (portref C (instanceref wwait_cnt_reg_7_)) + (portref C (instanceref wwait_cnt_reg_8_)) + (portref C (instanceref wwait_cnt_reg_9_)) + (portref O (instanceref upg_clk_i_IBUF_BUFG_inst)) + (portref s_axi_aclk (instanceref axi_uart_inst)) + ) + ) + (net upg_clk_o (joined + (portref O (instanceref upg_clk_o_OBUF_inst)) + (portref upg_clk_o) + ) + ) + (net upg_clk_o_OBUF (joined + (portref I (instanceref upg_clk_o_OBUF_inst)) + (portref O (instanceref upg_clk_o_OBUF_inst_i_1)) + ) + ) + (net upg_clk_o_OBUF_inst_i_2_n_0 (joined + (portref I0 (instanceref upg_wen_o_i_5)) + (portref I1 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I2 (instanceref disp_1__i_3)) + (portref I2 (instanceref disp_7__i_3)) + (portref I3 (instanceref disp_1__i_2)) + (portref I3 (instanceref disp_6__i_3)) + (portref O (instanceref upg_clk_o_OBUF_inst_i_2)) + ) + ) + (net (rename upg_dat_o_0_ "upg_dat_o[0]") (joined + (portref O (instanceref upg_dat_o_OBUF_0__inst)) + (portref (member upg_dat_o 31)) + ) + ) + (net (rename upg_dat_o_10_ "upg_dat_o[10]") (joined + (portref O (instanceref upg_dat_o_OBUF_10__inst)) + (portref (member upg_dat_o 21)) + ) + ) + (net (rename upg_dat_o_11_ "upg_dat_o[11]") (joined + (portref O (instanceref upg_dat_o_OBUF_11__inst)) + (portref (member upg_dat_o 20)) + ) + ) + (net (rename upg_dat_o_12_ "upg_dat_o[12]") (joined + (portref O (instanceref upg_dat_o_OBUF_12__inst)) + (portref (member upg_dat_o 19)) + ) + ) + (net (rename upg_dat_o_13_ "upg_dat_o[13]") (joined + (portref O (instanceref upg_dat_o_OBUF_13__inst)) + (portref (member upg_dat_o 18)) + ) + ) + (net (rename upg_dat_o_14_ "upg_dat_o[14]") (joined + (portref O (instanceref upg_dat_o_OBUF_14__inst)) + (portref (member upg_dat_o 17)) + ) + ) + (net (rename upg_dat_o_15_ "upg_dat_o[15]") (joined + (portref O (instanceref upg_dat_o_OBUF_15__inst)) + (portref (member upg_dat_o 16)) + ) + ) + (net (rename upg_dat_o_16_ "upg_dat_o[16]") (joined + (portref O (instanceref upg_dat_o_OBUF_16__inst)) + (portref (member upg_dat_o 15)) + ) + ) + (net (rename upg_dat_o_17_ "upg_dat_o[17]") (joined + (portref O (instanceref upg_dat_o_OBUF_17__inst)) + (portref (member upg_dat_o 14)) + ) + ) + (net (rename upg_dat_o_18_ "upg_dat_o[18]") (joined + (portref O (instanceref upg_dat_o_OBUF_18__inst)) + (portref (member upg_dat_o 13)) + ) + ) + (net (rename upg_dat_o_19_ "upg_dat_o[19]") (joined + (portref O (instanceref upg_dat_o_OBUF_19__inst)) + (portref (member upg_dat_o 12)) + ) + ) + (net (rename upg_dat_o_1_ "upg_dat_o[1]") (joined + (portref O (instanceref upg_dat_o_OBUF_1__inst)) + (portref (member upg_dat_o 30)) + ) + ) + (net (rename upg_dat_o_20_ "upg_dat_o[20]") (joined + (portref O (instanceref upg_dat_o_OBUF_20__inst)) + (portref (member upg_dat_o 11)) + ) + ) + (net (rename upg_dat_o_21_ "upg_dat_o[21]") (joined + (portref O (instanceref upg_dat_o_OBUF_21__inst)) + (portref (member upg_dat_o 10)) + ) + ) + (net (rename upg_dat_o_22_ "upg_dat_o[22]") (joined + (portref O (instanceref upg_dat_o_OBUF_22__inst)) + (portref (member upg_dat_o 9)) + ) + ) + (net (rename upg_dat_o_23_ "upg_dat_o[23]") (joined + (portref O (instanceref upg_dat_o_OBUF_23__inst)) + (portref (member upg_dat_o 8)) + ) + ) + (net (rename upg_dat_o_24_ "upg_dat_o[24]") (joined + (portref O (instanceref upg_dat_o_OBUF_24__inst)) + (portref (member upg_dat_o 7)) + ) + ) + (net (rename upg_dat_o_25_ "upg_dat_o[25]") (joined + (portref O (instanceref upg_dat_o_OBUF_25__inst)) + (portref (member upg_dat_o 6)) + ) + ) + (net (rename upg_dat_o_26_ "upg_dat_o[26]") (joined + (portref O (instanceref upg_dat_o_OBUF_26__inst)) + (portref (member upg_dat_o 5)) + ) + ) + (net (rename upg_dat_o_27_ "upg_dat_o[27]") (joined + (portref O (instanceref upg_dat_o_OBUF_27__inst)) + (portref (member upg_dat_o 4)) + ) + ) + (net (rename upg_dat_o_28_ "upg_dat_o[28]") (joined + (portref O (instanceref upg_dat_o_OBUF_28__inst)) + (portref (member upg_dat_o 3)) + ) + ) + (net (rename upg_dat_o_29_ "upg_dat_o[29]") (joined + (portref O (instanceref upg_dat_o_OBUF_29__inst)) + (portref (member upg_dat_o 2)) + ) + ) + (net (rename upg_dat_o_2_ "upg_dat_o[2]") (joined + (portref O (instanceref upg_dat_o_OBUF_2__inst)) + (portref (member upg_dat_o 29)) + ) + ) + (net (rename upg_dat_o_30_ "upg_dat_o[30]") (joined + (portref O (instanceref upg_dat_o_OBUF_30__inst)) + (portref (member upg_dat_o 1)) + ) + ) + (net (rename upg_dat_o_31_ "upg_dat_o[31]") (joined + (portref O (instanceref upg_dat_o_OBUF_31__inst)) + (portref (member upg_dat_o 0)) + ) + ) + (net (rename upg_dat_o_3_ "upg_dat_o[3]") (joined + (portref O (instanceref upg_dat_o_OBUF_3__inst)) + (portref (member upg_dat_o 28)) + ) + ) + (net (rename upg_dat_o_4_ "upg_dat_o[4]") (joined + (portref O (instanceref upg_dat_o_OBUF_4__inst)) + (portref (member upg_dat_o 27)) + ) + ) + (net (rename upg_dat_o_5_ "upg_dat_o[5]") (joined + (portref O (instanceref upg_dat_o_OBUF_5__inst)) + (portref (member upg_dat_o 26)) + ) + ) + (net (rename upg_dat_o_6_ "upg_dat_o[6]") (joined + (portref O (instanceref upg_dat_o_OBUF_6__inst)) + (portref (member upg_dat_o 25)) + ) + ) + (net (rename upg_dat_o_7_ "upg_dat_o[7]") (joined + (portref O (instanceref upg_dat_o_OBUF_7__inst)) + (portref (member upg_dat_o 24)) + ) + ) + (net (rename upg_dat_o_8_ "upg_dat_o[8]") (joined + (portref O (instanceref upg_dat_o_OBUF_8__inst)) + (portref (member upg_dat_o 23)) + ) + ) + (net (rename upg_dat_o_9_ "upg_dat_o[9]") (joined + (portref O (instanceref upg_dat_o_OBUF_9__inst)) + (portref (member upg_dat_o 22)) + ) + ) + (net (rename upg_dat_o_OBUF_0_ "upg_dat_o_OBUF[0]") (joined + (portref I (instanceref upg_dat_o_OBUF_0__inst)) + (portref Q (instanceref upg_dat_o_reg_0_)) + ) + ) + (net (rename upg_dat_o_OBUF_10_ "upg_dat_o_OBUF[10]") (joined + (portref I (instanceref upg_dat_o_OBUF_10__inst)) + (portref Q (instanceref upg_dat_o_reg_10_)) + ) + ) + (net (rename upg_dat_o_OBUF_11_ "upg_dat_o_OBUF[11]") (joined + (portref I (instanceref upg_dat_o_OBUF_11__inst)) + (portref Q (instanceref upg_dat_o_reg_11_)) + ) + ) + (net (rename upg_dat_o_OBUF_12_ "upg_dat_o_OBUF[12]") (joined + (portref I (instanceref upg_dat_o_OBUF_12__inst)) + (portref Q (instanceref upg_dat_o_reg_12_)) + ) + ) + (net (rename upg_dat_o_OBUF_13_ "upg_dat_o_OBUF[13]") (joined + (portref I (instanceref upg_dat_o_OBUF_13__inst)) + (portref Q (instanceref upg_dat_o_reg_13_)) + ) + ) + (net (rename upg_dat_o_OBUF_14_ "upg_dat_o_OBUF[14]") (joined + (portref I (instanceref upg_dat_o_OBUF_14__inst)) + (portref Q (instanceref upg_dat_o_reg_14_)) + ) + ) + (net (rename upg_dat_o_OBUF_15_ "upg_dat_o_OBUF[15]") (joined + (portref I (instanceref upg_dat_o_OBUF_15__inst)) + (portref Q (instanceref upg_dat_o_reg_15_)) + ) + ) + (net (rename upg_dat_o_OBUF_16_ "upg_dat_o_OBUF[16]") (joined + (portref I (instanceref upg_dat_o_OBUF_16__inst)) + (portref Q (instanceref upg_dat_o_reg_16_)) + ) + ) + (net (rename upg_dat_o_OBUF_17_ "upg_dat_o_OBUF[17]") (joined + (portref I (instanceref upg_dat_o_OBUF_17__inst)) + (portref Q (instanceref upg_dat_o_reg_17_)) + ) + ) + (net (rename upg_dat_o_OBUF_18_ "upg_dat_o_OBUF[18]") (joined + (portref I (instanceref upg_dat_o_OBUF_18__inst)) + (portref Q (instanceref upg_dat_o_reg_18_)) + ) + ) + (net (rename upg_dat_o_OBUF_19_ "upg_dat_o_OBUF[19]") (joined + (portref I (instanceref upg_dat_o_OBUF_19__inst)) + (portref Q (instanceref upg_dat_o_reg_19_)) + ) + ) + (net (rename upg_dat_o_OBUF_1_ "upg_dat_o_OBUF[1]") (joined + (portref I (instanceref upg_dat_o_OBUF_1__inst)) + (portref Q (instanceref upg_dat_o_reg_1_)) + ) + ) + (net (rename upg_dat_o_OBUF_20_ "upg_dat_o_OBUF[20]") (joined + (portref I (instanceref upg_dat_o_OBUF_20__inst)) + (portref Q (instanceref upg_dat_o_reg_20_)) + ) + ) + (net (rename upg_dat_o_OBUF_21_ "upg_dat_o_OBUF[21]") (joined + (portref I (instanceref upg_dat_o_OBUF_21__inst)) + (portref Q (instanceref upg_dat_o_reg_21_)) + ) + ) + (net (rename upg_dat_o_OBUF_22_ "upg_dat_o_OBUF[22]") (joined + (portref I (instanceref upg_dat_o_OBUF_22__inst)) + (portref Q (instanceref upg_dat_o_reg_22_)) + ) + ) + (net (rename upg_dat_o_OBUF_23_ "upg_dat_o_OBUF[23]") (joined + (portref I (instanceref upg_dat_o_OBUF_23__inst)) + (portref Q (instanceref upg_dat_o_reg_23_)) + ) + ) + (net (rename upg_dat_o_OBUF_24_ "upg_dat_o_OBUF[24]") (joined + (portref I (instanceref upg_dat_o_OBUF_24__inst)) + (portref Q (instanceref upg_dat_o_reg_24_)) + ) + ) + (net (rename upg_dat_o_OBUF_25_ "upg_dat_o_OBUF[25]") (joined + (portref I (instanceref upg_dat_o_OBUF_25__inst)) + (portref Q (instanceref upg_dat_o_reg_25_)) + ) + ) + (net (rename upg_dat_o_OBUF_26_ "upg_dat_o_OBUF[26]") (joined + (portref I (instanceref upg_dat_o_OBUF_26__inst)) + (portref Q (instanceref upg_dat_o_reg_26_)) + ) + ) + (net (rename upg_dat_o_OBUF_27_ "upg_dat_o_OBUF[27]") (joined + (portref I (instanceref upg_dat_o_OBUF_27__inst)) + (portref Q (instanceref upg_dat_o_reg_27_)) + ) + ) + (net (rename upg_dat_o_OBUF_28_ "upg_dat_o_OBUF[28]") (joined + (portref I (instanceref upg_dat_o_OBUF_28__inst)) + (portref Q (instanceref upg_dat_o_reg_28_)) + ) + ) + (net (rename upg_dat_o_OBUF_29_ "upg_dat_o_OBUF[29]") (joined + (portref I (instanceref upg_dat_o_OBUF_29__inst)) + (portref Q (instanceref upg_dat_o_reg_29_)) + ) + ) + (net (rename upg_dat_o_OBUF_2_ "upg_dat_o_OBUF[2]") (joined + (portref I (instanceref upg_dat_o_OBUF_2__inst)) + (portref Q (instanceref upg_dat_o_reg_2_)) + ) + ) + (net (rename upg_dat_o_OBUF_30_ "upg_dat_o_OBUF[30]") (joined + (portref I (instanceref upg_dat_o_OBUF_30__inst)) + (portref Q (instanceref upg_dat_o_reg_30_)) + ) + ) + (net (rename upg_dat_o_OBUF_31_ "upg_dat_o_OBUF[31]") (joined + (portref I (instanceref upg_dat_o_OBUF_31__inst)) + (portref Q (instanceref upg_dat_o_reg_31_)) + ) + ) + (net (rename upg_dat_o_OBUF_3_ "upg_dat_o_OBUF[3]") (joined + (portref I (instanceref upg_dat_o_OBUF_3__inst)) + (portref Q (instanceref upg_dat_o_reg_3_)) + ) + ) + (net (rename upg_dat_o_OBUF_4_ "upg_dat_o_OBUF[4]") (joined + (portref I (instanceref upg_dat_o_OBUF_4__inst)) + (portref Q (instanceref upg_dat_o_reg_4_)) + ) + ) + (net (rename upg_dat_o_OBUF_5_ "upg_dat_o_OBUF[5]") (joined + (portref I (instanceref upg_dat_o_OBUF_5__inst)) + (portref Q (instanceref upg_dat_o_reg_5_)) + ) + ) + (net (rename upg_dat_o_OBUF_6_ "upg_dat_o_OBUF[6]") (joined + (portref I (instanceref upg_dat_o_OBUF_6__inst)) + (portref Q (instanceref upg_dat_o_reg_6_)) + ) + ) + (net (rename upg_dat_o_OBUF_7_ "upg_dat_o_OBUF[7]") (joined + (portref I (instanceref upg_dat_o_OBUF_7__inst)) + (portref Q (instanceref upg_dat_o_reg_7_)) + ) + ) + (net (rename upg_dat_o_OBUF_8_ "upg_dat_o_OBUF[8]") (joined + (portref I (instanceref upg_dat_o_OBUF_8__inst)) + (portref Q (instanceref upg_dat_o_reg_8_)) + ) + ) + (net (rename upg_dat_o_OBUF_9_ "upg_dat_o_OBUF[9]") (joined + (portref I (instanceref upg_dat_o_OBUF_9__inst)) + (portref Q (instanceref upg_dat_o_reg_9_)) + ) + ) + (net upg_done_o (joined + (portref O (instanceref upg_done_o_OBUF_inst)) + (portref upg_done_o) + ) + ) + (net upg_done_o_OBUF (joined + (portref I (instanceref upg_done_o_OBUF_inst)) + (portref Q (instanceref upg_done_o_reg)) + ) + ) + (net upg_done_o_i_1_n_0 (joined + (portref CE (instanceref upg_done_o_reg)) + (portref O (instanceref upg_done_o_i_1)) + ) + ) + (net upg_done_o_i_2_n_0 (joined + (portref D (instanceref upg_done_o_reg)) + (portref I0 (instanceref s_axi_wdata_4__i_3)) + (portref I0 (instanceref upg_done_o_i_1)) + (portref I1 (instanceref s_axi_wstrb_3__i_1)) + (portref O (instanceref upg_done_o_i_2)) + ) + ) + (net upg_done_o_i_3_n_0 (joined + (portref I5 (instanceref upg_done_o_i_2)) + (portref O (instanceref upg_done_o_i_3)) + ) + ) + (net upg_rst_i (joined + (portref I (instanceref upg_rst_i_IBUF_inst)) + (portref upg_rst_i) + ) + ) + (net upg_rst_i_IBUF (joined + (portref CLR (instanceref RCS_reg_0_)) + (portref CLR (instanceref RCS_reg_1_)) + (portref CLR (instanceref RCS_reg_2_)) + (portref CLR (instanceref WCS_reg_0_)) + (portref CLR (instanceref WCS_reg_1_)) + (portref CLR (instanceref WCS_reg_2_)) + (portref CLR (instanceref bn_ascii_reg_0_)) + (portref CLR (instanceref bn_ascii_reg_10_)) + (portref CLR (instanceref bn_ascii_reg_11_)) + (portref CLR (instanceref bn_ascii_reg_13_)) + (portref CLR (instanceref bn_ascii_reg_14_)) + (portref CLR (instanceref bn_ascii_reg_16_)) + (portref CLR (instanceref bn_ascii_reg_17_)) + (portref CLR (instanceref bn_ascii_reg_18_)) + (portref CLR (instanceref bn_ascii_reg_19_)) + (portref CLR (instanceref bn_ascii_reg_1_)) + (portref CLR (instanceref bn_ascii_reg_21_)) + (portref CLR (instanceref bn_ascii_reg_22_)) + (portref CLR (instanceref bn_ascii_reg_24_)) + (portref CLR (instanceref bn_ascii_reg_25_)) + (portref CLR (instanceref bn_ascii_reg_26_)) + (portref CLR (instanceref bn_ascii_reg_27_)) + (portref CLR (instanceref bn_ascii_reg_29_)) + (portref CLR (instanceref bn_ascii_reg_2_)) + (portref CLR (instanceref bn_ascii_reg_30_)) + (portref CLR (instanceref bn_ascii_reg_32_)) + (portref CLR (instanceref bn_ascii_reg_33_)) + (portref CLR (instanceref bn_ascii_reg_34_)) + (portref CLR (instanceref bn_ascii_reg_35_)) + (portref CLR (instanceref bn_ascii_reg_37_)) + (portref CLR (instanceref bn_ascii_reg_38_)) + (portref CLR (instanceref bn_ascii_reg_3_)) + (portref CLR (instanceref bn_ascii_reg_40_)) + (portref CLR (instanceref bn_ascii_reg_41_)) + (portref CLR (instanceref bn_ascii_reg_42_)) + (portref CLR (instanceref bn_ascii_reg_43_)) + (portref CLR (instanceref bn_ascii_reg_45_)) + (portref CLR (instanceref bn_ascii_reg_46_)) + (portref CLR (instanceref bn_ascii_reg_48_)) + (portref CLR (instanceref bn_ascii_reg_49_)) + (portref CLR (instanceref bn_ascii_reg_50_)) + (portref CLR (instanceref bn_ascii_reg_51_)) + (portref CLR (instanceref bn_ascii_reg_53_)) + (portref CLR (instanceref bn_ascii_reg_54_)) + (portref CLR (instanceref bn_ascii_reg_56_)) + (portref CLR (instanceref bn_ascii_reg_57_)) + (portref CLR (instanceref bn_ascii_reg_58_)) + (portref CLR (instanceref bn_ascii_reg_59_)) + (portref CLR (instanceref bn_ascii_reg_5_)) + (portref CLR (instanceref bn_ascii_reg_61_)) + (portref CLR (instanceref bn_ascii_reg_62_)) + (portref CLR (instanceref bn_ascii_reg_6_)) + (portref CLR (instanceref bn_ascii_reg_8_)) + (portref CLR (instanceref bn_ascii_reg_9_)) + (portref CLR (instanceref byte_cnt_reg_0_)) + (portref CLR (instanceref byte_cnt_reg_10_)) + (portref CLR (instanceref byte_cnt_reg_11_)) + (portref CLR (instanceref byte_cnt_reg_12_)) + (portref CLR (instanceref byte_cnt_reg_13_)) + (portref CLR (instanceref byte_cnt_reg_14_)) + (portref CLR (instanceref byte_cnt_reg_15_)) + (portref CLR (instanceref byte_cnt_reg_16_)) + (portref CLR (instanceref byte_cnt_reg_17_)) + (portref CLR (instanceref byte_cnt_reg_18_)) + (portref CLR (instanceref byte_cnt_reg_19_)) + (portref CLR (instanceref byte_cnt_reg_1_)) + (portref CLR (instanceref byte_cnt_reg_20_)) + (portref CLR (instanceref byte_cnt_reg_21_)) + (portref CLR (instanceref byte_cnt_reg_22_)) + (portref CLR (instanceref byte_cnt_reg_23_)) + (portref CLR (instanceref byte_cnt_reg_24_)) + (portref CLR (instanceref byte_cnt_reg_25_)) + (portref CLR (instanceref byte_cnt_reg_26_)) + (portref CLR (instanceref byte_cnt_reg_27_)) + (portref CLR (instanceref byte_cnt_reg_28_)) + (portref CLR (instanceref byte_cnt_reg_29_)) + (portref CLR (instanceref byte_cnt_reg_2_)) + (portref CLR (instanceref byte_cnt_reg_30_)) + (portref CLR (instanceref byte_cnt_reg_31_)) + (portref CLR (instanceref byte_cnt_reg_3_)) + (portref CLR (instanceref byte_cnt_reg_4_)) + (portref CLR (instanceref byte_cnt_reg_5_)) + (portref CLR (instanceref byte_cnt_reg_6_)) + (portref CLR (instanceref byte_cnt_reg_7_)) + (portref CLR (instanceref byte_cnt_reg_8_)) + (portref CLR (instanceref byte_cnt_reg_9_)) + (portref CLR (instanceref byte_len_reg_0_)) + (portref CLR (instanceref byte_len_reg_1_)) + (portref CLR (instanceref byte_len_reg_2_)) + (portref CLR (instanceref byte_len_reg_3_)) + (portref CLR (instanceref byte_len_reg_4_)) + (portref CLR (instanceref byte_len_reg_5_)) + (portref CLR (instanceref byte_len_reg_6_)) + (portref CLR (instanceref byte_len_reg_7_)) + (portref CLR (instanceref byte_num_reg_0_)) + (portref CLR (instanceref byte_num_reg_10_)) + (portref CLR (instanceref byte_num_reg_11_)) + (portref CLR (instanceref byte_num_reg_12_)) + (portref CLR (instanceref byte_num_reg_13_)) + (portref CLR (instanceref byte_num_reg_14_)) + (portref CLR (instanceref byte_num_reg_15_)) + (portref CLR (instanceref byte_num_reg_16_)) + (portref CLR (instanceref byte_num_reg_17_)) + (portref CLR (instanceref byte_num_reg_18_)) + (portref CLR (instanceref byte_num_reg_19_)) + (portref CLR (instanceref byte_num_reg_1_)) + (portref CLR (instanceref byte_num_reg_20_)) + (portref CLR (instanceref byte_num_reg_21_)) + (portref CLR (instanceref byte_num_reg_22_)) + (portref CLR (instanceref byte_num_reg_23_)) + (portref CLR (instanceref byte_num_reg_24_)) + (portref CLR (instanceref byte_num_reg_25_)) + (portref CLR (instanceref byte_num_reg_26_)) + (portref CLR (instanceref byte_num_reg_27_)) + (portref CLR (instanceref byte_num_reg_28_)) + (portref CLR (instanceref byte_num_reg_29_)) + (portref CLR (instanceref byte_num_reg_2_)) + (portref CLR (instanceref byte_num_reg_30_)) + (portref CLR (instanceref byte_num_reg_31_)) + (portref CLR (instanceref byte_num_reg_3_)) + (portref CLR (instanceref byte_num_reg_4_)) + (portref CLR (instanceref byte_num_reg_5_)) + (portref CLR (instanceref byte_num_reg_6_)) + (portref CLR (instanceref byte_num_reg_7_)) + (portref CLR (instanceref byte_num_reg_8_)) + (portref CLR (instanceref byte_num_reg_9_)) + (portref CLR (instanceref dbuf_reg_0_)) + (portref CLR (instanceref dbuf_reg_10_)) + (portref CLR (instanceref dbuf_reg_11_)) + (portref CLR (instanceref dbuf_reg_12_)) + (portref CLR (instanceref dbuf_reg_13_)) + (portref CLR (instanceref dbuf_reg_14_)) + (portref CLR (instanceref dbuf_reg_15_)) + (portref CLR (instanceref dbuf_reg_16_)) + (portref CLR (instanceref dbuf_reg_17_)) + (portref CLR (instanceref dbuf_reg_18_)) + (portref CLR (instanceref dbuf_reg_19_)) + (portref CLR (instanceref dbuf_reg_1_)) + (portref CLR (instanceref dbuf_reg_20_)) + (portref CLR (instanceref dbuf_reg_21_)) + (portref CLR (instanceref dbuf_reg_22_)) + (portref CLR (instanceref dbuf_reg_23_)) + (portref CLR (instanceref dbuf_reg_2_)) + (portref CLR (instanceref dbuf_reg_3_)) + (portref CLR (instanceref dbuf_reg_4_)) + (portref CLR (instanceref dbuf_reg_5_)) + (portref CLR (instanceref dbuf_reg_6_)) + (portref CLR (instanceref dbuf_reg_7_)) + (portref CLR (instanceref dbuf_reg_8_)) + (portref CLR (instanceref dbuf_reg_9_)) + (portref CLR (instanceref disp_reg_0_)) + (portref CLR (instanceref disp_reg_1_)) + (portref CLR (instanceref disp_reg_2_)) + (portref CLR (instanceref disp_reg_3_)) + (portref CLR (instanceref disp_reg_4_)) + (portref CLR (instanceref disp_reg_5_)) + (portref CLR (instanceref disp_reg_6_)) + (portref CLR (instanceref disp_reg_7_)) + (portref CLR (instanceref initFlag_reg)) + (portref CLR (instanceref len_cnt_reg_0_)) + (portref CLR (instanceref len_cnt_reg_1_)) + (portref CLR (instanceref len_cnt_reg_2_)) + (portref CLR (instanceref len_cnt_reg_3_)) + (portref CLR (instanceref msg_indx_reg_0_)) + (portref CLR (instanceref msg_indx_reg_1_)) + (portref CLR (instanceref msg_indx_reg_2_)) + (portref CLR (instanceref msg_indx_reg_3_)) + (portref CLR (instanceref msg_indx_reg_4_)) + (portref CLR (instanceref msg_indx_reg_5_)) + (portref CLR (instanceref msg_indx_reg_6_)) + (portref CLR (instanceref msg_indx_reg_7_)) + (portref CLR (instanceref oldInitF_reg)) + (portref CLR (instanceref rdStat_reg)) + (portref CLR (instanceref recv_done_reg)) + (portref CLR (instanceref rwait_cnt_reg_10_)) + (portref CLR (instanceref rwait_cnt_reg_11_)) + (portref CLR (instanceref rwait_cnt_reg_12_)) + (portref CLR (instanceref rwait_cnt_reg_13_)) + (portref CLR (instanceref rwait_cnt_reg_14_)) + (portref CLR (instanceref rwait_cnt_reg_15_)) + (portref CLR (instanceref rwait_cnt_reg_1_)) + (portref CLR (instanceref rwait_cnt_reg_2_)) + (portref CLR (instanceref rwait_cnt_reg_3_)) + (portref CLR (instanceref rwait_cnt_reg_4_)) + (portref CLR (instanceref rwait_cnt_reg_5_)) + (portref CLR (instanceref rwait_cnt_reg_6_)) + (portref CLR (instanceref rwait_cnt_reg_7_)) + (portref CLR (instanceref rwait_cnt_reg_8_)) + (portref CLR (instanceref rwait_cnt_reg_9_)) + (portref CLR (instanceref rx_done_reg)) + (portref CLR (instanceref statReg_reg_0_)) + (portref CLR (instanceref uart_wen_reg)) + (portref CLR (instanceref upg_adr_o_reg_0_)) + (portref CLR (instanceref upg_adr_o_reg_10_)) + (portref CLR (instanceref upg_adr_o_reg_11_)) + (portref CLR (instanceref upg_adr_o_reg_12_)) + (portref CLR (instanceref upg_adr_o_reg_13_)) + (portref CLR (instanceref upg_adr_o_reg_14_)) + (portref CLR (instanceref upg_adr_o_reg_1_)) + (portref CLR (instanceref upg_adr_o_reg_2_)) + (portref CLR (instanceref upg_adr_o_reg_3_)) + (portref CLR (instanceref upg_adr_o_reg_4_)) + (portref CLR (instanceref upg_adr_o_reg_5_)) + (portref CLR (instanceref upg_adr_o_reg_6_)) + (portref CLR (instanceref upg_adr_o_reg_7_)) + (portref CLR (instanceref upg_adr_o_reg_8_)) + (portref CLR (instanceref upg_adr_o_reg_9_)) + (portref CLR (instanceref upg_dat_o_reg_0_)) + (portref CLR (instanceref upg_dat_o_reg_10_)) + (portref CLR (instanceref upg_dat_o_reg_11_)) + (portref CLR (instanceref upg_dat_o_reg_12_)) + (portref CLR (instanceref upg_dat_o_reg_13_)) + (portref CLR (instanceref upg_dat_o_reg_14_)) + (portref CLR (instanceref upg_dat_o_reg_15_)) + (portref CLR (instanceref upg_dat_o_reg_16_)) + (portref CLR (instanceref upg_dat_o_reg_17_)) + (portref CLR (instanceref upg_dat_o_reg_18_)) + (portref CLR (instanceref upg_dat_o_reg_19_)) + (portref CLR (instanceref upg_dat_o_reg_1_)) + (portref CLR (instanceref upg_dat_o_reg_20_)) + (portref CLR (instanceref upg_dat_o_reg_21_)) + (portref CLR (instanceref upg_dat_o_reg_22_)) + (portref CLR (instanceref upg_dat_o_reg_23_)) + (portref CLR (instanceref upg_dat_o_reg_24_)) + (portref CLR (instanceref upg_dat_o_reg_25_)) + (portref CLR (instanceref upg_dat_o_reg_26_)) + (portref CLR (instanceref upg_dat_o_reg_27_)) + (portref CLR (instanceref upg_dat_o_reg_28_)) + (portref CLR (instanceref upg_dat_o_reg_29_)) + (portref CLR (instanceref upg_dat_o_reg_2_)) + (portref CLR (instanceref upg_dat_o_reg_30_)) + (portref CLR (instanceref upg_dat_o_reg_31_)) + (portref CLR (instanceref upg_dat_o_reg_3_)) + (portref CLR (instanceref upg_dat_o_reg_4_)) + (portref CLR (instanceref upg_dat_o_reg_5_)) + (portref CLR (instanceref upg_dat_o_reg_6_)) + (portref CLR (instanceref upg_dat_o_reg_7_)) + (portref CLR (instanceref upg_dat_o_reg_8_)) + (portref CLR (instanceref upg_dat_o_reg_9_)) + (portref CLR (instanceref upg_done_o_reg)) + (portref CLR (instanceref upg_wen_o_reg)) + (portref CLR (instanceref wr_byte_len_done_reg)) + (portref CLR (instanceref wr_byte_num_done_reg)) + (portref CLR (instanceref wwait_cnt_reg_10_)) + (portref CLR (instanceref wwait_cnt_reg_11_)) + (portref CLR (instanceref wwait_cnt_reg_12_)) + (portref CLR (instanceref wwait_cnt_reg_13_)) + (portref CLR (instanceref wwait_cnt_reg_14_)) + (portref CLR (instanceref wwait_cnt_reg_15_)) + (portref CLR (instanceref wwait_cnt_reg_1_)) + (portref CLR (instanceref wwait_cnt_reg_2_)) + (portref CLR (instanceref wwait_cnt_reg_3_)) + (portref CLR (instanceref wwait_cnt_reg_4_)) + (portref CLR (instanceref wwait_cnt_reg_5_)) + (portref CLR (instanceref wwait_cnt_reg_6_)) + (portref CLR (instanceref wwait_cnt_reg_7_)) + (portref CLR (instanceref wwait_cnt_reg_8_)) + (portref CLR (instanceref wwait_cnt_reg_9_)) + (portref I0 (instanceref axi_uart_inst_i_1)) + (portref I0 (instanceref s_axi_arvalid_i_2)) + (portref I1 (instanceref recv_done_i_1)) + (portref I1 (instanceref s_axi_wdata_4__i_1)) + (portref I1 (instanceref s_axi_wdata_6__i_1)) + (portref I1 (instanceref uart_wen_i_1)) + (portref I1 (instanceref upg_wen_o_i_1)) + (portref I2 (instanceref s_axi_araddr_3__i_1)) + (portref I2 (instanceref s_axi_awaddr_3__i_1)) + (portref I2 (instanceref s_axi_awvalid_i_2)) + (portref I2 (instanceref upg_adr_o_14__i_1)) + (portref I3 (instanceref byte_cnt_31__i_1)) + (portref I3 (instanceref uart_rdat_7__i_1)) + (portref I4 (instanceref upg_wen_o_i_3)) + (portref O (instanceref upg_rst_i_IBUF_inst)) + (portref PRE (instanceref rwait_cnt_reg_0_)) + (portref PRE (instanceref wwait_cnt_reg_0_)) + ) + ) + (net upg_rx_i (joined + (portref I (instanceref upg_rx_i_IBUF_inst)) + (portref upg_rx_i) + ) + ) + (net upg_rx_i_IBUF (joined + (portref O (instanceref upg_rx_i_IBUF_inst)) + (portref rx (instanceref axi_uart_inst)) + ) + ) + (net upg_tx_o (joined + (portref O (instanceref upg_tx_o_OBUF_inst)) + (portref upg_tx_o) + ) + ) + (net upg_tx_o_OBUF (joined + (portref I (instanceref upg_tx_o_OBUF_inst)) + (portref tx (instanceref axi_uart_inst)) + ) + ) + (net upg_wen_o (joined + (portref O (instanceref upg_wen_o_OBUF_inst)) + (portref upg_wen_o) + ) + ) + (net upg_wen_o2_out (joined + (portref CE (instanceref upg_wen_o_reg)) + (portref O (instanceref upg_wen_o_i_1)) + ) + ) + (net upg_wen_o_OBUF (joined + (portref I (instanceref upg_wen_o_OBUF_inst)) + (portref Q (instanceref upg_wen_o_reg)) + ) + ) + (net upg_wen_o_i_2_n_0 (joined + (portref D (instanceref upg_wen_o_reg)) + (portref O (instanceref upg_wen_o_i_2)) + ) + ) + (net upg_wen_o_i_4_n_0 (joined + (portref I0 (instanceref upg_wen_o_i_2)) + (portref I1 (instanceref upg_adr_o_14__i_1)) + (portref I2 (instanceref upg_wen_o_i_1)) + (portref I3 (instanceref disp_6__i_2)) + (portref O (instanceref upg_wen_o_i_4)) + ) + ) + (net upg_wen_o_i_5_n_0 (joined + (portref I0 (instanceref upg_wen_o_i_3)) + (portref O (instanceref upg_wen_o_i_5)) + ) + ) + (net upg_wen_o_i_6_n_0 (joined + (portref I4 (instanceref upg_wen_o_i_4)) + (portref O (instanceref upg_wen_o_i_6)) + ) + ) + (net wr_byte_len_done0 (joined + (portref D (instanceref wr_byte_len_done_reg)) + (portref I0 (instanceref byte_len_7__i_1)) + (portref O (instanceref wr_byte_len_done_i_1)) + ) + ) + (net wr_byte_len_done_i_2_n_0 (joined + (portref I1 (instanceref wr_byte_len_done_i_1)) + (portref O (instanceref wr_byte_len_done_i_2)) + ) + ) + (net wr_byte_len_done_reg_n_0 (joined + (portref I0 (instanceref byte_num_31__i_1)) + (portref I0 (instanceref wr_byte_len_done_i_1)) + (portref I2 (instanceref bn_ascii_62__i_1)) + (portref Q (instanceref wr_byte_len_done_reg)) + ) + ) + (net wr_byte_num_done (joined + (portref CE (instanceref bn_ascii_reg_0_)) + (portref CE (instanceref bn_ascii_reg_10_)) + (portref CE (instanceref bn_ascii_reg_11_)) + (portref CE (instanceref bn_ascii_reg_13_)) + (portref CE (instanceref bn_ascii_reg_14_)) + (portref CE (instanceref bn_ascii_reg_16_)) + (portref CE (instanceref bn_ascii_reg_17_)) + (portref CE (instanceref bn_ascii_reg_18_)) + (portref CE (instanceref bn_ascii_reg_19_)) + (portref CE (instanceref bn_ascii_reg_1_)) + (portref CE (instanceref bn_ascii_reg_21_)) + (portref CE (instanceref bn_ascii_reg_22_)) + (portref CE (instanceref bn_ascii_reg_24_)) + (portref CE (instanceref bn_ascii_reg_25_)) + (portref CE (instanceref bn_ascii_reg_26_)) + (portref CE (instanceref bn_ascii_reg_27_)) + (portref CE (instanceref bn_ascii_reg_29_)) + (portref CE (instanceref bn_ascii_reg_2_)) + (portref CE (instanceref bn_ascii_reg_30_)) + (portref CE (instanceref bn_ascii_reg_32_)) + (portref CE (instanceref bn_ascii_reg_33_)) + (portref CE (instanceref bn_ascii_reg_34_)) + (portref CE (instanceref bn_ascii_reg_35_)) + (portref CE (instanceref bn_ascii_reg_37_)) + (portref CE (instanceref bn_ascii_reg_38_)) + (portref CE (instanceref bn_ascii_reg_3_)) + (portref CE (instanceref bn_ascii_reg_40_)) + (portref CE (instanceref bn_ascii_reg_41_)) + (portref CE (instanceref bn_ascii_reg_42_)) + (portref CE (instanceref bn_ascii_reg_43_)) + (portref CE (instanceref bn_ascii_reg_45_)) + (portref CE (instanceref bn_ascii_reg_46_)) + (portref CE (instanceref bn_ascii_reg_48_)) + (portref CE (instanceref bn_ascii_reg_49_)) + (portref CE (instanceref bn_ascii_reg_50_)) + (portref CE (instanceref bn_ascii_reg_51_)) + (portref CE (instanceref bn_ascii_reg_53_)) + (portref CE (instanceref bn_ascii_reg_54_)) + (portref CE (instanceref bn_ascii_reg_56_)) + (portref CE (instanceref bn_ascii_reg_57_)) + (portref CE (instanceref bn_ascii_reg_58_)) + (portref CE (instanceref bn_ascii_reg_59_)) + (portref CE (instanceref bn_ascii_reg_5_)) + (portref CE (instanceref bn_ascii_reg_61_)) + (portref CE (instanceref bn_ascii_reg_62_)) + (portref CE (instanceref bn_ascii_reg_6_)) + (portref CE (instanceref bn_ascii_reg_8_)) + (portref CE (instanceref bn_ascii_reg_9_)) + (portref CE (instanceref wr_byte_num_done_reg)) + (portref O (instanceref bn_ascii_62__i_1)) + ) + ) + (net wr_byte_num_done0 (joined + (portref D (instanceref wr_byte_num_done_reg)) + (portref I3 (instanceref bn_ascii_62__i_1)) + (portref O (instanceref wr_byte_num_done_i_1)) + ) + ) + (net wr_byte_num_done_i_2_n_0 (joined + (portref I5 (instanceref wr_byte_num_done_i_1)) + (portref O (instanceref wr_byte_num_done_i_2)) + ) + ) + (net wr_byte_num_done_i_3_n_0 (joined + (portref I5 (instanceref wr_byte_num_done_i_2)) + (portref O (instanceref wr_byte_num_done_i_3)) + ) + ) + (net wr_byte_num_done_reg_n_0 (joined + (portref I0 (instanceref bn_ascii_62__i_1)) + (portref I0 (instanceref disp_3__i_1)) + (portref I0 (instanceref disp_4__i_1)) + (portref I0 (instanceref disp_6__i_2)) + (portref I1 (instanceref byte_cnt_31__i_1)) + (portref I1 (instanceref disp_5__i_2)) + (portref I2 (instanceref byte_num_31__i_1)) + (portref I2 (instanceref disp_0__i_1)) + (portref I3 (instanceref disp_1__i_1)) + (portref I3 (instanceref disp_2__i_2)) + (portref I3 (instanceref recv_done_i_1)) + (portref Q (instanceref wr_byte_num_done_reg)) + ) + ) + (net (rename wwait_cnt_0_ "wwait_cnt[0]") (joined + (portref D (instanceref wwait_cnt_reg_0_)) + (portref O (instanceref wwait_cnt_0__i_1)) + ) + ) + (net (rename wwait_cnt_10_ "wwait_cnt[10]") (joined + (portref D (instanceref wwait_cnt_reg_10_)) + (portref O (instanceref wwait_cnt_10__i_1)) + ) + ) + (net (rename wwait_cnt_11_ "wwait_cnt[11]") (joined + (portref D (instanceref wwait_cnt_reg_11_)) + (portref O (instanceref wwait_cnt_11__i_1)) + ) + ) + (net (rename wwait_cnt_12_ "wwait_cnt[12]") (joined + (portref D (instanceref wwait_cnt_reg_12_)) + (portref O (instanceref wwait_cnt_12__i_1)) + ) + ) + (net (rename wwait_cnt_13_ "wwait_cnt[13]") (joined + (portref D (instanceref wwait_cnt_reg_13_)) + (portref O (instanceref wwait_cnt_13__i_1)) + ) + ) + (net (rename wwait_cnt_14_ "wwait_cnt[14]") (joined + (portref D (instanceref wwait_cnt_reg_14_)) + (portref O (instanceref wwait_cnt_14__i_1)) + ) + ) + (net (rename wwait_cnt_15_ "wwait_cnt[15]") (joined + (portref D (instanceref wwait_cnt_reg_15_)) + (portref O (instanceref wwait_cnt_15__i_2)) + ) + ) + (net (rename wwait_cnt_15__i_1_n_0 "wwait_cnt[15]_i_1_n_0") (joined + (portref CE (instanceref wwait_cnt_reg_0_)) + (portref CE (instanceref wwait_cnt_reg_10_)) + (portref CE (instanceref wwait_cnt_reg_11_)) + (portref CE (instanceref wwait_cnt_reg_12_)) + (portref CE (instanceref wwait_cnt_reg_13_)) + (portref CE (instanceref wwait_cnt_reg_14_)) + (portref CE (instanceref wwait_cnt_reg_15_)) + (portref CE (instanceref wwait_cnt_reg_1_)) + (portref CE (instanceref wwait_cnt_reg_2_)) + (portref CE (instanceref wwait_cnt_reg_3_)) + (portref CE (instanceref wwait_cnt_reg_4_)) + (portref CE (instanceref wwait_cnt_reg_5_)) + (portref CE (instanceref wwait_cnt_reg_6_)) + (portref CE (instanceref wwait_cnt_reg_7_)) + (portref CE (instanceref wwait_cnt_reg_8_)) + (portref CE (instanceref wwait_cnt_reg_9_)) + (portref O (instanceref wwait_cnt_15__i_1)) + ) + ) + (net (rename wwait_cnt_15__i_4_n_0 "wwait_cnt[15]_i_4_n_0") (joined + (portref I1 (instanceref wwait_cnt_10__i_1)) + (portref I1 (instanceref wwait_cnt_11__i_1)) + (portref I1 (instanceref wwait_cnt_12__i_1)) + (portref I1 (instanceref wwait_cnt_13__i_1)) + (portref I1 (instanceref wwait_cnt_14__i_1)) + (portref I1 (instanceref wwait_cnt_15__i_2)) + (portref I1 (instanceref wwait_cnt_1__i_1)) + (portref I1 (instanceref wwait_cnt_2__i_1)) + (portref I1 (instanceref wwait_cnt_3__i_1)) + (portref I1 (instanceref wwait_cnt_4__i_1)) + (portref I1 (instanceref wwait_cnt_5__i_1)) + (portref I1 (instanceref wwait_cnt_6__i_1)) + (portref I1 (instanceref wwait_cnt_7__i_1)) + (portref I1 (instanceref wwait_cnt_8__i_1)) + (portref I1 (instanceref wwait_cnt_9__i_1)) + (portref O (instanceref wwait_cnt_15__i_4)) + ) + ) + (net (rename wwait_cnt_15__i_5_n_0 "wwait_cnt[15]_i_5_n_0") (joined + (portref I0 (instanceref wwait_cnt_15__i_4)) + (portref O (instanceref wwait_cnt_15__i_5)) + ) + ) + (net (rename wwait_cnt_15__i_6_n_0 "wwait_cnt[15]_i_6_n_0") (joined + (portref I5 (instanceref wwait_cnt_15__i_4)) + (portref O (instanceref wwait_cnt_15__i_6)) + ) + ) + (net (rename wwait_cnt_15__i_7_n_0 "wwait_cnt[15]_i_7_n_0") (joined + (portref I4 (instanceref wwait_cnt_15__i_6)) + (portref O (instanceref wwait_cnt_15__i_7)) + ) + ) + (net (rename wwait_cnt_1_ "wwait_cnt[1]") (joined + (portref D (instanceref wwait_cnt_reg_1_)) + (portref O (instanceref wwait_cnt_1__i_1)) + ) + ) + (net (rename wwait_cnt_2_ "wwait_cnt[2]") (joined + (portref D (instanceref wwait_cnt_reg_2_)) + (portref O (instanceref wwait_cnt_2__i_1)) + ) + ) + (net (rename wwait_cnt_3_ "wwait_cnt[3]") (joined + (portref D (instanceref wwait_cnt_reg_3_)) + (portref O (instanceref wwait_cnt_3__i_1)) + ) + ) + (net (rename wwait_cnt_4_ "wwait_cnt[4]") (joined + (portref D (instanceref wwait_cnt_reg_4_)) + (portref O (instanceref wwait_cnt_4__i_1)) + ) + ) + (net (rename wwait_cnt_5_ "wwait_cnt[5]") (joined + (portref D (instanceref wwait_cnt_reg_5_)) + (portref O (instanceref wwait_cnt_5__i_1)) + ) + ) + (net (rename wwait_cnt_6_ "wwait_cnt[6]") (joined + (portref D (instanceref wwait_cnt_reg_6_)) + (portref O (instanceref wwait_cnt_6__i_1)) + ) + ) + (net (rename wwait_cnt_7_ "wwait_cnt[7]") (joined + (portref D (instanceref wwait_cnt_reg_7_)) + (portref O (instanceref wwait_cnt_7__i_1)) + ) + ) + (net (rename wwait_cnt_8_ "wwait_cnt[8]") (joined + (portref D (instanceref wwait_cnt_reg_8_)) + (portref O (instanceref wwait_cnt_8__i_1)) + ) + ) + (net (rename wwait_cnt_9_ "wwait_cnt[9]") (joined + (portref D (instanceref wwait_cnt_reg_9_)) + (portref O (instanceref wwait_cnt_9__i_1)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_0 "wwait_cnt_reg[12]_i_2_n_0") (joined + (portref CI (instanceref wwait_cnt_reg_15__i_3)) + (portref (member CO 0) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_1 "wwait_cnt_reg[12]_i_2_n_1") (joined + (portref (member CO 1) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_2 "wwait_cnt_reg[12]_i_2_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_3 "wwait_cnt_reg[12]_i_2_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_4 "wwait_cnt_reg[12]_i_2_n_4") (joined + (portref I0 (instanceref wwait_cnt_12__i_1)) + (portref (member O 0) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_5 "wwait_cnt_reg[12]_i_2_n_5") (joined + (portref I0 (instanceref wwait_cnt_11__i_1)) + (portref (member O 1) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_6 "wwait_cnt_reg[12]_i_2_n_6") (joined + (portref I0 (instanceref wwait_cnt_10__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_7 "wwait_cnt_reg[12]_i_2_n_7") (joined + (portref I0 (instanceref wwait_cnt_9__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_2 "wwait_cnt_reg[15]_i_3_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_3 "wwait_cnt_reg[15]_i_3_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_5 "wwait_cnt_reg[15]_i_3_n_5") (joined + (portref I0 (instanceref wwait_cnt_15__i_2)) + (portref (member O 1) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_6 "wwait_cnt_reg[15]_i_3_n_6") (joined + (portref I0 (instanceref wwait_cnt_14__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_7 "wwait_cnt_reg[15]_i_3_n_7") (joined + (portref I0 (instanceref wwait_cnt_13__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_0 "wwait_cnt_reg[4]_i_2_n_0") (joined + (portref CI (instanceref wwait_cnt_reg_8__i_2)) + (portref (member CO 0) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_1 "wwait_cnt_reg[4]_i_2_n_1") (joined + (portref (member CO 1) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_2 "wwait_cnt_reg[4]_i_2_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_3 "wwait_cnt_reg[4]_i_2_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_4 "wwait_cnt_reg[4]_i_2_n_4") (joined + (portref I0 (instanceref wwait_cnt_4__i_1)) + (portref (member O 0) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_5 "wwait_cnt_reg[4]_i_2_n_5") (joined + (portref I0 (instanceref wwait_cnt_3__i_1)) + (portref (member O 1) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_6 "wwait_cnt_reg[4]_i_2_n_6") (joined + (portref I0 (instanceref wwait_cnt_2__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_7 "wwait_cnt_reg[4]_i_2_n_7") (joined + (portref I0 (instanceref wwait_cnt_1__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_0 "wwait_cnt_reg[8]_i_2_n_0") (joined + (portref CI (instanceref wwait_cnt_reg_12__i_2)) + (portref (member CO 0) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_1 "wwait_cnt_reg[8]_i_2_n_1") (joined + (portref (member CO 1) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_2 "wwait_cnt_reg[8]_i_2_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_3 "wwait_cnt_reg[8]_i_2_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_4 "wwait_cnt_reg[8]_i_2_n_4") (joined + (portref I0 (instanceref wwait_cnt_8__i_1)) + (portref (member O 0) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_5 "wwait_cnt_reg[8]_i_2_n_5") (joined + (portref I0 (instanceref wwait_cnt_7__i_1)) + (portref (member O 1) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_6 "wwait_cnt_reg[8]_i_2_n_6") (joined + (portref I0 (instanceref wwait_cnt_6__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_7 "wwait_cnt_reg[8]_i_2_n_7") (joined + (portref I0 (instanceref wwait_cnt_5__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__0_ "wwait_cnt_reg_n_0_[0]") (joined + (portref CYINIT (instanceref wwait_cnt_reg_4__i_2)) + (portref I0 (instanceref wwait_cnt_0__i_1)) + (portref I1 (instanceref wwait_cnt_15__i_5)) + (portref I2 (instanceref WCS_2__i_4)) + (portref Q (instanceref wwait_cnt_reg_0_)) + ) + ) + (net (rename wwait_cnt_reg_n_0__10_ "wwait_cnt_reg_n_0_[10]") (joined + (portref I2 (instanceref WCS_2__i_2)) + (portref I3 (instanceref wwait_cnt_15__i_7)) + (portref Q (instanceref wwait_cnt_reg_10_)) + (portref (member S 2) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__11_ "wwait_cnt_reg_n_0_[11]") (joined + (portref I2 (instanceref wwait_cnt_15__i_7)) + (portref I4 (instanceref WCS_2__i_2)) + (portref Q (instanceref wwait_cnt_reg_11_)) + (portref (member S 1) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__12_ "wwait_cnt_reg_n_0_[12]") (joined + (portref I0 (instanceref wwait_cnt_15__i_6)) + (portref I3 (instanceref WCS_2__i_2)) + (portref Q (instanceref wwait_cnt_reg_12_)) + (portref (member S 0) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__13_ "wwait_cnt_reg_n_0_[13]") (joined + (portref I1 (instanceref WCS_2__i_2)) + (portref I1 (instanceref wwait_cnt_15__i_6)) + (portref Q (instanceref wwait_cnt_reg_13_)) + (portref (member S 3) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_n_0__14_ "wwait_cnt_reg_n_0_[14]") (joined + (portref I1 (instanceref WCS_2__i_5)) + (portref I1 (instanceref wwait_cnt_15__i_7)) + (portref Q (instanceref wwait_cnt_reg_14_)) + (portref (member S 2) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_n_0__15_ "wwait_cnt_reg_n_0_[15]") (joined + (portref I0 (instanceref WCS_2__i_3)) + (portref I3 (instanceref wwait_cnt_15__i_6)) + (portref Q (instanceref wwait_cnt_reg_15_)) + (portref (member S 1) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_n_0__1_ "wwait_cnt_reg_n_0_[1]") (joined + (portref I1 (instanceref WCS_2__i_3)) + (portref I2 (instanceref wwait_cnt_15__i_6)) + (portref Q (instanceref wwait_cnt_reg_1_)) + (portref (member S 3) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__2_ "wwait_cnt_reg_n_0_[2]") (joined + (portref I3 (instanceref WCS_2__i_4)) + (portref I3 (instanceref wwait_cnt_15__i_5)) + (portref Q (instanceref wwait_cnt_reg_2_)) + (portref (member S 2) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__3_ "wwait_cnt_reg_n_0_[3]") (joined + (portref I2 (instanceref WCS_2__i_5)) + (portref I2 (instanceref wwait_cnt_15__i_5)) + (portref Q (instanceref wwait_cnt_reg_3_)) + (portref (member S 1) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__4_ "wwait_cnt_reg_n_0_[4]") (joined + (portref I2 (instanceref wwait_cnt_15__i_4)) + (portref I3 (instanceref WCS_2__i_3)) + (portref Q (instanceref wwait_cnt_reg_4_)) + (portref (member S 0) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__5_ "wwait_cnt_reg_n_0_[5]") (joined + (portref I1 (instanceref wwait_cnt_15__i_4)) + (portref I2 (instanceref WCS_2__i_3)) + (portref Q (instanceref wwait_cnt_reg_5_)) + (portref (member S 3) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__6_ "wwait_cnt_reg_n_0_[6]") (joined + (portref I0 (instanceref WCS_2__i_4)) + (portref I3 (instanceref wwait_cnt_15__i_4)) + (portref Q (instanceref wwait_cnt_reg_6_)) + (portref (member S 2) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__7_ "wwait_cnt_reg_n_0_[7]") (joined + (portref I0 (instanceref wwait_cnt_15__i_5)) + (portref I1 (instanceref WCS_2__i_4)) + (portref Q (instanceref wwait_cnt_reg_7_)) + (portref (member S 1) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__8_ "wwait_cnt_reg_n_0_[8]") (joined + (portref I0 (instanceref WCS_2__i_5)) + (portref I0 (instanceref wwait_cnt_15__i_7)) + (portref Q (instanceref wwait_cnt_reg_8_)) + (portref (member S 0) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__9_ "wwait_cnt_reg_n_0_[9]") (joined + (portref I3 (instanceref WCS_2__i_5)) + (portref I4 (instanceref wwait_cnt_15__i_4)) + (portref Q (instanceref wwait_cnt_reg_9_)) + (portref (member S 3) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + ) + + (property ADDR_WIDTH (integer 15)) + (property DATA_WIDTH (integer 32)) + (property BYTE_NUM (integer 4)) + (property WIDLE (integer 0)) + (property WDATA_VALID (integer 1)) + (property JUDGE_WRDY (integer 2)) + (property WDATA (integer 3)) + (property WDELAY (integer 4)) + (property RIDLE (integer 0)) + (property RDATA_VALID (integer 1)) + (property JUDGE_RRDY (integer 2)) + (property RDATA (integer 3)) + (property RDELAY (integer 4)) + (property WAIT_NUM (integer 765)) + (property MSG_LEN (integer 38)) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design uart_bmpg + (cellref uart_bmpg (libraryref work)) + (property XLNX_PROJ_DIR (string "H:/Workspace_Xilinx/Vivado/uart_bmpg")) + (property PART (string "xc7a100tfgg484-1")) + ) +) diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v new file mode 100644 index 0000000..81d902b --- /dev/null +++ b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2018/04/27 07:17:21 +// Design Name: +// Module Name: uart_bmpg +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module uart_bmpg( + input wire upg_clk_i, // 10MHz + input wire upg_rst_i, // High active + // blkram signals + output wire upg_clk_o, + output reg upg_wen_o, + output reg [14:0] upg_adr_o, + output reg [31:0] upg_dat_o, + output reg upg_done_o, + // UART Pinouts + input wire upg_rx_i, + output wire upg_tx_o +); + +endmodule diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v new file mode 100644 index 0000000..78d3576 --- /dev/null +++ b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2018/07/12 08:40:58 +// Design Name: +// Module Name: upg +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module upg( + input upg_clk_i, // 10MHz + input upg_rst_i, // High active + // blkram signals + output upg_clk_o, + output upg_wen_o, + output [14:0] upg_adr_o, + output [31:0] upg_dat_o, + output upg_done_o, + // UART Pinouts + input upg_rx_i, + output upg_tx_o +); + + uart_bmpg upg_inst ( + .upg_clk_i (upg_clk_i), // 10MHz + .upg_rst_i (upg_rst_i), // High active + // blkram signals + .upg_clk_o (upg_clk_o), + .upg_wen_o (upg_wen_o), + .upg_adr_o (upg_adr_o), + .upg_dat_o (upg_dat_o), + .upg_done_o (upg_done_o), + // UART Pinouts + .upg_rx_i (upg_rx_i), + .upg_tx_o (upg_tx_o) + ); + +endmodule diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl new file mode 100644 index 0000000..d789dd1 --- /dev/null +++ b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl @@ -0,0 +1,71 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set page [ipgui::add_page $IPINST -name "page"] + set_property tooltip {page} ${page} + ipgui::add_param $IPINST -name "Reset" -parent ${page} + ipgui::add_param $IPINST -name "Input_Clock_Freqency" -parent ${page} + ipgui::add_param $IPINST -name "Baud_Rate" -parent ${page} + ipgui::add_param $IPINST -name "Data_Bits" -parent ${page} + ipgui::add_param $IPINST -name "Parity" -parent ${page} + ipgui::add_param $IPINST -name "Stop_Bits" -parent ${page} + + +} + +proc update_PARAM_VALUE.Baud_Rate { PARAM_VALUE.Baud_Rate } { + # Procedure called to update Baud_Rate when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Baud_Rate { PARAM_VALUE.Baud_Rate } { + # Procedure called to validate Baud_Rate + return true +} + +proc update_PARAM_VALUE.Data_Bits { PARAM_VALUE.Data_Bits } { + # Procedure called to update Data_Bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Data_Bits { PARAM_VALUE.Data_Bits } { + # Procedure called to validate Data_Bits + return true +} + +proc update_PARAM_VALUE.Input_Clock_Freqency { PARAM_VALUE.Input_Clock_Freqency } { + # Procedure called to update Input_Clock_Freqency when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Input_Clock_Freqency { PARAM_VALUE.Input_Clock_Freqency } { + # Procedure called to validate Input_Clock_Freqency + return true +} + +proc update_PARAM_VALUE.Parity { PARAM_VALUE.Parity } { + # Procedure called to update Parity when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Parity { PARAM_VALUE.Parity } { + # Procedure called to validate Parity + return true +} + +proc update_PARAM_VALUE.Reset { PARAM_VALUE.Reset } { + # Procedure called to update Reset when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Reset { PARAM_VALUE.Reset } { + # Procedure called to validate Reset + return true +} + +proc update_PARAM_VALUE.Stop_Bits { PARAM_VALUE.Stop_Bits } { + # Procedure called to update Stop_Bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Stop_Bits { PARAM_VALUE.Stop_Bits } { + # Procedure called to validate Stop_Bits + return true +} + + -- Gitee From c884991b345b23a50e190a809e077e1b89c18178 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:36:04 +0800 Subject: [PATCH 12/57] =?UTF-8?q?feat(mips):=20=20=E6=8E=A5=E5=8F=A3?= =?UTF-8?q?=E8=B0=83=E6=95=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/demo_flow.mips | 7 +- main/mips/cpu_test/situation2.md | 9 +++ main/mips/cpu_test/situation2.mips | 126 ++++++++++++++++++----------- 3 files changed, 94 insertions(+), 48 deletions(-) create mode 100644 main/mips/cpu_test/situation2.md diff --git a/main/mips/cpu_test/demo_flow.mips b/main/mips/cpu_test/demo_flow.mips index 71557f9..f02af91 100644 --- a/main/mips/cpu_test/demo_flow.mips +++ b/main/mips/cpu_test/demo_flow.mips @@ -1,8 +1,9 @@ +.include "../commons/std_io_minisys.macro.mips" .data .text jal static_initialization -while0: +begin: case0: li $a0 7 jal write_data @@ -45,6 +46,6 @@ case7: jal write_control li $v0 500 jal sleep - j while0 -.include "../commons/std_io_minisys.mips" + j begin +.include "../commons/std_io_minisys.impl.mips" diff --git a/main/mips/cpu_test/situation2.md b/main/mips/cpu_test/situation2.md new file mode 100644 index 0000000..557b965 --- /dev/null +++ b/main/mips/cpu_test/situation2.md @@ -0,0 +1,9 @@ +## 娴嬭瘯鍦烘櫙2鏂囨。 + +### 杈撳叆杈撳嚭姒傝堪 + +#### 寮鏈哄惎鍔 + +#### 绛夊緟杈撳叆 + +### \ No newline at end of file diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index d8dc199..603eac4 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -1,58 +1,94 @@ +.include "../commons/std_io_minisys.macro.mips" .data .text +.globl main +main: # todo: 娌′粈涔堢敤锛宑oe鏂囦欢涓嶈兘浣嶇疆鏃犲叧銆 jal static_initialization begin: - jal decode # 浼氳鐩朼0 a1鐨勫笺 - beq $a0 $zero case0 - beq $a0 $s1 case1 - beq $a0 $s2 case2 - beq $a0 $s3 case3 - beq $a0 $s4 case4 - beq $a0 $s5 case5 - beq $a0 $s6 case6 - beq $a0 $s7 case7 + li $v0 10 + jal sleep # 闄嶄綆閫熷害 + + jal decode # 浼氳鐩朼0 a1鐨勫笺 + move $a2 $a0 + + sll $a0 $a0 5 + jal write_control # 鎸囩ず褰撳墠鏄摢涓涓猚ase + set_s_to_be_seven_numbers() + beq $a2 $zero case0 + beq $a2 $s1 case1 + beq $a2 $s2 case2 + beq $a2 $s3 case3 + beq $a2 $s4 case4 + beq $a2 $s5 case5 + beq $a2 $s6 case6 + beq $a2 $s7 case7 case0: - jal read - # jal write_data - li $a0 0xFF - jal write_control - li $v0 1000 - jal sleep - li $a0 0x00 - jal write_control - li $v0 1000 - jal sleep - j begin + jal read + move $s1 $a0 # s1=n锛岃〃绀烘暟缁勯暱搴 + + bne $s1 $zero end_if_case0_0 + jal exception_hint # 濡傛灉鏄0锛屽彧鏄鍛婏紝涓嶉噸鏂拌緭鍏ャ + end_if_case0_0: + li $t0 10 + ble $s1 $t0 end_if_case0_1 + jal exception_hint # 濡傛灉姣10澶э紝鍙槸璀﹀憡锛屼笉閲嶆柊杈撳叆銆 + end_if_case0_1: + addi $s2 $fp 0 # 0鍊嶇殑s0锛 s2鐜板湪鏄暟鎹泦0鐨勫熀鍦板潃銆 + for_case0: + ble $s1 $zero end_for_case0 + # 鐢╟ontrol鐨勫彸杈瑰洓涓伅鎻愮ず姝ｅ湪璇荤鍑犱釜鏁 + li $v0 0 + srl $v1 $s1 0 + jal write_control_set + li $v0 1 + srl $v1 $s1 1 + jal write_control_set + li $v0 2 + srl $v1 $s1 2 + jal write_control_set + li $v0 3 + srl $v1 $s1 3 + jal write_control_set + sleep(100) + # 璇诲彇鏂扮殑鏁般 + jal read + sw $a0 0($s2) # 瀛樺叆s2 + addi $s1 $s1 -1 + addi $s2 $s2 4 # 鎸囬拡鍙崇Щ + j for_case0 + end_for_case0: + j begin case1: - li $a0 0 - jal write_data - li $a0 2 - jal write_control - - j begin + li $a0 0 + jal write_data + li $a0 2 + jal write_control + + j begin case2: - li $v0 7 - jal write_control_set - j begin + li $v0 7 + jal write_control_set + j begin case3: - li $a0 8 - jal write_control - j begin + li $a0 8 + jal write_control + j begin case4: - li $a0 16 - jal write_control - j begin + li $a0 16 + jal write_control + j begin case5: - li $a0 32 - jal write_control - j begin + li $a0 32 + jal write_control + j begin case6: - li $a0 64 - jal write_control - j begin + li $a0 64 + jal write_control + j begin case7: - li $a0 128 - jal write_control - j begin + li $a0 128 + jal write_control + j begin j begin -.include "../commons/std_io_minisys.mips" + +.include "../commons/std_io_minisys.impl.mips" \ No newline at end of file -- Gitee From c91d668b908d5bdd65d1d51313c38ff50edf6093 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:36:49 +0800 Subject: [PATCH 13/57] =?UTF-8?q?feat(mips):=20=E6=96=B0=E7=AE=80=E5=8D=95?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E5=9C=BA=E6=99=AF=EF=BC=9A=E5=86=85=E5=AD=98?= =?UTF-8?q?=E8=AF=BB=E5=86=99=EF=BC=8C=E7=81=AF=E6=A0=87=E5=87=86=E8=BE=93?= =?UTF-8?q?=E5=85=A5=E8=BE=93=E5=87=BA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/datamemory_test.mips | 10 +++++ main/mips/cpu_test/new_situation1.mips | 50 +++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 main/mips/cpu_test/datamemory_test.mips create mode 100644 main/mips/cpu_test/new_situation1.mips diff --git a/main/mips/cpu_test/datamemory_test.mips b/main/mips/cpu_test/datamemory_test.mips new file mode 100644 index 0000000..c5c855c --- /dev/null +++ b/main/mips/cpu_test/datamemory_test.mips @@ -0,0 +1,10 @@ +.include "../commons/std_io_minisys.macro.mips" +.data + buf: .word 0x0000FFFF +.text +begin: + la $t0 buf + lw $a0 0($t0) + jal write_data + j begin +.include "../commons/std_io_minisys.impl.mips" diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips new file mode 100644 index 0000000..12ec432 --- /dev/null +++ b/main/mips/cpu_test/new_situation1.mips @@ -0,0 +1,50 @@ +.include "../commons/std_io_minisys.macro.mips" +.data +.text +.globl main +main: # todo: 娌′粈涔堢敤锛宑oe鏂囦欢涓嶈兘浣嶇疆鏃犲叧銆 +jal static_initialization +begin: + li $v0 10 + jal sleep # 闄嶄綆閫熷害 + + jal decode # 浼氳鐩朼0 a1鐨勫笺 + move $a2 $a0 + + sll $a0 $a0 5 + jal write_control # 鎸囩ず褰撳墠鏄摢涓涓猚ase + set_s_to_be_seven_numbers() + beq $a2 $zero case0 + beq $a2 $s1 case1 + beq $a2 $s2 case2 + beq $a2 $s3 case3 + beq $a2 $s4 case4 + beq $a2 $s5 case5 + beq $a2 $s6 case6 + beq $a2 $s7 case7 +case0: + jal read + jal static_initialization + # jal write_data + # jal is_binary_palindrome + # move $v1 $v0 + # li $v0 0 + # jal write_control_set + j begin +case1: + j begin +case2: + j begin +case3: + j begin +case4: + j begin +case5: + j begin +case6: + j begin +case7: + j begin +j begin +.include "../commons/std_io_minisys.impl.mips" +.include "../commons/std_palindrome.impl.mips" \ No newline at end of file -- Gitee From 45935470a27715e21aad92037b1d4ace59b778be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 17:52:00 +0800 Subject: [PATCH 14/57] =?UTF-8?q?refrac(verilog):=20=E5=A2=9E=E5=8A=A0?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E5=89=8D=E6=B3=A8=E9=87=8A=EF=BC=9B=E9=87=8D?= =?UTF-8?q?=E6=96=B0=E5=AE=89=E6=8E=92=E6=96=87=E4=BB=B6=E5=A4=B9=EF=BC=8C?= =?UTF-8?q?=E4=BB=A5=E4=BD=93=E7=8E=B0=E6=A8=A1=E5=9D=97=E4=B9=8B=E9=97=B4?= =?UTF-8?q?=E4=BE=9D=E8=B5=96=E5=85=B3=E7=B3=BB=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/coe/dmem32_flow.coe | 4096 +++++++++ main/mips/coe/prgmip32_flow.coe | 8192 +++++++++++++++++ .../{basic_modules => mips_cpu}/CPUTOP.v | 19 +- .../{basic_modules => mips_cpu}/TOP_all.v | 17 +- .../{ => mips_cpu}/basic_modules/Decoder.v | 12 + .../{ => mips_cpu}/basic_modules/Ifetc32.v | 21 +- .../{ => mips_cpu}/basic_modules/LED.v | 24 +- .../{ => mips_cpu}/basic_modules/MemOrIO.v | 21 +- .../{ => mips_cpu}/basic_modules/control32.v | 21 +- .../{ => mips_cpu}/basic_modules/dmemory32.v | 21 +- .../{ => mips_cpu}/basic_modules/executs32.v | 21 +- .../{ => mips_cpu}/basic_modules/program.v | 21 +- .../{ => mips_cpu}/basic_modules/switch.v | 26 +- .../light_switch.v | 0 .../test_light_swich.v | 0 15 files changed, 12368 insertions(+), 144 deletions(-) create mode 100644 main/mips/coe/dmem32_flow.coe create mode 100644 main/mips/coe/prgmip32_flow.coe rename main/verilog/{basic_modules => mips_cpu}/CPUTOP.v (97%) rename main/verilog/{basic_modules => mips_cpu}/TOP_all.v (36%) rename main/verilog/{ => mips_cpu}/basic_modules/Decoder.v (90%) rename main/verilog/{ => mips_cpu}/basic_modules/Ifetc32.v (88%) rename main/verilog/{ => mips_cpu}/basic_modules/LED.v (75%) rename main/verilog/{ => mips_cpu}/basic_modules/MemOrIO.v (85%) rename main/verilog/{ => mips_cpu}/basic_modules/control32.v (93%) rename main/verilog/{ => mips_cpu}/basic_modules/dmemory32.v (82%) rename main/verilog/{ => mips_cpu}/basic_modules/executs32.v (94%) rename main/verilog/{ => mips_cpu}/basic_modules/program.v (79%) rename main/verilog/{ => mips_cpu}/basic_modules/switch.v (75%) rename main/verilog/{testMinisys => test_minisys}/light_switch.v (100%) rename test/verilog/{testMinisys => test_minisys}/test_light_swich.v (100%) diff --git a/main/mips/coe/dmem32_flow.coe b/main/mips/coe/dmem32_flow.coe new file mode 100644 index 0000000..acac71c --- /dev/null +++ b/main/mips/coe/dmem32_flow.coe @@ -0,0 +1,4096 @@ +0c000024 +24040007 +0c0000aa +24040001 +0c0000a4 +240201f4 +0c000053 +24040002 +0c0000a4 +240201f4 +0c000053 +24040004 +0c0000a4 +240201f4 +0c000053 +24040008 +0c0000a4 +240201f4 +0c000053 +24040010 +0c0000a4 +240201f4 +0c000053 +24040020 +0c0000a4 +240201f4 +0c000053 +24040040 +0c0000a4 +240201f4 +0c000053 +24040080 +0c0000a4 +240201f4 +0c000053 +08000001 +241cfc00 +241d0100 +241e0200 +2410000b +23bdfff0 +001dd021 +001fd821 +24040000 +0c0000a4 +24040000 +0c0000aa +24100080 +12000007 +8f440004 +00902020 +0c0000a4 +00108042 +24020029 +0c000053 +08000030 +34108000 +12000007 +8f440000 +00902020 +0c0000aa +00108042 +24020029 +0c000053 +08000039 +24040000 +0c0000a4 +24040000 +0c0000aa +24020064 +0c000053 +240400ff +0c0000a4 +3404ffff +0c0000aa +240203e8 +0c000053 +24040000 +0c0000a4 +24040000 +0c0000aa +001bf821 +03e00008 +00024900 +000240c0 +01094020 +01021022 +00024a80 +00025100 +000240c0 +012a1022 +00481022 +2042ffff +1440fffe +03e00008 +8f840072 +00042102 +30850001 +00042042 +03e00008 +001fd821 +24020004 +24030001 +0c00008b +0c00005f +24020064 +0c000053 +1486ff95 +14a0fff7 +24020004 +24030000 +0c00008b +240200c8 +0c000053 +0c00005f +1486ff8d +24020004 +0c00009a +8f840070 +00048021 +0c0000aa +10a0fff6 +24040000 +0c0000aa +24020004 +24030000 +0c00008b +24020003 +0c00009a +24020002 +0c00009a +24020190 +0c000053 +24020003 +0c00009a +24020002 +0c00009a +001bf821 +03e00008 +8f490004 +30630001 +00431804 +00494006 +31080001 +11000002 +01234824 +08000094 +01234825 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +8f490004 +24080001 +00481804 +01234826 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440000 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +001fd821 +8f4f0000 +3404ffff +0c0000aa +24020002 +24030001 +0c00008b +24020003 +24030001 +0c00008b +240203e8 +0c000053 +000f2021 +0c0000aa +24020002 +24030000 +0c00008b +24020003 +24030000 +0c00008b +240201f4 +0c000053 +8f4f0000 +3404ffff +0c0000aa +24020002 +24030001 +0c00008b +24020003 +24030001 +0c00008b +240203e8 +0c000053 +000f2021 +0c0000aa +24020002 +24030000 +0c00008b +24020003 +24030000 +0c00008b +240201f4 +0c000053 +001bf821 +03e00008 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/main/mips/coe/prgmip32_flow.coe b/main/mips/coe/prgmip32_flow.coe new file mode 100644 index 0000000..5d331f7 --- /dev/null +++ b/main/mips/coe/prgmip32_flow.coe @@ -0,0 +1,8192 @@ +0c000024 +24040007 +0c0000aa +24040001 +0c0000a4 +240201f4 +0c000053 +24040002 +0c0000a4 +240201f4 +0c000053 +24040004 +0c0000a4 +240201f4 +0c000053 +24040008 +0c0000a4 +240201f4 +0c000053 +24040010 +0c0000a4 +240201f4 +0c000053 +24040020 +0c0000a4 +240201f4 +0c000053 +24040040 +0c0000a4 +240201f4 +0c000053 +24040080 +0c0000a4 +240201f4 +0c000053 +08000001 +241cfc00 +241d0100 +241e0200 +2410000b +23bdfff0 +001dd021 +001fd821 +24040000 +0c0000a4 +24040000 +0c0000aa +24100080 +12000007 +8f440004 +00902020 +0c0000a4 +00108042 +24020029 +0c000053 +08000030 +34108000 +12000007 +8f440000 +00902020 +0c0000aa +00108042 +24020029 +0c000053 +08000039 +24040000 +0c0000a4 +24040000 +0c0000aa +24020064 +0c000053 +240400ff +0c0000a4 +3404ffff +0c0000aa +240203e8 +0c000053 +24040000 +0c0000a4 +24040000 +0c0000aa +001bf821 +03e00008 +00024900 +000240c0 +01094020 +01021022 +00024a80 +00025100 +000240c0 +012a1022 +00481022 +2042ffff +1440fffe +03e00008 +8f840072 +00042102 +30850001 +00042042 +03e00008 +001fd821 +24020004 +24030001 +0c00008b +0c00005f +24020064 +0c000053 +1486ff95 +14a0fff7 +24020004 +24030000 +0c00008b +240200c8 +0c000053 +0c00005f +1486ff8d +24020004 +0c00009a +8f840070 +00048021 +0c0000aa +10a0fff6 +24040000 +0c0000aa +24020004 +24030000 +0c00008b +24020003 +0c00009a +24020002 +0c00009a +24020190 +0c000053 +24020003 +0c00009a +24020002 +0c00009a +001bf821 +03e00008 +8f490004 +30630001 +00431804 +00494006 +31080001 +11000002 +01234824 +08000094 +01234825 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +8f490004 +24080001 +00481804 +01234826 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440000 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +001fd821 +8f4f0000 +3404ffff +0c0000aa +24020002 +24030001 +0c00008b +24020003 +24030001 +0c00008b +240203e8 +0c000053 +000f2021 +0c0000aa +24020002 +24030000 +0c00008b +24020003 +24030000 +0c00008b +240201f4 +0c000053 +8f4f0000 +3404ffff +0c0000aa +24020002 +24030001 +0c00008b +24020003 +24030001 +0c00008b +240203e8 +0c000053 +000f2021 +0c0000aa +24020002 +24030000 +0c00008b +24020003 +24030000 +0c00008b +240201f4 +0c000053 +001bf821 +03e00008 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/main/verilog/basic_modules/CPUTOP.v b/main/verilog/mips_cpu/CPUTOP.v similarity index 97% rename from main/verilog/basic_modules/CPUTOP.v rename to main/verilog/mips_cpu/CPUTOP.v index 071a1a5..ab503ca 100644 --- a/main/verilog/basic_modules/CPUTOP.v +++ b/main/verilog/mips_cpu/CPUTOP.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology ?????? +// Engineer: ??? // // Create Date: 2022/05/07 12:58:45 -// Design Name: // Module Name: CPU_TOP -// Project Name: -// Target Devices: -// Tool Versions: +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module CPUTOP( input fpga_rst, //Active High input fpga_clk, @@ -168,7 +159,7 @@ Ifetc32 Ifetc32_instance( dmemory32 dmemory32_instance( .ram_clk_i(cpu_clk), .ram_wen_i(MemWrite), - .ram_adr_i(addr_out), + .ram_adr_i(addr_out[15:2]), .ram_dat_i(m_wdata), .ram_dat_o(ram_dat_o), .upg_rst_i(upg_rst), diff --git a/main/verilog/basic_modules/TOP_all.v b/main/verilog/mips_cpu/TOP_all.v similarity index 36% rename from main/verilog/basic_modules/TOP_all.v rename to main/verilog/mips_cpu/TOP_all.v index e982fd8..f163109 100644 --- a/main/verilog/basic_modules/TOP_all.v +++ b/main/verilog/mips_cpu/TOP_all.v @@ -1,8 +1,19 @@ `timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у +// Engineer: 寮犲姏瀹, 鍙剁挩閾 +// +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. +// Description: +// +////////////////////////////////////////////////////////////////////////////////// module TOP_all( input[23:0]Minisys_Switches, output[23:0]Minisys_Lights, input Minisys_Clock, input[4:0] Minisys_Button, -input EGO1_Uart_fromPC, output EGO1_Uart_toPC +input Minisys_Uart_fromPC, output Minisys_Uart_toPC ); CPUTOP top_instance( @@ -11,7 +22,7 @@ CPUTOP top_instance( .fpga_clk(Minisys_Clock), .start_pg(Minisys_Button[4]), .fpga_rst(Minisys_Button[3]), -.rx( EGO1_Uart_fromPC), -.tx( EGO1_Uart_toPC) +.rx( Minisys_Uart_fromPC), +.tx( Minisys_Uart_toPC) ); endmodule diff --git a/main/verilog/basic_modules/Decoder.v b/main/verilog/mips_cpu/basic_modules/Decoder.v similarity index 90% rename from main/verilog/basic_modules/Decoder.v rename to main/verilog/mips_cpu/basic_modules/Decoder.v index f8f6e02..a1c1fa1 100644 --- a/main/verilog/basic_modules/Decoder.v +++ b/main/verilog/mips_cpu/basic_modules/Decoder.v @@ -1,3 +1,15 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 叶璨铭 +// +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. +// Description: +// +////////////////////////////////////////////////////////////////////////////////// module decode32(read_data_1,read_data_2,Instruction,mem_data,ALU_result, Jal,RegWrite,MemtoReg,RegDst,Sign_extend,clock,reset,opcplus4); //////////////// 输入输出 //////////////// diff --git a/main/verilog/basic_modules/Ifetc32.v b/main/verilog/mips_cpu/basic_modules/Ifetc32.v similarity index 88% rename from main/verilog/basic_modules/Ifetc32.v rename to main/verilog/mips_cpu/basic_modules/Ifetc32.v index 21a89c3..61df165 100644 --- a/main/verilog/basic_modules/Ifetc32.v +++ b/main/verilog/mips_cpu/basic_modules/Ifetc32.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 王睿 // -// Create Date: 2022/05/18 01:21:06 -// Design Name: -// Module Name: Ifetc32 -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module Ifetc32(Instruction_i,Instruction_o,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr,rom_adr_o); input[31:0] Instruction_i; output[31:0] Instruction_o; // 根据PC的值从存放指令的prgrom中取出的指令 diff --git a/main/verilog/basic_modules/LED.v b/main/verilog/mips_cpu/basic_modules/LED.v similarity index 75% rename from main/verilog/basic_modules/LED.v rename to main/verilog/mips_cpu/basic_modules/LED.v index 0eccd00..f5c0127 100644 --- a/main/verilog/basic_modules/LED.v +++ b/main/verilog/mips_cpu/basic_modules/LED.v @@ -1,26 +1,14 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 张力宇 // -// Create Date: 2021/05/12 19:56:34 -// Design Name: -// Module Name: io_out -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// module LED(led_clk, ledrst, ledwrite, ledcs, ledaddr,ledwdata, ledout); diff --git a/main/verilog/basic_modules/MemOrIO.v b/main/verilog/mips_cpu/basic_modules/MemOrIO.v similarity index 85% rename from main/verilog/basic_modules/MemOrIO.v rename to main/verilog/mips_cpu/basic_modules/MemOrIO.v index 00e6bbf..d2eef52 100644 --- a/main/verilog/basic_modules/MemOrIO.v +++ b/main/verilog/mips_cpu/basic_modules/MemOrIO.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology ?????? +// Engineer: ??? // -// Create Date: 2022/04/27 11:49:18 -// Design Name: -// Module Name: MemOrIO -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module MemOrIO( mRead, mWrite, ioRead, ioWrite,addr_in, addr_out, m_rdata, io_rdata, r_wdata, r_rdata, write_data, LEDCtrl, SwitchCtrl); input mRead; // read memory, from Controller input mWrite; // write memory, from Controller diff --git a/main/verilog/basic_modules/control32.v b/main/verilog/mips_cpu/basic_modules/control32.v similarity index 93% rename from main/verilog/basic_modules/control32.v rename to main/verilog/mips_cpu/basic_modules/control32.v index ba43e8a..9619c10 100644 --- a/main/verilog/basic_modules/control32.v +++ b/main/verilog/mips_cpu/basic_modules/control32.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у +// Engineer: 鐜嬬澘 // -// Create Date: 2022/05/02 23:30:37 -// Design Name: -// Module Name: control32 -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module control32(Opcode,Function_opcode,Jr,Branch,nBranch,Jmp,Jal, Alu_resultHigh, RegDST, MemorIOtoReg, RegWrite, MemRead, MemWrite, IORead, IOWrite, ALUSrc,ALUOp,Sftmd,I_format); input[5:0] Opcode; // instruction[31:26], opcode diff --git a/main/verilog/basic_modules/dmemory32.v b/main/verilog/mips_cpu/basic_modules/dmemory32.v similarity index 82% rename from main/verilog/basic_modules/dmemory32.v rename to main/verilog/mips_cpu/basic_modules/dmemory32.v index f615063..215fde5 100644 --- a/main/verilog/basic_modules/dmemory32.v +++ b/main/verilog/mips_cpu/basic_modules/dmemory32.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у +// Engineer: 鐜嬬澘锛屽紶鍔涘畤 // -// Create Date: 2022/05/18 01:22:24 -// Design Name: -// Module Name: dmemory32 -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module dmemory32 ( input ram_clk_i, // from CPU top input ram_wen_i, // from Controller diff --git a/main/verilog/basic_modules/executs32.v b/main/verilog/mips_cpu/basic_modules/executs32.v similarity index 94% rename from main/verilog/basic_modules/executs32.v rename to main/verilog/mips_cpu/basic_modules/executs32.v index 13f8363..e4ab776 100644 --- a/main/verilog/basic_modules/executs32.v +++ b/main/verilog/mips_cpu/basic_modules/executs32.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 张力宇 // -// Create Date: 2022/05/13 18:36:31 -// Design Name: -// Module Name: executs32 -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module executs32( input[31:0] Read_data_1,//the source of Ainput input[31:0] Read_data_2,//one of the sources of Binput diff --git a/main/verilog/basic_modules/program.v b/main/verilog/mips_cpu/basic_modules/program.v similarity index 79% rename from main/verilog/basic_modules/program.v rename to main/verilog/mips_cpu/basic_modules/program.v index ac27c97..b1473c5 100644 --- a/main/verilog/basic_modules/program.v +++ b/main/verilog/mips_cpu/basic_modules/program.v @@ -1,25 +1,16 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у +// Engineer: 鐜嬬澘 // -// Create Date: 2022/05/10 01:36:24 -// Design Name: -// Module Name: programrom -// Project Name: -// Target Devices: -// Tool Versions: +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. // Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// ////////////////////////////////////////////////////////////////////////////////// - module programrom ( // Program ROM Pinouts input rom_clk_i, // ROM clock diff --git a/main/verilog/basic_modules/switch.v b/main/verilog/mips_cpu/basic_modules/switch.v similarity index 75% rename from main/verilog/basic_modules/switch.v rename to main/verilog/mips_cpu/basic_modules/switch.v index 3e527d0..f3fe5c2 100644 --- a/main/verilog/basic_modules/switch.v +++ b/main/verilog/mips_cpu/basic_modules/switch.v @@ -1,26 +1,14 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 张力宇 // -// Create Date: 2021/05/12 19:56:47 -// Design Name: -// Module Name: io_in -// Project Name: -// Target Devices: -// Tool Versions: -// Description: There are no description from yx. +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. +// Description: // -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// module Switch(switclk, switchrst, switchread, switchctl,switchaddr, switchrdata, switch_input); diff --git a/main/verilog/testMinisys/light_switch.v b/main/verilog/test_minisys/light_switch.v similarity index 100% rename from main/verilog/testMinisys/light_switch.v rename to main/verilog/test_minisys/light_switch.v diff --git a/test/verilog/testMinisys/test_light_swich.v b/test/verilog/test_minisys/test_light_swich.v similarity index 100% rename from test/verilog/testMinisys/test_light_swich.v rename to test/verilog/test_minisys/test_light_swich.v -- Gitee From c30c2b35b6cd29f54fa8adf142b186314a1d7700 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 22:10:26 +0800 Subject: [PATCH 15/57] =?UTF-8?q?feat(mips):=20=E5=86=85=E5=AD=98io?= =?UTF-8?q?=E6=B2=A1=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 3 +-- main/mips/cpu_test/datamemory_test.mips | 14 +++++++++++--- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index ec027c2..b8601e2 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -101,8 +101,7 @@ read_wait_for_enter: write_control_negate(3) write_control_negate(2) - # move $a0 $s0 - # jal write_data + move $a0 $s0 load_ra() jr $ra diff --git a/main/mips/cpu_test/datamemory_test.mips b/main/mips/cpu_test/datamemory_test.mips index c5c855c..f759100 100644 --- a/main/mips/cpu_test/datamemory_test.mips +++ b/main/mips/cpu_test/datamemory_test.mips @@ -1,10 +1,18 @@ .include "../commons/std_io_minisys.macro.mips" .data - buf: .word 0x0000FFFF + buf: .word 0x00FF + ptr: .word 0x0009 .text +jal static_initialization begin: - la $t0 buf - lw $a0 0($t0) + # la $t0 buf + # lw $a0 0($t0) + # jal write_data + + li $t4 0xFFFF + sw $t4 buf($zero) + lw $a0 buf($zero) + jal write_data j begin .include "../commons/std_io_minisys.impl.mips" -- Gitee From 0635b85d4b4f816c166f203fe7e7b7cb2486ab17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Tue, 24 May 2022 23:14:00 +0800 Subject: [PATCH 16/57] =?UTF-8?q?feat(mips):=20=E5=9C=BA=E6=99=AF2?= =?UTF-8?q?=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_algorithm.mips | 24 +++++ main/mips/commons/std_io_minisys.impl.mips | 2 +- main/mips/commons/std_io_minisys.macro.mips | 14 +++ main/mips/cpu_test/new_situation1.mips | 50 ++++++++-- main/mips/cpu_test/situation2.mips | 104 ++++++++++++++++---- 5 files changed, 166 insertions(+), 28 deletions(-) diff --git a/main/mips/commons/std_algorithm.mips b/main/mips/commons/std_algorithm.mips index 50d1cf2..5277d18 100644 --- a/main/mips/commons/std_algorithm.mips +++ b/main/mips/commons/std_algorithm.mips @@ -71,3 +71,27 @@ insertion_sort: j for_insertion_sort0 end_for_insertion_sort0: jr $ra + + +# 姹侷EEE 754 鍗曠簿搴︽诞鐐规暟缂栫爜鐨勭鍙蜂綅鍜屾寚鏁颁綅 锛堜竴鍏1+8=9浣嶏級銆 +# 杈撳叆 a0锛 杩斿洖a0 +getFloat: + # 绗﹀彿浣 锛1浣嶏級 + srl $t0 $a0 7 # 鍙栫7浣 + andi $t0 $t0 1 + xori $t0 $t0 1 # 鍙栧弽銆 + sll $t0 $t0 8 # 鏀惧湪绗8浣嶃7..0鐣欑粰鎸囨暟浣 + # 鎸囨暟浣 锛8浣嶏級 + # 鍙栫粷瀵瑰 + xori $t1 $t2 0xFF + addi $t1 $t1 1 + andi $t1 $t1 0xFF + # 鍙崇Щ澶氬皯娆″彉鎴0 - 1 + li $t3 0 + do_while_case6: + srl $t1 $t1 1 + addi $t3 $t3 1 + bne $t1 $zero do_while_case6 + addi $t3 $t3 0x7f # 鍔犱笂bias + or $a0 $t3 $t0 # 鍚堝苟涓や釜鏁 + jr $ra \ No newline at end of file diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index b8601e2..ae2cc1e 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -6,7 +6,7 @@ static_initialization: la $sp 256 # 鏍堟寚閽 la $fp 512 #base 鏁版嵁鐨勫熀纭鍦板潃 # 鏁版嵁闆嗛棿闅 - li $s0 11 #space + li $s0 44 #space 11涓暟锛屾瘡涓暟4涓猙yte #鐢宠缂撳瓨鐏殑鍊煎埌涓鍧楃湡瀹炲唴瀛樸 addi $sp $sp -16 # 鏀寔0, 4, 8, 12 鍥涗釜鍙橀噺 move $k0 $sp # k0鏄笓闂ㄧ殑鐏寚閽 diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 6aba668..ac7793b 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -74,4 +74,18 @@ .macro sleep(%msec) la $v0 %msec jal sleep +.end_macro + +# 浠庢爣鍑嗚緭鍏ヨ鍙栦竴涓暟锛岃〃绀烘暟鎹泦缂栧彿 +# 灏嗘暟鎹泦鐨勫熀鍦板潃鏀惧埌s1 +.macro getBase() + jal read + andi $a0 $a0 3 # 鍙彇鏈鍚庝袱浣嶃 + lw $s1 0($fp) #base + for_case4: + beq $a0 $zero end_for_case4 + add $s1 $s1 $s0 # s0 鍙锛屾案杩滄槸space + addi $a0 $a0 -1 + j for_case4 + end_for_case4: .end_macro \ No newline at end of file diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index 12ec432..011eb85 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -4,9 +4,11 @@ .globl main main: # todo: 娌′粈涔堢敤锛宑oe鏂囦欢涓嶈兘浣嶇疆鏃犲叧銆 jal static_initialization +# a = 0($fp) b = a = 4($fp) +sw $zero 0($fp) +sw $zero 4($fp) begin: - li $v0 10 - jal sleep # 闄嶄綆閫熷害 + sleep(50) jal decode # 浼氳鐩朼0 a1鐨勫笺 move $a2 $a0 @@ -24,26 +26,58 @@ begin: beq $a2 $s7 case7 case0: jal read - jal static_initialization - # jal write_data - # jal is_binary_palindrome - # move $v1 $v0 - # li $v0 0 - # jal write_control_set + sw $a0 0($fp) + jal write_data + jal is_binary_palindrome + move $v1 $v0 + li $v0 0 + jal write_control_set j begin case1: + jal read + sw $a0 0($fp) + jal write_data + sw $a0 4($fp) + jal read + jal write_data j begin case2: + lw $s0 0($fp) + lw $s1 4($fp) + and $a0 $s0 $s1 + jal write_data j begin case3: + lw $s0 0($fp) + lw $s1 4($fp) + or $a0 $s0 $s1 + jal write_data j begin case4: + lw $s0 0($fp) + lw $s1 4($fp) + xor $a0 $s0 $s1 + jal write_data j begin case5: + lw $s0 0($fp) + lw $s1 4($fp) + sllv $a0 $s0 $s1 + jal write_data j begin case6: + lw $s0 0($fp) + lw $s1 4($fp) + srlv $a0 $s0 $s1 + jal write_data j begin case7: + lw $s0 0($fp) + lw $s1 4($fp) + sll $s0 $s0 8 + sra $s0 $s0 8 # 鏈夌鍙峰寲 + srav $a0 $s0 $s1 + jal write_data j begin j begin .include "../commons/std_io_minisys.impl.mips" diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 603eac4..6c5b38c 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -25,6 +25,7 @@ begin: case0: jal read move $s1 $a0 # s1=n锛岃〃绀烘暟缁勯暱搴 + sw $s1 44($fp) # 44($fp) 涓烘暟缁勯暱搴 bne $s1 $zero end_if_case0_0 jal exception_hint # 濡傛灉鏄0锛屽彧鏄鍛婏紝涓嶉噸鏂拌緭鍏ャ @@ -52,43 +53,108 @@ case0: sleep(100) # 璇诲彇鏂扮殑鏁般 jal read - sw $a0 0($s2) # 瀛樺叆s2 + sw $a0 0($s2) # 瀛樺叆s2瀵瑰簲鐨勫唴瀛 addi $s1 $s1 -1 addi $s2 $s2 4 # 鎸囬拡鍙崇Щ j for_case0 end_for_case0: + warn_data() # 琛ㄧず杈撳叆缁撴潫銆 j begin case1: - li $a0 0 - jal write_data - li $a0 2 - jal write_control - + move $v0 $fp # 鏁版嵁闆0澶 + lw $s1 44($fp) # 鏁扮粍瀹為檯闀垮害n + sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 + add $v1 $v0 $s1 # 鏁版嵁闆0灏 + add $a0 $v0 $s0 # 鏁版嵁闆1澶 + move $s2 $a0 # 鏁版嵁闆1澶 + jal copy + move $v0 $s2 # 鏁版嵁闆1澶 + add $v1 $v0 $s1 # 鏁版嵁闆1灏 + jal insertion_sort + warn_data() # 琛ㄧず鎺掑簭缁撴潫銆 j begin case2: - li $v0 7 - jal write_control_set + move $v0 $fp # 鏁版嵁闆0澶 + lw $s1 44($fp) + sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 + add $v1 $v0 $s1 # 鏁版嵁闆0灏 + add $a0 $v0 $s0 # 鏁版嵁闆1澶 + add $a0 $a0 $s0 # 鏁版嵁闆2澶 + jal to_signed_array + warn_data() j begin case3: - li $a0 8 - jal write_control + move $v0 $fp # 鏁版嵁闆0澶 + add $v0 $v0 $s0 # 鏁版嵁闆1澶 + add $v0 $v0 $s0 # 鏁版嵁闆2澶 + lw $s1 44($fp) + sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 + add $v1 $v0 $s1 # 鏁版嵁闆2灏 + add $a0 $v0 $s0 # 鏁版嵁闆3澶 + move $s2 $a0 + jal copy + + move $v0 $s2 # 鏁版嵁闆3澶 + add $v1 $v0 $s1 # 鏁版嵁闆3灏 + jal insertion_sort + + warn_data() # 琛ㄧず鎺掑簭缁撴潫銆 j begin case4: - li $a0 16 - jal write_control + getBase() + # s1 鐜板湪鏄 鏁版嵁闆嗗ご + move $v0 $s1 + lw $s2 44($fp) # n + sll $s2 $s2 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 + add $s2 $v0 $s2 # 鏁版嵁闆嗗熬 + move $v1 $s2 + jal max + move $s3 $a0 # s3 鏄渶澶у + move $v0 $s1 + move $v1 $s2 + jal min + move $s4 $a0 # s4 鏄渶灏忓 + sub $a0 $s3 $s4 + jal write_data j begin case5: - li $a0 32 - jal write_control + getBase() + # s1 鐜板湪鏄 鏁版嵁闆嗗ご + jal read + sll $a0 $a0 2 # 涓嬫爣*4 + add $s1 $s1 $a0 # 鐩爣鍦板潃 + lw $a0 0($s1) # 鐩爣鏁 + jal write_data j begin case6: - li $a0 64 - jal write_control + getBase() + # s1 鐜板湪鏄 鏁版嵁闆嗗ご + jal read + sll $a0 $a0 2 # 涓嬫爣*4 + add $s1 $s1 $a0 # 鐩爣鍦板潃 + lw $t2 0($s1) # 鐩爣鏁 + + andi $a0 $t2 0xFF # 鍙冭檻8浣 + jal getFloat + jal write_data j begin case7: - li $a0 128 - jal write_control + move $s1 $fp # 鏁版嵁闆0 澶 + jal read + sll $a0 $a0 2 # 涓嬫爣*4 + add $s1 $s1 $a0 # 鐩爣鍦板潃 + lw $t2 0($s1) # 鐩爣鏁 + + move $a0 $t2 + jal write_data + sleep(5000) + + move $a0 $t2 + jal getFloat + jal write_data + sleep(5000) j begin j begin -.include "../commons/std_io_minisys.impl.mips" \ No newline at end of file +.include "../commons/std_io_minisys.impl.mips" +.include "../commons/std_algorithm.mips" \ No newline at end of file -- Gitee From 0ae20788ab06e9a17966143b4876dbe29bb37326 Mon Sep 17 00:00:00 2001 From: zhang <2674793917@qq.com> Date: Wed, 25 May 2022 11:43:23 +0800 Subject: [PATCH 17/57] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E7=8E=8B=E8=96=87?= =?UTF-8?q?=E8=AF=B4=E7=9A=84=E9=82=A3=E4=B8=AAALU?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/mips_cpu/basic_modules/executs32.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/main/verilog/mips_cpu/basic_modules/executs32.v b/main/verilog/mips_cpu/basic_modules/executs32.v index e4ab776..4f7e26e 100644 --- a/main/verilog/mips_cpu/basic_modules/executs32.v +++ b/main/verilog/mips_cpu/basic_modules/executs32.v @@ -82,7 +82,7 @@ end always @* begin //set type operation (slt, slti, sltu, sltiu) if(((ALU_ctL==3'b111) && (Exe_code[3]==1)) || (I_format==1 && ALU_ctL[2:1]==2'b11)) - reg_ALU_Result[31:0] = $signed(Ainput) < $signed(Binput); + reg_ALU_Result[31:0] = (Exe_code[2:0] == 3'b011) ? Ainput < Binput : $signed(Ainput) < $signed(Binput); // if((ALU_ctL==3'b111) && (Exe_code[0]==1)) begin // reg_ALU_Result = (Ainput< Binput) ? 32'd1 : 32'd0; // end -- Gitee From a1072f37c04775d11d42c93615138646174e0f70 Mon Sep 17 00:00:00 2001 From: zhang <2674793917@qq.com> Date: Wed, 25 May 2022 14:05:38 +0800 Subject: [PATCH 18/57] =?UTF-8?q?situationplus=E6=98=AF=E5=8F=AF=E4=BB=A5?= =?UTF-8?q?=E7=94=A8=E7=9A=84=E6=B5=8B=E8=AF=95=E5=9C=BA=E6=99=AF=E4=B8=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/situation1.mips | 4 +- main/mips/cpu_test/situation1plus.asm | 96 +++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 2 deletions(-) create mode 100644 main/mips/cpu_test/situation1plus.asm diff --git a/main/mips/cpu_test/situation1.mips b/main/mips/cpu_test/situation1.mips index 0ff11fd..74acd03 100644 --- a/main/mips/cpu_test/situation1.mips +++ b/main/mips/cpu_test/situation1.mips @@ -1,5 +1,5 @@ -.data 0x0000 -.text 0x0000 +.data +.text ini: addi $v1, $zero, 1 addi $21, $zero, 1 diff --git a/main/mips/cpu_test/situation1plus.asm b/main/mips/cpu_test/situation1plus.asm new file mode 100644 index 0000000..6934a12 --- /dev/null +++ b/main/mips/cpu_test/situation1plus.asm @@ -0,0 +1,96 @@ +.data + buf: .word 0x0000 +.text +ini: + sw $3, 0x62($20) + addi $21, $zero, 1 + addi $22, $zero, 2 + addi $23, $zero, 3 + addi $24,$zero, 4 + addi $25,$zero, 5 + addi $26, $zero, 6 + addi $27, $zero, 7 + lui $20, 0xFFFF + ori $20, $20, 0xFC00 # 20 is the basic address + lui $19, 0x8FFF + ori $19, $19, 0xFFFF #the submask + +master: lw $2, 0x72($20) # read the sw23,22,21 + srl $2, $2, 5 # 移动到我的指令的位数 + beq $2, $zero, case0 + beq $2, $21, case1 + beq $2, $22, case2 + beq $2, $23, case3 + beq $2, $24, case4 + beq $2, $25, case5 + beq $2, $26, case6 + beq $2, $27, case7 + +case0: + lw $1, 0x70($20) + sw $1, 0x60($20) # 警惕2个led灯管互相刷新 + add $4, $zero, $1 # 存一下这个内容 + addi $6, $zero, 0 +loop: + beq $4,$zero,exit #全变0退出,4这个变量没用 + andi $11,$4,1 + sll $6,$6,1 + add $6,$6,$11 + srl $4,$4,1 + j loop +exit: + beq $1, $6,led16light + bne $1, $6,led16notlight + j master +led16light: + addi $10, $zero, 1 + sw $10, 0x62($20) + j master# 存储读取的数字存储在￥3和￥5中 +led16notlight: + addi $10, $zero, 0 + sw $10, 0x62($20) + j master +case1: + lw $4, 0x72($20) + srl $4, $4, 2 # SW18是1代表我的值被锁定了,顺序输入第一个数，拨sw16，拨sw18.输入第二个数 拨sw17.#但凡想要取消，再SW18是0就可以取消 + andi $4, $4, 0x0001 + bne $4, $zero,master + lw $3, 0x70($20) + sw $3, 0x60($20) + sw $zero, 0x62($20) + lw $4, 0x72($20) + andi $4, $4, 0x0001 #SW16代表第一个读取完毕 + beq $4, $zero, case1 # 你需要反复读取 +case1read2: + lw $5, 0x70($20) + sw $5, 0x60($20) + lw $4, 0x72($20) + srl $4, $4, 1 # SW17代表第二个数读取完毕 + andi $4, $4, 0x0001 + beq $4, $zero, case1read2 + j master + +case2: + and $6, $3, $5 + sw $6, 0x60($20) + j master +case3: + or $6, $3, $5 + sw $6, 0x60($20) + j master +case4: + xor $6, $3, $5 + sw $6, 0x60($20) + j master +case5: + sllv $6, $3, $5 + sw $6, 0x60($20) + j master +case6: + srlv $6, $3, $5 + sw $6, 0x60($20) + j master +case7: + srav $6, $3, $5 + sw $6, 0x60($20) + j master -- Gitee From 4458bcf004fe95fd6efde529c7a5ec0c151e6604 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Wed, 25 May 2022 22:01:22 +0800 Subject: [PATCH 19/57] =?UTF-8?q?feat(mips):=20=E5=A2=9E=E5=8A=A0=E5=9C=BA?= =?UTF-8?q?=E6=99=AF1=E6=A8=A1=E6=8B=9Fverilog=E6=B5=8B=E8=AF=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- ...00\346\237\245\346\270\205\345\215\225.md" | 37 + main/mips/coe/dmem32.coe | 16388 +--------------- main/mips/coe/new_situation1/dmem32.coe | 4096 ++++ main/mips/coe/new_situation1/prgmip32.coe | 8192 ++++++++ main/mips/commons/std_io_minisys.impl.mips | 27 +- main/mips/commons/std_io_minisys.macro.mips | 29 +- main/mips/cpu_test/datamemory_test.mips | 19 +- main/mips/cpu_test/new_situation1.mips | 7 +- main/mips/cpu_test/situation1.mips | 38 +- test/verilog/TestNewSituation1.v | 36 + .../{testCpuTop.v => TestSituation1.v} | 3 +- 11 files changed, 12430 insertions(+), 16442 deletions(-) create mode 100644 "main/mips/MIPS\345\274\200\345\217\221\346\243\200\346\237\245\346\270\205\345\215\225.md" create mode 100644 main/mips/coe/new_situation1/dmem32.coe create mode 100644 main/mips/coe/new_situation1/prgmip32.coe create mode 100644 test/verilog/TestNewSituation1.v rename test/verilog/{testCpuTop.v => TestSituation1.v} (98%) diff --git "a/main/mips/MIPS\345\274\200\345\217\221\346\243\200\346\237\245\346\270\205\345\215\225.md" "b/main/mips/MIPS\345\274\200\345\217\221\346\243\200\346\237\245\346\270\205\345\215\225.md" new file mode 100644 index 0000000..93a6e24 --- /dev/null +++ "b/main/mips/MIPS\345\274\200\345\217\221\346\243\200\346\237\245\346\270\205\345\215\225.md" @@ -0,0 +1,37 @@ +## MIPS 寮鍙戞鏌ユ竻鍗 + + + +### 瀵勫瓨鍣ㄤ娇鐢ㄨ鑼 + +#### 缁濆瀛愬嚱鏁/瀹 + +- t绯诲垪瀵勫瓨鍣 + - 鍏佽浣跨敤 + - 鍙互鏈熷緟姝ｅ父琛屼负 +- s绯诲垪瀵勫瓨鍣 + - 涓嶅厑璁镐娇鐢 +- a绯诲垪 +- v绯诲垪 + +#### 缁濆鐖跺嚱鏁 + +ra淇濆瓨绛栫暐 + +- 涓嶉渶瑕佷繚瀛樸 + +#### 鏅氬嚱鏁 + +- ra淇濆瓨绛栫暐 + - 蹇呴』淇濆瓨銆 + +- t绯诲垪瀵勫瓨鍣 + - 鍏佽浣跨敤 + - 鍦ㄨ皟鐢ㄥ埆鐨勫嚱鏁版椂锛屼笉鍙互鏈熷緟t涓嶈淇敼 +- s绯诲垪瀵勫瓨鍣 + - 鍙互浣跨敤銆 + - 鍦ㄨ皟鐢ㄧ粷瀵瑰瓙鍑芥暟鏃讹紝鍙互鏈熷緟s鐨勫间笉鍙戠敓鏀瑰彉銆 + +- a绯诲垪 +- v绯诲垪 + diff --git a/main/mips/coe/dmem32.coe b/main/mips/coe/dmem32.coe index 4688b32..380b50f 100644 --- a/main/mips/coe/dmem32.coe +++ b/main/mips/coe/dmem32.coe @@ -1,16386 +1,2 @@ -memory_initialization_radix = 16; -memory_initialization_vector = -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000, -00000000; +memory_initialization_radix=16; +memory_initialization_vector=0c000046 afc00000 afc00004 0c00007b 00043021 00042140 0c0000bd 24110001 24120002 24130003 24140004 24150005 24160006 24170007 10c00007 10d1000e 10d20014 10d30018 10d4001c 10d50020 10d60024 10d70028 0c000080 afc40000 0c0000c3 0c0000f8 00021821 24020000 0c0000a4 08000003 0c000080 afc40000 0c0000c3 0c000080 afc40004 0c0000c3 08000003 8fd00000 8fd10004 02112024 0c0000c3 08000003 8fd00000 8fd10004 02112025 0c0000c3 08000003 8fd00000 8fd10004 02112026 0c0000c3 08000003 8fd00000 8fd10004 02302004 0c0000c3 08000003 8fd00000 8fd10004 02302006 0c0000c3 08000003 8fd00000 8fd10004 00108200 00108203 02302007 0c0000c3 08000003 08000003 241cfc00 241d0100 241e0200 2410002c 23bdfff0 001dd021 23bdfffc afbf0000 24040000 0c0000bd 24040000 0c0000c3 24120080 12400005 8f440004 00922020 0c0000bd 00129042 08000053 34128000 12400005 8f440000 00922020 0c0000c3 00129042 0800005a 24040000 0c0000bd 24040000 0c0000c3 240400ff 0c0000bd 3404ffff 0c0000c3 24040000 0c0000bd 24040000 0c0000c3 8fbf0000 23bd0004 03e00008 00024900 000240c0 01094020 01021022 00024a80 00025100 000240c0 012a1022 00481022 2042ffff 1440fffe 03e00008 8f840072 00042102 30850001 00042042 03e00008 23bdfffc afbf0000 24020004 24030001 0c0000a4 0c00007b 1486ff7c 14a0fff8 24020004 24030000 0c0000a4 0c00007b 1486ff76 24020004 0c0000b3 8f840070 0004b821 0c0000c3 10a0fff8 24040000 0c0000c3 24020004 24030000 0c0000a4 24020003 0c0000b3 24020002 0c0000b3 24020003 0c0000b3 24020002 0c0000b3 00172021 8fbf0000 23bd0004 03e00008 8f490004 30630001 00431804 00494006 31080001 11000002 01234824 080000ad 01234825 af490004 8f480004 af880062 8f480000 af880060 03e00008 8f490004 24080001 00481804 01234826 af490004 8f480004 af880062 8f480000 af880060 03e00008 af440004 8f480004 af880062 8f480000 af880060 03e00008 af440000 8f480004 af880062 8f480000 af880060 03e00008 23bdfffc afbf0000 8f4f0000 3404ffff 0c0000c3 24020002 24030001 0c0000a4 24020003 24030001 0c0000a4 240203e8 0c00006f 000f2021 0c0000c3 24020002 24030000 0c0000a4 24020003 24030000 0c0000a4 240201f4 0c00006f 8f4f0000 3404ffff 0c0000c3 24020002 24030001 0c0000a4 24020003 24030001 0c0000a4 240203e8 0c00006f 000f2021 0c0000c3 24020002 24030000 0c0000a4 24020003 24030000 0c0000a4 240201f4 0c00006f 8fbf0000 23bd0004 03e00008 24050000 00044021 20a50001 00084042 1500fffd 23bdfffc afbf0000 0c000103 8fbf0000 23bd0004 03e00008 20010001 0025082a 14200002 24020001 0800011e 24a8ffff 01044806 30880001 15280011 23bdfff4 afa40000 afa50004 afbf0008 20a5fffe 24080001 00a84004 2108ffff 00084040 01042024 00042042 0c000103 8fa40000 8fa50004 8fbf0008 23bd000c 0800011e 24020000 03e00008 24050000 00044021 20a50001 00084102 1500fffd 23bdfffc afbf0000 0c00012a 8fbf0000 23bd0004 03e00008 20010001 0025082a 14200002 24020001 08000147 24a8ffff 00084080 01044806 3088000f 15280012 23bdfff4 afa40000 afa50004 afbf0008 20a5fffe 00054080 24090001 01094804 2129ffff 00094900 01242024 00042102 0c00011f 8fa40000 8fa50004 8fbf0008 23bd000c 08000147 24020000 03e00008 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ; diff --git a/main/mips/coe/new_situation1/dmem32.coe b/main/mips/coe/new_situation1/dmem32.coe new file mode 100644 index 0000000..9b650de --- /dev/null +++ b/main/mips/coe/new_situation1/dmem32.coe @@ -0,0 +1,4096 @@ +0c000046 +afc00000 +afc00004 +0c00007b +00043021 +00042140 +0c0000bd +24110001 +24120002 +24130003 +24140004 +24150005 +24160006 +24170007 +10c00007 +10d1000e +10d20014 +10d30018 +10d4001c +10d50020 +10d60024 +10d70028 +0c000080 +afc40000 +0c0000c3 +0c0000f8 +00021821 +24020000 +0c0000a4 +08000003 +0c000080 +afc40000 +0c0000c3 +0c000080 +afc40004 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02112024 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02112025 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02112026 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02302004 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02302006 +0c0000c3 +08000003 +8fd00000 +8fd10004 +00108200 +00108203 +02302007 +0c0000c3 +08000003 +08000003 +241cfc00 +241d0100 +241e0200 +2410002c +23bdfff0 +001dd021 +23bdfffc +afbf0000 +24040000 +0c0000bd +24040000 +0c0000c3 +24120080 +12400005 +8f440004 +00922020 +0c0000bd +00129042 +08000053 +34128000 +12400005 +8f440000 +00922020 +0c0000c3 +00129042 +0800005a +24040000 +0c0000bd +24040000 +0c0000c3 +240400ff +0c0000bd +3404ffff +0c0000c3 +24040000 +0c0000bd +24040000 +0c0000c3 +8fbf0000 +23bd0004 +03e00008 +00024900 +000240c0 +01094020 +01021022 +00024a80 +00025100 +000240c0 +012a1022 +00481022 +2042ffff +1440fffe +03e00008 +8f840072 +00042102 +30850001 +00042042 +03e00008 +23bdfffc +afbf0000 +24020004 +24030001 +0c0000a4 +0c00007b +1486ff7c +14a0fff8 +24020004 +24030000 +0c0000a4 +0c00007b +1486ff76 +24020004 +0c0000b3 +8f840070 +0004b821 +0c0000c3 +10a0fff8 +24040000 +0c0000c3 +24020004 +24030000 +0c0000a4 +24020003 +0c0000b3 +24020002 +0c0000b3 +24020003 +0c0000b3 +24020002 +0c0000b3 +00172021 +8fbf0000 +23bd0004 +03e00008 +8f490004 +30630001 +00431804 +00494006 +31080001 +11000002 +01234824 +080000ad +01234825 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +8f490004 +24080001 +00481804 +01234826 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440000 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +23bdfffc +afbf0000 +8f4f0000 +3404ffff +0c0000c3 +24020002 +24030001 +0c0000a4 +24020003 +24030001 +0c0000a4 +240203e8 +0c00006f +000f2021 +0c0000c3 +24020002 +24030000 +0c0000a4 +24020003 +24030000 +0c0000a4 +240201f4 +0c00006f +8f4f0000 +3404ffff +0c0000c3 +24020002 +24030001 +0c0000a4 +24020003 +24030001 +0c0000a4 +240203e8 +0c00006f +000f2021 +0c0000c3 +24020002 +24030000 +0c0000a4 +24020003 +24030000 +0c0000a4 +240201f4 +0c00006f +8fbf0000 +23bd0004 +03e00008 +24050000 +00044021 +20a50001 +00084042 +1500fffd +23bdfffc +afbf0000 +0c000103 +8fbf0000 +23bd0004 +03e00008 +20010001 +0025082a +14200002 +24020001 +0800011e +24a8ffff +01044806 +30880001 +15280011 +23bdfff4 +afa40000 +afa50004 +afbf0008 +20a5fffe +24080001 +00a84004 +2108ffff +00084040 +01042024 +00042042 +0c000103 +8fa40000 +8fa50004 +8fbf0008 +23bd000c +0800011e +24020000 +03e00008 +24050000 +00044021 +20a50001 +00084102 +1500fffd +23bdfffc +afbf0000 +0c00012a +8fbf0000 +23bd0004 +03e00008 +20010001 +0025082a +14200002 +24020001 +08000147 +24a8ffff +00084080 +01044806 +3088000f +15280012 +23bdfff4 +afa40000 +afa50004 +afbf0008 +20a5fffe +00054080 +24090001 +01094804 +2129ffff +00094900 +01242024 +00042102 +0c00011f +8fa40000 +8fa50004 +8fbf0008 +23bd000c +08000147 +24020000 +03e00008 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/main/mips/coe/new_situation1/prgmip32.coe b/main/mips/coe/new_situation1/prgmip32.coe new file mode 100644 index 0000000..47dd957 --- /dev/null +++ b/main/mips/coe/new_situation1/prgmip32.coe @@ -0,0 +1,8192 @@ +0c000046 +afc00000 +afc00004 +0c00007b +00043021 +00042140 +0c0000bd +24110001 +24120002 +24130003 +24140004 +24150005 +24160006 +24170007 +10c00007 +10d1000e +10d20014 +10d30018 +10d4001c +10d50020 +10d60024 +10d70028 +0c000080 +afc40000 +0c0000c3 +0c0000f8 +00021821 +24020000 +0c0000a4 +08000003 +0c000080 +afc40000 +0c0000c3 +0c000080 +afc40004 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02112024 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02112025 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02112026 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02302004 +0c0000c3 +08000003 +8fd00000 +8fd10004 +02302006 +0c0000c3 +08000003 +8fd00000 +8fd10004 +00108200 +00108203 +02302007 +0c0000c3 +08000003 +08000003 +241cfc00 +241d0100 +241e0200 +2410002c +23bdfff0 +001dd021 +23bdfffc +afbf0000 +24040000 +0c0000bd +24040000 +0c0000c3 +24120080 +12400005 +8f440004 +00922020 +0c0000bd +00129042 +08000053 +34128000 +12400005 +8f440000 +00922020 +0c0000c3 +00129042 +0800005a +24040000 +0c0000bd +24040000 +0c0000c3 +240400ff +0c0000bd +3404ffff +0c0000c3 +24040000 +0c0000bd +24040000 +0c0000c3 +8fbf0000 +23bd0004 +03e00008 +00024900 +000240c0 +01094020 +01021022 +00024a80 +00025100 +000240c0 +012a1022 +00481022 +2042ffff +1440fffe +03e00008 +8f840072 +00042102 +30850001 +00042042 +03e00008 +23bdfffc +afbf0000 +24020004 +24030001 +0c0000a4 +0c00007b +1486ff7c +14a0fff8 +24020004 +24030000 +0c0000a4 +0c00007b +1486ff76 +24020004 +0c0000b3 +8f840070 +0004b821 +0c0000c3 +10a0fff8 +24040000 +0c0000c3 +24020004 +24030000 +0c0000a4 +24020003 +0c0000b3 +24020002 +0c0000b3 +24020003 +0c0000b3 +24020002 +0c0000b3 +00172021 +8fbf0000 +23bd0004 +03e00008 +8f490004 +30630001 +00431804 +00494006 +31080001 +11000002 +01234824 +080000ad +01234825 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +8f490004 +24080001 +00481804 +01234826 +af490004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440004 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +af440000 +8f480004 +af880062 +8f480000 +af880060 +03e00008 +23bdfffc +afbf0000 +8f4f0000 +3404ffff +0c0000c3 +24020002 +24030001 +0c0000a4 +24020003 +24030001 +0c0000a4 +240203e8 +0c00006f +000f2021 +0c0000c3 +24020002 +24030000 +0c0000a4 +24020003 +24030000 +0c0000a4 +240201f4 +0c00006f +8f4f0000 +3404ffff +0c0000c3 +24020002 +24030001 +0c0000a4 +24020003 +24030001 +0c0000a4 +240203e8 +0c00006f +000f2021 +0c0000c3 +24020002 +24030000 +0c0000a4 +24020003 +24030000 +0c0000a4 +240201f4 +0c00006f +8fbf0000 +23bd0004 +03e00008 +24050000 +00044021 +20a50001 +00084042 +1500fffd +23bdfffc +afbf0000 +0c000103 +8fbf0000 +23bd0004 +03e00008 +20010001 +0025082a +14200002 +24020001 +0800011e +24a8ffff +01044806 +30880001 +15280011 +23bdfff4 +afa40000 +afa50004 +afbf0008 +20a5fffe +24080001 +00a84004 +2108ffff +00084040 +01042024 +00042042 +0c000103 +8fa40000 +8fa50004 +8fbf0008 +23bd000c +0800011e +24020000 +03e00008 +24050000 +00044021 +20a50001 +00084102 +1500fffd +23bdfffc +afbf0000 +0c00012a +8fbf0000 +23bd0004 +03e00008 +20010001 +0025082a +14200002 +24020001 +08000147 +24a8ffff +00084080 +01044806 +3088000f +15280012 +23bdfff4 +afa40000 +afa50004 +afbf0008 +20a5fffe +00054080 +24090001 +01094804 +2129ffff +00094900 +01242024 +00042102 +0c00011f +8fa40000 +8fa50004 +8fbf0008 +23bd000c +08000147 +24020000 +03e00008 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index ae2cc1e..a25f504 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -13,23 +13,23 @@ static_initialization: save_ra() # 瑕佹兂jal鍏朵粬鏂规硶锛屽厛瑕佷繚瀛榬a # 寮鏈虹壒鏁 鐐逛寒 all_lights_off() - li $s0 0x80 + li $s2 0x80 for_initialization0: - beq $s0 $zero end_for_initialization0 + beq $s2 $zero end_for_initialization0 lw $a0 4($k0) - add $a0 $a0 $s0 + add $a0 $a0 $s2 jal write_control - srl $s0 $s0 1 + srl $s2 $s2 1 sleep(41) j for_initialization0 end_for_initialization0: - li $s0 0x8000 + li $s2 0x8000 for_initialization1: - beq $s0 $zero end_for_initialization1 + beq $s2 $zero end_for_initialization1 lw $a0 0($k0) - add $a0 $a0 $s0 + add $a0 $a0 $s2 jal write_data - srl $s0 $s0 1 + srl $s2 $s2 1 sleep(41) j for_initialization1 end_for_initialization1: @@ -78,19 +78,18 @@ read: jal decode # 浼氳鐩朼0 a1鐨勫笺 sleep(100) bne $a0 $a2 begin - bne $a1 $zero read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟enter鏄0 - # bne $a1 $zero begin # 鍏佽鍥炲埌begin閲嶆柊閫夋嫨鍔熻兘銆 + bne $a1 $zero read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟鐩村埌enter鏄0 write_control_set_false(4) -read_wait_for_enter: +_read_wait_for_enter: sleep(200) #li $t0 0 jal decode bne $a0 $a2 begin write_control_negate(4) lw $a0 0x70($gp) - move $s0 $a0 + move $s7 $a0 jal write_data - beq $a1 $zero read_wait_for_enter # 绛夊埌enter鏄1銆 + beq $a1 $zero _read_wait_for_enter # 绛夊埌enter鏄1銆 li $a0 0 jal write_data # 娓呯┖杈撳叆 @@ -101,7 +100,7 @@ read_wait_for_enter: write_control_negate(3) write_control_negate(2) - move $a0 $s0 + move $a0 $s7 load_ra() jr $ra diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index ac7793b..292b4d6 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -1,3 +1,13 @@ +# 璁〤PU 鐫＄湢msec姣銆 +# 璋冪敤杩欎釜鍑芥暟鐨勫満鏅槸锛宻witch鎿嶄綔鏃朵俊鍙峰彲鑳戒笉绋冲畾锛屼細鍑虹幇鐭椂0,1浜ゆ浛锛屽鑷磋绠楅昏緫鏈夐棶棰樸 +# note:vivado 浠跨湡鏃讹紝涓嶅惎鐢╯leep銆傚洜涓簐ivado妯℃嫙鏃舵病鏈変俊鍙蜂笉绋冲畾鐨勯棶棰樸 +.macro sleep(%msec) +#not vivado + #la $v0 %msec + #jal sleep +#vivado +.end_macro + #娴嬭瘯鐘舵侊細鍙俊 # 浠庣紦瀛樺唴瀛樼殑鍊煎啓鍏ュ埌鐏腑銆傝繖鏄痯rivate鏂规硶锛屼笉瑕佽交鏄撹皟鐢ㄣ .macro flush_lights() @@ -7,14 +17,14 @@ sw $t0 0x60($gp) .end_macro .macro save_ra() - # addi $sp $sp -4 - # sw $ra 0($sp) - move $k1 $ra + addi $sp $sp -4 + sw $ra 0($sp) + #move $k1 $ra .end_macro .macro load_ra() - # lw $ra 0($sp) - # addi $sp $sp 4 - move $ra $k1 # 鍔ㄧ敤k1 + lw $ra 0($sp) + addi $sp $sp 4 + #move $ra $k1 # 鍔ㄧ敤k1 .end_macro .macro write_control_set_true(%index) li $v0 %index @@ -71,10 +81,7 @@ jal write_data .end_macro -.macro sleep(%msec) - la $v0 %msec - jal sleep -.end_macro + # 浠庢爣鍑嗚緭鍏ヨ鍙栦竴涓暟锛岃〃绀烘暟鎹泦缂栧彿 # 灏嗘暟鎹泦鐨勫熀鍦板潃鏀惧埌s1 @@ -88,4 +95,4 @@ addi $a0 $a0 -1 j for_case4 end_for_case4: -.end_macro \ No newline at end of file +.end_macro diff --git a/main/mips/cpu_test/datamemory_test.mips b/main/mips/cpu_test/datamemory_test.mips index f759100..6cc06fc 100644 --- a/main/mips/cpu_test/datamemory_test.mips +++ b/main/mips/cpu_test/datamemory_test.mips @@ -1,18 +1,19 @@ .include "../commons/std_io_minisys.macro.mips" .data - buf: .word 0x00FF + buf: .word 0x0F ptr: .word 0x0009 .text jal static_initialization begin: - # la $t0 buf - # lw $a0 0($t0) - # jal write_data + la $t0 buf + lw $a0 0($t0) + lw $a0 buf($zero) + #li $a0 0x0F + jal write_data - li $t4 0xFFFF - sw $t4 buf($zero) - lw $a0 buf($zero) - - jal write_data + # li $t4 0x0F + #sw $t4 buf($zero) + #lw $a0 buf($zero) + #jal write_data j begin .include "../commons/std_io_minisys.impl.mips" diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index 011eb85..b670ea0 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -1,5 +1,6 @@ .include "../commons/std_io_minisys.macro.mips" .data + dataset0: .word 0 .text .globl main main: # todo: 娌′粈涔堢敤锛宑oe鏂囦欢涓嶈兘浣嶇疆鏃犲叧銆 @@ -14,7 +15,7 @@ begin: move $a2 $a0 sll $a0 $a0 5 - jal write_control # 鎸囩ず褰撳墠鏄摢涓涓猚ase + jal write_control # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 鍙兘浼氬鍐欏墠闈㈢殑鐏 set_s_to_be_seven_numbers() beq $a2 $zero case0 beq $a2 $s1 case1 @@ -37,8 +38,8 @@ case1: jal read sw $a0 0($fp) jal write_data - sw $a0 4($fp) jal read + sw $a0 4($fp) jal write_data j begin case2: @@ -81,4 +82,4 @@ case7: j begin j begin .include "../commons/std_io_minisys.impl.mips" -.include "../commons/std_palindrome.impl.mips" \ No newline at end of file +.include "../commons/std_palindrome.impl.mips" diff --git a/main/mips/cpu_test/situation1.mips b/main/mips/cpu_test/situation1.mips index 74acd03..53da942 100644 --- a/main/mips/cpu_test/situation1.mips +++ b/main/mips/cpu_test/situation1.mips @@ -1,5 +1,7 @@ +.include "../commons/std_io_minisys.macro.mips" .data .text +jal static_initialization ini: addi $v1, $zero, 1 addi $21, $zero, 1 @@ -14,8 +16,8 @@ ini: lui $19, 0x8FFF ori $19, $19, 0xFFFF #the submask -master: lw $2, 0x72($20) # read the sw23,22,21，72是左边，70是右边 - srl $2, $2, 5 # 移动到我的指令的位数 +begin: lw $2, 0x72($20) # read the sw23,22,21锟斤拷72锟斤拷锟斤拷撸锟70锟斤拷锟揭憋拷 + srl $2, $2, 5 # 锟狡讹拷锟斤拷锟揭碉拷指锟斤拷锟轿伙拷锟 beq $2, $zero, case0 beq $2, $21, case1 beq $2, $22, case2 @@ -27,12 +29,12 @@ master: lw $2, 0x72($20) # read the sw23,22,21 case0: lw $3, 0x70($20) - sw $3, 0x60($20) # 警惕2个led灯管互相刷新 + sw $3, 0x60($20) # 锟斤拷锟斤拷2锟斤拷led锟狡管伙拷锟斤拷刷锟斤拷 add $4, $zero, $3 sll $4, $4, 16 addi $5, $zero, 0 # the control varible addi $8, $zero, 1 # the signal -shiftl: # make the leftmost1 in the highest 先把第一个1移到最左边 +shiftl: # make the leftmost1 in the highest 锟饺把碉拷一锟斤拷1锟狡碉拷锟斤拷锟斤拷锟 sll $4, $4, 1 slti $10, $4, 0 # 0 > $4 then jump bne $10, $zero, panduan @@ -44,55 +46,57 @@ shiftl: # make the leftmost1 in the highest panduan: andi $6, $3, 0xfff8 srl $7, $4, 31 - sll $4, $4, 1 # 这个记得不断左移 + sll $4, $4, 1 # 锟斤拷锟斤拷堑貌锟斤拷锟斤拷锟斤拷锟 srl $3, $3, 1 bne $6, $7, outcase0 addi $5, $5, 1 slti $10, $5, 16 - beq $10, $zero, panduan #如果是还没到16就继续判断 + beq $10, $zero, panduan #锟斤拷锟斤拷腔锟矫伙拷锟16锟酵硷拷锟斤拷锟叫讹拷 led16light: addi $10, $zero, 1 sw $10, 0x62($20) outcase0: - j master + j begin ############################################################ -# 存储读取的数字存储在￥3和￥5中 +# 锟芥储锟斤拷取锟斤拷锟斤拷锟街存储锟节ｏ拷3锟酵ｏ拷5锟斤拷 case1: lw $3, 0x70($20) sw $3, 0x60($20) lw $4, 0x72($20) andi $4, $4, 0xfff8 - beq $4, $zero, case1 # 你需要反复读取 + beq $4, $zero, case1 # 锟斤拷锟斤拷要锟斤拷锟斤拷锟斤拷取 case1read2: lw $5, 0x70($20) sw $5, 0x60($20) lw $4, 0x72($20) - srl $4, $4, 1 # SW17代表第二个数读取完毕 + srl $4, $4, 1 # SW17锟斤拷锟斤拷诙锟斤拷锟斤拷锟斤拷锟饺★拷锟斤拷 andi $4, $4, 0xfff8 beq $4, $zero, case1read2 - j master + j begin case2: and $6, $3, $5 sw $5, 0x60($20) - j master + j begin case3: or $6, $3, $5 sw $5, 0x60($20) - j master + j begin case4: xor $6, $3, $5 sw $5, 0x60($20) - j master + j begin case5: sllv $6, $3, $5 sw $5, 0x60($20) - j master + j begin case6: srlv $6, $3, $5 sw $5, 0x60($20) - j master + j begin case7: srav $6, $3, $5 sw $5, 0x60($20) - j master + j begin + +.include "../commons/std_io_minisys.impl.mips" diff --git a/test/verilog/TestNewSituation1.v b/test/verilog/TestNewSituation1.v new file mode 100644 index 0000000..211c73a --- /dev/null +++ b/test/verilog/TestNewSituation1.v @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +module TestNewSituation1( + ); +reg[23:0]Minisys_Switches; +wire [23:0]Minisys_Lights; +reg Minisys_Clock; +reg[4:0] Minisys_Button; +always begin + #1 Minisys_Clock = ~Minisys_Clock;//这个是外部的clock +end + +TOP_all use_main(Minisys_Switches,Minisys_Lights,Minisys_Clock,Minisys_Button); + +initial begin + Minisys_Clock = 1'b0; + Minisys_Button = 5'b00000; + Minisys_Switches[23:0] = 24'h0; + # 100 Minisys_Button = 5'b01000; + # 50 Minisys_Button = 5'b00000; + #4000 + // 此时理论上 开机特效圆满结束了。 + + // 测试case 000. + Minisys_Switches[23:0] = 24'h1; // a的值 + #10000 + Minisys_Switches[20] =1; // enter的值 + #10000 + // assert: 现在右边的灯显示1. 左边的灯显示enter正在等待放下。显示case0， 显示 + Minisys_Switches[20] =0; // 重新进入case 0， 理论上要求重新输入 + #10000 + Minisys_Switches[20] =1; //再次输入1. + #100003 + Minisys_Switches[20] =1; //此时右灯应该是1 +end + +endmodule diff --git a/test/verilog/testCpuTop.v b/test/verilog/TestSituation1.v similarity index 98% rename from test/verilog/testCpuTop.v rename to test/verilog/TestSituation1.v index 418be7e..854fcea 100644 --- a/test/verilog/testCpuTop.v +++ b/test/verilog/TestSituation1.v @@ -1,6 +1,5 @@ `timescale 1ns / 1ps -module TOP_all_test( - +module TestSituation1( ); reg[23:0]Minisys_Switches; wire [23:0]Minisys_Lights; -- Gitee From acea5c889991fbab8d4540de83de314d83877f19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Wed, 25 May 2022 22:31:43 +0800 Subject: [PATCH 20/57] =?UTF-8?q?fix(mips):=20=E4=BF=AE=E5=A4=8Dra?= =?UTF-8?q?=E6=BC=8F=E6=B4=9E?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 62 ++++++++++++++------- main/mips/commons/std_io_minisys.macro.mips | 13 ++++- main/mips/cpu_test/new_situation1.mips | 4 +- 3 files changed, 54 insertions(+), 25 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index a25f504..8e71e04 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -74,21 +74,34 @@ decode: # note: a2 涓簉ead涔嬪墠绯荤粺鐨刢ase鐘舵侊紝濡傛灉绛夊緟璇诲彇鐨勮繃绋嬪彂鐜板彉鍖栵紝浼氳繑鍥炲埌begin銆 read: save_ra() - write_control_set_true(4) - jal decode # 浼氳鐩朼0 a1鐨勫笺 - sleep(100) - bne $a0 $a2 begin - bne $a1 $zero read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟鐩村埌enter鏄0 + while_read: + sleep(100) + write_control_set_true(4) + + jal decode # 浼氳鐩朼0 a1鐨勫笺 + + load_ra() + write_control_set_false(4) + bne $a0 $a2 begin #濡傛灉case鍙戠敓鏇存敼锛屽甫涓妑a鎻愬墠璺戣矾 + write_control_set_true(4) + save_ra() # 濡傛灉娌℃湁鏀癸紝灏辩户缁 + + bne $a1 $zero while_read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟鐩村埌enter鏄0 + write_control_set_false(4) -_read_wait_for_enter: - sleep(200) - #li $t0 0 - jal decode - bne $a0 $a2 begin - write_control_negate(4) - lw $a0 0x70($gp) - move $s7 $a0 - jal write_data + + _read_wait_for_enter: + sleep(200) + write_control_negate(4) + jal decode + + load_ra() + bne $a0 $a2 begin + save_ra() + + lw $a0 0x70($gp) + move $s7 $a0 + jal write_data beq $a1 $zero _read_wait_for_enter # 绛夊埌enter鏄1銆 li $a0 0 @@ -104,19 +117,25 @@ _read_wait_for_enter: load_ra() jr $ra -# 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涙牴鎹畍1鐨勫肩殑鏈鍚庝竴浣嶆槸鍚︽槸1鏉ヤ慨鏀 +# 鐘舵: 娴嬭瘯涓 +# 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涙牴鎹畍1鐨勫肩殑鏈鍚庝竴浣嶆槸鍚︽槸1鏉ヤ慨鏀广 write_control_set: lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 - # 鎿嶄綔v1 - andi $v1 $v1 1 # 鍙栨渶鍚庝竴浣 - sllv $v1 $v1 $v0 # 宸︾Щ v0浣 - # 璁゛0鐨勫搴斾綅鍐欏湪t1涓娿 + andi $v1 $v1 1 # 鍙彇鏈鍚庝竴浣 + + # 鏍规嵁 t1 鐨勫搴斾綅鏉ュ喅瀹氭庝箞鎿嶄綔銆 + srlv $t0 $t1 $v0 andi $t0 $t0 1 # 鍙栫浉搴斾綅銆 - beq $t0 $zero if0 + + beq $t0 $zero if0 # 濡傛灉t1瀵瑰簲浣嶆槸0. 姣斿t1= 0000 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负1. + li $t2 0xFF + sllv $v1 $v1 $v0 + and $v1 $v1 $t2 and $t1 $t1 $v1 j endif0 - if0: + if0: # 濡傛灉t1瀵瑰簲浣嶆槸1. 姣斿t1= 0100 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负0. + sllv $v1 $v1 $v0 # 宸︾Щ v0浣 or $t1 $t1 $v1 endif0: sw $t1 4($k0) # 鎶妕1鐨勮绠楃粨鏋滈佸洖鐏笂銆 @@ -149,3 +168,4 @@ exception_hint: warn_data() load_ra() jr $ra + diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 292b4d6..62bde11 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -3,8 +3,8 @@ # note:vivado 浠跨湡鏃讹紝涓嶅惎鐢╯leep銆傚洜涓簐ivado妯℃嫙鏃舵病鏈変俊鍙蜂笉绋冲畾鐨勯棶棰樸 .macro sleep(%msec) #not vivado - #la $v0 %msec - #jal sleep + la $v0 %msec + jal sleep #vivado .end_macro @@ -96,3 +96,12 @@ j for_case4 end_for_case4: .end_macro + +# 浠巃0 璇诲彇case缂栧彿锛屼功鍐欏埌鎺у埗鐏渶宸﹁竟涓変綅 +.macro hint_case_number() + sll $a0 $a0 5 + lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 + or $t1 $t1 $a0 # 鐢╫r鎶奱0娣诲姞涓婂幓 + sw $t1 4($k0) # 鎶妕1鐨勮绠楃粨鏋滈佸洖鐏笂銆 + flush_lights() +.end_macro diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index b670ea0..3d27af8 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -14,8 +14,8 @@ begin: jal decode # 浼氳鐩朼0 a1鐨勫笺 move $a2 $a0 - sll $a0 $a0 5 - jal write_control # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 鍙兘浼氬鍐欏墠闈㈢殑鐏 + hint_case_number() # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 涓嶄細骞叉壈鍓嶉潰宸叉湁鐨勭伅銆 + set_s_to_be_seven_numbers() beq $a2 $zero case0 beq $a2 $s1 case1 -- Gitee From e72b3315641f1b236023f632f032c78c277f4df0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Wed, 25 May 2022 22:35:59 +0800 Subject: [PATCH 21/57] =?UTF-8?q?fix(mips):=20=E4=BF=AE=E5=A4=8Dcase?= =?UTF-8?q?=E6=8F=90=E7=A4=BA=E7=9A=84=E6=BC=8F=E6=B4=9E?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.macro.mips | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 62bde11..09941ee 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -99,9 +99,19 @@ # 浠巃0 璇诲彇case缂栧彿锛屼功鍐欏埌鎺у埗鐏渶宸﹁竟涓変綅 .macro hint_case_number() - sll $a0 $a0 5 - lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 - or $t1 $t1 $a0 # 鐢╫r鎶奱0娣诲姞涓婂幓 - sw $t1 4($k0) # 鎶妕1鐨勮绠楃粨鏋滈佸洖鐏笂銆 - flush_lights() + andi $a0 $a0 0x7 # 鍙鏈鍚庝笁浣 + li $v0 5 + andi $v1 $a0 1 # 鏈鍚庝竴浣 + jal write_control_set + + srl $a0 $a0 1 + li $v0 6 + andi $v1 $a0 1 # 鏈鍚庝竴浣 + jal write_control_set + + srl $a0 $a0 1 + li $v0 7 + andi $v1 $a0 1 # 鏈鍚庝竴浣 + jal write_control_set + .end_macro -- Gitee From 7f960aa1fd95aa9d76687447be415ec5b29405ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 11:18:43 +0800 Subject: [PATCH 22/57] =?UTF-8?q?feat(mips):=20=E4=BF=AE=E5=A4=8Dread?= =?UTF-8?q?=E5=87=BD=E6=95=B0=E4=B8=AD=E7=9A=84ra=E6=BC=8F=E6=B4=9E?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 29 +++++++++++++-------- main/mips/commons/std_io_minisys.macro.mips | 3 ++- main/mips/cpu_test/new_situation1.mips | 5 ++-- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index 8e71e04..429ec2c 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -44,6 +44,7 @@ static_initialization: jr $ra #娴嬭瘯鐘舵侊細鍙俊 # 鐫＄湢 v0涓殑姣鏁般傚叕寮 T=TPC*CPI*I, 寰楀埌I = Tf (T涓烘椂闂达紝鍗曚綅ms, f涓烘椂閽熼鐜) +# t2, t1, t0, v0 鍙戠敓鍙樺寲銆傚叾涓璿0鍙樹负0. t2, t1, t0 閮藉彉鎴愭瘮杈冨ぇ鐨勬暣鏁般 sleep: sll $t1 $v0 4 # 23=16+8-1 sll $t0 $v0 3 @@ -61,6 +62,7 @@ sleep: #娴嬭瘯鐘舵侊細鍙俊 # 鏈琣sm鐨勬帶鍒惰緭鍏ワ紙宸﹀紑鍏筹級瀹氫箟锛氬乏寮鍏冲墠涓変綅涓篶ase锛岀鍥涗綅涓篹nter銆俥nter涓1鐘舵佹椂绛夊緟鍙樹负0锛屼负0鏃剁瓑寰呰緭鍏ョ殑纭畾銆 # decode: 杈撳叆a0(宸)銆傝В鏋愪负a0=case锛 a1=enter +# 浠呬粎淇敼浜哸0鍜宎1瀵勫瓨鍣 decode: lw $a0 0x72($gp) # 7,6,...,0. @@ -76,24 +78,24 @@ read: save_ra() while_read: sleep(100) - write_control_set_true(4) + write_control_set_true(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 jal decode # 浼氳鐩朼0 a1鐨勫笺 + write_control_set_false(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 load_ra() - write_control_set_false(4) bne $a0 $a2 begin #濡傛灉case鍙戠敓鏇存敼锛屽甫涓妑a鎻愬墠璺戣矾 - write_control_set_true(4) save_ra() # 濡傛灉娌℃湁鏀癸紝灏辩户缁 + write_control_set_true(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 bne $a1 $zero while_read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟鐩村埌enter鏄0 - write_control_set_false(4) + write_control_set_false(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 _read_wait_for_enter: sleep(200) - write_control_negate(4) - jal decode + write_control_negate(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 + jal decode # a0 a1 閮芥敼浜 load_ra() bne $a0 $a2 begin @@ -119,25 +121,28 @@ read: # 鐘舵: 娴嬭瘯涓 # 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涙牴鎹畍1鐨勫肩殑鏈鍚庝竴浣嶆槸鍚︽槸1鏉ヤ慨鏀广 +# 淇敼v1锛 t1, t0, t2. write_control_set: - lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 andi $v1 $v1 1 # 鍙彇鏈鍚庝竴浣 + lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 # 鏍规嵁 t1 鐨勫搴斾綅鏉ュ喅瀹氭庝箞鎿嶄綔銆 srlv $t0 $t1 $v0 andi $t0 $t0 1 # 鍙栫浉搴斾綅銆 - beq $t0 $zero if0 # 濡傛灉t1瀵瑰簲浣嶆槸0. 姣斿t1= 0000 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负1. + bne $t0 $zero if_write_control_set + # 濡傛灉t1瀵瑰簲浣嶆槸0. 姣斿t1= 0000 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负1. li $t2 0xFF sllv $v1 $v1 $v0 and $v1 $v1 $t2 and $t1 $t1 $v1 - j endif0 - if0: # 濡傛灉t1瀵瑰簲浣嶆槸1. 姣斿t1= 0100 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负0. + if_write_control_set: + # 濡傛灉t1瀵瑰簲浣嶆槸1. 姣斿t1= 0100 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负0. sllv $v1 $v1 $v0 # 宸︾Щ v0浣 or $t1 $t1 $v1 - endif0: + j end_if_write_control_set + end_if_write_control_set: sw $t1 4($k0) # 鎶妕1鐨勮绠楃粨鏋滈佸洖鐏笂銆 flush_lights() jr $ra @@ -151,11 +156,13 @@ write_control_negate: flush_lights() jr $ra #杈撳嚭鎺у埗鐏紙宸︾伅锛; 鐩存帴杈撳嚭a0鐨勫笺 +# 浼氫慨鏀箃0鐨勫(鍙樻垚a0鎴栬0)鍜4($k0)鐨勫 write_control: sw $a0 4($k0) flush_lights() jr $ra #杈撳嚭鏁版嵁鐏紙鍙崇伅锛; 鐩存帴杈撳嚭a0鐨勫笺 +# 浼氫慨鏀箃0鐨勫(鍙樻垚a0鎴栬0)鍜0($k0)鐨勫 write_data: sw $a0 0($k0) flush_lights() diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 09941ee..2e41574 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -10,6 +10,7 @@ #娴嬭瘯鐘舵侊細鍙俊 # 浠庣紦瀛樺唴瀛樼殑鍊煎啓鍏ュ埌鐏腑銆傝繖鏄痯rivate鏂规硶锛屼笉瑕佽交鏄撹皟鐢ㄣ +# 浼氫慨鏀箃0鐨勫煎拰鐏殑鍊笺 .macro flush_lights() lw $t0 4($k0) sw $t0 0x62($gp) @@ -113,5 +114,5 @@ li $v0 7 andi $v1 $a0 1 # 鏈鍚庝竴浣 jal write_control_set - + # sleep(200) .end_macro diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index 3d27af8..90c74cd 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -1,6 +1,5 @@ .include "../commons/std_io_minisys.macro.mips" .data - dataset0: .word 0 .text .globl main main: # todo: 娌′粈涔堢敤锛宑oe鏂囦欢涓嶈兘浣嶇疆鏃犲叧銆 @@ -15,7 +14,7 @@ begin: move $a2 $a0 hint_case_number() # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 涓嶄細骞叉壈鍓嶉潰宸叉湁鐨勭伅銆 - + set_s_to_be_seven_numbers() beq $a2 $zero case0 beq $a2 $s1 case1 @@ -26,8 +25,10 @@ begin: beq $a2 $s6 case6 beq $a2 $s7 case7 case0: + sleep(200) jal read sw $a0 0($fp) + sleep(200) jal write_data jal is_binary_palindrome move $v1 $v0 -- Gitee From 28e8ff28565464e7b3203c75644c16355352c67a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 11:19:12 +0800 Subject: [PATCH 23/57] =?UTF-8?q?feat(mips):=20situation2=20=E7=8E=B0?= =?UTF-8?q?=E4=BB=A3=E6=8E=A5=E5=8F=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/situation2.mips | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 6c5b38c..5d62e73 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -5,14 +5,13 @@ main: # todo: 娌′粈涔堢敤锛宑oe鏂囦欢涓嶈兘浣嶇疆鏃犲叧銆 jal static_initialization begin: - li $v0 10 - jal sleep # 闄嶄綆閫熷害 + sleep(50) jal decode # 浼氳鐩朼0 a1鐨勫笺 move $a2 $a0 - sll $a0 $a0 5 - jal write_control # 鎸囩ず褰撳墠鏄摢涓涓猚ase + hint_case_number() # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 涓嶄細骞叉壈鍓嶉潰宸叉湁鐨勭伅銆 + set_s_to_be_seven_numbers() beq $a2 $zero case0 beq $a2 $s1 case1 @@ -35,6 +34,7 @@ case0: jal exception_hint # 濡傛灉姣10澶э紝鍙槸璀﹀憡锛屼笉閲嶆柊杈撳叆銆 end_if_case0_1: addi $s2 $fp 0 # 0鍊嶇殑s0锛 s2鐜板湪鏄暟鎹泦0鐨勫熀鍦板潃銆 + for_case0: ble $s1 $zero end_for_case0 # 鐢╟ontrol鐨勫彸杈瑰洓涓伅鎻愮ず姝ｅ湪璇荤鍑犱釜鏁 @@ -157,4 +157,4 @@ case7: j begin .include "../commons/std_io_minisys.impl.mips" -.include "../commons/std_algorithm.mips" \ No newline at end of file +.include "../commons/std_algorithm.mips" -- Gitee From cdf92358cd5beb76665379d8ba38cb5f6b9a8543 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 12:09:28 +0800 Subject: [PATCH 24/57] =?UTF-8?q?feat(mips):=20=E6=96=B0=E7=89=88=E5=9C=BA?= =?UTF-8?q?=E6=99=AF1=E6=97=A0bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 37 ++++++++++----------- main/mips/commons/std_io_minisys.macro.mips | 16 +++++---- main/mips/cpu_test/new_situation1.mips | 7 ++-- 3 files changed, 33 insertions(+), 27 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index 429ec2c..ef56585 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -70,30 +70,30 @@ decode: andi $a1 $a0 1 srl $a0 $a0 1 jr $ra -#娴嬭瘯鐘舵侊細鍗遍櫓 +#娴嬭瘯鐘舵侊細娴嬭瘯涓 # 鏍规嵁a1鐨別nter淇″彿鎺у埗锛岀瓑寰呰緭鍏ヤ竴涓暣鏁帮紙閫氳繃鍙冲紑鍏筹級锛岀粨鏋滀繚瀛樺埌a0銆 # a1鍜宎0閮戒細鏀瑰彉銆 # note: a2 涓簉ead涔嬪墠绯荤粺鐨刢ase鐘舵侊紝濡傛灉绛夊緟璇诲彇鐨勮繃绋嬪彂鐜板彉鍖栵紝浼氳繑鍥炲埌begin銆 read: save_ra() + write_control_set_true(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 while_read: sleep(100) - write_control_set_true(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 jal decode # 浼氳鐩朼0 a1鐨勫笺 - write_control_set_false(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 - load_ra() - bne $a0 $a2 begin #濡傛灉case鍙戠敓鏇存敼锛屽甫涓妑a鎻愬墠璺戣矾 - save_ra() # 濡傛灉娌℃湁鏀癸紝灏辩户缁 - write_control_set_true(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 + beq $a0 $a2 end_if_while_read #濡傛灉case鍙戠敓鏇存敼锛屽甫涓妑a鎻愬墠璺戣矾 + load_ra() # 涓昏鐩殑鏄仮澶峴p锛宺a鐨勫艰繖閲屼笉鍏冲績銆 + write_control_set_false(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 + j begin + end_if_while_read: bne $a1 $zero while_read # 濡傛灉enter涓嶆槸0锛屽氨缁х画绛夊緟鐩村埌enter鏄0 write_control_set_false(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 _read_wait_for_enter: - sleep(200) + sleep(300) write_control_negate(4) # 娉ㄦ剰杩欐槸鏈塲al鍦ㄩ噷闈㈢殑锛 v0, v1, t0 t1閮戒慨鏀逛簡 jal decode # a0 a1 閮芥敼浜 @@ -123,22 +123,18 @@ read: # 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涙牴鎹畍1鐨勫肩殑鏈鍚庝竴浣嶆槸鍚︽槸1鏉ヤ慨鏀广 # 淇敼v1锛 t1, t0, t2. write_control_set: - andi $v1 $v1 1 # 鍙彇鏈鍚庝竴浣 lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 + andi $v1 $v1 1 # 鍙彇鏈鍚庝竴浣 - # 鏍规嵁 t1 鐨勫搴斾綅鏉ュ喅瀹氭庝箞鎿嶄綔銆 - - srlv $t0 $t1 $v0 - andi $t0 $t0 1 # 鍙栫浉搴斾綅銆 - - bne $t0 $zero if_write_control_set - # 濡傛灉t1瀵瑰簲浣嶆槸0. 姣斿t1= 0000 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负1. - li $t2 0xFF + # 鏍规嵁 v1 鐨勫搴斾綅鏉ュ喅瀹氭庝箞鎿嶄綔銆 + bne $v1 $zero if_write_control_set + # 濡傛灉v1瀵瑰簲浣嶆槸0. 姣斿t1= 0000 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负1. + li $t2 0xFFFFFFFF # and 鎺╃爜 sllv $v1 $v1 $v0 and $v1 $v1 $t2 and $t1 $t1 $v1 if_write_control_set: - # 濡傛灉t1瀵瑰簲浣嶆槸1. 姣斿t1= 0100 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负0. + # 濡傛灉v1瀵瑰簲浣嶆槸1. 姣斿t1= 0100 0000 鎴戜滑瑕佷慨鏀圭6浣嶄负0. sllv $v1 $v1 $v0 # 宸︾Щ v0浣 or $t1 $t1 $v1 j end_if_write_control_set @@ -146,6 +142,7 @@ write_control_set: sw $t1 4($k0) # 鎶妕1鐨勮绠楃粨鏋滈佸洖鐏笂銆 flush_lights() jr $ra +# 娴嬭瘯鐘舵侊細鍙俊 # 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涘璇ョ伅鐨勫煎彇鍙嶃 write_control_negate: lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 @@ -155,12 +152,14 @@ write_control_negate: sw $t1 4($k0) # 鎶妕1鐨勮绠楃粨鏋滈佸洖鐏笂銆 flush_lights() jr $ra +# 娴嬭瘯鐘舵侊細鍙俊 #杈撳嚭鎺у埗鐏紙宸︾伅锛; 鐩存帴杈撳嚭a0鐨勫笺 # 浼氫慨鏀箃0鐨勫(鍙樻垚a0鎴栬0)鍜4($k0)鐨勫 write_control: sw $a0 4($k0) flush_lights() jr $ra +# 娴嬭瘯鐘舵侊細鍙俊 #杈撳嚭鏁版嵁鐏紙鍙崇伅锛; 鐩存帴杈撳嚭a0鐨勫笺 # 浼氫慨鏀箃0鐨勫(鍙樻垚a0鎴栬0)鍜0($k0)鐨勫 write_data: @@ -168,7 +167,7 @@ write_data: flush_lights() jr $ra - +# 鎻愮ず杈撳叆鏁版嵁瀛樺湪寮傚父鎯呭喌銆 exception_hint: save_ra() warn_data() diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 2e41574..f028afa 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -54,18 +54,22 @@ .macro warn_data() lw $t7 0($k0) + lw $t8 4($k0) + li $a0 0xFFFF jal write_data + write_control_set_true(2) write_control_set_true(3) - li $v0 1000 - jal sleep + sleep(1000) # 淇濇寔鐘舵1s + +# 鎭㈠鍘熸牱 move $a0 $t7 jal write_data - write_control_set_false(2) - write_control_set_false(3) - li $v0 500 - jal sleep + + move $a0 $t8 + jal write_control + .end_macro .macro all_lights_on() diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index 90c74cd..51b199e 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -13,7 +13,7 @@ begin: jal decode # 浼氳鐩朼0 a1鐨勫笺 move $a2 $a0 - hint_case_number() # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 涓嶄細骞叉壈鍓嶉潰宸叉湁鐨勭伅銆 + # hint_case_number() # 鎸囩ず褰撳墠鏄摢涓涓猚ase. 涓嶄細骞叉壈鍓嶉潰宸叉湁鐨勭伅銆 set_s_to_be_seven_numbers() beq $a2 $zero case0 @@ -25,7 +25,6 @@ begin: beq $a2 $s6 case6 beq $a2 $s7 case7 case0: - sleep(200) jal read sw $a0 0($fp) sleep(200) @@ -34,6 +33,8 @@ case0: move $v1 $v0 li $v0 0 jal write_control_set + + sleep(1000) j begin case1: jal read @@ -42,6 +43,8 @@ case1: jal read sw $a0 4($fp) jal write_data + + sleep(1000) j begin case2: lw $s0 0($fp) -- Gitee From 479d1a9f7bbcf3d9ae77de88e93addefa1918efd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 12:12:36 +0800 Subject: [PATCH 25/57] =?UTF-8?q?feat(mips):=E5=88=86=E6=94=AF=E5=90=88?= =?UTF-8?q?=E5=B9=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/situation1.mips | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/main/mips/cpu_test/situation1.mips b/main/mips/cpu_test/situation1.mips index 53da942..63a4966 100644 --- a/main/mips/cpu_test/situation1.mips +++ b/main/mips/cpu_test/situation1.mips @@ -16,8 +16,8 @@ ini: lui $19, 0x8FFF ori $19, $19, 0xFFFF #the submask -begin: lw $2, 0x72($20) # read the sw23,22,21锟斤拷72锟斤拷锟斤拷撸锟70锟斤拷锟揭憋拷 - srl $2, $2, 5 # 锟狡讹拷锟斤拷锟揭碉拷指锟斤拷锟轿伙拷锟 +begin: lw $2, 0x72($20) # read the sw23,22,21锟斤拷72锟斤拷锟斤拷撸锟?70锟斤拷锟揭憋拷 + srl $2, $2, 5 # 锟狡讹拷锟斤拷锟揭碉拷指锟斤拷锟轿伙拷锟? beq $2, $zero, case0 beq $2, $21, case1 beq $2, $22, case2 @@ -34,7 +34,7 @@ case0: sll $4, $4, 16 addi $5, $zero, 0 # the control varible addi $8, $zero, 1 # the signal -shiftl: # make the leftmost1 in the highest 锟饺把碉拷一锟斤拷1锟狡碉拷锟斤拷锟斤拷锟 +shiftl: # make the leftmost1 in the highest 锟饺把碉拷一锟斤拷1锟狡碉拷锟斤拷锟斤拷锟? sll $4, $4, 1 slti $10, $4, 0 # 0 > $4 then jump bne $10, $zero, panduan @@ -46,12 +46,12 @@ shiftl: # make the leftmost1 in the highest 锟饺把碉拷一锟斤拷1锟狡碉拷锟斤拷锟 panduan: andi $6, $3, 0xfff8 srl $7, $4, 31 - sll $4, $4, 1 # 锟斤拷锟斤拷堑貌锟斤拷锟斤拷锟斤拷锟 + sll $4, $4, 1 # 锟斤拷锟斤拷堑貌锟斤拷锟斤拷锟斤拷锟? srl $3, $3, 1 bne $6, $7, outcase0 addi $5, $5, 1 slti $10, $5, 16 - beq $10, $zero, panduan #锟斤拷锟斤拷腔锟矫伙拷锟16锟酵硷拷锟斤拷锟叫讹拷 + beq $10, $zero, panduan #锟斤拷锟斤拷腔锟矫伙拷锟?16锟酵硷拷锟斤拷锟叫讹拷 led16light: addi $10, $zero, 1 sw $10, 0x62($20) -- Gitee From 451536a0a2f889ca63ae1b819ac0f2c19df2e065 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 12:14:36 +0800 Subject: [PATCH 26/57] =?UTF-8?q?feat(mips)=EF=BC=9A=E5=90=88=E5=B9=B6?= =?UTF-8?q?=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/situation1.mips | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/main/mips/cpu_test/situation1.mips b/main/mips/cpu_test/situation1.mips index 63a4966..570d978 100644 --- a/main/mips/cpu_test/situation1.mips +++ b/main/mips/cpu_test/situation1.mips @@ -2,7 +2,7 @@ .data .text jal static_initialization -ini: +begin: addi $v1, $zero, 1 addi $21, $zero, 1 addi $22, $zero, 2 -- Gitee From c66b26144d352c2fd06fd586c92f2dda935b4006 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 13:08:26 +0800 Subject: [PATCH 27/57] =?UTF-8?q?feat(mips)=EF=BC=9A=20=E5=90=88=E5=B9=B6?= =?UTF-8?q?=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../{situation1plus.asm => situation1.asm} | 48 +++++---- main/mips/cpu_test/situation1.mips | 102 ------------------ 2 files changed, 25 insertions(+), 125 deletions(-) rename main/mips/cpu_test/{situation1plus.asm => situation1.asm} (56%) delete mode 100644 main/mips/cpu_test/situation1.mips diff --git a/main/mips/cpu_test/situation1plus.asm b/main/mips/cpu_test/situation1.asm similarity index 56% rename from main/mips/cpu_test/situation1plus.asm rename to main/mips/cpu_test/situation1.asm index 6934a12..f93eabc 100644 --- a/main/mips/cpu_test/situation1plus.asm +++ b/main/mips/cpu_test/situation1.asm @@ -1,6 +1,7 @@ -.data - buf: .word 0x0000 -.text +.include "../commons/std_io_minisys.macro.mips" +.data +.text +jal static_initialization ini: sw $3, 0x62($20) addi $21, $zero, 1 @@ -15,8 +16,8 @@ ini: lui $19, 0x8FFF ori $19, $19, 0xFFFF #the submask -master: lw $2, 0x72($20) # read the sw23,22,21 - srl $2, $2, 5 # 移动到我的指令的位数 +begin: lw $2, 0x72($20) # read the sw23,22,21 + srl $2, $2, 5 # 锟狡讹拷锟斤拷锟揭碉拷指锟斤拷锟轿伙拷锟? beq $2, $zero, case0 beq $2, $21, case1 beq $2, $22, case2 @@ -28,11 +29,11 @@ master: lw $2, 0x72($20) # read the sw23,22,21 case0: lw $1, 0x70($20) - sw $1, 0x60($20) # 警惕2个led灯管互相刷新 - add $4, $zero, $1 # 存一下这个内容 + sw $1, 0x60($20) # 锟斤拷锟斤拷2锟斤拷led锟狡管伙拷锟斤拷刷锟斤拷 + add $4, $zero, $1 # 锟斤拷一锟斤拷锟斤拷锟斤拷锟斤拷锟? addi $6, $zero, 0 loop: - beq $4,$zero,exit #全变0退出,4这个变量没用 + beq $4,$zero,exit #全锟斤拷0锟剿筹拷,4锟斤拷锟斤拷锟斤拷锟矫伙拷锟? andi $11,$4,1 sll $6,$6,1 add $6,$6,$11 @@ -41,56 +42,57 @@ loop: exit: beq $1, $6,led16light bne $1, $6,led16notlight - j master + j begin led16light: addi $10, $zero, 1 sw $10, 0x62($20) - j master# 存储读取的数字存储在￥3和￥5中 + j begin# 锟芥储锟斤拷取锟斤拷锟斤拷锟街存储锟节ｏ拷3锟酵ｏ拷5锟斤拷 led16notlight: addi $10, $zero, 0 sw $10, 0x62($20) - j master + j begin case1: lw $4, 0x72($20) - srl $4, $4, 2 # SW18是1代表我的值被锁定了,顺序输入第一个数，拨sw16，拨sw18.输入第二个数 拨sw17.#但凡想要取消，再SW18是0就可以取消 + srl $4, $4, 2 # SW18锟斤拷1锟斤拷锟斤拷锟揭碉拷值锟斤拷锟斤拷锟斤拷锟斤拷,顺锟斤拷锟斤拷锟斤拷锟揭伙拷锟斤拷锟斤拷锟斤拷锟絪w16锟斤拷锟斤拷sw18.锟斤拷锟斤拷诙锟斤拷锟斤拷锟? 锟斤拷sw17.#锟斤拷锟斤拷锟斤拷要取锟斤拷锟斤拷锟斤拷SW18锟斤拷0锟酵匡拷锟斤拷取锟斤拷 andi $4, $4, 0x0001 - bne $4, $zero,master + bne $4, $zero,begin lw $3, 0x70($20) sw $3, 0x60($20) sw $zero, 0x62($20) lw $4, 0x72($20) - andi $4, $4, 0x0001 #SW16代表第一个读取完毕 - beq $4, $zero, case1 # 你需要反复读取 + andi $4, $4, 0x0001 #SW16锟斤拷锟斤拷锟揭伙拷锟斤拷锟饺★拷锟斤拷 + beq $4, $zero, case1 # 锟斤拷锟斤拷要锟斤拷锟斤拷锟斤拷取 case1read2: lw $5, 0x70($20) sw $5, 0x60($20) lw $4, 0x72($20) - srl $4, $4, 1 # SW17代表第二个数读取完毕 + srl $4, $4, 1 # SW17锟斤拷锟斤拷诙锟斤拷锟斤拷锟斤拷锟饺★拷锟斤拷 andi $4, $4, 0x0001 beq $4, $zero, case1read2 - j master + j begin case2: and $6, $3, $5 sw $6, 0x60($20) - j master + j begin case3: or $6, $3, $5 sw $6, 0x60($20) - j master + j begin case4: xor $6, $3, $5 sw $6, 0x60($20) - j master + j begin case5: sllv $6, $3, $5 sw $6, 0x60($20) - j master + j begin case6: srlv $6, $3, $5 sw $6, 0x60($20) - j master + j begin case7: srav $6, $3, $5 sw $6, 0x60($20) - j master + j begin +.include "../commons/std_io_minisys.impl.mips" diff --git a/main/mips/cpu_test/situation1.mips b/main/mips/cpu_test/situation1.mips deleted file mode 100644 index 570d978..0000000 --- a/main/mips/cpu_test/situation1.mips +++ /dev/null @@ -1,102 +0,0 @@ -.include "../commons/std_io_minisys.macro.mips" -.data -.text -jal static_initialization -begin: - addi $v1, $zero, 1 - addi $21, $zero, 1 - addi $22, $zero, 2 - addi $23, $zero, 3 - addi $24,$zero, 4 - addi $25,$zero, 5 - addi $26, $zero, 6 - addi $27, $zero, 7 - lui $20, 0xFFFF - ori $20, $20, 0xFC00 # 20 is the basic address - lui $19, 0x8FFF - ori $19, $19, 0xFFFF #the submask - -begin: lw $2, 0x72($20) # read the sw23,22,21锟斤拷72锟斤拷锟斤拷撸锟?70锟斤拷锟揭憋拷 - srl $2, $2, 5 # 锟狡讹拷锟斤拷锟揭碉拷指锟斤拷锟轿伙拷锟? - beq $2, $zero, case0 - beq $2, $21, case1 - beq $2, $22, case2 - beq $2, $23, case3 - beq $2, $24, case4 - beq $2, $25, case5 - beq $2, $26, case6 - beq $2, $27, case7 - -case0: - lw $3, 0x70($20) - sw $3, 0x60($20) # 锟斤拷锟斤拷2锟斤拷led锟狡管伙拷锟斤拷刷锟斤拷 - add $4, $zero, $3 - sll $4, $4, 16 - addi $5, $zero, 0 # the control varible - addi $8, $zero, 1 # the signal -shiftl: # make the leftmost1 in the highest 锟饺把碉拷一锟斤拷1锟狡碉拷锟斤拷锟斤拷锟? - sll $4, $4, 1 - slti $10, $4, 0 # 0 > $4 then jump - bne $10, $zero, panduan - addi $5, $5, 1 - slti $10, $5, 16 - beq $10, $zero, shiftl - -######################### -panduan: - andi $6, $3, 0xfff8 - srl $7, $4, 31 - sll $4, $4, 1 # 锟斤拷锟斤拷堑貌锟斤拷锟斤拷锟斤拷锟? - srl $3, $3, 1 - bne $6, $7, outcase0 - addi $5, $5, 1 - slti $10, $5, 16 - beq $10, $zero, panduan #锟斤拷锟斤拷腔锟矫伙拷锟?16锟酵硷拷锟斤拷锟叫讹拷 -led16light: - addi $10, $zero, 1 - sw $10, 0x62($20) -outcase0: - j begin -############################################################ -# 锟芥储锟斤拷取锟斤拷锟斤拷锟街存储锟节ｏ拷3锟酵ｏ拷5锟斤拷 -case1: - lw $3, 0x70($20) - sw $3, 0x60($20) - lw $4, 0x72($20) - andi $4, $4, 0xfff8 - beq $4, $zero, case1 # 锟斤拷锟斤拷要锟斤拷锟斤拷锟斤拷取 -case1read2: - lw $5, 0x70($20) - sw $5, 0x60($20) - lw $4, 0x72($20) - srl $4, $4, 1 # SW17锟斤拷锟斤拷诙锟斤拷锟斤拷锟斤拷锟饺★拷锟斤拷 - andi $4, $4, 0xfff8 - beq $4, $zero, case1read2 - j begin - -case2: - and $6, $3, $5 - sw $5, 0x60($20) - j begin -case3: - or $6, $3, $5 - sw $5, 0x60($20) - j begin -case4: - xor $6, $3, $5 - sw $5, 0x60($20) - j begin -case5: - sllv $6, $3, $5 - sw $5, 0x60($20) - j begin -case6: - srlv $6, $3, $5 - sw $5, 0x60($20) - j begin -case7: - srav $6, $3, $5 - sw $5, 0x60($20) - j begin - -.include "../commons/std_io_minisys.impl.mips" -- Gitee From 8da34c93310d8d7d8acccc1b689702a88b4acdc8 Mon Sep 17 00:00:00 2001 From: zhang <2674793917@qq.com> Date: Thu, 26 May 2022 14:20:55 +0800 Subject: [PATCH 28/57] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=E6=95=B0=E7=A0=81?= =?UTF-8?q?=E7=AE=A1=EF=BC=8C=E6=9C=AC=E5=9C=B0=E8=BF=98=E6=B2=A1=E8=B7=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/mips_cpu/CPUTOP.v | 37 ++++--- main/verilog/mips_cpu/TOP_all.v | 9 +- .../mips_cpu/basic_modules/digital_tube.v | 104 ++++++++++++++++++ 3 files changed, 133 insertions(+), 17 deletions(-) create mode 100644 main/verilog/mips_cpu/basic_modules/digital_tube.v diff --git a/main/verilog/mips_cpu/CPUTOP.v b/main/verilog/mips_cpu/CPUTOP.v index ab503ca..4fbba5d 100644 --- a/main/verilog/mips_cpu/CPUTOP.v +++ b/main/verilog/mips_cpu/CPUTOP.v @@ -18,9 +18,11 @@ input[23:0] switch2N4, output[23:0] led2N4, // UART Programmer Pinouts // start Uart communicate at high level -input start_pg, // Active High， if +input start_pg, // Active High艁殴 if input rx,// receive data by UART -output tx // send data by UART +output tx, // send data by UART +output[7:0] Dig, //which tubs to light +output[7:0]Y //light what ); @@ -108,10 +110,10 @@ Ifetc32 Ifetc32_instance( wire [31:0]ALU_Result; wire MemorIOtoReg; wire[31:0]Sign_extend; - wire [31:0] r_wdata;//鍐欏埌register鐨勬暟鎹? + wire [31:0] r_wdata;//暮聠聶暮聢掳register莽職聞膰聲掳膰聧? decode32 decoder_instance( - .read_data_1(read_data_1),//decoder鐨勮緭鍑? - .read_data_2(read_data_2),//decoder鐨勮緭鍑?,杩欎釜杈撳嚭鏄粰memory鐨勮緭鍑? + .read_data_1(read_data_1),//decoder莽職聞膷啪聯暮聡? + .read_data_2(read_data_2),//decoder莽職聞膷啪聯暮聡?,膷偶聶盲赂艦膷啪聯暮聡艧膰聵呕莽钮聶memory莽職聞膷啪聯暮聡? .Instruction(Instruction_o_Ifetc32), .mem_data(r_wdata), .ALU_result(ALU_Result), @@ -152,8 +154,8 @@ Ifetc32 Ifetc32_instance( ); wire[31:0]write_data_fromMemoryIO; - wire[31:0] m_wdata; // 鍐欏埌memory鐨勬暟鎹? - assign m_wdata = write_data_fromMemoryIO;//杩欎釜涔熸槸ior_data + wire[31:0] m_wdata; // 暮聠聶暮聢掳memory莽職聞膰聲掳膰聧? + assign m_wdata = write_data_fromMemoryIO;//膷偶聶盲赂艦盲拧聼膰聵呕ior_data wire [31:0] ram_dat_o; wire [31:0] addr_out; dmemory32 dmemory32_instance( @@ -174,10 +176,10 @@ Ifetc32 Ifetc32_instance( wire [31:0] addr_in; - wire [15:0] ioread_data;//杩欎釜鏄粡杩囧鐞嗙殑16bit鏁版嵁 + wire [15:0] ioread_data;//膷偶聶盲赂艦膰聵呕莽钮聫膷偶聡暮陇聞莽聬聠莽職聞16bit膰聲掳膰聧沤 wire LEDCtrl; wire SwitchCtrl; - assign addr_in = ALU_Result; //杩欎竴娈靛崟绾繚鎸佸悕瀛楃浉鍚? + assign addr_in = ALU_Result; //膷偶聶盲赂聙膰沤木暮聧聲莽艧呕盲偶聺膰聦聛暮聬聧暮颅聴莽聸赂暮聬? MemOrIO MemOrIO_instance( .mRead(MemRead), // read memory, from Controller .mWrite(MemWrite), // write memory, from Controller @@ -189,7 +191,7 @@ Ifetc32 Ifetc32_instance( .io_rdata(ioread_data), // data read from IO,16 bits .r_wdata(r_wdata), // data to Decoder(register file) .r_rdata(read_data_2), // data read from Decoder(register file) - .write_data(write_data_fromMemoryIO), // data to memor y or I/O锛坢_wdata, io_wdata锛? + .write_data(write_data_fromMemoryIO), // data to memor y or I/O膹藕聢m_wdata, io_wdata膹藕? .LEDCtrl(LEDCtrl), // LED Chip Select .SwitchCtrl(SwitchCtrl) // Switch Chip Select ); @@ -210,7 +212,7 @@ Ifetc32 Ifetc32_instance( //means l-Type instruction except beq, bne, LW,sw .I_format(I_format), .Jr(Jr), - .Zero(Zero),//杩欎釜涔熸槸璁＄畻鏄惁闇?瑕佽烦杞? + .Zero(Zero),//膷偶聶盲赂艦盲拧聼膰聵呕膷沤膭莽沤聴膰聵呕暮聬艢茅聹?膷艢聛膷藝艂膷藵? .ALU_Result(ALU_Result), .Addr_Result(Addr_Result),//This means that upper right output .PC_plus_4(branch_base_addr)//pc+4 @@ -222,19 +224,26 @@ Ifetc32 Ifetc32_instance( .switchread(IORead), .switchctl(SwitchCtrl), .switchaddr(addr_in[1:0]), - .switchrdata(ioread_data), //杩欎釜鏄?15浣嶇殑 + .switchrdata(ioread_data), //膷偶聶盲赂艦膰聵?15盲藵聧莽職聞 .switch_input(switch2N4) ); LED led_instance( .led_clk(cpu_clk), .ledrst(rst), - .ledwrite(IOWrite),//浠巆ontroller鏉ョ殑 + .ledwrite(IOWrite),//盲钮聨controller膰聺慕莽職聞 .ledcs(LEDCtrl), .ledaddr(addr_in[1:0]), .ledwdata(write_data_fromMemoryIO[15:0]), .ledout(led2N4) ); - + Tubs tubs_instance( + .clock(fpga_clk), + .reset(fpga_rst), + .IOWrite(IOWrite), + .Dig(Dig), + .Y(Y), + .in_num(write_data_fromMemoryIO) + ); endmodule diff --git a/main/verilog/mips_cpu/TOP_all.v b/main/verilog/mips_cpu/TOP_all.v index f163109..87991ec 100644 --- a/main/verilog/mips_cpu/TOP_all.v +++ b/main/verilog/mips_cpu/TOP_all.v @@ -1,7 +1,7 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у -// Engineer: 寮犲姏瀹, 鍙剁挩閾 +// Engineer: 寮犲姏瀹?, 鍙剁挩閾? // // Create Date: 2022/05/07 12:58:45 // Module Name: CPU_TOP @@ -13,7 +13,8 @@ module TOP_all( input[23:0]Minisys_Switches, output[23:0]Minisys_Lights, input Minisys_Clock, input[4:0] Minisys_Button, -input Minisys_Uart_fromPC, output Minisys_Uart_toPC +input Minisys_Uart_fromPC, output Minisys_Uart_toPC, +output[7:0] Minisys_DigitalTubes_NotEnable,output[7:0]Minisys_DigitalTube_Shape ); CPUTOP top_instance( @@ -23,6 +24,8 @@ CPUTOP top_instance( .start_pg(Minisys_Button[4]), .fpga_rst(Minisys_Button[3]), .rx( Minisys_Uart_fromPC), -.tx( Minisys_Uart_toPC) +.tx( Minisys_Uart_toPC), +.Dig(Minisys_DigitalTubes_NotEnable), +.Y(Minisys_DigitalTube_Shape) ); endmodule diff --git a/main/verilog/mips_cpu/basic_modules/digital_tube.v b/main/verilog/mips_cpu/basic_modules/digital_tube.v new file mode 100644 index 0000000..cb6fb10 --- /dev/null +++ b/main/verilog/mips_cpu/basic_modules/digital_tube.v @@ -0,0 +1,104 @@ +`timescale 1ns / 1ps +module Tubs(clock, reset, IOWrite, Dig, Y, in_num); + input clock, reset, IOWrite; + output wire [7:0] Dig; + output wire [7:0] Y; + input [31:0] in_num; // The input from the top module. Just like the led. + + reg [7:0] Dig_r; // The rnverse of Digital selection. + reg [6:0] Y_r; // The reverse of Digital. + wire rst; + assign Dig = ~Dig_r; + assign Y = {{1'b1},{~Y_r}}; //this is notenable, + assign rst =~reset;//有效是1 + reg clk; + reg [31:0] clk_cnt; + reg [3:0] scanner_cnt; + initial begin + clk = 1'b0; + end + + parameter half_period = 40000;//这个是换一个clock + always @(posedge clock or negedge rst) begin + if (!rst) + clk_cnt <= 0; + else begin + clk_cnt <= clk_cnt + 1; + if (clk_cnt == (half_period >> 1) - 1) + clk <= 1'b1; + else if (clk_cnt == half_period - 1) begin + clk <= 1'b0; + clk_cnt <= 32'h00000000; + end + end + end + + always @(posedge clk or negedge rst) begin + if (!rst) begin + scanner_cnt <= 4'b0000; + end + else begin + scanner_cnt <= scanner_cnt + 1'b1; + if(scanner_cnt == 4'd9) begin + scanner_cnt <= 4'b0000; + end + end + end + //下面这2个描述就是和当年开发EGO1是一样的需要分时显示 + always @(scanner_cnt) begin + if(IOWrite) begin + case(scanner_cnt) + 4'b0001 : Dig_r <= 8'b0000_0001; + 4'b0010 : Dig_r <= 8'b0000_0010; + 4'b0011 : Dig_r <= 8'b0000_0100; + 4'b0100 : Dig_r <= 8'b0000_1000; + 4'b0101 : Dig_r <= 8'b0001_0000; + 4'b0110 : Dig_r <= 8'b0010_0000; + 4'b0111 : Dig_r <= 8'b0100_0000; + 4'b1000 : Dig_r <= 8'b1000_0000; + default :Dig_r <= 8'b0000_0000; + endcase + end + else begin + Dig_r <= 8'b0000_0000; //when IOWrite, I should write + end + end +reg [3:0] which_trans; + + always @(scanner_cnt) begin + case(scanner_cnt) + 4'b0001 : which_trans <= in_num[3:0]; + 4'b0010 : which_trans <= in_num[7:4]; + 4'b0011 : which_trans <= in_num[11:8]; + 4'b0100 :which_trans <= in_num[15:12]; + 4'b0101 : which_trans <= in_num[19:16]; + 4'b0110 : which_trans <= in_num[23:20]; + 4'b0111 : which_trans <= in_num[27:24]; + 4'b1000 : which_trans <= in_num[31:28]; + default :which_trans <= 8'b0000_0000; + endcase + end + + always @(which_trans) begin + case(which_trans)//higher bit is gfdcba,高位dp + 4'd0 : Y_r <=7'b0111111; + 4'd1 : Y_r <= 7'b0000110;//1 + 4'd2 : Y_r <= 7'b1011011; // 2 + 4'd3 : Y_r <= 7'b1001111; // 3 + 4'd4 : Y_r <= 7'b1100110; // 4 + 4'd5 : Y_r <= 7'b1101101; // 5 + 4'd6 : Y_r <= 7'b1111101; // 6 + 4'd7 : Y_r <= 7'b0100111; // 7 + 4'd8 : Y_r <= 7'b1111111; // 8 + 4'd9 : Y_r <= 7'b1100111; // 9 + 4'd10: Y_r <= 7'b1110111; // A + 4'd11: Y_r <= 7'b1111100; // B + 4'd12: Y_r <= 7'b0111001; // C + 4'd13:Y_r <= 7'b1011110; // D + 4'd14: Y_r <= 7'b1111001; // E + 4'd15: Y_r <= 7'b1110001; // F + default: Y_r <=7'b0000000; + endcase + end +endmodule + -- Gitee From cc75c3a7e222fbdb7a5c43a10fc0ab858f21c25e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 23:19:36 +0800 Subject: [PATCH 29/57] feat(structure): add gitignore --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 810f857..5a3a1d5 100644 --- a/.gitignore +++ b/.gitignore @@ -20,4 +20,5 @@ bin-release/ # ide specific vivado/ vivado_impl/ -.vscode/ \ No newline at end of file +.vscode/ +.idea/ \ No newline at end of file -- Gitee From d0abecc94846bf8f70a388c61a809ab350814899 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Thu, 26 May 2022 23:20:48 +0800 Subject: [PATCH 30/57] feat(mips): add mars test and sim test md; add getFloat test --- main/mips/test/test.md => test/mips/mars_test.md | 4 ++-- test/mips/test_getFloat.mips | 9 +++++++++ main/mips/test/testsort.mips => test/mips/test_sort.mips | 2 +- test/verilog/vivado_sim_test.md | 8 ++++++++ 4 files changed, 20 insertions(+), 3 deletions(-) rename main/mips/test/test.md => test/mips/mars_test.md (88%) create mode 100644 test/mips/test_getFloat.mips rename main/mips/test/testsort.mips => test/mips/test_sort.mips (90%) create mode 100644 test/verilog/vivado_sim_test.md diff --git a/main/mips/test/test.md b/test/mips/mars_test.md similarity index 88% rename from main/mips/test/test.md rename to test/mips/mars_test.md index 237c599..7b0b087 100644 --- a/main/mips/test/test.md +++ b/test/mips/mars_test.md @@ -1,6 +1,6 @@ -## mips/test 鏂囦欢澶 +## test/mips 鏂囦欢澶 -鏈枃浠跺す鏀剧疆mips姹囩紪鏂囦欢锛岃繖浜涙眹缂栨枃浠跺彲浠ュ湪MARS浠跨湡鐜涓嬭繍琛屻 +鏈枃浠跺す鏀剧疆mips姹囩紪鏂囦欢锛岃繖浜涙眹缂栨枃浠跺彲浠ュ湪**MARS浠跨湡鐜**涓嬭繍琛屻 浠庤岄獙璇乵ips姹囩紪绠楁硶銆佸嚱鏁扮殑姝ｇ‘鎬с ### 娴嬭瘯椤圭洰 diff --git a/test/mips/test_getFloat.mips b/test/mips/test_getFloat.mips new file mode 100644 index 0000000..808cd0a --- /dev/null +++ b/test/mips/test_getFloat.mips @@ -0,0 +1,9 @@ +.data +.text + li $a0 25 + jal getFloat + li $v0 1 + syscall + li $v0 10 + syscall +.include "../../main/mips/commons/std_algorithm.mips" diff --git a/main/mips/test/testsort.mips b/test/mips/test_sort.mips similarity index 90% rename from main/mips/test/testsort.mips rename to test/mips/test_sort.mips index e36e384..2e67491 100644 --- a/main/mips/test/testsort.mips +++ b/test/mips/test_sort.mips @@ -36,4 +36,4 @@ li $v0 10 syscall -.include "../commons/std_algorithm.mips" +.include "../../main/mips/commons/std_algorithm.mips" diff --git a/test/verilog/vivado_sim_test.md b/test/verilog/vivado_sim_test.md new file mode 100644 index 0000000..c7a6507 --- /dev/null +++ b/test/verilog/vivado_sim_test.md @@ -0,0 +1,8 @@ +## test/verilog 鏂囦欢澶 + +鏈枃浠跺す鏀剧疆 verilog 浠跨湡鏂囦欢锛岃繖浜涗豢鐪熸枃浠跺彲浠ュ湪**Vivado娉㈠舰浠跨湡鐜**涓嬭繍琛屻 +浠庤岄獙璇 verilog 纭欢璁捐鐨勬纭с + +### 娴嬭瘯椤圭洰 + +### 娴嬭瘯鐘舵 \ No newline at end of file -- Gitee From d5f92efdca050a13e6ffa961a05863023e192f65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 11:44:35 +0800 Subject: [PATCH 31/57] =?UTF-8?q?fix(mips):=20=E4=BF=AE=E5=A4=8D=E6=96=B0?= =?UTF-8?q?=E7=89=88=E5=9C=BA=E6=99=AF1=E7=AE=97=E6=9C=AF=E5=8F=B3?= =?UTF-8?q?=E7=A7=BB=E6=9C=89=E7=AC=A6=E5=8F=B7=E5=8C=96=E7=9A=84bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 1 + main/mips/cpu_test/new_situation1.mips | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index ef56585..0ede5d6 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -116,6 +116,7 @@ read: write_control_negate(2) move $a0 $s7 + andi $a0 $a0 0xFFFF # 闃叉淇″彿娉㈠姩瀵艰嚧宸﹁竟16浣嶄笉鏄0 load_ra() jr $ra diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index 51b199e..a52ec5e 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -79,8 +79,8 @@ case6: case7: lw $s0 0($fp) lw $s1 4($fp) - sll $s0 $s0 8 - sra $s0 $s0 8 # 鏈夌鍙峰寲 + sll $s0 $s0 16 + sra $s0 $s0 16 # 鏈夌鍙峰寲 srav $a0 $s0 $s1 jal write_data j begin -- Gitee From 9882c2d78deb8f4f3434549774eecdf9613d862e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 12:03:59 +0800 Subject: [PATCH 32/57] =?UTF-8?q?feat(mips):=20=E4=BF=AE=E6=94=B9=E4=B8=8A?= =?UTF-8?q?=E4=B8=80=E6=AC=A1commit=E7=9A=84=E6=97=A0=E7=AC=A6=E5=8F=B7?= =?UTF-8?q?=E8=AF=BB=E5=85=A5=E3=80=81=E7=AC=A6=E5=8F=B7=E8=BD=AC=E6=8D=A2?= =?UTF-8?q?=E6=8E=A5=E5=8F=A3=E3=80=82=20=E6=96=B0=E5=9C=BA=E6=99=AF1?= =?UTF-8?q?=E5=B7=B2=E7=BB=8F=E7=A8=B3=E5=AE=9A=E6=97=A0bug=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 1 - main/mips/commons/std_io_minisys.macro.mips | 23 +++++++++++++++++++++ main/mips/cpu_test/new_situation1.mips | 9 ++++---- 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index 0ede5d6..ef56585 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -116,7 +116,6 @@ read: write_control_negate(2) move $a0 $s7 - andi $a0 $a0 0xFFFF # 闃叉淇″彿娉㈠姩瀵艰嚧宸﹁竟16浣嶄笉鏄0 load_ra() jr $ra diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index f028afa..0e91de0 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -120,3 +120,26 @@ jal write_control_set # sleep(200) .end_macro + +.macro read_8_as_unsigned(%register) + jal read + andi $a0 $a0 0xFF + move %register $a0 +.end_macro + +.macro read_16_as_unsigned(%register) + jal read + andi $a0 $a0 0xFFFF # 闃叉淇″彿娉㈠姩瀵艰嚧宸﹁竟16浣嶄笉鏄0 + move %register $a0 +.end_macro + +# 杈撳叆register瀵勫瓨鍣紝 璁＄畻register瀵勫瓨鍣ㄤ綔涓8浣嶆湁绗﹀彿鏁扮殑绛変环32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 +.macro convert_8_as_signed(%register) + sll %register %register 24 + sra %register %register 24 +.end_macro +# 杈撳叆register瀵勫瓨鍣紝 璁＄畻register瀵勫瓨鍣ㄤ綔涓16浣嶆湁绗﹀彿鏁扮殑绛変环32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 +.macro convert_16_as_signed(%register) + sll %register %register 16 + sra %register %register 16 +.end_macro \ No newline at end of file diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index a52ec5e..9d12be1 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -25,7 +25,7 @@ begin: beq $a2 $s6 case6 beq $a2 $s7 case7 case0: - jal read + read_16_as_unsigned($a0) sw $a0 0($fp) sleep(200) jal write_data @@ -37,10 +37,10 @@ case0: sleep(1000) j begin case1: - jal read + read_16_as_unsigned($a0) sw $a0 0($fp) jal write_data - jal read + read_16_as_unsigned($a0) sw $a0 4($fp) jal write_data @@ -79,8 +79,7 @@ case6: case7: lw $s0 0($fp) lw $s1 4($fp) - sll $s0 $s0 16 - sra $s0 $s0 16 # 鏈夌鍙峰寲 + convert_16_as_signed($s0) srav $a0 $s0 $s1 jal write_data j begin -- Gitee From c7aa9144e1563140b9090c82806c7643469875a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 12:57:17 +0800 Subject: [PATCH 33/57] =?UTF-8?q?fix(mips):=20=E4=BF=AE=E5=A4=8Dexception?= =?UTF-8?q?=5Fhint=20=E5=8F=AA=E6=98=AF=E5=8D=95=E9=97=AA=E8=80=8C?= =?UTF-8?q?=E4=B8=8D=E6=98=AF=E5=8F=8C=E9=97=AA=E7=9A=84bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 1 + 1 file changed, 1 insertion(+) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index ef56585..4a6015f 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -171,6 +171,7 @@ write_data: exception_hint: save_ra() warn_data() + sleep(500) warn_data() load_ra() jr $ra -- Gitee From 1374ff81ff17a0805ee0946021001d8d3ea4264c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 12:58:30 +0800 Subject: [PATCH 34/57] =?UTF-8?q?fix(mips)=EF=BC=9A=E5=9C=BA=E6=99=AF2=20c?= =?UTF-8?q?ase0=20=E4=BF=AE=E5=A4=8D=E4=B8=8D=E8=83=BD=E6=8F=90=E7=A4=BA?= =?UTF-8?q?=E6=AD=A3=E5=9C=A8=E8=BE=93=E5=85=A5=E4=BB=80=E4=B9=88=E6=95=B0?= =?UTF-8?q?=E7=9A=84bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/situation2.mips | 51 ++++++++++++++++-------------- 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 5d62e73..583ba31 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -21,43 +21,42 @@ begin: beq $a2 $s5 case5 beq $a2 $s6 case6 beq $a2 $s7 case7 + +# case0 娴嬭瘯鐘舵侊細璇诲叆閫昏緫鍙俊銆 +# 缁撴灉淇濆瓨浣嶇疆 +# n = 44($fp)锛 array = $fp, $fp+4, $fp+8, ... case0: - jal read - move $s1 $a0 # s1=n锛岃〃绀烘暟缁勯暱搴 + read_8_as_unsigned($s1) # s1=n锛岃〃绀烘暟缁勯暱搴 sw $s1 44($fp) # 44($fp) 涓烘暟缁勯暱搴 bne $s1 $zero end_if_case0_0 jal exception_hint # 濡傛灉鏄0锛屽彧鏄鍛婏紝涓嶉噸鏂拌緭鍏ャ - end_if_case0_0: - li $t0 10 +end_if_case0_0: + li $t0 10 ble $s1 $t0 end_if_case0_1 - jal exception_hint # 濡傛灉姣10澶э紝鍙槸璀﹀憡锛屼笉閲嶆柊杈撳叆銆 - end_if_case0_1: + jal exception_hint # 濡傛灉姣10澶э紝鍙槸璀﹀憡锛屼笉閲嶆柊杈撳叆銆 +end_if_case0_1: + addi $s2 $fp 0 # 0鍊嶇殑s0锛 s2鐜板湪鏄暟鎹泦0鐨勫熀鍦板潃銆 for_case0: - ble $s1 $zero end_for_case0 + beq $s1 $zero end_for_case0 # 鐢╟ontrol鐨勫彸杈瑰洓涓伅鎻愮ず姝ｅ湪璇荤鍑犱釜鏁 - li $v0 0 - srl $v1 $s1 0 - jal write_control_set - li $v0 1 - srl $v1 $s1 1 - jal write_control_set - li $v0 2 - srl $v1 $s1 2 - jal write_control_set - li $v0 3 - srl $v1 $s1 3 - jal write_control_set + lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 + andi $t1 $t1 0xFFFFFFF0 # 灏嗘渶鍚4浣嶅己琛屾竻闄や负0 + andi $t9 $s1 0xFF # 涓囦竴杈撳叆鐨刵鏄紓甯告暟瀛楋紝涔熷彧鏄剧ず鏈鍚庡嚑浣 + or $t1 $t1 $t9 + sw $t1 4($k0) + flush_lights() sleep(100) - # 璇诲彇鏂扮殑鏁般 - jal read + # 璇诲彇鏂扮殑鏁般 + read_8_as_unsigned($a0) sw $a0 0($s2) # 瀛樺叆s2瀵瑰簲鐨勫唴瀛 addi $s1 $s1 -1 addi $s2 $s2 4 # 鎸囬拡鍙崇Щ j for_case0 end_for_case0: + warn_data() # 琛ㄧず杈撳叆缁撴潫銆 j begin case1: @@ -65,12 +64,16 @@ case1: lw $s1 44($fp) # 鏁扮粍瀹為檯闀垮害n sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 add $v1 $v0 $s1 # 鏁版嵁闆0灏 - add $a0 $v0 $s0 # 鏁版嵁闆1澶 - move $s2 $a0 # 鏁版嵁闆1澶 + + add $a0 $v0 $s0 # 鏁版嵁闆1澶 . 璁板緱鍚楋紵s0 涓嶈兘琚殢鎰忔敼锛宻0鏄44. + move $s2 $a0 # 鏁版嵁闆1澶. a0 鏄粰copy浼犲弬鏁拌岃缃紝s2鏄浣忔暟鎹泦1鐨勫ご鏂逛究鍚庣画鎿嶄綔銆 + jal copy + move $v0 $s2 # 鏁版嵁闆1澶 - add $v1 $v0 $s1 # 鏁版嵁闆1灏 + add $v1 $v0 $s1 # 鏁版嵁闆1灏俱 璁板緱鍚楋紵s1鏄暟缁勯暱搴︾殑鍥涘嶏紝涔熷氨鏄痵izeof鏁扮粍銆 jal insertion_sort + warn_data() # 琛ㄧず鎺掑簭缁撴潫銆 j begin case2: -- Gitee From 40a8858e50f323ea7d85510694aa938c682534bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 14:15:40 +0800 Subject: [PATCH 35/57] =?UTF-8?q?refrac(mips):=20=E5=88=86=E7=A6=BB?= =?UTF-8?q?=E7=AE=97=E6=B3=95=E5=87=BD=E6=95=B0=E4=B8=8E=E7=AE=97=E6=B3=95?= =?UTF-8?q?=E5=AE=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- ...algorithm.mips => std_algorithm.impl.mips} | 16 ++++++---- main/mips/commons/std_algorithm.macro.mips | 18 +++++++++++ main/mips/commons/std_io_minisys.impl.mips | 1 + main/mips/commons/std_io_minisys.macro.mips | 32 ++++++++++++------- main/mips/cpu_test/new_situation1.mips | 3 +- main/mips/cpu_test/situation2.mips | 12 ++++--- 6 files changed, 58 insertions(+), 24 deletions(-) rename main/mips/commons/{std_algorithm.mips => std_algorithm.impl.mips} (93%) create mode 100644 main/mips/commons/std_algorithm.macro.mips diff --git a/main/mips/commons/std_algorithm.mips b/main/mips/commons/std_algorithm.impl.mips similarity index 93% rename from main/mips/commons/std_algorithm.mips rename to main/mips/commons/std_algorithm.impl.mips index 5277d18..e0f73b1 100644 --- a/main/mips/commons/std_algorithm.mips +++ b/main/mips/commons/std_algorithm.impl.mips @@ -76,16 +76,20 @@ insertion_sort: # 姹侷EEE 754 鍗曠簿搴︽诞鐐规暟缂栫爜鐨勭鍙蜂綅鍜屾寚鏁颁綅 锛堜竴鍏1+8=9浣嶏級銆 # 杈撳叆 a0锛 杩斿洖a0 getFloat: + andi $a0 $a0 0xFF # 鍙叧蹇冩渶鍚8浣嶃 # 绗﹀彿浣 锛1浣嶏級 srl $t0 $a0 7 # 鍙栫7浣 andi $t0 $t0 1 - xori $t0 $t0 1 # 鍙栧弽銆 - sll $t0 $t0 8 # 鏀惧湪绗8浣嶃7..0鐣欑粰鎸囨暟浣 + sll $t1 $t0 8 # 鏀惧湪绗8浣嶃7..0鐣欑粰鎸囨暟浣 # 鎸囨暟浣 锛8浣嶏級 # 鍙栫粷瀵瑰 - xori $t1 $t2 0xFF - addi $t1 $t1 1 - andi $t1 $t1 0xFF + bne $t0 $zero else_getFloat + + else_getFloat: + + end_if_getFloat: + + # 鍙崇Щ澶氬皯娆″彉鎴0 - 1 li $t3 0 do_while_case6: @@ -94,4 +98,4 @@ getFloat: bne $t1 $zero do_while_case6 addi $t3 $t3 0x7f # 鍔犱笂bias or $a0 $t3 $t0 # 鍚堝苟涓や釜鏁 - jr $ra \ No newline at end of file + jr $ra diff --git a/main/mips/commons/std_algorithm.macro.mips b/main/mips/commons/std_algorithm.macro.mips new file mode 100644 index 0000000..35a758d --- /dev/null +++ b/main/mips/commons/std_algorithm.macro.mips @@ -0,0 +1,18 @@ +######################## 鏈夌鍙/鏃犵鍙 鏈夊叧澶勭悊瀹 ######################## +# 杈撳叆register瀵勫瓨鍣紝 璁＄畻register瀵勫瓨鍣ㄤ綔涓8浣嶆湁绗﹀彿鏁扮殑绛変环32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 +.macro convert_8_to_signed(%register) + sll %register %register 24 + sra %register %register 24 +.end_macro +# 杈撳叆register瀵勫瓨鍣紝 璁＄畻register瀵勫瓨鍣ㄤ綔涓16浣嶆湁绗﹀彿鏁扮殑绛変环32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 +.macro convert_16_to_signed(%register) + sll %register %register 16 + sra %register %register 16 +.end_macro +# 杈撳叆register瀵勫瓨鍣紝 璁＄畻 +# register瀵勫瓨鍣ㄤ綔涓8浣 7, 6....0 = 绗﹀彿, 缁濆鍊 +# 鐨勭瓑浠32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 +.macro convert_signedAbs8_to_signed() + +.end_macro + \ No newline at end of file diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index 4a6015f..0bf5c5a 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -144,6 +144,7 @@ write_control_set: jr $ra # 娴嬭瘯鐘舵侊細鍙俊 # 杈撳嚭鎺у埗鐏紙宸︾伅锛夛紝鏍规嵁v0鐨勫(7,6,5,4,3,2,1,0)鍐冲畾杈撳嚭淇敼宸﹁竟鐨勫摢涓伅锛涘璇ョ伅鐨勫煎彇鍙嶃 +# 淇敼鐨勫瘎瀛樺櫒: t1, t0, v1 write_control_negate: lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 li $t0 1 diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 0e91de0..35dab10 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -1,3 +1,5 @@ +######################## 鏍瑰熀 瀹忋 姝ら儴鍒嗗畯闈炲父閲嶈锛屽湪澶氬閮戒細浣跨敤銆######################## + # 璁〤PU 鐫＄湢msec姣銆 # 璋冪敤杩欎釜鍑芥暟鐨勫満鏅槸锛宻witch鎿嶄綔鏃朵俊鍙峰彲鑳戒笉绋冲畾锛屼細鍑虹幇鐭椂0,1浜ゆ浛锛屽鑷磋绠楅昏緫鏈夐棶棰樸 # note:vivado 浠跨湡鏃讹紝涓嶅惎鐢╯leep銆傚洜涓簐ivado妯℃嫙鏃舵病鏈変俊鍙蜂笉绋冲畾鐨勯棶棰樸 @@ -10,7 +12,7 @@ #娴嬭瘯鐘舵侊細鍙俊 # 浠庣紦瀛樺唴瀛樼殑鍊煎啓鍏ュ埌鐏腑銆傝繖鏄痯rivate鏂规硶锛屼笉瑕佽交鏄撹皟鐢ㄣ -# 浼氫慨鏀箃0鐨勫煎拰鐏殑鍊笺 +# 淇敼鐨勫瘎瀛樺櫒锛氫細淇敼t0鐨勫煎拰鐏殑鍊笺 .macro flush_lights() lw $t0 4($k0) sw $t0 0x62($gp) @@ -27,16 +29,25 @@ addi $sp $sp 4 #move $ra $k1 # 鍔ㄧ敤k1 .end_macro + +######################## 蹇烮O瀹忋 姝ら儴鍒嗗畯鏄负浜嗚鐏佸紑鍏崇殑IO鏇村姞渚挎嵎銆######################## + +# 灏 index 浣嶇疆鐨勫乏鐏缃负1 +# 淇敼鐨勫瘎瀛樺櫒锛歷1, t1, t0, t2. .macro write_control_set_true(%index) li $v0 %index li $v1 1 jal write_control_set .end_macro +# 灏 index 浣嶇疆鐨勫乏鐏缃负0 +# 淇敼鐨勫瘎瀛樺櫒锛歷1, t1, t0, t2. .macro write_control_set_false(%index) li $v0 %index li $v1 0 jal write_control_set .end_macro +# 灏 index 浣嶇疆鐨勫乏鐏姸鎬佸弽杞 +# 淇敼鐨勫瘎瀛樺櫒: t1, t0, v1 .macro write_control_negate(%index) li $v0 %index jal write_control_negate @@ -52,6 +63,9 @@ li $s7 7 .end_macro +# 闂竴闂乏鐏殑2銆3浣嶅拰鍙崇伅銆傞棯瀹屼箣鍚庢仮澶嶅師鏉ョ殑鐏牱銆 +# 淇敼t7, t8, a0, v1, t1, t0, t2 +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro warn_data() lw $t7 0($k0) lw $t8 4($k0) @@ -72,6 +86,7 @@ .end_macro +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro all_lights_on() li $a0 0xFF jal write_control @@ -79,6 +94,7 @@ jal write_data .end_macro +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro all_lights_off() li $a0 0 jal write_control @@ -90,6 +106,7 @@ # 浠庢爣鍑嗚緭鍏ヨ鍙栦竴涓暟锛岃〃绀烘暟鎹泦缂栧彿 # 灏嗘暟鎹泦鐨勫熀鍦板潃鏀惧埌s1 +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro getBase() jal read andi $a0 $a0 3 # 鍙彇鏈鍚庝袱浣嶃 @@ -103,6 +120,7 @@ .end_macro # 浠巃0 璇诲彇case缂栧彿锛屼功鍐欏埌鎺у埗鐏渶宸﹁竟涓変綅 +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro hint_case_number() andi $a0 $a0 0x7 # 鍙鏈鍚庝笁浣 li $v0 5 @@ -120,7 +138,7 @@ jal write_control_set # sleep(200) .end_macro - +######################## 鏈夌鍙/鏃犵鍙 鏈夊叧澶勭悊瀹 ######################## .macro read_8_as_unsigned(%register) jal read andi $a0 $a0 0xFF @@ -133,13 +151,3 @@ move %register $a0 .end_macro -# 杈撳叆register瀵勫瓨鍣紝 璁＄畻register瀵勫瓨鍣ㄤ綔涓8浣嶆湁绗﹀彿鏁扮殑绛変环32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 -.macro convert_8_as_signed(%register) - sll %register %register 24 - sra %register %register 24 -.end_macro -# 杈撳叆register瀵勫瓨鍣紝 璁＄畻register瀵勫瓨鍣ㄤ綔涓16浣嶆湁绗﹀彿鏁扮殑绛変环32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 -.macro convert_16_as_signed(%register) - sll %register %register 16 - sra %register %register 16 -.end_macro \ No newline at end of file diff --git a/main/mips/cpu_test/new_situation1.mips b/main/mips/cpu_test/new_situation1.mips index 9d12be1..ba16b26 100644 --- a/main/mips/cpu_test/new_situation1.mips +++ b/main/mips/cpu_test/new_situation1.mips @@ -1,4 +1,5 @@ .include "../commons/std_io_minisys.macro.mips" +.include "../commons/std_algorithm.macro.mips" .data .text .globl main @@ -79,7 +80,7 @@ case6: case7: lw $s0 0($fp) lw $s1 4($fp) - convert_16_as_signed($s0) + convert_16_to_signed($s0) srav $a0 $s0 $s1 jal write_data j begin diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 583ba31..5aa6cbb 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -1,4 +1,5 @@ .include "../commons/std_io_minisys.macro.mips" +.include "../commons/std_algorithm.macro.mips" .data .text .globl main @@ -39,20 +40,20 @@ end_if_case0_1: addi $s2 $fp 0 # 0鍊嶇殑s0锛 s2鐜板湪鏄暟鎹泦0鐨勫熀鍦板潃銆 + li $s7 0 # i 鍙橀噺. 鐢╯绯诲垪锛岄槻姝㈣皟鐢ㄥ嚱鏁板悗澶辨晥銆 for_case0: - beq $s1 $zero end_for_case0 + beq $t7 $s1 end_for_case0 # 鐢╟ontrol鐨勫彸杈瑰洓涓伅鎻愮ず姝ｅ湪璇荤鍑犱釜鏁 lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 andi $t1 $t1 0xFFFFFFF0 # 灏嗘渶鍚4浣嶅己琛屾竻闄や负0 - andi $t9 $s1 0xFF # 涓囦竴杈撳叆鐨刵鏄紓甯告暟瀛楋紝涔熷彧鏄剧ず鏈鍚庡嚑浣 - or $t1 $t1 $t9 + or $t1 $t1 $s7 sw $t1 4($k0) flush_lights() sleep(100) # 璇诲彇鏂扮殑鏁般 read_8_as_unsigned($a0) sw $a0 0($s2) # 瀛樺叆s2瀵瑰簲鐨勫唴瀛 - addi $s1 $s1 -1 + addi $s7 $s7 1 addi $s2 $s2 4 # 鎸囬拡鍙崇Щ j for_case0 end_for_case0: @@ -80,6 +81,7 @@ case2: move $v0 $fp # 鏁版嵁闆0澶 lw $s1 44($fp) sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 + add $v1 $v0 $s1 # 鏁版嵁闆0灏 add $a0 $v0 $s0 # 鏁版嵁闆1澶 add $a0 $a0 $s0 # 鏁版嵁闆2澶 @@ -160,4 +162,4 @@ case7: j begin .include "../commons/std_io_minisys.impl.mips" -.include "../commons/std_algorithm.mips" +.include "../commons/std_algorithm.impl.mips" -- Gitee From d2e9cda5cb6ab7057e8b8d508050fc8313618a92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 15:17:11 +0800 Subject: [PATCH 36/57] =?UTF-8?q?feat(mips)=EF=BC=9A=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E5=9C=BA=E6=99=AF2=20case2=20=E6=9C=89=E7=AC=A6=E5=8F=B7?= =?UTF-8?q?=E6=95=B0=20mars=E6=B5=8B=E8=AF=95=E9=80=9A=E8=BF=87=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_algorithm.impl.mips | 8 ++++-- main/mips/commons/std_algorithm.macro.mips | 17 ++++++++--- main/mips/commons/std_io_mars.macro.mips | 33 ++++++++++++++++++++++ test/mips/test_to_signed_array.mips | 33 ++++++++++++++++++++++ 4 files changed, 84 insertions(+), 7 deletions(-) create mode 100644 main/mips/commons/std_io_mars.macro.mips create mode 100644 test/mips/test_to_signed_array.mips diff --git a/main/mips/commons/std_algorithm.impl.mips b/main/mips/commons/std_algorithm.impl.mips index e0f73b1..a9c2375 100644 --- a/main/mips/commons/std_algorithm.impl.mips +++ b/main/mips/commons/std_algorithm.impl.mips @@ -3,15 +3,17 @@ to_signed_array: for_to_signed_array: bge $v0 $v1 end_for_to_signed_array# 纰板埌灏惧厓绱狅紝寰幆缁撴潫 - lw $t0 0($v0) - sll $t0 $t0 24 - sra $t0 $t0 24 + + lw $t0 0($v0) # t0鏄綋鍓嶅鐞嗙殑鏁 + convert_signedAbs8_to_signed($t0) sw $t0 0($a0) + addi $a0 $a0 4 addi $v0 $v0 4 j for_to_signed_array end_for_to_signed_array: jr $ra + # 灏嗘暟缁勬嫹璐濆埌鏂扮殑浣嶇疆 # v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛 a0 鐩爣鏁扮粍棣栧厓绱犲湴鍧; copy: diff --git a/main/mips/commons/std_algorithm.macro.mips b/main/mips/commons/std_algorithm.macro.mips index 35a758d..8792efe 100644 --- a/main/mips/commons/std_algorithm.macro.mips +++ b/main/mips/commons/std_algorithm.macro.mips @@ -11,8 +11,17 @@ .end_macro # 杈撳叆register瀵勫瓨鍣紝 璁＄畻 # register瀵勫瓨鍣ㄤ綔涓8浣 7, 6....0 = 绗﹀彿, 缁濆鍊 -# 鐨勭瓑浠32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒銆 -.macro convert_signedAbs8_to_signed() - +# 鐨勭瓑浠32浣嶆湁绗﹀彿鏁板苟瀛樺洖璇ュ瘎瀛樺櫒 +# 浼氫慨鏀箃0:2 瀵勫瓨鍣 +.macro convert_signedAbs8_to_signed(%register) + move $t2 %register # 涓轰簡闃叉鍘熸湰鐨勫瘎瀛樺櫒灏辨槸t0鎴栬卼1锛屾垜浠厛鐢╰2澶囦唤鍘熸湰瀵勫瓨鍣ㄧ殑鍊笺 + andi $t0 $t2 0x7F # 鍙栧嚭缁濆鍊兼斁鍦╰0 + andi $t1 $t2 0x80 # 鍙栧嚭绗﹀彿浣嶆斁鍦╰1 + srl $t1 $t1 7 # 寰楀埌 0鎴栬1. 0璇存槑鏄鏁帮紝1璇存槑鏄礋鏁般 + beq $t1 $zero end_if_convert_signedAbs8 # 濡傛灉鏄鏁帮紝閭ｄ箞涓嶉渶瑕佸鐞嗭紝鐩存帴杩斿洖t0 + # 濡傛灉鏄礋鏁, 鍋氫竴涓嬪鐞 + sub $t0 $zero $t0 + end_if_convert_signedAbs8: + move %register $t0 .end_macro - \ No newline at end of file + diff --git a/main/mips/commons/std_io_mars.macro.mips b/main/mips/commons/std_io_mars.macro.mips new file mode 100644 index 0000000..70eea59 --- /dev/null +++ b/main/mips/commons/std_io_mars.macro.mips @@ -0,0 +1,33 @@ +.macro echo (%str) + .data + pstr: .asciiz %str #pstr: .asciiz "\n" vs pstr: .asciiz \n (not ok) + .text + la $a0,pstr + li $v0,4 + syscall +.end_macro +.macro puts %str #涔熷彲浠ユ病鏈夋嫭鍙 + echo %str +.end_macro + +.macro exit + li $v0,10 + syscall +.end_macro + +# 浠呴檺mars浣跨敤. 鎵撳嵃鐨勬槸32浣嶆湁绗﹀彿鏁 鏁扮粍銆 +# v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧 +.macro print_array_mars + move $t0 $v0 + move $t1 $v1 + for_print_array_mars: + bge $t0 $t1 end_for_print_array_mars + lw $a0 0($t0) + li $v0 1 + syscall + echo " " + addi $t0 $t0 4 + j for_print_array_mars + end_for_print_array_mars: + echo "\n" +.end_macro diff --git a/test/mips/test_to_signed_array.mips b/test/mips/test_to_signed_array.mips new file mode 100644 index 0000000..98205dc --- /dev/null +++ b/test/mips/test_to_signed_array.mips @@ -0,0 +1,33 @@ +.include "../../main/mips/commons/std_io_mars.macro.mips" +.include "../../main/mips/commons/std_algorithm.macro.mips" +.data + array: .space 40 +.text + li $t0 0x80 # -0 + li $t1 0x81 # -1 + li $t2 0x82 # -2 + li $t3 0x02 # +2 + li $t4 0x01 # +1 + la $s0 array + sw $t4 0($s0) + sw $t2 4($s0) + sw $t3 8($s0) + sw $t1 12($s0) + sw $t0 16($s0) + + move $v0 $s0 + addi $v1 $v0 20 + move $a0 $v1 + jal to_signed_array + + move $v0 $s0 + addi $v1 $v0 20 + print_array_mars() + + move $v0 $s0 + addi $v0 $v0 20 + addi $v1 $v0 20 + print_array_mars() + exit() +.include "../../main/mips/commons/std_algorithm.impl.mips" + -- Gitee From 012d88ae7690f9e4694d67a1b1db7c329fdac630 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 15:23:33 +0800 Subject: [PATCH 37/57] =?UTF-8?q?feat(mips):=20=E7=AE=97=E6=B3=95=E5=BA=93?= =?UTF-8?q?=EF=BC=9A=E6=8E=92=E5=BA=8F=EF=BC=8C=E6=8B=B7=E8=B4=9D=EF=BC=8C?= =?UTF-8?q?=E6=9C=89=E7=AC=A6=E5=8F=B7=E5=8C=96=EF=BC=8C=E6=9C=89=E7=AC=A6?= =?UTF-8?q?=E5=8F=B7=E6=95=B0=E7=BB=84=E6=8E=92=E5=BA=8F=E7=AD=89=E6=B5=8B?= =?UTF-8?q?=E8=AF=95=E9=80=9A=E8=BF=87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- test/mips/test_sort.mips | 41 ++++++++++++++++++----------- test/mips/test_to_signed_array.mips | 11 ++++++++ 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/test/mips/test_sort.mips b/test/mips/test_sort.mips index 2e67491..cead88e 100644 --- a/test/mips/test_sort.mips +++ b/test/mips/test_sort.mips @@ -1,5 +1,7 @@ +.include "../../main/mips/commons/std_io_mars.macro.mips" +.include "../../main/mips/commons/std_algorithm.macro.mips" .data - array: .space 40 + array: .space 40 .text li $t0 0 li $t1 1 @@ -12,28 +14,35 @@ sw $t3 8($s0) sw $t1 12($s0) sw $t0 16($s0) + move $v0 $s0 addi $v1 $v0 20 move $a0 $v1 - # jal copy - jal to_signed_array - + jal copy + addi $v0 $s0 20 addi $v1 $v0 20 jal insertion_sort + + addi $v0 $s0 20 + addi $v1 $v0 20 + print_array_mars - addi $v0 $s0 20 - addi $v1 $v0 20 - jal max + echo "max value is: " + addi $v0 $s0 20 + addi $v1 $v0 20 + jal max li $v0 1 - syscall - addi $v0 $s0 20 - addi $v1 $v0 20 - jal min + syscall + + echo "\nmin value is: " + addi $v0 $s0 20 + addi $v1 $v0 20 + jal min li $v0 1 - syscall - - li $v0 10 - syscall + syscall + + + exit -.include "../../main/mips/commons/std_algorithm.mips" +.include "../../main/mips/commons/std_algorithm.impl.mips" diff --git a/test/mips/test_to_signed_array.mips b/test/mips/test_to_signed_array.mips index 98205dc..d28706d 100644 --- a/test/mips/test_to_signed_array.mips +++ b/test/mips/test_to_signed_array.mips @@ -28,6 +28,17 @@ addi $v0 $v0 20 addi $v1 $v0 20 print_array_mars() + + move $v0 $s0 + addi $v0 $v0 20 + addi $v1 $v0 20 + jal insertion_sort + + move $v0 $s0 + addi $v0 $v0 20 + addi $v1 $v0 20 + print_array_mars() + exit() .include "../../main/mips/commons/std_algorithm.impl.mips" -- Gitee From 37955f524d851830e499446473ce82da4fd46511 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 16:17:58 +0800 Subject: [PATCH 38/57] =?UTF-8?q?feat(mips):=20=E9=87=8D=E6=96=B0review=20?= =?UTF-8?q?=E5=9C=BA=E6=99=AF2=E4=BB=A3=E7=A0=81case4567?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_algorithm.impl.mips | 27 +--------- main/mips/commons/std_algorithm.macro.mips | 32 +++++++++++ main/mips/commons/std_io_minisys.impl.mips | 2 +- main/mips/commons/std_io_minisys.macro.mips | 26 +++++++-- main/mips/cpu_test/situation2.mips | 59 +++++++++++++-------- 5 files changed, 94 insertions(+), 52 deletions(-) diff --git a/main/mips/commons/std_algorithm.impl.mips b/main/mips/commons/std_algorithm.impl.mips index a9c2375..e936fcf 100644 --- a/main/mips/commons/std_algorithm.impl.mips +++ b/main/mips/commons/std_algorithm.impl.mips @@ -27,6 +27,7 @@ copy: end_for_copy: jr $ra # v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛涙眰鏁扮粍鐨勬渶澶у兼斁鍒癮0銆傞粯璁ゆ湁绗﹀彿姣旇緝锛屽8浣嶆棤绗﹀彿鐨勬瘮杈冧篃鏄湁鏁堢殑銆 +# 淇敼鐨勫瘎瀛樺櫒锛歷0锛宎0锛宼0 max: lw $a0 0($v0) for_max: @@ -39,6 +40,7 @@ max: end_for_max: jr $ra # v0 鏁扮粍棣栧厓绱犲湴鍧, v1 鏁扮粍灏惧厓绱犲湴鍧锛涙眰鏁扮粍鐨勬渶灏忓兼斁鍒癮0銆傞粯璁ゆ湁绗﹀彿姣旇緝锛屽8浣嶆棤绗﹀彿鐨勬瘮杈冧篃鏄湁鏁堢殑銆 +# 淇敼鐨勫瘎瀛樺櫒锛歷0锛宎0锛宼0 min: lw $a0 0($v0) for_min: @@ -75,29 +77,4 @@ insertion_sort: jr $ra -# 姹侷EEE 754 鍗曠簿搴︽诞鐐规暟缂栫爜鐨勭鍙蜂綅鍜屾寚鏁颁綅 锛堜竴鍏1+8=9浣嶏級銆 -# 杈撳叆 a0锛 杩斿洖a0 -getFloat: - andi $a0 $a0 0xFF # 鍙叧蹇冩渶鍚8浣嶃 - # 绗﹀彿浣 锛1浣嶏級 - srl $t0 $a0 7 # 鍙栫7浣 - andi $t0 $t0 1 - sll $t1 $t0 8 # 鏀惧湪绗8浣嶃7..0鐣欑粰鎸囨暟浣 - # 鎸囨暟浣 锛8浣嶏級 - # 鍙栫粷瀵瑰 - bne $t0 $zero else_getFloat - else_getFloat: - - end_if_getFloat: - - - # 鍙崇Щ澶氬皯娆″彉鎴0 - 1 - li $t3 0 - do_while_case6: - srl $t1 $t1 1 - addi $t3 $t3 1 - bne $t1 $zero do_while_case6 - addi $t3 $t3 0x7f # 鍔犱笂bias - or $a0 $t3 $t0 # 鍚堝苟涓や釜鏁 - jr $ra diff --git a/main/mips/commons/std_algorithm.macro.mips b/main/mips/commons/std_algorithm.macro.mips index 8792efe..5a2b28b 100644 --- a/main/mips/commons/std_algorithm.macro.mips +++ b/main/mips/commons/std_algorithm.macro.mips @@ -25,3 +25,35 @@ move %register $t0 .end_macro +# 姹侷EEE 754 鍗曠簿搴︽诞鐐规暟缂栫爜鐨勭鍙蜂綅鍜屾寚鏁颁綅 锛堜竴鍏1+8=9浣嶏級銆 +# 杈撳叆 register(8浣嶆湁绗﹀彿鏁存暟)锛 杩斿洖register +# 寤鸿鐨剅egister鏄$a0 +.macro convert_signed8_to_float(%register) + andi %register %register 0xFF # 鍙叧蹇冩渶鍚8浣嶃傝浆鎹负8浣嶆湁绗﹀彿鏁存暟浜嗐 + + # 绗﹀彿浣 锛1浣嶏級 + srl $t0 %register 7 # 鍙栫7浣嶃 + andi $t0 $t0 1 # 鐜板湪t0涓1琛ㄧず鏄礋鏁帮紝鍚﹀垯鏄鏁般 + sll $t1 $t0 8 # 鏀惧湪绗8浣嶏紝鐜板湪t1鏄粨鏋滅殑涓閮ㄥ垎銆7..0鐣欑粰鎸囨暟浣 + + # 鎸囨暟浣 锛8浣嶏級 + # 鍙栫粷瀵瑰 鍒癮0. + beq $t0 $zero end_if_getFloat # 濡傛灉鏄鏁板氨涓嶇敤绠′簡銆 a0灏辨槸绛旀銆 + # 濡傛灉鏄礋鏁般 + xori %register %register 0xFF # 涓嶆槸0x7F. 鎴戜滑鐜板湪鏄8浣嶆湁绗﹀彿鏁帮紝姹傜浉鍙嶆暟銆 + addi %register %register 1 + andi %register %register 0xFF # 娉ㄦ剰鍘绘帀婧㈠嚭鐨1. 鎴戜滑杩樻槸8浣嶆湁绗﹀彿鏁般 + end_if_getFloat: + + + # 缁濆鍊煎彸绉诲灏戞鍙樻垚0 灏辨槸 鎸囨暟浣嶇殑澶у皬銆 + li $t3 0 + do_while_case6: + srl %register %register 1 # a0鏄8浣嶆湁绗﹀彿姝ｆ暟銆 + addi $t3 $t3 1 + bne $t1 $zero do_while_case6 + addi $t3 $t3 0x7f # 鍔犱笂bias + andi $t3 $t3 0xFF #娉ㄦ剰鎴戜滑杩樻槸8浣嶆暟锛岀幇鍦ㄦ槸娴偣鏁扮殑鎸囨暟浣嶃 + + or %register $t3 $t1 # 鍚堝苟涓や釜鏁 +.end_macro \ No newline at end of file diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index 0bf5c5a..038ec27 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -72,7 +72,7 @@ decode: jr $ra #娴嬭瘯鐘舵侊細娴嬭瘯涓 # 鏍规嵁a1鐨別nter淇″彿鎺у埗锛岀瓑寰呰緭鍏ヤ竴涓暣鏁帮紙閫氳繃鍙冲紑鍏筹級锛岀粨鏋滀繚瀛樺埌a0銆 -# a1鍜宎0閮戒細鏀瑰彉銆 +# 淇敼鐨勫瘎瀛樺櫒: a1鍜宎0閮戒細鏀瑰彉銆 # note: a2 涓簉ead涔嬪墠绯荤粺鐨刢ase鐘舵侊紝濡傛灉绛夊緟璇诲彇鐨勮繃绋嬪彂鐜板彉鍖栵紝浼氳繑鍥炲埌begin銆 read: save_ra() diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index 35dab10..b88def0 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -105,15 +105,17 @@ # 浠庢爣鍑嗚緭鍏ヨ鍙栦竴涓暟锛岃〃绀烘暟鎹泦缂栧彿 -# 灏嗘暟鎹泦鐨勫熀鍦板潃鏀惧埌s1 +# 灏嗘暟鎹泦鐨勫熀鍦板潃鏀惧埌 %register (寤鸿鏄痵1) +# 淇敼鐨勫瘎瀛樺櫒锛歛0 a1 # ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 -.macro getBase() +.macro getBase(%register) jal read andi $a0 $a0 3 # 鍙彇鏈鍚庝袱浣嶃 - lw $s1 0($fp) #base +# todo 闈炴硶杈撳叆璀﹀憡銆 + lw %register 0($fp) #base for_case4: beq $a0 $zero end_for_case4 - add $s1 $s1 $s0 # s0 鍙锛屾案杩滄槸space + add %register %register $s0 # 璁板緱鍚楋紵s0 鍙锛屾案杩滄槸space=44 addi $a0 $a0 -1 j for_case4 end_for_case4: @@ -139,15 +141,31 @@ # sleep(200) .end_macro ######################## 鏈夌鍙/鏃犵鍙 鏈夊叧澶勭悊瀹 ######################## + +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro read_8_as_unsigned(%register) jal read andi $a0 $a0 0xFF move %register $a0 .end_macro +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 .macro read_16_as_unsigned(%register) jal read andi $a0 $a0 0xFFFF # 闃叉淇″彿娉㈠姩瀵艰嚧宸﹁竟16浣嶄笉鏄0 move %register $a0 .end_macro +# 鎶妑egister褰撳仛8浣嶆暣鏁拌緭鍑哄埌鍙崇伅銆 +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 +.macro write_data_8(%register) + andi $a0 %register 0xFF + jal write_data +.end_macro + +# 鎶妑egister褰撳仛16浣嶆暣鏁拌緭鍑哄埌鍙崇伅銆 +# ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 +.macro write_data_16(%register) + andi $a0 %register 0xFFFF + jal write_data +.end_macro \ No newline at end of file diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 5aa6cbb..a18c6e8 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -76,6 +76,7 @@ case1: jal insertion_sort warn_data() # 琛ㄧず鎺掑簭缁撴潫銆 + sleep(1000) j begin case2: move $v0 $fp # 鏁版嵁闆0澶 @@ -87,16 +88,19 @@ case2: add $a0 $a0 $s0 # 鏁版嵁闆2澶 jal to_signed_array warn_data() + sleep(1000) j begin case3: move $v0 $fp # 鏁版嵁闆0澶 add $v0 $v0 $s0 # 鏁版嵁闆1澶 add $v0 $v0 $s0 # 鏁版嵁闆2澶 + lw $s1 44($fp) sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 add $v1 $v0 $s1 # 鏁版嵁闆2灏 + add $a0 $v0 $s0 # 鏁版嵁闆3澶 - move $s2 $a0 + move $s2 $a0 # 鏁版嵁闆3澶 jal copy move $v0 $s2 # 鏁版嵁闆3澶 @@ -104,9 +108,10 @@ case3: jal insertion_sort warn_data() # 琛ㄧず鎺掑簭缁撴潫銆 + sleep(1000) j begin case4: - getBase() + getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご move $v0 $s1 lw $s2 44($fp) # n @@ -115,49 +120,59 @@ case4: move $v1 $s2 jal max move $s3 $a0 # s3 鏄渶澶у - move $v0 $s1 - move $v1 $s2 + move $v0 $s1 # 鏁版嵁闆嗗ご + move $v1 $s2 # 鏁版嵁闆嗗熬 jal min move $s4 $a0 # s4 鏄渶灏忓 sub $a0 $s3 $s4 - jal write_data + write_data_8($a0) + sleep(1000) j begin case5: - getBase() + getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご - jal read + read_8_as_unsigned($a0) + # todo: 濡傛灉瓒呭嚭鑼冨洿锛屽彂鍑鸿鍛娿 sll $a0 $a0 2 # 涓嬫爣*4 add $s1 $s1 $a0 # 鐩爣鍦板潃 lw $a0 0($s1) # 鐩爣鏁 - jal write_data + write_data_8($a0) + sleep(1000) j begin case6: - getBase() + getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご - jal read + read_8_as_unsigned($a0) sll $a0 $a0 2 # 涓嬫爣*4 add $s1 $s1 $a0 # 鐩爣鍦板潃 lw $t2 0($s1) # 鐩爣鏁 andi $a0 $t2 0xFF # 鍙冭檻8浣 - jal getFloat - jal write_data + convert_signed8_to_float($a0) + jal write_data # 娉ㄦ剰锛屼笉姝8浣, 鐢ㄥ師鐢熺殑jal write_data銆 + sleep(1000) j begin case7: move $s1 $fp # 鏁版嵁闆0 澶 - jal read + read_8_as_unsigned($a0) sll $a0 $a0 2 # 涓嬫爣*4 add $s1 $s1 $a0 # 鐩爣鍦板潃 - lw $t2 0($s1) # 鐩爣鏁 + lw $s2 0($s1) # 鐩爣鏁. 涓嶈鐢╰绯诲垪锛屼笅闈㈣皟鐢ㄦ柟娉曚細鏀箃绯诲垪瀵勫瓨鍣ㄣ - move $a0 $t2 - jal write_data - sleep(5000) - - move $a0 $t2 - jal getFloat - jal write_data - sleep(5000) + while_case7: # 寰幆浜ゆ浛鏄剧ず + move $a0 $s2 + jal write_data + sleep(5000) + + move $a0 $s2 + convert_signed8_to_float($a0) + jal write_data + sleep(5000) + + jal decode + bne $a0 $a2 begin # 濡傛灉case缂栧彿鍙樺寲锛屽洖鍒癰egin + j while_case7 + end_while_case7: j begin j begin -- Gitee From 3c0fdda1031a2520e8d3bcbe7f04ca35c34c0af7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 17:08:11 +0800 Subject: [PATCH 39/57] =?UTF-8?q?fix(mips):=20=E4=BF=AE=E5=A4=8D=E4=BA=86s?= =?UTF-8?q?7=E5=86=B2=E7=AA=81=E7=9A=84bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_io_minisys.impl.mips | 6 +++--- main/mips/commons/std_io_minisys.macro.mips | 21 ++++++++++++++++----- 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/main/mips/commons/std_io_minisys.impl.mips b/main/mips/commons/std_io_minisys.impl.mips index 038ec27..83b9fe3 100644 --- a/main/mips/commons/std_io_minisys.impl.mips +++ b/main/mips/commons/std_io_minisys.impl.mips @@ -102,10 +102,10 @@ read: save_ra() lw $a0 0x70($gp) - move $s7 $a0 jal write_data beq $a1 $zero _read_wait_for_enter # 绛夊埌enter鏄1銆 - + + save_before_call($a0) li $a0 0 jal write_data # 娓呯┖杈撳叆 write_control_set_false(4) @@ -115,7 +115,7 @@ read: write_control_negate(3) write_control_negate(2) - move $a0 $s7 + load_before_return($a0) load_ra() jr $ra diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index b88def0..aa63df2 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -19,17 +19,27 @@ lw $t0 0($k0) sw $t0 0x60($gp) .end_macro -.macro save_ra() + +#璀﹀憡锛氳鍕挎妸杩欎釜鏀惧埌寰幆褰撲腑銆 +.macro save_before_call(%register) addi $sp $sp -4 - sw $ra 0($sp) + sw %register 0($sp) #move $k1 $ra .end_macro -.macro load_ra() - lw $ra 0($sp) +#璀﹀憡锛氳鍕挎妸杩欎釜鏀惧埌寰幆褰撲腑銆 +.macro load_before_return(%register) + lw %register 0($sp) addi $sp $sp 4 #move $ra $k1 # 鍔ㄧ敤k1 .end_macro +.macro save_ra() + save_before_call($ra) +.end_macro +.macro load_ra() + load_before_return($ra) +.end_macro + ######################## 蹇烮O瀹忋 姝ら儴鍒嗗畯鏄负浜嗚鐏佸紑鍏崇殑IO鏇村姞渚挎嵎銆######################## # 灏 index 浣嶇疆鐨勫乏鐏缃负1 @@ -123,6 +133,7 @@ # 浠巃0 璇诲彇case缂栧彿锛屼功鍐欏埌鎺у埗鐏渶宸﹁竟涓変綅 # ra淇濆瓨绛栫暐锛氭湰瀹忓唴璋冪敤浜嗗嚱鏁帮紝鑻ユ偍涓哄嚱鏁帮紝璇峰Ε鍠勪繚瀛樿嚜宸辩殑ra銆 +# 淇敼鐨勫瘎瀛樺櫒锛歛0 v0 v1 v1锛 t1, t0, t2. .macro hint_case_number() andi $a0 $a0 0x7 # 鍙鏈鍚庝笁浣 li $v0 5 @@ -168,4 +179,4 @@ .macro write_data_16(%register) andi $a0 %register 0xFFFF jal write_data -.end_macro \ No newline at end of file +.end_macro -- Gitee From 261c675ac125ff9fdae923fa4e3bb81274bcde6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Fri, 27 May 2022 17:08:54 +0800 Subject: [PATCH 40/57] =?UTF-8?q?fix(mips):=20=E4=BF=AE=E5=A4=8D=E4=BA=86?= =?UTF-8?q?=E5=9C=BA=E6=99=AF2=E7=9A=84=E8=AF=BB=E5=85=A5=E8=AE=A1?= =?UTF-8?q?=E6=95=B0=EF=BC=8C=E7=8E=B0=E5=9C=A8case0=E4=BF=9D=E8=AF=81?= =?UTF-8?q?=E6=B2=A1=E9=97=AE=E9=A2=98=E8=83=BD=E5=A4=9F=E8=AF=BB=E5=85=A5?= =?UTF-8?q?=E4=BA=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/cpu_test/situation2.mips | 32 +++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index a18c6e8..3430344 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -32,17 +32,17 @@ case0: bne $s1 $zero end_if_case0_0 jal exception_hint # 濡傛灉鏄0锛屽彧鏄鍛婏紝涓嶉噸鏂拌緭鍏ャ -end_if_case0_0: + end_if_case0_0: li $t0 10 ble $s1 $t0 end_if_case0_1 jal exception_hint # 濡傛灉姣10澶э紝鍙槸璀﹀憡锛屼笉閲嶆柊杈撳叆銆 -end_if_case0_1: + end_if_case0_1: addi $s2 $fp 0 # 0鍊嶇殑s0锛 s2鐜板湪鏄暟鎹泦0鐨勫熀鍦板潃銆 li $s7 0 # i 鍙橀噺. 鐢╯绯诲垪锛岄槻姝㈣皟鐢ㄥ嚱鏁板悗澶辨晥銆 for_case0: - beq $t7 $s1 end_for_case0 + beq $s7 $s1 end_for_case0 # 鐢╟ontrol鐨勫彸杈瑰洓涓伅鎻愮ず姝ｅ湪璇荤鍑犱釜鏁 lw $t1 4($k0) # t1涓哄乏鐏殑鍊笺 andi $t1 $t1 0xFFFFFFF0 # 灏嗘渶鍚4浣嶅己琛屾竻闄や负0 @@ -110,6 +110,8 @@ case3: warn_data() # 琛ㄧず鎺掑簭缁撴潫銆 sleep(1000) j begin + +# 娴嬭瘯鐘舵侊細鍗遍櫓 case4: getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご @@ -120,14 +122,18 @@ case4: move $v1 $s2 jal max move $s3 $a0 # s3 鏄渶澶у + move $v0 $s1 # 鏁版嵁闆嗗ご move $v1 $s2 # 鏁版嵁闆嗗熬 jal min move $s4 $a0 # s4 鏄渶灏忓 + sub $a0 $s3 $s4 write_data_8($a0) sleep(1000) j begin + +# 娴嬭瘯鐘舵侊細 瀵规暟鎹泦0鐨勬暟涔熶笉鍙互姝ｇ‘璇诲彇銆 case5: getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご @@ -135,23 +141,28 @@ case5: # todo: 濡傛灉瓒呭嚭鑼冨洿锛屽彂鍑鸿鍛娿 sll $a0 $a0 2 # 涓嬫爣*4 add $s1 $s1 $a0 # 鐩爣鍦板潃 - lw $a0 0($s1) # 鐩爣鏁 - write_data_8($a0) + lw $s2 0($s1) # 鐩爣鏁. 涓嶈鐢╰绯诲垪锛屼笅闈㈣皟鐢ㄦ柟娉曚細鏀箃绯诲垪瀵勫瓨鍣ㄣ + + write_data_8($s2) sleep(1000) j begin + +# 娴嬭瘯鐘舵侊細 瀵规暟鎹泦0鐨勬暟鍙互姝ｇ‘璇诲彇锛屽彲浠ュ啓鍑烘诞鐐规暟. case6: getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご read_8_as_unsigned($a0) sll $a0 $a0 2 # 涓嬫爣*4 add $s1 $s1 $a0 # 鐩爣鍦板潃 - lw $t2 0($s1) # 鐩爣鏁 + lw $s2 0($s1) # 鐩爣鏁 - andi $a0 $t2 0xFF # 鍙冭檻8浣 + andi $a0 $s2 0xFF # 鍙冭檻8浣 convert_signed8_to_float($a0) jal write_data # 娉ㄦ剰锛屼笉姝8浣, 鐢ㄥ師鐢熺殑jal write_data銆 sleep(1000) j begin + +# 娴嬭瘯鐘舵侊細 瀵规暟鎹泦0鐨勬暟鍙互姝ｇ‘璇诲彇锛屽彲浠ュ啓鍑烘诞鐐规暟鍜屽師鏁般 case7: move $s1 $fp # 鏁版嵁闆0 澶 read_8_as_unsigned($a0) @@ -162,12 +173,15 @@ case7: while_case7: # 寰幆浜ゆ浛鏄剧ず move $a0 $s2 jal write_data - sleep(5000) + sleep(1250) + + jal decode + bne $a0 $a2 begin # 濡傛灉case缂栧彿鍙樺寲锛屽洖鍒癰egin move $a0 $s2 convert_signed8_to_float($a0) jal write_data - sleep(5000) + sleep(1250) jal decode bne $a0 $a2 begin # 濡傛灉case缂栧彿鍙樺寲锛屽洖鍒癰egin -- Gitee From 91fb37cd5f170218dea1182977c2bba8220281f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 13:36:02 +0800 Subject: [PATCH 41/57] =?UTF-8?q?doc(verilog):=20=E5=BC=80=E5=8F=91Verilog?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E7=BC=96=E5=86=99=E8=A7=84=E8=8C=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- dev-doc/style/Verilog Style.md | 82 ++++++++++++++++++ ...1\346\214\207\345\257\274\344\271\246.pdf" | Bin .../style/ref/\345\243\260\346\230\216.md" | 4 + 3 files changed, 86 insertions(+) rename "dev-doc/style/\345\215\216\344\270\272_\345\244\247\350\247\204\346\250\241\351\200\273\350\276\221\350\256\276\350\256\241\346\214\207\345\257\274\344\271\246.pdf" => "dev-doc/style/ref/\345\215\216\344\270\272_\345\244\247\350\247\204\346\250\241\351\200\273\350\276\221\350\256\276\350\256\241\346\214\207\345\257\274\344\271\246.pdf" (100%) create mode 100644 "dev-doc/style/ref/\345\243\260\346\230\216.md" diff --git a/dev-doc/style/Verilog Style.md b/dev-doc/style/Verilog Style.md index e69de29..be64907 100644 --- a/dev-doc/style/Verilog Style.md +++ b/dev-doc/style/Verilog Style.md @@ -0,0 +1,82 @@ +# 鍗楃鍥炬櫤 Verilog FPGA 浠ｇ爜缂栧啓瑙勮寖 +鍙剁挩閾紝 12011404@mail.sustech.edu.cn +[TOC] +## 0. 鍓嶈█ +## 1. 鍩烘湰绾﹀畾 +### 1.1 鏂囦欢缂栫爜 + +- 鏂囦欢缂栫爜锛氬浜庡浗浜轰负涓昏寮鍙戣呯殑椤圭洰锛屼娇鐢℅BK缂栫爜锛岀悊鐢卞涓 + - Vivado鏂逛究鎬э細 + - VsCode鏂逛究鎬э細 + - 缂栫爜澶у皬锛欸BK +- 濡備綍姝ｇ‘浣跨敤GBK缂栫爜锛 + - 瀹為檯寮鍙戜腑锛屽父甯稿嚭鐜版帹閫佸埌git鍒嗘敮鍚庢枃浠剁紪鐮佷贡鐮侊紝鍦ㄥ叾浠栦汉鐢佃剳鏃犳硶鏄剧ず鐨勯棶棰樸 + - + +### 1.2 鏂囦欢澶逛笌鏂囦欢澶圭粨鏋 + + +### 1.3 + +## 2. Verilog 缂栫▼瑙勮寖 + +### 2.1 鏂囦欢 +- 鏂囦欢澶存敞閲 + - 绂佹浣跨敤vivado鑷甫娉ㄩ噴銆 + - 浣跨敤鐭屾湁鏁堢殑娉ㄩ噴銆 + - +- 鏂囦欢鐨勬蹇 + - 鏄ā鍧楃殑闆嗗悎锛屼竴涓枃浠跺寘鎷涓ā鍧椼 + - 绾﹀畾锛 + - 鏂囦欢瀵瑰鏆撮湶涓涓叕鍏辨ā鍧楋紝璇ユā鍧楀彲浠ヨ鍏朵粬鏂囦欢鐨勬ā鍧椾緥鍖栥 + - 鏂囦欢鍐呭叾浠栨ā鍧椾粎鑳藉湪鏂囦欢鍐呰繘琛屼緥鍖栥 + - 鐞嗙敱锛氬熼壌Java缂栫▼瑙勮寖銆傝繖鏍疯兘澶熷疄鐜伴珮鍐呰仛锛堢鏈夋ā鍧楀彧鍦ㄦ枃浠跺唴鍙銆佷簰鐩歌皟鐢級浣庤﹀悎锛堟枃浠朵箣闂寸殑鍏崇郴鏈澶氭秹鍙婁竴涓ā鍧楋級銆 + +- 鏂囦欢鍚 + - 绾﹀畾锛氭枃浠跺悕搴旇涓庡叕鍏辨ā鍧楀悕涓鑷淬 + - 鐞嗙敱锛氬熼壌Java缂栫▼瑙勮寖銆傝繖鏍疯兘澶熻鐪嬪埌鏂囦欢鐨勪汉涓鐩簡鐒躲 +### 2.2 妯″潡姒傝堪 + +- 妯″潡鐨勬蹇点 + - 妯″潡鏄杈撳叆淇″彿杩涜缁勭粐銆佽繛鎺ワ紝涓嶆柇鎻愪緵杈撳嚭淇″彿鐨勭數璺娊璞″眰娆° + - 妯″潡绫讳技浜庝竴涓被锛屽彲浠ヨ瀹炰緥鍖栥 + - 鏈夋垚鍛樺彉閲忥紝骞朵笖鍙互鍒嗕负杈撳叆鍜岃緭鍑轰袱绉嶅彉閲忥紝瀵瑰簲鍙啓/鍙鎴愬憳鍙橀噺銆 + - 鎴愬憳鍑芥暟/鏂规硶閫氳繃浣胯兘淇″彿鏉ュ疄鐜般 +- 妯″潡鍚 + - 澶у啓椹煎嘲 + - 鐞嗙敱锛氬搴擩ava绫汇 +- 杈撳叆杈撳嚭椋庢牸 + - 鍛藉悕锛歩/o+澶у啓椹煎嘲 + - 渚嬪瓙锛 + - 鐞嗙敱锛氬搴旂被鐨勫彧鍐/鍙鎴愬憳鍙橀噺 + - 渚嬪锛岀鑴氱害鏉熷彉閲忎娇鐢 **澶у啓涓嬪垝绾**鍒嗗壊澶у崟璇嶏紝**澶у啓椹煎嘲**鍒嗗壊灏忓崟璇嶃 +- 灞閮ㄥ彉閲 + - 涓轰簡杩涜杩炵嚎锛屽眬閮ㄥ線寰浜х敓wire绫诲瀷鐨勪腑闂村彉閲忋 + + - 绾﹀畾锛氫娇鐢**灏忓啓椹煎嘲** + - 绫讳技浜庤蒋浠剁紪绋嬭瑷鐨勫嚱鏁板唴灞閮ㄥ彉閲忋 + - 鍙互璁や负鎴戜滑瀵筕erilog妯″潡缂栧啓鐨勬墍鏈変唬鐮侊紝閮芥槸鍦ㄥ绫昏繘琛屾瀯閫犮傛垜浠湪涓涓瀯閫犲嚱鏁颁腑銆 +- 鏁版嵁鍙橀噺 + - 涓轰簡杩涜鏁版嵁銆佺姸鎬佺殑淇濆瓨锛屽線寰灞閮ㄤ娇鐢╮eg绫诲瀷 + - - 绾﹀畾锛氫娇鐢**d+澶у啓椹煎嘲**锛宒琛ㄧずdata(鏁版嵁)銆 +- 妯″潡渚嬪寲 + - 渚嬪寲鐩稿綋浜庢槸闈㈠悜瀵硅薄鐨勭粍鍚堬紝鎻忚堪浜嗕竴绉嶇粦瀹氬叧绯汇 + - 渚嬪寲鐨勫悓鏃讹紝瀛愭ā鍧椾細鏈夎嚜宸辩殑鏁版嵁鐘舵侊紝鍥犳渚嬪寲鍙互瑙嗕綔渚嬪寲鑰呰嚜韬氳繃渚嬪寲琚緥鍖栫殑妯″潡鑾峰緱浜嗘暟鎹彉閲忋 + - 鍥犳渚嬪寲涔熸槸鐢**d+澶у啓椹煎嘲**鐨勬牸寮忋 +### 2.3 妯″潡渚嬪寲 +- 妯″潡渚嬪寲鍦╒erilog涓湁涓ょ椋庢牸锛 + - 绫讳技C璇█缁撴瀯浣撶殑.缁戝畾 + - 绫讳技鍑芥暟璋冪敤鐨勯『搴忕粦瀹氥 +- 绾﹀畾锛氱姝娇鐢ㄩ『搴忕粦瀹 +- 鐞嗙敱锛 + - 鍩烘湰鍘熷垯锛氶噸鏋勫湪杞欢寮鍙戜腑闈炲父閲嶈銆傛垜浠富瑕佽冭檻閲嶆瀯鐨勬柟渚挎с + + + +### 2.4 妯″潡杈撳叆杈撳嚭 +- 妯″潡杈撳叆杈撳嚭鍦╒erilog涓湁涓ょ椋庢牸锛 + - +## 鍙傝冩枃鐚 +[^1]: 鍗庝负澶ц妯￠昏緫璁捐鎸囧涔.pdf + +[^2]: https://verilogcodingstyle.readthedocs.io/en/latest/source/1BasicSyntax_cn.html \ No newline at end of file diff --git "a/dev-doc/style/\345\215\216\344\270\272_\345\244\247\350\247\204\346\250\241\351\200\273\350\276\221\350\256\276\350\256\241\346\214\207\345\257\274\344\271\246.pdf" "b/dev-doc/style/ref/\345\215\216\344\270\272_\345\244\247\350\247\204\346\250\241\351\200\273\350\276\221\350\256\276\350\256\241\346\214\207\345\257\274\344\271\246.pdf" similarity index 100% rename from "dev-doc/style/\345\215\216\344\270\272_\345\244\247\350\247\204\346\250\241\351\200\273\350\276\221\350\256\276\350\256\241\346\214\207\345\257\274\344\271\246.pdf" rename to "dev-doc/style/ref/\345\215\216\344\270\272_\345\244\247\350\247\204\346\250\241\351\200\273\350\276\221\350\256\276\350\256\241\346\214\207\345\257\274\344\271\246.pdf" diff --git "a/dev-doc/style/ref/\345\243\260\346\230\216.md" "b/dev-doc/style/ref/\345\243\260\346\230\216.md" new file mode 100644 index 0000000..cfd8944 --- /dev/null +++ "b/dev-doc/style/ref/\345\243\260\346\230\216.md" @@ -0,0 +1,4 @@ +## 鍙傝冭祫鏂欑増鏉冨０鏄 + +鏈湰鏂囦欢澶逛笅鐨勬墍鏈塸df鍧囨潵鑷綉缁滐紝浠呬负瀛︿範浜ゆ祦浣跨敤锛屽凡琛ㄦ槑鍘熶綔鑰呫 +杩欎簺鏂囦欢涓嶅睘浜庢湰寮婧愰」鐩殑鏈ㄥ叞璁稿彲璇佸紑婧愯寖鍥达紝鑻ユ偍鍙戠幇渚电姱浜嗘偍鐨勭増鏉冿紝璇峰強鏃舵彁issue鑱旂郴銆 -- Gitee From 0805776a9c8ff761945e2603f53291eabc440d53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 14:55:06 +0800 Subject: [PATCH 42/57] =?UTF-8?q?doc(verilog):=20=E4=BB=A3=E7=A0=81?= =?UTF-8?q?=E8=A7=84=E8=8C=83=E6=9B=B4=E6=96=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- dev-doc/style/Verilog Style.md | 133 +++++++++++++++++++++++---------- 1 file changed, 95 insertions(+), 38 deletions(-) diff --git a/dev-doc/style/Verilog Style.md b/dev-doc/style/Verilog Style.md index be64907..29b6c96 100644 --- a/dev-doc/style/Verilog Style.md +++ b/dev-doc/style/Verilog Style.md @@ -1,11 +1,36 @@ -# 鍗楃鍥炬櫤 Verilog FPGA 浠ｇ爜缂栧啓瑙勮寖 +# 鍗楃鍥炬櫤 绠鏄揤erilog FPGA 浠ｇ爜缂栧啓瑙勮寖 鍙剁挩閾紝 12011404@mail.sustech.edu.cn [TOC] ## 0. 鍓嶈█ + +### 0.0 浠涔堟槸浠ｇ爜瑙勮寖锛熶负浠涔堣鏈塚erilog浠ｇ爜瑙勮寖锛 + +浠ｇ爜瑙勮寖鏄寚瀵逛唬鐮佺殑鍛藉悕涔犳儻銆佺紪鍐欓鏍硷紝浠ｇ爜鏂囦欢鐨勫偍瀛樻柟寮忋佺粍缁囨柟寮忕殑鎸囧鎬ц瀹氥 + +濂界殑浠ｇ爜瑙勮寖鍙互閬垮厤涓嶅繀瑕佺殑閲嶅鍔冲姩锛屼粠鑰屾彁楂樿璁℃晥鐜嘯^3]銆傝壇濂界殑浠ｇ爜瑙勮寖瀵筕erilog寮鍙戣璁＄殑甯姪涓昏浣撶幇鍦ㄤ竴涓嬪嚑涓柟闈細 + +- 閬靛惊瑙勮寖缂栧啓鐨勪唬鐮侊紝鍙鎬ц緝楂 + - 杩欐牱涓嶄粎鎻愰珮浜嗙‖浠朵唬鐮佽璁′汉鍛樼殑宸ヤ綔鏁堢巼锛屼篃甯姪鍦ㄨ皟璇曞鏉傜郴缁熸椂鍙戠幇鍜屽垎鏋愪粬浜轰唬鐮佸拰鑷繁缂栧啓浠ｇ爜瀛樺湪鐨勯棶棰樸俒^3] +- 閬靛惊瑙勮寖缂栧啓鐨勪唬鐮侊紝鍙墿灞曟ц緝濂 + - 涓ユ牸閬靛畧缁熶竴瑙勮寖缂栧啓鐨勭‖浠朵唬鐮侊紝瀹规槗淇敼[^3] + - 鍙互鏄捐憲鎻愰珮寮鍙戝洟闃熸暣浣撶殑璁捐鏁堢巼锛岃妭鐪佷汉鍔涜祫婧愩俒^3] +- 閬靛惊瑙勮寖缂栧啓鐨勪唬鐮侊紝鍙互琚粷澶у鏁颁豢鐪熷拰缁煎悎宸ュ叿鎵鎺ュ彈銆 + - 澶уぇ鍑忓皯浠ｇ爜鍦ㄤ笉鍚岃璁°佺患鍚堝拰浠跨湡骞冲彴涔嬮棿杩佺Щ鐨勫伐浣滈噺[^3] + +鍦╣it鍗忎綔寮鍙戣繃绋嬩腑锛屼竴鏃﹀彂鐜颁换浣曚笉绗﹀悎瑙勮寖鐨勪唬鐮侊紝璐熻矗妯″潡楠屾敹鍜孋odeReview鐨勪汉鍛樻湁涔夊姟鍚戣璁¤呮彁鍑轰笉绗﹀悎瑙勮寖鐨勫湴鏂癸紝浠ゅ叾鍙婃椂鍋氬嚭淇銆俒^3]涓嶈兘鍥犱负閫氳繃绯荤粺娴嬭瘯鑰屽拷瑙嗚鑼, 鍚﹀垯锛屸滃睅灞扁濊秺鍫嗚秺澶э紝灏嗗鑷村悗鏈熸棤娉曢噸鏋勩 + +褰撶劧锛屾湰瑙勮寖涔熶笉鏄濇斁涔嬪洓娴疯岀殕鍑嗏溿傚浜庣壒娈婃儏鍐碉紝鍙互鍏蜂綋闂鍏蜂綋鍒嗘瀽銆 + +### 0.1 涓轰粈涔堢紪鍐欐湰鏂囨。锛 + +鏈枃妗ｈ瀹氫簡鍗楃澶у浘鐏电彮CS214 CPU璁捐灏忕粍杩涜鐢佃矾鎻忚堪鏃舵帹鑽愰伒瀹堢殑浠ｇ爜瑙勮寖銆 + +鏈枃妗ｄ富瑕佹槸瀵圭綉涓婄殑涓浜沄erilog璁捐瑙勮寖锛岀粨鍚堟湰灏忕粍鐨勫紑鍙戝疄璺电粡楠岋紝缁撳悎CS214澶т綔涓氱殑璁捐瑕佹眰锛岃繘琛岀殑鏁寸悊涓庣畝鍖栥傞櫎浜嗙綉涓婅鑼冩彁鍒扮殑Verilog璇硶锛屾湰鏂囨。杩樺鏂囦欢銆佹枃浠跺す缁勭粐鏈夌嫭鍒扮殑瑙佽В銆 + ## 1. 鍩烘湰绾﹀畾 -### 1.1 鏂囦欢缂栫爜 +### 1.0 鏂囦欢缂栫爜 -- 鏂囦欢缂栫爜锛氬浜庡浗浜轰负涓昏寮鍙戣呯殑椤圭洰锛屼娇鐢℅BK缂栫爜锛岀悊鐢卞涓 +- 鏂囦欢缂栫爜锛氬浜庡浗浜轰负涓昏寮鍙戣呯殑椤圭洰锛屼娇鐢**GBK缂栫爜**锛岀悊鐢卞涓 - Vivado鏂逛究鎬э細 - VsCode鏂逛究鎬э細 - 缂栫爜澶у皬锛欸BK @@ -13,18 +38,16 @@ - 瀹為檯寮鍙戜腑锛屽父甯稿嚭鐜版帹閫佸埌git鍒嗘敮鍚庢枃浠剁紪鐮佷贡鐮侊紝鍦ㄥ叾浠栦汉鐢佃剳鏃犳硶鏄剧ず鐨勯棶棰樸 - -### 1.2 鏂囦欢澶逛笌鏂囦欢澶圭粨鏋 +### 1.1 鏂囦欢澶逛笌鏂囦欢澶圭粨鏋 -### 1.3 +### 1.2 ## 2. Verilog 缂栫▼瑙勮寖 +### 2.0 鏂囦欢澶逛笌Vivado + ### 2.1 鏂囦欢 -- 鏂囦欢澶存敞閲 - - 绂佹浣跨敤vivado鑷甫娉ㄩ噴銆 - - 浣跨敤鐭屾湁鏁堢殑娉ㄩ噴銆 - - - 鏂囦欢鐨勬蹇 - 鏄ā鍧楃殑闆嗗悎锛屼竴涓枃浠跺寘鎷涓ā鍧椼 - 绾﹀畾锛 @@ -32,51 +55,85 @@ - 鏂囦欢鍐呭叾浠栨ā鍧椾粎鑳藉湪鏂囦欢鍐呰繘琛屼緥鍖栥 - 鐞嗙敱锛氬熼壌Java缂栫▼瑙勮寖銆傝繖鏍疯兘澶熷疄鐜伴珮鍐呰仛锛堢鏈夋ā鍧楀彧鍦ㄦ枃浠跺唴鍙銆佷簰鐩歌皟鐢級浣庤﹀悎锛堟枃浠朵箣闂寸殑鍏崇郴鏈澶氭秹鍙婁竴涓ā鍧楋級銆 -- 鏂囦欢鍚 - - 绾﹀畾锛氭枃浠跺悕搴旇涓庡叕鍏辨ā鍧楀悕涓鑷淬 - - 鐞嗙敱锛氬熼壌Java缂栫▼瑙勮寖銆傝繖鏍疯兘澶熻鐪嬪埌鏂囦欢鐨勪汉涓鐩簡鐒躲 -### 2.2 妯″潡姒傝堪 + +#### 2.1.0 鏂囦欢鍚 + +- 绾﹀畾锛氭枃浠跺悕搴旇涓庡叕鍏辨ā鍧楀悕涓鑷淬 +- 鐞嗙敱锛氬熼壌Java缂栫▼瑙勮寖銆傝繖鏍疯兘澶熻鐪嬪埌鏂囦欢鐨勪汉涓鐩簡鐒躲 + +#### 2.1.1 鏂囦欢澶存敞閲 + +- 绂佹浣跨敤vivado鑷甫娉ㄩ噴銆 +- 浣跨敤鐭屾湁鏁堢殑娉ㄩ噴銆 + +### 2.2 妯″潡 - 妯″潡鐨勬蹇点 - 妯″潡鏄杈撳叆淇″彿杩涜缁勭粐銆佽繛鎺ワ紝涓嶆柇鎻愪緵杈撳嚭淇″彿鐨勭數璺娊璞″眰娆° - 妯″潡绫讳技浜庝竴涓被锛屽彲浠ヨ瀹炰緥鍖栥 - 鏈夋垚鍛樺彉閲忥紝骞朵笖鍙互鍒嗕负杈撳叆鍜岃緭鍑轰袱绉嶅彉閲忥紝瀵瑰簲鍙啓/鍙鎴愬憳鍙橀噺銆 - 鎴愬憳鍑芥暟/鏂规硶閫氳繃浣胯兘淇″彿鏉ュ疄鐜般 -- 妯″潡鍚 - - 澶у啓椹煎嘲 - - 鐞嗙敱锛氬搴擩ava绫汇 -- 杈撳叆杈撳嚭椋庢牸 - - 鍛藉悕锛歩/o+澶у啓椹煎嘲 - - 渚嬪瓙锛 - - 鐞嗙敱锛氬搴旂被鐨勫彧鍐/鍙鎴愬憳鍙橀噺 - - 渚嬪锛岀鑴氱害鏉熷彉閲忎娇鐢 **澶у啓涓嬪垝绾**鍒嗗壊澶у崟璇嶏紝**澶у啓椹煎嘲**鍒嗗壊灏忓崟璇嶃 -- 灞閮ㄥ彉閲 - - 涓轰簡杩涜杩炵嚎锛屽眬閮ㄥ線寰浜х敓wire绫诲瀷鐨勪腑闂村彉閲忋 - - - 绾﹀畾锛氫娇鐢**灏忓啓椹煎嘲** - - 绫讳技浜庤蒋浠剁紪绋嬭瑷鐨勫嚱鏁板唴灞閮ㄥ彉閲忋 - - 鍙互璁や负鎴戜滑瀵筕erilog妯″潡缂栧啓鐨勬墍鏈変唬鐮侊紝閮芥槸鍦ㄥ绫昏繘琛屾瀯閫犮傛垜浠湪涓涓瀯閫犲嚱鏁颁腑銆 -- 鏁版嵁鍙橀噺 - - 涓轰簡杩涜鏁版嵁銆佺姸鎬佺殑淇濆瓨锛屽線寰灞閮ㄤ娇鐢╮eg绫诲瀷 - - - 绾﹀畾锛氫娇鐢**d+澶у啓椹煎嘲**锛宒琛ㄧずdata(鏁版嵁)銆 -- 妯″潡渚嬪寲 - - 渚嬪寲鐩稿綋浜庢槸闈㈠悜瀵硅薄鐨勭粍鍚堬紝鎻忚堪浜嗕竴绉嶇粦瀹氬叧绯汇 - - 渚嬪寲鐨勫悓鏃讹紝瀛愭ā鍧椾細鏈夎嚜宸辩殑鏁版嵁鐘舵侊紝鍥犳渚嬪寲鍙互瑙嗕綔渚嬪寲鑰呰嚜韬氳繃渚嬪寲琚緥鍖栫殑妯″潡鑾峰緱浜嗘暟鎹彉閲忋 - - 鍥犳渚嬪寲涔熸槸鐢**d+澶у啓椹煎嘲**鐨勬牸寮忋 -### 2.3 妯″潡渚嬪寲 + +#### 2.1.0 鏂囦欢鍚嶆ā鍧楀悕 + +- 澶у啓椹煎嘲 +- 鐞嗙敱锛氬搴擩ava绫汇 + +#### 2.1.1 妯″潡渚嬪寲 + - 妯″潡渚嬪寲鍦╒erilog涓湁涓ょ椋庢牸锛 - 绫讳技C璇█缁撴瀯浣撶殑.缁戝畾 - 绫讳技鍑芥暟璋冪敤鐨勯『搴忕粦瀹氥 - 绾﹀畾锛氱姝娇鐢ㄩ『搴忕粦瀹 - 鐞嗙敱锛 - 鍩烘湰鍘熷垯锛氶噸鏋勫湪杞欢寮鍙戜腑闈炲父閲嶈銆傛垜浠富瑕佽冭檻閲嶆瀯鐨勬柟渚挎с - +#### 2.1.2 妯″潡杈撳叆杈撳嚭绔彛 -### 2.4 妯″潡杈撳叆杈撳嚭 - 妯″潡杈撳叆杈撳嚭鍦╒erilog涓湁涓ょ椋庢牸锛 - + +### 2.2 鍙橀噺锛堝寘鍚俊鍙凤級 + +鎵鏈変俊鍙烽噰鐢 **灏忛┘宄** 鍛藉悕鏂瑰紡銆俒^2] + +- 鍏朵腑閮ㄥ垎淇″彿娣诲姞鍓嶇紑銆 +- 绠¤剼缁戝畾淇″彿灞炰簬瀹忓畾涔夈佸父鏁扮殑鍛藉悕鏂瑰紡锛岀壒娈婂鐞嗐 + +#### 2.2.0 妯″潡杈撳叆杈撳嚭绔彛 鐨勫懡鍚嶉鏍 + +- 鍛藉悕锛歩/o+澶у啓椹煎嘲 + - 渚嬪瓙锛 + - 鐞嗙敱锛氬搴旂被鐨勫彧鍐/鍙鎴愬憳鍙橀噺 + - 鍙傝冭祫鏂橻^2] + - 渚嬪锛岀鑴氱害鏉熷彉閲忎娇鐢 **澶у啓涓嬪垝绾**鍒嗗壊澶у崟璇嶏紝**澶у啓椹煎嘲**鍒嗗壊灏忓崟璇嶃 + +#### 2.2.1 灞閮ㄥ彉閲 + +- 涓轰簡杩涜杩炵嚎锛屽眬閮ㄥ線寰浜х敓wire绫诲瀷鐨勪腑闂村彉閲忋 + +- 绾﹀畾锛氫娇鐢**灏忓啓椹煎嘲** +- 绫讳技浜庤蒋浠剁紪绋嬭瑷鐨勫嚱鏁板唴灞閮ㄥ彉閲忋 + - 鍙互璁や负鎴戜滑瀵筕erilog妯″潡缂栧啓鐨勬墍鏈変唬鐮侊紝閮芥槸鍦ㄥ绫昏繘琛屾瀯閫犮傛垜浠湪涓涓瀯閫犲嚱鏁颁腑銆 + +- - + +#### 2.2.2 鏁版嵁鍙橀噺 + +- 涓轰簡杩涜鏁版嵁銆佺姸鎬佺殑淇濆瓨锛屽線寰灞閮ㄤ娇鐢╮eg绫诲瀷 +- 绾﹀畾锛氫娇鐢**d+澶у啓椹煎嘲**锛宒琛ㄧずdata(鏁版嵁)銆 + +#### 2.2.3 妯″潡渚嬪寲鍙橀噺 + +妯″潡渚嬪寲 + +- 渚嬪寲鐩稿綋浜庢槸闈㈠悜瀵硅薄鐨勭粍鍚堬紝鎻忚堪浜嗕竴绉嶇粦瀹氬叧绯汇 +- 渚嬪寲鐨勫悓鏃讹紝瀛愭ā鍧椾細鏈夎嚜宸辩殑鏁版嵁鐘舵侊紝鍥犳渚嬪寲鍙互瑙嗕綔渚嬪寲鑰呰嚜韬氳繃渚嬪寲琚緥鍖栫殑妯″潡鑾峰緱浜嗘暟鎹彉閲忋 +- 鍥犳渚嬪寲涔熸槸鐢**d+澶у啓椹煎嘲**鐨勬牸寮忋 + ## 鍙傝冩枃鐚 [^1]: 鍗庝负澶ц妯￠昏緫璁捐鎸囧涔.pdf -[^2]: https://verilogcodingstyle.readthedocs.io/en/latest/source/1BasicSyntax_cn.html \ No newline at end of file +[^2]: [Zion Verilog Code Style](https://verilogcodingstyle.readthedocs.io/en/latest/source/1BasicSyntax_cn.html) ([github](https://github.com/zion-group/VerilogCodingStyle)涓婂紑婧) + +[^3]: [楂橀氱粷瀵哣ERILOG 缂栫爜瑙勮寖](https://www.docin.com/p-1308800576.html#:~:text=Verilog%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83%E8%BD%AFIP%E9%87%8D%E7%94%A8%E6%A0%87%E5%87%86%EF%BC%88%E8%8D%89%E6%A1%88%202011-1-10%EF%BC%89%20%EF%BC%88%E4%BB%85%E4%BE%9B%E9%AB%98%E9%80%9A%E5%86%85%E9%83%A8%E4%BD%BF%E7%94%A8%EF%BC%89%20%E5%AE%97%E6%97%A8%E6%9C%AC%E8%A7%84%E8%8C%83%E4%B8%BA%E5%85%AC%E5%8F%B8%E5%86%85%E9%83%A8%E5%BC%BA%E5%88%B6%E5%AE%9E%E6%96%BD%E7%9A%84%20Verilog%20HDL%20%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83%E3%80%82.,%E6%AF%8F%E4%B8%AAIP%E8%AE%BE%E8%AE%A1%E4%BA%BA%E5%91%98%E5%BF%85%E9%A1%BB%E4%B8%A5%E6%A0%BC%E9%81%B5%E5%AE%88%EF%BC%8C%E4%BB%A5%20%E9%81%BF%E5%85%8D%E4%B8%8D%E5%BF%85%E8%A6%81%E7%9A%84%E9%87%8D%E5%A4%8D%E5%8A%B3%E5%8A%A8%EF%BC%8C%E4%BB%8E%E8%80%8C%E6%8F%90%E9%AB%98%E8%AE%BE%E8%AE%A1%E6%95%88%E7%8E%87%E3%80%82.%20%E6%9C%AC%E8%A7%84%E8%8C%83%E9%80%82%E7%94%A8%E4%BA%8E%E4%B8%8B%E5%88%97%E4%B8%89%E7%A7%8D%20Verilog%E4%BB%A3%E7%A0%81%E6%96%87%E4%BB%B6%E7%9A%84%E7%BC%96%20%E5%86%99%EF%BC%9A1%EF%BC%89%E5%8F%AF%E7%BB%BC%E5%90%88%E9%80%BB%E8%BE%91%E9%83%A8%E4%BB%B6%EF%BC%9B2%EF%BC%89%E8%99%9A%E6%8B%9F%E9%83%A8%E4%BB%B6%EF%BC%88Virtual%20Component--VC%EF%BC%89%EF%BC%9B3%EF%BC%89%E6%B5%8B%E8%AF%95%E6%A8%A1%E5%9D%97%EF%BC%88testbenches%EF%BC%89%E3%80%82.%20%E8%A7%84%E8%8C%83%E8%BF%98%E5%AF%B9%E6%A8%A1%E5%9D%97%E6%96%87%E4%BB%B6%E7%9A%84%E5%91%BD%E5%90%8D%E4%B9%A0%E6%83%AF%E3%80%81%E4%BB%A3%E7%A0%81%E6%96%87%E4%BB%B6%E7%9A%84%E5%82%A8%E5%AD%98%E3%80%81%E4%BB%A3%E7%A0%81%E6%96%87%E4%BB%B6%E7%9A%84%E7%BC%96%E5%86%99%E9%A3%8E%E6%A0%BC%E5%81%9A%E4%BA%86%E5%BC%BA%E5%88%B6%E6%80%A7%E7%9A%84%E8%A7%84%E5%AE%9A%E3%80%82.%20%E5%85%AC%E5%8F%B8%E5%86%85%E7%9A%84%E6%AF%8F%E4%B8%AA%E8%AE%BE%E8%AE%A1%E4%BA%BA%E5%91%98%E5%BF%85%E9%A1%BB%E4%B8%A5%E6%A0%BC%E9%81%B5%E7%85%A7%E6%9C%AC%E8%A7%84%E8%8C%83%E6%9D%A5%E7%BC%96%E5%86%99%E4%BB%A3%E7%A0%81%EF%BC%8C%E4%BB%A5%E6%8F%90%E9%AB%98%E4%BB%A3%E7%A0%81%E7%9A%84%E5%8F%AF%E8%AF%BB%E6%80%A7%E3%80%82.) \ No newline at end of file -- Gitee From a3b37c2cdfc9768a59bd4124af4ef93092a6c75e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 15:45:09 +0800 Subject: [PATCH 43/57] =?UTF-8?q?feat(verilog=20mips=20cpu):=20=E4=BF=AE?= =?UTF-8?q?=E6=94=B9Instruction=20Fetcher=E4=B8=BA=E7=BB=9F=E4=B8=80?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E9=A3=8E=E6=A0=BC,=20=E6=B7=BB=E5=8A=A0?= =?UTF-8?q?=E6=B3=A8=E9=87=8A=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/mips_cpu/basic_modules/Ifetc32.v | 55 ---------------- .../basic_modules/InstructionFetcher.v | 63 +++++++++++++++++++ 2 files changed, 63 insertions(+), 55 deletions(-) delete mode 100644 main/verilog/mips_cpu/basic_modules/Ifetc32.v create mode 100644 main/verilog/mips_cpu/basic_modules/InstructionFetcher.v diff --git a/main/verilog/mips_cpu/basic_modules/Ifetc32.v b/main/verilog/mips_cpu/basic_modules/Ifetc32.v deleted file mode 100644 index 61df165..0000000 --- a/main/verilog/mips_cpu/basic_modules/Ifetc32.v +++ /dev/null @@ -1,55 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: Southern University of Science and Technology 南方科技大学 -// Engineer: 王睿 -// -// Create Date: 2022/05/07 12:58:45 -// Module Name: CPU_TOP -// Project Name: MIPS Single Cycle CPU -// Target Devices: Xilinx Board. Tested on MINISYS. -// Description: -// -////////////////////////////////////////////////////////////////////////////////// - -module Ifetc32(Instruction_i,Instruction_o,branch_base_addr,Addr_result,Read_data_1,Branch,nBranch,Jmp,Jal,Jr,Zero,clock,reset,link_addr,rom_adr_o); - input[31:0] Instruction_i; - output[31:0] Instruction_o; // 根据PC的值从存放指令的prgrom中取出的指令 - output[31:0] branch_base_addr; // 对于有条件跳转类的指令而言，该值为(pc+4)送往ALU - input[31:0] Addr_result; // 来自ALU,为ALU计算出的跳转地址 - input[31:0] Read_data_1; // 来自Decoder，jr指令用的地址 - input Branch; // 来自控制单元 - input nBranch; // 来自控制单元 - input Jmp; // 来自控制单元 - input Jal; // 来自控制单元 - input Jr; // 来自控制单元 - input Zero; //来自ALU，Zero为1表示两个值相等，反之表示不相等 - input clock,reset; //时钟与复位,复位信号用于给PC赋初始值，复位信号高电平有效 - output[31:0] link_addr; // JAL指令专用的PC+4 - output[13:0] rom_adr_o; -reg[31:0] PC, Next_PC; -reg [31:0] jalpc; -assign rom_adr_o=PC[15:2]; -assign branch_base_addr = PC+4; -assign link_addr = jalpc; -assign Instruction_o=Instruction_i; -always @* begin -if(((Branch == 1) && (Zero == 1 )) || ((nBranch == 1) && (Zero == 0))) // beq, bne -Next_PC = Addr_result; // the calculated new value for PC -else if(Jr == 1) -Next_PC = Read_data_1; // the value of $31 register -else Next_PC = PC+4; // PC+4 -end -always @(negedge clock) begin -if(reset == 1) -PC <= 32'h0000_0000; -else begin -if(Jal==1)begin -jalpc = PC+4; -end -if((Jmp == 1) || (Jal == 1)) begin -PC <= {PC[31:28],Instruction_i[25:0],2'b00}; -end -else PC <= Next_PC; -end -end -endmodule diff --git a/main/verilog/mips_cpu/basic_modules/InstructionFetcher.v b/main/verilog/mips_cpu/basic_modules/InstructionFetcher.v new file mode 100644 index 0000000..b90b229 --- /dev/null +++ b/main/verilog/mips_cpu/basic_modules/InstructionFetcher.v @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 王睿 +// +// Create Date: 2022/05/07 12:58:45 +// Module Name: CPU_TOP +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. +// Description: +// +////////////////////////////////////////////////////////////////////////////////// + +module InstructionFetcher(iInstruction,oInstruction,oBranchBaseAddress,iAluAddrResult,iRegisterAddressResult,iIsBeq,iIsBne,iIsJ,iIsJal,iIsJr,iIsAluZero,iCpuClock,iCpuReset,oLinkAddress,oProgromFetchAddr); + input[31:0] iInstruction; + output[31:0] oInstruction; // 根据PC的值从存放指令的prgrom中取出的指令 + output[31:0] oBranchBaseAddress; // 对于有条件跳转类的指令而言，该值为(pc+4)送往ALU + input[31:0] iAluAddrResult; // 来自ALU,为ALU计算出的跳转地址 + input[31:0] iRegisterAddressResult; // 来自Decoder，jr指令用的地址 + input iIsBeq; // 来自控制单元 + input iIsBne; // 来自控制单元 + input iIsJ; // 来自控制单元 + input iIsJal; // 来自控制单元 + input iIsJr; // 来自控制单元 + input iIsAluZero; //来自ALU，Zero为1表示两个值相等，反之表示不相等 + input iCpuClock,iCpuReset; //时钟与复位,复位信号用于给PC赋初始值，复位信号高电平有效 + output[31:0] oLinkAddress; // JAL指令专用的PC+4 + output[13:0] oProgromFetchAddr; // 向Progrom请求的地址 + + + reg[31:0] dProgramCounter, dNextProgramCounter; + reg [31:0] dJalPc; + + assign oProgromFetchAddr=dProgramCounter[15:2]; + assign oBranchBaseAddress = dProgramCounter+4; + assign oLinkAddress = dJalPc; + assign oInstruction=iInstruction; + + // 组合逻辑，只要ALU、寄存器算完，就设置 dNextProgramCounter + always @* begin + if(((iIsBeq == 1) && (iIsAluZero == 1 )) || ((iIsBne == 1) && (iIsAluZero == 0))) // beq, bne + dNextProgramCounter = iAluAddrResult; // the calculated new value for dProgramCounter + else if(iIsJr == 1) + dNextProgramCounter = iRegisterAddressResult; // the value of $31 register + else dNextProgramCounter = dProgramCounter+4; // dProgramCounter+4 + end + + // 同步时序逻辑：复位、改变PC + always @(negedge iCpuClock) begin + if(iCpuReset == 1) + dProgramCounter <= 32'h0000_0000; // 复位 + else begin + if(iIsJal==1) begin + dJalPc = dProgramCounter+4; // 如果是Jal， 那么把JalPc 赋一下值 + end + if((iIsJ == 1) || (iIsJal == 1)) begin // 如果是Jal或者J，就是跳转J类型指令 + dProgramCounter <= {dProgramCounter[31:28], iInstruction[25:0],2'b00}; // 按照它的要求改PC + end + //否则按照之前（还没到下降沿时）我们算过（上面那个always的组合逻辑）的 dNextProgramCounter 来更新PC + else dProgramCounter <= dNextProgramCounter; + end + end +endmodule -- Gitee From e9871bfa7676763f4d7a4ba207c7af28a553421c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 16:03:19 +0800 Subject: [PATCH 44/57] =?UTF-8?q?feat(verilog=20mips):=20decoder=20?= =?UTF-8?q?=E5=91=BD=E5=90=8D=E8=A7=84=E8=8C=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../basic_modules/{Decoder.v => CpuDecoder.v} | 107 +++++++++--------- 1 file changed, 54 insertions(+), 53 deletions(-) rename main/verilog/mips_cpu/basic_modules/{Decoder.v => CpuDecoder.v} (35%) diff --git a/main/verilog/mips_cpu/basic_modules/Decoder.v b/main/verilog/mips_cpu/basic_modules/CpuDecoder.v similarity index 35% rename from main/verilog/mips_cpu/basic_modules/Decoder.v rename to main/verilog/mips_cpu/basic_modules/CpuDecoder.v index a1c1fa1..f8fcbea 100644 --- a/main/verilog/mips_cpu/basic_modules/Decoder.v +++ b/main/verilog/mips_cpu/basic_modules/CpuDecoder.v @@ -10,54 +10,54 @@ // Description: // ////////////////////////////////////////////////////////////////////////////////// -module decode32(read_data_1,read_data_2,Instruction,mem_data,ALU_result, - Jal,RegWrite,MemtoReg,RegDst,Sign_extend,clock,reset,opcplus4); +module InstructionDecoder(oDataRead1,oDataRead2,iInstruction,iMemoryData,iAluResult, + iIsJal,iDoWriteReg,iIsRegFromMem,iIsRdOrRtWritten,oSignExtentedImmediate,iCpuClock,iCpuReset,iJalLinkAddress); //////////////// 输入输出 //////////////// - output[31:0] read_data_1; // 输出的第一操作数 - output[31:0] read_data_2; // 输出的第二操作数 - input[31:0] Instruction; // 取指单元来的指令 - input[31:0] mem_data; // 从DATA RAM or I/O port取出的数据 - input[31:0] ALU_result; // 从执行单元来的运算的结果 - input Jal; // 来自控制单元，说明是JAL指令 - input RegWrite; // 来自控制单元, 是否写入寄存器 - input MemtoReg; // 来自控制单元，表示写回数据的来源 - input RegDst; //来自控制单元，表示是rd还是rt作为写回寄存器地址 - output[31:0] Sign_extend; // 扩展后的32位立即数 - input clock,reset; // 时钟和复位 - input[31:0] opcplus4; // 来自取指单元，JAL中用. 是PC plus 4 + output[31:0] oDataRead1; // 输出的第一操作数 + output[31:0] oDataRead2; // 输出的第二操作数 + input[31:0] iInstruction; // 取指单元来的指令 + input[31:0] iMemoryData; // 从DATA RAM or I/O port取出的数据 + input[31:0] iAluResult; // 从执行单元来的运算的结果 + input iIsJal; // 来自控制单元，说明是JAL指令 + input iDoWriteReg; // 来自控制单元, 是否写入寄存器 + input iIsRegFromMem; // 来自控制单元，表示写回数据的来源 + input iIsRdOrRtWritten; //来自控制单元，表示是rd还是rt作为写回寄存器地址 + output[31:0] oSignExtentedImmediate; // 扩展后的32位立即数 + input iCpuClock,iCpuReset; // 时钟和复位 + input[31:0] iJalLinkAddress; // 来自取指单元，JAL中用. 是PC plus 4 //////////////// 代码逻辑 //////////////// //////////////// 成员变量 //////////////// - wire [4:0] rs = Instruction[25:21]; - wire [4:0] rt = Instruction[20:16]; - wire [4:0] rd = Instruction[15:11]; - wire [15:0] imm = Instruction[15:0]; + wire [4:0] rs = iInstruction[25:21]; + wire [4:0] rt = iInstruction[20:16]; + wire [4:0] rd = iInstruction[15:11]; + wire [15:0] imm = iInstruction[15:0]; //////////////// 实例化寄存器 //////////////// - reg [4:0] registerDestination; - reg [31:0] writingData; - always @(*) begin - if (!Jal) begin - registerDestination = RegDst?rd:rt; - writingData = MemtoReg?mem_data:ALU_result; + reg [4:0] dRegisterDestination; //要被写入的寄存器的地址 + reg [31:0] dWritingData; //要被写入寄存器的数据 + always @(*) begin // 虽然不一定要写入寄存器，但是这些数值要赋值。 + if (iIsJal) begin + dRegisterDestination = 5'b11111; //31， 也就是ra寄存器 + dWritingData = iJalLinkAddress; // 要链接的地址，也就是pc+4. 暂存到ra。 end else begin - registerDestination = 5'b11111; - writingData = opcplus4; + dRegisterDestination = iIsRdOrRtWritten?rd:rt; + dWritingData = iIsRegFromMem?iMemoryData:iAluResult; end end - Registers mRegisters(clock, reset, rs, rt, - registerDestination, writingData, - RegWrite, read_data_1, read_data_2); + Registers dRegisters(iCpuClock, iCpuReset, rs, rt, + dRegisterDestination, dWritingData, + iDoWriteReg, oDataRead1, oDataRead2); //////////////// 实例化扩展器 //////////////// wire[5:0] opcode; // 指令码 - assign opcode = Instruction[31:26]; //OP - SignExtension mSignExtension(opcode, imm, Sign_extend); + assign opcode = iInstruction[31:26]; //OP + SignExtension mSignExtension(opcode, imm, oSignExtentedImmediate); endmodule module SignExtension ( - input [5:0] opcode, - input [15:0] immediate, - output[31:0] extendedImmediate + input [5:0] iOpcode, + input [15:0] iImmediate, + output[31:0] oExtendedImmediate ); - // assign extendedImmediate=immediate[15]?{16{1'b1}, immediate}:{16{1'b0}, immediate}; + // assign oExtendedImmediate=iImmediate[15]?{16{1'b1}, iImmediate}:{16{1'b0}, iImmediate}; //andi, ori xori 属于 zeroExtension情况，其他I format都是signExtension // sltiu 是特殊情况，取决于ALU如何实现sltiu的算法。 // 如果是 32位数-ext(16位立即数) 然后判断符号，那么用零扩展比较合理。 @@ -65,34 +65,35 @@ module SignExtension ( // 优化一下逻辑？ 都是001开头，连续的3,4,5,6？ 答：没法优化，卡诺图没什么规律。 // another question: LUI 是什么extension？也是取决于ALU怎么实现。 // 目前我是按照sign extension去处理。 - assign extendedImmediate=(6'b001100 == opcode || 6'b001101 == opcode || - 6'b001110 == opcode|| 6'b001011==opcode)?{{16{1'b0}},immediate}: - {{16{immediate[15]}}, immediate}; + assign oExtendedImmediate=(6'b001100 == iOpcode || 6'b001101 == iOpcode || + 6'b001110 == iOpcode|| 6'b001011==iOpcode)?{{16{1'b0}},iImmediate}: + {{16{iImmediate[15]}}, iImmediate}; //Verilog语法：https://stackoverflow.com/questions/49539345/error-in-compilation-replication-operator-in-verilog endmodule + module Registers( - input clock,reset, // 时钟和复位 - input [4:0] registerSource1, //registerSource1 - input [4:0] registerSource2, //registerSource2 - input [4:0] registerDestination, //registerDestination - input [31:0] writingData, // the data being written to R[registerDestination]. + input iCpuClock,iCpuReset, // 时钟和复位 + input [4:0] iRegisterSource1, //iRegisterSource1 + input [4:0] iRegisterSource2, //iRegisterSource2 + input [4:0] iRegisterDestination, //iRegisterDestination + input [31:0] iWritingData, // the data being written to R[iRegisterDestination]. input regWrite, //whether enable write - output [31:0] dataRead1, // R[registerSource1], the data that is read. - output [31:0] dataRead2 // R[registerSource2], the data that is read. + output [31:0] oDataRead1, // R[iRegisterSource1], the data that is read. + output [31:0] oDataRead2 // R[iRegisterSource2], the data that is read. ); - reg[31:0] mRegisters [0:31]; - assign dataRead1 = mRegisters[registerSource1]; - assign dataRead2 = mRegisters[registerSource2]; + reg[31:0] dRegisters [0:31]; + assign oDataRead1 = dRegisters[iRegisterSource1]; + assign oDataRead2 = dRegisters[iRegisterSource2]; // write data when posedge, so that when cpu goes to reg, the data has been written. integer i; - always @(posedge clock, posedge reset) begin - if (reset) begin + always @(posedge iCpuClock, posedge iCpuReset) begin + if (iCpuReset) begin for (i=0; i<32; i=i+1) begin //for 是辅助生成电路的手段。 - mRegisters[i] <= 32'h00000000; // 把所有寄存器复位为0。 + dRegisters[i] <= 32'h00000000; // 把所有寄存器复位为0。 end end else begin - if (regWrite && registerDestination!=0) //$0要焊死为0 - mRegisters[registerDestination] <= writingData; + if (regWrite && iRegisterDestination!=0) //$0要焊死为0 + dRegisters[iRegisterDestination] <= iWritingData; end end endmodule //Registers \ No newline at end of file -- Gitee From 19619f76c87b073585457f6b6ab5f92b54b93f87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 16:21:30 +0800 Subject: [PATCH 45/57] =?UTF-8?q?feat(verilog=20mips=20cpu):=20=E4=BF=AE?= =?UTF-8?q?=E6=94=B9InstructionMemory=E7=AC=A6=E5=90=88=E5=91=BD=E5=90=8D?= =?UTF-8?q?=E8=A7=84=E8=8C=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../basic_modules/InstructionMemory.v | 36 +++++++++++++++++++ main/verilog/mips_cpu/basic_modules/program.v | 36 ------------------- 2 files changed, 36 insertions(+), 36 deletions(-) create mode 100644 main/verilog/mips_cpu/basic_modules/InstructionMemory.v delete mode 100644 main/verilog/mips_cpu/basic_modules/program.v diff --git a/main/verilog/mips_cpu/basic_modules/InstructionMemory.v b/main/verilog/mips_cpu/basic_modules/InstructionMemory.v new file mode 100644 index 0000000..74f9240 --- /dev/null +++ b/main/verilog/mips_cpu/basic_modules/InstructionMemory.v @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у +// Engineer: 鐜嬬澘锛 鍙剁挩閾 +// +// Create Date: 2022/05/07 12:58:45 +// Module Name: InstructionMemory +// Project Name: MIPS Single Cycle CPU +// Target Devices: Xilinx Board. Tested on MINISYS. +// Description: +// +////////////////////////////////////////////////////////////////////////////////// + +module InstructionMemory ( + // Program ROM Pinouts + input iRomClock, // ROM clock + input[13:0] iAddressRequested, // From IFetch + output [31:0] oInstructionFetched, // To IFetch + // UART Programmer Pinouts + input iUpgReset, // UPG reset (Active High) + input iUpgClock, // UPG clock (10MHz) + input iDoUpgWrites, // UPG write enable + input[13:0] iUpgWriteAddress, // UPG write address + input[31:0] iUpgWriteData, // UPG write data + input iIsUpgDone // 1 if program finished +); + /* if kickOff is 1 means CPU work on normal mode, otherwise CPU work on Uart communication mode */ + wire kickOff = iUpgReset | (~iUpgReset & iIsUpgDone ); + prgrom instmem ( + .clka (kickOff ? iRomClock : iUpgClock ), + .wea (kickOff ? 1'b0 : iDoUpgWrites ), + .addra (kickOff ? iAddressRequested : iUpgWriteAddress ), + .dina (kickOff ? 32'h00000000 : iUpgWriteData ), + .douta (oInstructionFetched) + ); +endmodule diff --git a/main/verilog/mips_cpu/basic_modules/program.v b/main/verilog/mips_cpu/basic_modules/program.v deleted file mode 100644 index b1473c5..0000000 --- a/main/verilog/mips_cpu/basic_modules/program.v +++ /dev/null @@ -1,36 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: Southern University of Science and Technology 鍗楁柟绉戞妧澶у -// Engineer: 鐜嬬澘 -// -// Create Date: 2022/05/07 12:58:45 -// Module Name: CPU_TOP -// Project Name: MIPS Single Cycle CPU -// Target Devices: Xilinx Board. Tested on MINISYS. -// Description: -// -////////////////////////////////////////////////////////////////////////////////// - -module programrom ( -// Program ROM Pinouts -input rom_clk_i, // ROM clock -input[13:0] rom_adr_i, // From IFetch -output [31:0] Instruction_o, // To IFetch -// UART Programmer Pinouts -input upg_rst_i, // UPG reset (Active High) -input upg_clk_i, // UPG clock (10MHz) -input upg_wen_i, // UPG write enable -input[13:0] upg_adr_i, // UPG write address -input[31:0] upg_dat_i, // UPG write data -input upg_done_i // 1 if program finished -); -/* if kickOff is 1 means CPU work on normal mode, otherwise CPU work on Uart communication mode */ -wire kickOff = upg_rst_i | (~upg_rst_i & upg_done_i ); -prgrom instmem ( -.clka (kickOff ? rom_clk_i : upg_clk_i ), -.wea (kickOff ? 1'b0 : upg_wen_i ), -.addra (kickOff ? rom_adr_i : upg_adr_i ), -.dina (kickOff ? 32'h00000000 : upg_dat_i ), -.douta (Instruction_o) -); -endmodule -- Gitee From b63dd2c91ec5d9f29d61f9e2308548a8737949d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 16:23:52 +0800 Subject: [PATCH 46/57] =?UTF-8?q?feat(verilog=20mips=20cpu):=20=E4=BF=AE?= =?UTF-8?q?=E6=94=B9=E7=B1=BB=E5=90=8D=E8=A7=84=E8=8C=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/mips_cpu/CPUTOP.v | 357 +++++++++--------- main/verilog/mips_cpu/{TOP_all.v => TopAll.v} | 34 +- .../{control32.v => CpuController.v} | 2 +- .../{executs32.v => CpuExecutor.v} | 116 +++--- .../{dmemory32.v => DataMemory.v} | 46 +-- .../basic_modules/{LED.v => LightDriver.v} | 2 +- .../{switch.v => SwitchDriver.v} | 2 +- .../{digital_tube.v => TubeDriver.v} | 10 +- 8 files changed, 285 insertions(+), 284 deletions(-) rename main/verilog/mips_cpu/{TOP_all.v => TopAll.v} (42%) rename main/verilog/mips_cpu/basic_modules/{control32.v => CpuController.v} (95%) rename main/verilog/mips_cpu/basic_modules/{executs32.v => CpuExecutor.v} (39%) rename main/verilog/mips_cpu/basic_modules/{dmemory32.v => DataMemory.v} (34%) rename main/verilog/mips_cpu/basic_modules/{LED.v => LightDriver.v} (94%) rename main/verilog/mips_cpu/basic_modules/{switch.v => SwitchDriver.v} (93%) rename main/verilog/mips_cpu/basic_modules/{digital_tube.v => TubeDriver.v} (92%) diff --git a/main/verilog/mips_cpu/CPUTOP.v b/main/verilog/mips_cpu/CPUTOP.v index 4fbba5d..e89311d 100644 --- a/main/verilog/mips_cpu/CPUTOP.v +++ b/main/verilog/mips_cpu/CPUTOP.v @@ -1,7 +1,7 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: Southern University of Science and Technology ?????? -// Engineer: ??? +// Company: Southern University of Science and Technology 南方科技大学 +// Engineer: 张力宇, 叶璨铭 // // Create Date: 2022/05/07 12:58:45 // Module Name: CPU_TOP @@ -11,154 +11,155 @@ // ////////////////////////////////////////////////////////////////////////////////// -module CPUTOP( -input fpga_rst, //Active High -input fpga_clk, -input[23:0] switch2N4, -output[23:0] led2N4, -// UART Programmer Pinouts -// start Uart communicate at high level -input start_pg, // Active High艁殴 if -input rx,// receive data by UART -output tx, // send data by UART -output[7:0] Dig, //which tubs to light -output[7:0]Y //light what -); - - -// UART Programmer Pinouts -wire upg_clk, upg_clk_o; -wire upg_wen_o; //Uart write out enable -wire upg_done_o; //Uart rx data have done -//data to which memory unit of program_rom/dmemory32 -wire [14:0] upg_adr_o; -//data to program_rom or dmemory32 -wire [31:0] upg_dat_o; -wire spg_bufg; -BUFG U1(.I(start_pg), .O(spg_bufg)); // de-twitter -// Generate UART Programmer reset signal -reg upg_rst; -always @ (posedge fpga_clk) begin -if (spg_bufg) upg_rst = 0; -if (fpga_rst) upg_rst = 1; -end -//used for other modules which don't relate to UART -wire rst; -assign rst = fpga_rst | !upg_rst; - -uart_bmpg_0 uart_instance( -.upg_clk_i(upg_clk), -.upg_rst_i(upg_rst), -.upg_rx_i(rx), -.upg_clk_o(upg_clk_o), -.upg_wen_o(upg_wen_o), -.upg_adr_o(upg_adr_o), -.upg_dat_o(upg_dat_o), -.upg_done_o(upg_done_o) -); - -wire cpu_clk; -cpuclk cpuclk_instance( -.clk_in1(fpga_clk), -.clk_out1(cpu_clk), -.clk_out2(upg_clk) +module CpuTop( + input iFpgaRst, //Active High + input iFpgaClk, + input[23:0] iSwitches, + output[23:0] oLights, + // UART Programmer Pinouts + // start Uart communicate at high level + input iStartReceiveCoe, // Active High艁殴 if + input iFpgaUartFromPc,// receive data by UART + output oFpgaUartToPc, // send data by UART // 实际上没有用到。 + output[7:0] oDigitalTubeNotEnable, //which tubs to light + output[7:0] oDigitalTubeShape //light what ); +///////////// Cpu Clock ///////////// + wire cpu_clk; + cpuclk cpuclk_instance( + .clk_in1(iFpgaClk), + .clk_out1(cpu_clk), + .clk_out2(upg_clk) + ); +///////////// UART Programmer Pinouts ///////////// + wire upg_clk, upg_clk_o; + wire upg_wen_o; //Uart write out enable + wire upg_done_o; //Uart iFpgaUartFromPc data have done + //data to which memory unit of program_rom/dmemory32 + wire [14:0] upg_adr_o; + //data to program_rom or dmemory32 + wire [31:0] upg_dat_o; + wire spg_bufg; + BUFG U1(.I(iStartReceiveCoe), .O(spg_bufg)); // de-twitter + // Generate UART Programmer reset signal + reg upg_rst; + always @ (posedge iFpgaClk) begin + if (spg_bufg) upg_rst = 0; + if (iFpgaRst) upg_rst = 1; + end + //used for other modules which don't relate to UART + wire rst; + assign rst = iFpgaRst | !upg_rst; + uart_bmpg_0 uart_instance( + .upg_clk_i(upg_clk), + .upg_rst_i(upg_rst), + .upg_rx_i(iFpgaUartFromPc), + .upg_clk_o(upg_clk_o), + .upg_wen_o(upg_wen_o), + .upg_adr_o(upg_adr_o), + .upg_dat_o(upg_dat_o), + .upg_done_o(upg_done_o) + ); -// Control signals -wire Branch, nBranch, Jmp, Jal, Jr, Zero, RegWrite, RegDst; -wire [31:0] branch_base_addr; -wire [31:0] Addr_Result; -wire [31:0] read_data_1; -wire [31:0] read_data_2; -wire [31:0] read_data; -wire [31:0] link_addr; -wire [31:0] Instruction_i; -wire [31:0] Instruction_o_Ifetc32; -wire [13:0] rom_adr_o; -Ifetc32 Ifetc32_instance( - .Instruction_i(Instruction_i), - .Instruction_o(Instruction_o_Ifetc32), - .branch_base_addr(branch_base_addr), - .Addr_result(Addr_Result), - .Read_data_1(read_data_1), - .Branch(Branch), - .nBranch(nBranch), - .Jmp(Jmp), - .Jal(Jal), - .Jr(Jr), - .Zero(Zero), - .clock(cpu_clk), - .reset(rst), - .link_addr(link_addr), - .rom_adr_o(rom_adr_o) +///////////// Ifetc32 和 progrom ///////////// + // Control signals + wire Branch, nBranch, Jmp, Jal, Jr, Zero, RegWrite, RegDst; + wire [31:0] branch_base_addr; + wire [31:0] Addr_Result; + wire [31:0] read_data_1; + wire [31:0] read_data_2; + wire [31:0] read_data; + wire [31:0] link_addr; + wire [31:0] Instruction_i; + wire [31:0] Instruction_o_Ifetc32; + wire [13:0] rom_adr_o; + InstructionFetcher dInstructionFetcher( + .iInstruction(Instruction_i), + .oInstruction(Instruction_o_Ifetc32), + .oBranchBaseAddress(branch_base_addr), + .iAluAddrResult(Addr_Result), + .iRegisterAddressResult(read_data_1), + .iIsBeq(Branch), + .iIsBne(nBranch), + .iIsJ(Jmp), + .iIsJal(Jal), + .iIsJr(Jr), + .iIsAluZero(Zero), + .iCpuClock(cpu_clk), + .iCpuReset(rst), + .oLinkAddress(link_addr), + .oProgromFetchAddr(rom_adr_o) ); - programrom programrom_instance( - .rom_clk_i(cpu_clk), - .rom_adr_i(rom_adr_o), - .Instruction_o(Instruction_i), - .upg_rst_i(upg_rst), - .upg_clk_i(upg_clk_o), - .upg_wen_i(upg_wen_o & (!upg_adr_o[14])), - .upg_adr_i(upg_adr_o[13:0]), - .upg_dat_i(upg_dat_o), - .upg_done_i(upg_done_o) + // 这里利用到到了uart IP 核的信号，用来接受数据。 + InstructionMemory dInstructionMemory( + .iRomClock(cpu_clk), + .iAddressRequested(rom_adr_o), + .oInstructionFetched(Instruction_i), + .iUpgReset(upg_rst), + .iUpgClock(upg_clk_o), + .iDoUpgWrites(upg_wen_o & (!upg_adr_o[14])), + .iUpgWriteAddress(upg_adr_o[13:0]), + .iUpgWriteData(upg_dat_o), + .iIsUpgDone(upg_done_o) ); +///////////// CpuDecoder ///////////// wire [31:0]ALU_Result; wire MemorIOtoReg; wire[31:0]Sign_extend; wire [31:0] r_wdata;//暮聠聶暮聢掳register莽職聞膰聲掳膰聧? - decode32 decoder_instance( - .read_data_1(read_data_1),//decoder莽職聞膷啪聯暮聡? - .read_data_2(read_data_2),//decoder莽職聞膷啪聯暮聡?,膷偶聶盲赂艦膷啪聯暮聡艧膰聵呕莽钮聶memory莽職聞膷啪聯暮聡? - .Instruction(Instruction_o_Ifetc32), - .mem_data(r_wdata), - .ALU_result(ALU_Result), - .Jal(Jal), - .RegWrite(RegWrite), - .MemtoReg(MemorIOtoReg), - .RegDst(RegDst), - .Sign_extend(Sign_extend), - .clock(cpu_clk), - .reset(rst), - .opcplus4(link_addr) + CpuDecoder dCpuDecoder( + .oDataRead1(read_data_1),//decoder莽職聞膷啪聯暮聡? + .oDataRead2(read_data_2),//decoder莽職聞膷啪聯暮聡?,膷偶聶盲赂艦膷啪聯暮聡艧膰聵呕莽钮聶memory莽職聞膷啪聯暮聡? + .iInstruction(Instruction_o_Ifetc32), + .iMemoryData(r_wdata), + .iAluResult(ALU_Result), + .iIsJal(Jal), + .iDoWriteReg(RegWrite), + .iIsRegFromMem(MemorIOtoReg), + .iIsRdOrRtWritten(RegDst), + .oSignExtentedImmediate(Sign_extend), + .iCpuClock(cpu_clk), + .iCpuReset(rst), + .iJalLinkAddress(link_addr) ); - +///////////// CpuController ///////////// wire MemRead,MemWrite, IORead, IOWrite, ALUSrc, I_format, Sftmd; wire[1:0]ALUOp; - control32 control32_instance( - .Opcode(Instruction_o_Ifetc32[31:26]), - .Function_opcode(Instruction_o_Ifetc32[5:0]), - .Jr(Jr), - .Branch(Branch), - .nBranch(nBranch), - .Jmp(Jmp), - .Jal(Jal), - .Alu_resultHigh(ALU_Result[31:10]), - .RegDST(RegDst), - .MemorIOtoReg(MemorIOtoReg), - .RegWrite(RegWrite), - .MemRead(MemRead), - .MemWrite(MemWrite), - .IORead(IORead), - .IOWrite(IOWrite), - .ALUSrc(ALUSrc), - .Sftmd(Sftmd), - .I_format(I_format), - .ALUOp(ALUOp) - ); - - wire[31:0]write_data_fromMemoryIO; - wire[31:0] m_wdata; // 暮聠聶暮聢掳memory莽職聞膰聲掳膰聧? - assign m_wdata = write_data_fromMemoryIO;//膷偶聶盲赂艦盲拧聼膰聵呕ior_data - wire [31:0] ram_dat_o; - wire [31:0] addr_out; - dmemory32 dmemory32_instance( + CpuController dCpuController( + .Opcode(Instruction_o_Ifetc32[31:26]), + .Function_opcode(Instruction_o_Ifetc32[5:0]), + .Jr(Jr), + .Branch(Branch), + .nBranch(nBranch), + .Jmp(Jmp), + .Jal(Jal), + .Alu_resultHigh(ALU_Result[31:10]), + .RegDST(RegDst), + .MemorIOtoReg(MemorIOtoReg), + .RegWrite(RegWrite), + .MemRead(MemRead), + .MemWrite(MemWrite), + .IORead(IORead), + .IOWrite(IOWrite), + .ALUSrc(ALUSrc), + .Sftmd(Sftmd), + .I_format(I_format), + .ALUOp(ALUOp) + ); +///////////// DataMemory ///////////// + wire[31:0]write_data_fromMemoryIO; + wire[31:0] m_wdata; // 暮聠聶暮聢掳memory莽職聞膰聲掳膰聧? + assign m_wdata = write_data_fromMemoryIO;//膷偶聶盲赂艦盲拧聼膰聵呕ior_data + wire [31:0] ram_dat_o; + wire [31:0] addr_out; + // 这里利用到到了uart IP 核的信号，用来接受数据。 + DataMemory dDataMemory( .ram_clk_i(cpu_clk), .ram_wen_i(MemWrite), .ram_adr_i(addr_out[15:2]), @@ -170,17 +171,15 @@ Ifetc32 Ifetc32_instance( .upg_adr_i(upg_adr_o[13:0]), .upg_dat_i(upg_dat_o), .upg_done_i(upg_done_o) - ); - - + ); - wire [31:0] addr_in; - wire [15:0] ioread_data;//膷偶聶盲赂艦膰聵呕莽钮聫膷偶聡暮陇聞莽聬聠莽職聞16bit膰聲掳膰聧沤 - wire LEDCtrl; - wire SwitchCtrl; - assign addr_in = ALU_Result; //膷偶聶盲赂聙膰沤木暮聧聲莽艧呕盲偶聺膰聦聛暮聬聧暮颅聴莽聸赂暮聬? - MemOrIO MemOrIO_instance( + wire [31:0] addr_in; + wire [15:0] ioread_data;//膷偶聶盲赂艦膰聵呕莽钮聫膷偶聡暮陇聞莽聬聠莽職聞16bit膰聲掳膰聧沤 + wire LEDCtrl; + wire SwitchCtrl; + assign addr_in = ALU_Result; //膷偶聶盲赂聙膰沤木暮聧聲莽艧呕盲偶聺膰聦聛暮聬聧暮颅聴莽聸赂暮聬? + MemOrIO MemOrIO_instance( .mRead(MemRead), // read memory, from Controller .mWrite(MemWrite), // write memory, from Controller .ioRead(IORead), // read IO, from Controller @@ -194,11 +193,9 @@ Ifetc32 Ifetc32_instance( .write_data(write_data_fromMemoryIO), // data to memor y or I/O膹藕聢m_wdata, io_wdata膹藕? .LEDCtrl(LEDCtrl), // LED Chip Select .SwitchCtrl(SwitchCtrl) // Switch Chip Select - ); - - - - executs32 executs32_instance( + ); +///////////////////// CpuExecutor ///////////////////// + CpuExecutor dCpuExecutor( .Read_data_1(read_data_1),//the source of Ainput .Read_data_2(read_data_2),//one of the sources of Binput .Sign_extend(Sign_extend),//one of the sources of Binput llinstruction[31:26] @@ -210,40 +207,40 @@ Ifetc32 Ifetc32_instance( .Sftmd(Sftmd), // means this is a shift instruction .ALUSrc(ALUSrc),//means the 2nd operand is an immediate (except beq,bne) //means l-Type instruction except beq, bne, LW,sw - .I_format(I_format), - .Jr(Jr), - .Zero(Zero),//膷偶聶盲赂艦盲拧聼膰聵呕膷沤膭莽沤聴膰聵呕暮聬艢茅聹?膷艢聛膷藝艂膷藵? - .ALU_Result(ALU_Result), - .Addr_Result(Addr_Result),//This means that upper right output - .PC_plus_4(branch_base_addr)//pc+4 - ); + .I_format(I_format), + .Jr(Jr), + .Zero(Zero),//膷偶聶盲赂艦盲拧聼膰聵呕膷沤膭莽沤聴膰聵呕暮聬艢茅聹?膷艢聛膷藝艂膷藵? + .ALU_Result(ALU_Result), + .Addr_Result(Addr_Result),//This means that upper right output + .PC_plus_4(branch_base_addr)//pc+4 + ); - Switch switch_instance( - .switclk(cpu_clk), - .switchrst(rst), - .switchread(IORead), - .switchctl(SwitchCtrl), - .switchaddr(addr_in[1:0]), - .switchrdata(ioread_data), //膷偶聶盲赂艦膰聵?15盲藵聧莽職聞 - .switch_input(switch2N4) - ); + SwitchDriver dSwitchDriver( + .switclk(cpu_clk), + .switchrst(rst), + .switchread(IORead), + .switchctl(SwitchCtrl), + .switchaddr(addr_in[1:0]), + .switchrdata(ioread_data), //膷偶聶盲赂艦膰聵?15盲藵聧莽職聞 + .switch_input(iSwitches) + ); - LED led_instance( - .led_clk(cpu_clk), - .ledrst(rst), - .ledwrite(IOWrite),//盲钮聨controller膰聺慕莽職聞 - .ledcs(LEDCtrl), - .ledaddr(addr_in[1:0]), - .ledwdata(write_data_fromMemoryIO[15:0]), - .ledout(led2N4) - ); - Tubs tubs_instance( - .clock(fpga_clk), - .reset(fpga_rst), - .IOWrite(IOWrite), - .Dig(Dig), - .Y(Y), - .in_num(write_data_fromMemoryIO) - ); + LightDriver dLightDriver( + .led_clk(cpu_clk), + .ledrst(rst), + .ledwrite(IOWrite),//盲钮聨controller膰聺慕莽職聞 + .ledcs(LEDCtrl), + .ledaddr(addr_in[1:0]), + .ledwdata(write_data_fromMemoryIO[15:0]), + .ledout(oLights) + ); + TubeDriver dTubeDriver( + .clock(iFpgaClk), + .reset(iFpgaRst), + .IOWrite(IOWrite), + .oDigitalTubeNotEnable(oDigitalTubeNotEnable), + .oDigitalTubeShape(oDigitalTubeShape), + .in_num(write_data_fromMemoryIO) + ); endmodule diff --git a/main/verilog/mips_cpu/TOP_all.v b/main/verilog/mips_cpu/TopAll.v similarity index 42% rename from main/verilog/mips_cpu/TOP_all.v rename to main/verilog/mips_cpu/TopAll.v index 87991ec..c1e24ff 100644 --- a/main/verilog/mips_cpu/TOP_all.v +++ b/main/verilog/mips_cpu/TopAll.v @@ -10,22 +10,26 @@ // Description: // ////////////////////////////////////////////////////////////////////////////////// -module TOP_all( -input[23:0]Minisys_Switches, output[23:0]Minisys_Lights, input Minisys_Clock, -input[4:0] Minisys_Button, -input Minisys_Uart_fromPC, output Minisys_Uart_toPC, -output[7:0] Minisys_DigitalTubes_NotEnable,output[7:0]Minisys_DigitalTube_Shape +module TopAll( + input[23:0]Minisys_Switches, + output[23:0]Minisys_Lights, + input Minisys_Clock, + input[4:0] Minisys_Button, + input Minisys_Uart_FromPc, + output Minisys_Uart_ToPc, + output[7:0] Minisys_DigitalTubes_NotEnable, + output[7:0]Minisys_DigitalTube_Shape ); -CPUTOP top_instance( -.switch2N4(Minisys_Switches), -.led2N4(Minisys_Lights), -.fpga_clk(Minisys_Clock), -.start_pg(Minisys_Button[4]), -.fpga_rst(Minisys_Button[3]), -.rx( Minisys_Uart_fromPC), -.tx( Minisys_Uart_toPC), -.Dig(Minisys_DigitalTubes_NotEnable), -.Y(Minisys_DigitalTube_Shape) +CpuTop dCpuTop( + .iSwitches(Minisys_Switches), + .oLights(Minisys_Lights), + .iFpgaClk(Minisys_Clock), + .iStartReceiveCoe(Minisys_Button[4]), + .iFpgaRst(Minisys_Button[3]), + .iFpgaUartFromPc( Minisys_Uart_FromPc), + .oFpgaUartToPc( Minisys_Uart_ToPc), + .oDigitalTubeNotEnable(Minisys_DigitalTubes_NotEnable), + .oDigitalTubeShape(Minisys_DigitalTube_Shape)) ); endmodule diff --git a/main/verilog/mips_cpu/basic_modules/control32.v b/main/verilog/mips_cpu/basic_modules/CpuController.v similarity index 95% rename from main/verilog/mips_cpu/basic_modules/control32.v rename to main/verilog/mips_cpu/basic_modules/CpuController.v index 9619c10..fb4582f 100644 --- a/main/verilog/mips_cpu/basic_modules/control32.v +++ b/main/verilog/mips_cpu/basic_modules/CpuController.v @@ -11,7 +11,7 @@ // ////////////////////////////////////////////////////////////////////////////////// -module control32(Opcode,Function_opcode,Jr,Branch,nBranch,Jmp,Jal, Alu_resultHigh, RegDST, MemorIOtoReg, RegWrite, MemRead, MemWrite, IORead, IOWrite, +module CpuController(Opcode,Function_opcode,Jr,Branch,nBranch,Jmp,Jal, Alu_resultHigh, RegDST, MemorIOtoReg, RegWrite, MemRead, MemWrite, IORead, IOWrite, ALUSrc,ALUOp,Sftmd,I_format); input[5:0] Opcode; // instruction[31:26], opcode input[5:0] Function_opcode; // instructions[5:0], funct diff --git a/main/verilog/mips_cpu/basic_modules/executs32.v b/main/verilog/mips_cpu/basic_modules/CpuExecutor.v similarity index 39% rename from main/verilog/mips_cpu/basic_modules/executs32.v rename to main/verilog/mips_cpu/basic_modules/CpuExecutor.v index 4f7e26e..102124e 100644 --- a/main/verilog/mips_cpu/basic_modules/executs32.v +++ b/main/verilog/mips_cpu/basic_modules/CpuExecutor.v @@ -11,24 +11,24 @@ // ////////////////////////////////////////////////////////////////////////////////// -module executs32( -input[31:0] Read_data_1,//the source of Ainput -input[31:0] Read_data_2,//one of the sources of Binput -input[31:0] Sign_extend,//one of the sources of Binput llinstruction[31:26] -// from lFetch -input[5:0] Function_opcode,//instructions[5:0] -input[5:0]Exe_opcode, -input[1:0]ALUOp,//{(R_format || l_format), (Branch|| nBranch)} -input[4:0]Shamt,//instruction[10:6], the amount of shift bits -input Sftmd, // means this is a shift instruction -input ALUSrc,//means the 2nd operand is an immediate (except beq,bne) - //means l-Type instruction except beq, bne, LW,sw -input I_format, -input Jr, -output Zero,//这个也是计算是否需要跳转 -output [31:0] ALU_Result, -output [31:0]Addr_Result,//This means that upper right output,这个是instruction的addr -input[31:0] PC_plus_4//pc+4 +module CpuExecutor( + input[31:0] Read_data_1,//the source of Ainput + input[31:0] Read_data_2,//one of the sources of Binput + input[31:0] Sign_extend,//one of the sources of Binput llinstruction[31:26] + // from lFetch + input[5:0] Function_opcode,//instructions[5:0] + input[5:0]Exe_opcode, + input[1:0]ALUOp,//{(R_format || l_format), (Branch|| nBranch)} + input[4:0]Shamt,//instruction[10:6], the amount of shift bits + input Sftmd, // means this is a shift instruction + input ALUSrc,//means the 2nd operand is an immediate (except beq,bne) + //means l-Type instruction except beq, bne, LW,sw + input I_format, + input Jr, + output Zero,//这个也是计算是否需要跳转 + output [31:0] ALU_Result, + output [31:0]Addr_Result,//This means that upper right output,这个是instruction的addr + input[31:0] PC_plus_4//pc+4 ); wire[31:0]Ainput,Binput; assign Ainput = Read_data_1; @@ -36,7 +36,7 @@ input[31:0] PC_plus_4//pc+4 wire[2:0] ALU_ctL; wire[5:0] Exe_code; -assign Exe_code = ( I_format==0) ? Function_opcode : { 3'b000 , Exe_opcode[2:0] }; + assign Exe_code = ( I_format==0) ? Function_opcode : { 3'b000 , Exe_opcode[2:0] }; assign ALU_ctL[0] = (Exe_code[0] | Exe_code[3]) & ALUOp[1]; assign ALU_ctL[1] = ((!Exe_code[2]) | (!ALUOp[1])); @@ -60,50 +60,50 @@ assign Exe_code = ( I_format==0) ? Function_opcode : { 3'b000 , Exe_opcode[2:0] default:ALU_output_mux = 32'h00000000; endcase end -////////////////////////////// -wire[2:0] Sftm; -assign Sftm = Function_opcode[2:0]; //the code of shift operations -reg[31:0] Shift_Result; //the result of shift operation -always @* begin// six types of shift instructions -if(Sftmd) - case(Sftm[2:0]) - 3'b000:Shift_Result =Binput<> Shamt; //Srl rd,rt,shamt 00010 - 3'b100:Shift_Result = Binput<>Ainput; //Srlv rd,rt,rs 000110 - 3'b011:Shift_Result = $signed(Binput) >>>Shamt; //Sra rd,rt,shamt 00011 这个有可能有sign - 3'b111:Shift_Result =$signed(Binput) >>>Ainput; //Srav rd,rt,rs 00111 - default:Shift_Result= Binput; - endcase -else - Shift_Result = Binput; -end + ////////////////////////////// + wire[2:0] Sftm; + assign Sftm = Function_opcode[2:0]; //the code of shift operations + reg[31:0] Shift_Result; //the result of shift operation + always @* begin// six types of shift instructions + if(Sftmd) + case(Sftm[2:0]) + 3'b000:Shift_Result =Binput<> Shamt; //Srl rd,rt,shamt 00010 + 3'b100:Shift_Result = Binput<>Ainput; //Srlv rd,rt,rs 000110 + 3'b011:Shift_Result = $signed(Binput) >>>Shamt; //Sra rd,rt,shamt 00011 这个有可能有sign + 3'b111:Shift_Result =$signed(Binput) >>>Ainput; //Srav rd,rt,rs 00111 + default:Shift_Result= Binput; + endcase + else + Shift_Result = Binput; + end ////////////////////////////////////////////////////////////////////// always @* begin //set type operation (slt, slti, sltu, sltiu) if(((ALU_ctL==3'b111) && (Exe_code[3]==1)) || (I_format==1 && ALU_ctL[2:1]==2'b11)) - reg_ALU_Result[31:0] = (Exe_code[2:0] == 3'b011) ? Ainput < Binput : $signed(Ainput) < $signed(Binput); -// if((ALU_ctL==3'b111) && (Exe_code[0]==1)) begin -// reg_ALU_Result = (Ainput< Binput) ? 32'd1 : 32'd0; -// end -// else if((ALU_ctL ==3'b111 && Exe_code[3:0]==4'b1010)||(ALU_ctL ==3'b110 && Exe_code[3:0]==4'b0010))begin -// reg_ALU_Result = ($signed(Ainput) < $signed(Binput)) ? 32'd1 : 32'd0; -// end - //lui operation - else if((ALU_ctL==3'b101) && (I_format==1)) begin - reg_ALU_Result[31:0]={Binput[15:0],{16{1'b0}}}; + reg_ALU_Result[31:0] = (Exe_code[2:0] == 3'b011) ? Ainput < Binput : $signed(Ainput) < $signed(Binput); + // if((ALU_ctL==3'b111) && (Exe_code[0]==1)) begin + // reg_ALU_Result = (Ainput< Binput) ? 32'd1 : 32'd0; + // end + // else if((ALU_ctL ==3'b111 && Exe_code[3:0]==4'b1010)||(ALU_ctL ==3'b110 && Exe_code[3:0]==4'b0010))begin + // reg_ALU_Result = ($signed(Ainput) < $signed(Binput)) ? 32'd1 : 32'd0; + // end + //lui operation + else if((ALU_ctL==3'b101) && (I_format==1)) begin + reg_ALU_Result[31:0]={Binput[15:0],{16{1'b0}}}; + end + //shift operation + else if(Sftmd==1) begin + reg_ALU_Result = Shift_Result; + end + //other types of operation in ALU (arithmatic or logic calculation) + else begin + reg_ALU_Result = ALU_output_mux[31:0]; + end end - //shift operation - else if(Sftmd==1) begin - reg_ALU_Result = Shift_Result; - end - //other types of operation in ALU (arithmatic or logic calculation) - else begin - reg_ALU_Result = ALU_output_mux[31:0]; - end -end -/////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////// -assign Zero = (ALU_output_mux==32'h00000000)? 1'b1:1'b0;//1代表等于，0代表不等于 + assign Zero = (ALU_output_mux==32'h00000000)? 1'b1:1'b0;//1代表等于，0代表不等于 endmodule \ No newline at end of file diff --git a/main/verilog/mips_cpu/basic_modules/dmemory32.v b/main/verilog/mips_cpu/basic_modules/DataMemory.v similarity index 34% rename from main/verilog/mips_cpu/basic_modules/dmemory32.v rename to main/verilog/mips_cpu/basic_modules/DataMemory.v index 215fde5..407d34a 100644 --- a/main/verilog/mips_cpu/basic_modules/dmemory32.v +++ b/main/verilog/mips_cpu/basic_modules/DataMemory.v @@ -11,30 +11,30 @@ // ////////////////////////////////////////////////////////////////////////////////// -module dmemory32 ( -input ram_clk_i, // from CPU top -input ram_wen_i, // from Controller -input [13:0] ram_adr_i, // from alu_result of ALU -input [31:0] ram_dat_i, // from read_data_2 of Decoder -output [31:0] ram_dat_o, // the data read from data-ram -// UART Programmer Pinouts -input upg_rst_i, // UPG reset (Active High) -input upg_clk_i, // UPG ram_clk_i (10MHz) -input upg_wen_i, // UPG write enable -input [13:0] upg_adr_i, // UPG write address -input [31:0] upg_dat_i, // UPG write data -input upg_done_i // 1 if programming is finished -); -wire ram_clk = !ram_clk_i; -/* CPU work on normal mode when kickOff is 1. CPU work on Uart communicate mode when kickOff is 0.*/ -wire kickOff = upg_rst_i | (~upg_rst_i & upg_done_i); -RAM ram ( -.clka (kickOff ? ram_clk : upg_clk_i), -.wea (kickOff ? ram_wen_i : upg_wen_i), -.addra (kickOff ? ram_adr_i : upg_adr_i), -.dina (kickOff ? ram_dat_i : upg_dat_i), -.douta (ram_dat_o) +module DataMemory ( + input ram_clk_i, // from CPU top + input ram_wen_i, // from Controller + input [13:0] ram_adr_i, // from alu_result of ALU + input [31:0] ram_dat_i, // from read_data_2 of Decoder + output [31:0] ram_dat_o, // the data read from data-ram + // UART Programmer Pinouts + input upg_rst_i, // UPG reset (Active High) + input upg_clk_i, // UPG ram_clk_i (10MHz) + input upg_wen_i, // UPG write enable + input [13:0] upg_adr_i, // UPG write address + input [31:0] upg_dat_i, // UPG write data + input upg_done_i // 1 if programming is finished ); + wire ram_clk = !ram_clk_i; + /* CPU work on normal mode when kickOff is 1. CPU work on Uart communicate mode when kickOff is 0.*/ + wire kickOff = upg_rst_i | (~upg_rst_i & upg_done_i); + RAM ram ( + .clka (kickOff ? ram_clk : upg_clk_i), + .wea (kickOff ? ram_wen_i : upg_wen_i), + .addra (kickOff ? ram_adr_i : upg_adr_i), + .dina (kickOff ? ram_dat_i : upg_dat_i), + .douta (ram_dat_o) + ); //assign upg_wen_i=upg_wen_o & upg_adr_o[14]; endmodule diff --git a/main/verilog/mips_cpu/basic_modules/LED.v b/main/verilog/mips_cpu/basic_modules/LightDriver.v similarity index 94% rename from main/verilog/mips_cpu/basic_modules/LED.v rename to main/verilog/mips_cpu/basic_modules/LightDriver.v index f5c0127..d50dad3 100644 --- a/main/verilog/mips_cpu/basic_modules/LED.v +++ b/main/verilog/mips_cpu/basic_modules/LightDriver.v @@ -11,7 +11,7 @@ // ////////////////////////////////////////////////////////////////////////////////// -module LED(led_clk, ledrst, ledwrite, ledcs, ledaddr,ledwdata, ledout); +module LightDriver(led_clk, ledrst, ledwrite, ledcs, ledaddr,ledwdata, ledout); input led_clk; // 时钟信号 input ledrst; // 复位信号 input ledwrite; // 写信号 diff --git a/main/verilog/mips_cpu/basic_modules/switch.v b/main/verilog/mips_cpu/basic_modules/SwitchDriver.v similarity index 93% rename from main/verilog/mips_cpu/basic_modules/switch.v rename to main/verilog/mips_cpu/basic_modules/SwitchDriver.v index f3fe5c2..19d0af5 100644 --- a/main/verilog/mips_cpu/basic_modules/switch.v +++ b/main/verilog/mips_cpu/basic_modules/SwitchDriver.v @@ -11,7 +11,7 @@ // ////////////////////////////////////////////////////////////////////////////////// -module Switch(switclk, switchrst, switchread, switchctl,switchaddr, switchrdata, switch_input); +module SwitchDriver(switclk, switchrst, switchread, switchctl,switchaddr, switchrdata, switch_input); input switclk; // 时钟信号 input switchrst; // 复位信号 input switchctl; // 从memorio来的switch片 !!!!!!!!!! diff --git a/main/verilog/mips_cpu/basic_modules/digital_tube.v b/main/verilog/mips_cpu/basic_modules/TubeDriver.v similarity index 92% rename from main/verilog/mips_cpu/basic_modules/digital_tube.v rename to main/verilog/mips_cpu/basic_modules/TubeDriver.v index cb6fb10..b202495 100644 --- a/main/verilog/mips_cpu/basic_modules/digital_tube.v +++ b/main/verilog/mips_cpu/basic_modules/TubeDriver.v @@ -1,15 +1,15 @@ `timescale 1ns / 1ps -module Tubs(clock, reset, IOWrite, Dig, Y, in_num); +module TubeDriver(clock, reset, IOWrite, oDigitalTubeNotEnable, oDigitalTubeShape, in_num); input clock, reset, IOWrite; - output wire [7:0] Dig; - output wire [7:0] Y; + output wire [7:0] oDigitalTubeNotEnable; + output wire [7:0] oDigitalTubeShape; input [31:0] in_num; // The input from the top module. Just like the led. reg [7:0] Dig_r; // The rnverse of Digital selection. reg [6:0] Y_r; // The reverse of Digital. wire rst; - assign Dig = ~Dig_r; - assign Y = {{1'b1},{~Y_r}}; //this is notenable, + assign oDigitalTubeNotEnable = ~Dig_r; + assign oDigitalTubeShape = {{1'b1},{~Y_r}}; //this is notenable, assign rst =~reset;//有效是1 reg clk; reg [31:0] clk_cnt; -- Gitee From 77c9dab7aef185d8e6521b17724988ba7338dfae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 17:02:49 +0800 Subject: [PATCH 47/57] =?UTF-8?q?feat(mips=20cpu):=20LightDriver=20?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E8=A7=84=E8=8C=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../mips_cpu/basic_modules/LightDriver.v | 39 +++++++++---------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/main/verilog/mips_cpu/basic_modules/LightDriver.v b/main/verilog/mips_cpu/basic_modules/LightDriver.v index d50dad3..3798319 100644 --- a/main/verilog/mips_cpu/basic_modules/LightDriver.v +++ b/main/verilog/mips_cpu/basic_modules/LightDriver.v @@ -4,38 +4,37 @@ // Engineer: 张力宇 // // Create Date: 2022/05/07 12:58:45 -// Module Name: CPU_TOP +// Module Name: LightDriver // Project Name: MIPS Single Cycle CPU // Target Devices: Xilinx Board. Tested on MINISYS. // Description: // ////////////////////////////////////////////////////////////////////////////////// -module LightDriver(led_clk, ledrst, ledwrite, ledcs, ledaddr,ledwdata, ledout); - input led_clk; // 时钟信号 - input ledrst; // 复位信号 - input ledwrite; // 写信号 - input ledcs; // 从memorio来的LED片选信号 !!!!!!!!!!!!!! - input[1:0] ledaddr; // 到LED模块的地址低端 !!!!!!!!!!!!!!!!!!!! - input[15:0] ledwdata; // 写到LED模块的数据，注意数据线只有16根 - output[23:0] ledout; // 向板子上输出的24位LED信号 +module LightDriver(iCpuClock, iCpuReset, iDoIOWrite, iDoLedWrite, iLightAddress,iLightDataToWrite, oFpgaLights); + input iCpuClock; // 时钟信号 + input iCpuReset; // 复位信号 + input iDoIOWrite; // 写信号 + input iDoLedWrite; // 从memorio来的LED片选信号 !!!!!!!!!!!!!! + input[1:0] iLightAddress; // 到LED模块的地址低端 !!!!!!!!!!!!!!!!!!!! + input[15:0] iLightDataToWrite; // 写到LED模块的数据，注意数据线只有16根 + output reg [23:0] oFpgaLights; // 向板子上输出的24位LED信号 - reg [23:0] ledout; - always@(posedge led_clk or posedge ledrst) begin - if(ledrst) begin - ledout <= 24'h000000; + always@(posedge iCpuClock or posedge iCpuReset) begin + if(iCpuReset) begin + oFpgaLights <= 24'h000000; end - else if(ledcs && ledwrite) begin - if(ledaddr == 2'b00) - ledout[23:0] <= { ledout[23:16], ledwdata[15:0] }; - else if(ledaddr == 2'b10 ) - ledout[23:0] <= { ledwdata[7:0], ledout[15:0] }; + else if(iDoLedWrite && iDoIOWrite) begin + if(iLightAddress == 2'b00) + oFpgaLights[15:0] <= iLightDataToWrite[15:0]; + else if(iLightAddress == 2'b10 ) + oFpgaLights[23:16] <= iLightDataToWrite[7:0]; else - ledout <= ledout; + oFpgaLights <= oFpgaLights; end else begin - ledout <= ledout; + oFpgaLights <= oFpgaLights; end end endmodule -- Gitee From 218ccbc2d803c7223ed29aafb673a8255011e635 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Sat, 28 May 2022 17:04:44 +0800 Subject: [PATCH 48/57] =?UTF-8?q?feat(mips=20cpu):=20driver.v=E6=8D=A2?= =?UTF-8?q?=E6=96=87=E4=BB=B6=E5=A4=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/mips_cpu/{basic_modules => drivers}/LightDriver.v | 0 main/verilog/mips_cpu/{basic_modules => drivers}/SwitchDriver.v | 0 main/verilog/mips_cpu/{basic_modules => drivers}/TubeDriver.v | 0 3 files changed, 0 insertions(+), 0 deletions(-) rename main/verilog/mips_cpu/{basic_modules => drivers}/LightDriver.v (100%) rename main/verilog/mips_cpu/{basic_modules => drivers}/SwitchDriver.v (100%) rename main/verilog/mips_cpu/{basic_modules => drivers}/TubeDriver.v (100%) diff --git a/main/verilog/mips_cpu/basic_modules/LightDriver.v b/main/verilog/mips_cpu/drivers/LightDriver.v similarity index 100% rename from main/verilog/mips_cpu/basic_modules/LightDriver.v rename to main/verilog/mips_cpu/drivers/LightDriver.v diff --git a/main/verilog/mips_cpu/basic_modules/SwitchDriver.v b/main/verilog/mips_cpu/drivers/SwitchDriver.v similarity index 100% rename from main/verilog/mips_cpu/basic_modules/SwitchDriver.v rename to main/verilog/mips_cpu/drivers/SwitchDriver.v diff --git a/main/verilog/mips_cpu/basic_modules/TubeDriver.v b/main/verilog/mips_cpu/drivers/TubeDriver.v similarity index 100% rename from main/verilog/mips_cpu/basic_modules/TubeDriver.v rename to main/verilog/mips_cpu/drivers/TubeDriver.v -- Gitee From f85db235175558c31f70125446d512a64d8e8e94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 00:18:56 +0800 Subject: [PATCH 49/57] =?UTF-8?q?fix(mips)=20=E5=9C=BA=E6=99=AF2=20?= =?UTF-8?q?=E9=80=9A=E8=BF=87=E6=B5=8B=E8=AF=95=E3=80=82=20=E4=BF=AE?= =?UTF-8?q?=E5=A4=8D=E4=BA=86n=E5=AD=98=E5=82=A8=E9=97=AE=E9=A2=98?= =?UTF-8?q?=E3=80=81=E6=B5=AE=E7=82=B9=E6=95=B0=E8=A1=A8=E7=A4=BA=E4=B8=8D?= =?UTF-8?q?=E5=90=88=E8=A6=81=E6=B1=82=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/mips/commons/std_algorithm.macro.mips | 18 +++---- main/mips/commons/std_io_minisys.macro.mips | 2 +- main/mips/cpu_test/situation2.mips | 54 ++++++++++++++++----- 3 files changed, 53 insertions(+), 21 deletions(-) diff --git a/main/mips/commons/std_algorithm.macro.mips b/main/mips/commons/std_algorithm.macro.mips index 5a2b28b..3e968b0 100644 --- a/main/mips/commons/std_algorithm.macro.mips +++ b/main/mips/commons/std_algorithm.macro.mips @@ -26,13 +26,13 @@ .end_macro # 姹侷EEE 754 鍗曠簿搴︽诞鐐规暟缂栫爜鐨勭鍙蜂綅鍜屾寚鏁颁綅 锛堜竴鍏1+8=9浣嶏級銆 -# 杈撳叆 register(8浣嶆湁绗﹀彿鏁存暟)锛 杩斿洖register +# 杈撳叆 register(32浣嶆湁绗﹀彿鏁存暟)锛 杩斿洖register # 寤鸿鐨剅egister鏄$a0 -.macro convert_signed8_to_float(%register) - andi %register %register 0xFF # 鍙叧蹇冩渶鍚8浣嶃傝浆鎹负8浣嶆湁绗﹀彿鏁存暟浜嗐 +.macro convert_signed32_to_float(%register) + # 鎴戜滑瀵32浣嶆湁绗﹀彿鏁板仛娴偣鏁拌浆鎹紝鑰屼笉鏄8浣嶃傝繖鏍锋暟鎹泦1鍜屾暟鎹泦3鐨勫鐞嗘墠鏄粺涓鐨勩 # 绗﹀彿浣 锛1浣嶏級 - srl $t0 %register 7 # 鍙栫7浣嶃 + srl $t0 %register 31 # 鍙栫31浣嶃 andi $t0 $t0 1 # 鐜板湪t0涓1琛ㄧず鏄礋鏁帮紝鍚﹀垯鏄鏁般 sll $t1 $t0 8 # 鏀惧湪绗8浣嶏紝鐜板湪t1鏄粨鏋滅殑涓閮ㄥ垎銆7..0鐣欑粰鎸囨暟浣 @@ -40,9 +40,8 @@ # 鍙栫粷瀵瑰 鍒癮0. beq $t0 $zero end_if_getFloat # 濡傛灉鏄鏁板氨涓嶇敤绠′簡銆 a0灏辨槸绛旀銆 # 濡傛灉鏄礋鏁般 - xori %register %register 0xFF # 涓嶆槸0x7F. 鎴戜滑鐜板湪鏄8浣嶆湁绗﹀彿鏁帮紝姹傜浉鍙嶆暟銆 + xori %register %register 0xFFFFFFFF # 涓嶆槸0x7FFFFFFF. 鎴戜滑鐜板湪鏄32浣嶆湁绗﹀彿鏁帮紝姹傜浉鍙嶆暟銆 addi %register %register 1 - andi %register %register 0xFF # 娉ㄦ剰鍘绘帀婧㈠嚭鐨1. 鎴戜滑杩樻槸8浣嶆湁绗﹀彿鏁般 end_if_getFloat: @@ -51,9 +50,10 @@ do_while_case6: srl %register %register 1 # a0鏄8浣嶆湁绗﹀彿姝ｆ暟銆 addi $t3 $t3 1 - bne $t1 $zero do_while_case6 + bne %register $zero do_while_case6 + addi $t3 $t3 -1 addi $t3 $t3 0x7f # 鍔犱笂bias - andi $t3 $t3 0xFF #娉ㄦ剰鎴戜滑杩樻槸8浣嶆暟锛岀幇鍦ㄦ槸娴偣鏁扮殑鎸囨暟浣嶃 + andi $t3 $t3 0xFF #鐜板湪鏄诞鐐规暟鐨勬寚鏁颁綅, 鍙湁8浣嶏紝涓囦竴婧㈠嚭浜嗐 or %register $t3 $t1 # 鍚堝苟涓や釜鏁 -.end_macro \ No newline at end of file +.end_macro diff --git a/main/mips/commons/std_io_minisys.macro.mips b/main/mips/commons/std_io_minisys.macro.mips index aa63df2..d45dc38 100644 --- a/main/mips/commons/std_io_minisys.macro.mips +++ b/main/mips/commons/std_io_minisys.macro.mips @@ -122,7 +122,7 @@ jal read andi $a0 $a0 3 # 鍙彇鏈鍚庝袱浣嶃 # todo 闈炴硶杈撳叆璀﹀憡銆 - lw %register 0($fp) #base + move %register $fp #base for_case4: beq $a0 $zero end_for_case4 add %register %register $s0 # 璁板緱鍚楋紵s0 鍙锛屾案杩滄槸space=44 diff --git a/main/mips/cpu_test/situation2.mips b/main/mips/cpu_test/situation2.mips index 3430344..497fc8c 100644 --- a/main/mips/cpu_test/situation2.mips +++ b/main/mips/cpu_test/situation2.mips @@ -25,10 +25,10 @@ begin: # case0 娴嬭瘯鐘舵侊細璇诲叆閫昏緫鍙俊銆 # 缁撴灉淇濆瓨浣嶇疆 -# n = 44($fp)锛 array = $fp, $fp+4, $fp+8, ... +# n = 176($fp)锛 array = $fp, $fp+4, $fp+8, ... case0: read_8_as_unsigned($s1) # s1=n锛岃〃绀烘暟缁勯暱搴 - sw $s1 44($fp) # 44($fp) 涓烘暟缁勯暱搴 + sw $s1 176($fp) # 176($fp) 涓烘暟缁勯暱搴 bne $s1 $zero end_if_case0_0 jal exception_hint # 濡傛灉鏄0锛屽彧鏄鍛婏紝涓嶉噸鏂拌緭鍏ャ @@ -62,7 +62,7 @@ case0: j begin case1: move $v0 $fp # 鏁版嵁闆0澶 - lw $s1 44($fp) # 鏁扮粍瀹為檯闀垮害n + lw $s1 176($fp) # 鏁扮粍瀹為檯闀垮害n sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 add $v1 $v0 $s1 # 鏁版嵁闆0灏 @@ -80,7 +80,7 @@ case1: j begin case2: move $v0 $fp # 鏁版嵁闆0澶 - lw $s1 44($fp) + lw $s1 176($fp) sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 add $v1 $v0 $s1 # 鏁版嵁闆0灏 @@ -95,7 +95,7 @@ case3: add $v0 $v0 $s0 # 鏁版嵁闆1澶 add $v0 $v0 $s0 # 鏁版嵁闆2澶 - lw $s1 44($fp) + lw $s1 176($fp) sll $s1 $s1 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 add $v1 $v0 $s1 # 鏁版嵁闆2灏 @@ -113,10 +113,21 @@ case3: # 娴嬭瘯鐘舵侊細鍗遍櫓 case4: +#debug + # lw $a0 44($fp) + # write_data_8($a0) + # sleep(2000) + # lw $a0 48($fp) + # write_data_8($a0) + # sleep(2000) + # lw $a0 52($fp) + # write_data_8($a0) + # sleep(2000) + getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご move $v0 $s1 - lw $s2 44($fp) # n + lw $s2 176($fp) # n sll $s2 $s2 2 # 鏁扮粍闀垮害宸︾Щ涓や綅涔4 add $s2 $v0 $s2 # 鏁版嵁闆嗗熬 move $v1 $s2 @@ -135,6 +146,17 @@ case4: # 娴嬭瘯鐘舵侊細 瀵规暟鎹泦0鐨勬暟涔熶笉鍙互姝ｇ‘璇诲彇銆 case5: +#debug + # lw $a0 88($fp) + # write_data_8($a0) + # sleep(2000) + # lw $a0 92($fp) + # write_data_8($a0) + # sleep(2000) + # lw $a0 96($fp) + # write_data_8($a0) + # sleep(2000) + getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご read_8_as_unsigned($a0) @@ -149,15 +171,25 @@ case5: # 娴嬭瘯鐘舵侊細 瀵规暟鎹泦0鐨勬暟鍙互姝ｇ‘璇诲彇锛屽彲浠ュ啓鍑烘诞鐐规暟. case6: +#debug + # lw $a0 132($fp) + # write_data_8($a0) + # sleep(2000) + # lw $a0 136($fp) + # write_data_8($a0) + # sleep(2000) + # lw $a0 140($fp) + # write_data_8($a0) + # sleep(2000) + getBase($s1) # s1 鐜板湪鏄 鏁版嵁闆嗗ご read_8_as_unsigned($a0) sll $a0 $a0 2 # 涓嬫爣*4 add $s1 $s1 $a0 # 鐩爣鍦板潃 - lw $s2 0($s1) # 鐩爣鏁 - - andi $a0 $s2 0xFF # 鍙冭檻8浣 - convert_signed8_to_float($a0) + lw $a0 0($s1) # 鐩爣鏁 + + convert_signed32_to_float($a0) jal write_data # 娉ㄦ剰锛屼笉姝8浣, 鐢ㄥ師鐢熺殑jal write_data銆 sleep(1000) j begin @@ -179,7 +211,7 @@ case7: bne $a0 $a2 begin # 濡傛灉case缂栧彿鍙樺寲锛屽洖鍒癰egin move $a0 $s2 - convert_signed8_to_float($a0) + convert_signed32_to_float($a0) jal write_data sleep(1250) -- Gitee From fd8cadbcadd514e589777baa59d073cc461ff50e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 00:20:36 +0800 Subject: [PATCH 50/57] =?UTF-8?q?fix(verilog):=20=E4=BF=AE=E5=A4=8D?= =?UTF-8?q?=E5=B0=8F=E8=AF=AD=E6=B3=95=E9=94=99=E8=AF=AF=EF=BC=8C=E6=81=A2?= =?UTF-8?q?=E5=A4=8D=E5=8F=AF=E7=BC=96=E8=AF=91=E7=8A=B6=E6=80=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/mips_cpu/CPUTOP.v | 16 +++++++--------- main/verilog/mips_cpu/TopAll.v | 2 +- main/verilog/mips_cpu/basic_modules/CpuDecoder.v | 2 +- 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/main/verilog/mips_cpu/CPUTOP.v b/main/verilog/mips_cpu/CPUTOP.v index e89311d..7525f49 100644 --- a/main/verilog/mips_cpu/CPUTOP.v +++ b/main/verilog/mips_cpu/CPUTOP.v @@ -24,14 +24,6 @@ module CpuTop( output[7:0] oDigitalTubeNotEnable, //which tubs to light output[7:0] oDigitalTubeShape //light what ); -///////////// Cpu Clock ///////////// - wire cpu_clk; - cpuclk cpuclk_instance( - .clk_in1(iFpgaClk), - .clk_out1(cpu_clk), - .clk_out2(upg_clk) - ); - ///////////// UART Programmer Pinouts ///////////// wire upg_clk, upg_clk_o; wire upg_wen_o; //Uart write out enable @@ -62,7 +54,13 @@ module CpuTop( .upg_dat_o(upg_dat_o), .upg_done_o(upg_done_o) ); - +///////////// Cpu Clock ///////////// + wire cpu_clk; + cpuclk cpuclk_instance( + .clk_in1(iFpgaClk), + .clk_out1(cpu_clk), + .clk_out2(upg_clk) + ); ///////////// Ifetc32 和 progrom ///////////// // Control signals wire Branch, nBranch, Jmp, Jal, Jr, Zero, RegWrite, RegDst; diff --git a/main/verilog/mips_cpu/TopAll.v b/main/verilog/mips_cpu/TopAll.v index c1e24ff..ef40fee 100644 --- a/main/verilog/mips_cpu/TopAll.v +++ b/main/verilog/mips_cpu/TopAll.v @@ -30,6 +30,6 @@ CpuTop dCpuTop( .iFpgaUartFromPc( Minisys_Uart_FromPc), .oFpgaUartToPc( Minisys_Uart_ToPc), .oDigitalTubeNotEnable(Minisys_DigitalTubes_NotEnable), - .oDigitalTubeShape(Minisys_DigitalTube_Shape)) + .oDigitalTubeShape(Minisys_DigitalTube_Shape) ); endmodule diff --git a/main/verilog/mips_cpu/basic_modules/CpuDecoder.v b/main/verilog/mips_cpu/basic_modules/CpuDecoder.v index f8fcbea..a5764ee 100644 --- a/main/verilog/mips_cpu/basic_modules/CpuDecoder.v +++ b/main/verilog/mips_cpu/basic_modules/CpuDecoder.v @@ -10,7 +10,7 @@ // Description: // ////////////////////////////////////////////////////////////////////////////////// -module InstructionDecoder(oDataRead1,oDataRead2,iInstruction,iMemoryData,iAluResult, +module CpuDecoder(oDataRead1,oDataRead2,iInstruction,iMemoryData,iAluResult, iIsJal,iDoWriteReg,iIsRegFromMem,iIsRdOrRtWritten,oSignExtentedImmediate,iCpuClock,iCpuReset,iJalLinkAddress); //////////////// 输入输出 //////////////// output[31:0] oDataRead1; // 输出的第一操作数 -- Gitee From 78fea2df07ebfee885122ace6bf7e550705018d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 00:21:01 +0800 Subject: [PATCH 51/57] =?UTF-8?q?fix(verilog):=20=E4=BF=AE=E5=A4=8Dip?= =?UTF-8?q?=E6=A0=B8=E4=BD=8D=E7=BD=AE=EF=BC=8C=E5=88=86=E6=96=87=E4=BB=B6?= =?UTF-8?q?=E5=A4=B9=E5=AD=98=E5=82=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/ip/RAM.xci | 267 ------- .../xgui/uart_bmpg_v1_3.tcl | 71 -- main/verilog/ip/clk_wiz_0.xci | 677 ----------------- main/verilog/ip/cpuclk.xci | 688 ------------------ main/verilog/ip/prgrom.xci | 267 ------- main/verilog/ip/uart_bmpg_0.xci | 41 -- 6 files changed, 2011 deletions(-) delete mode 100644 main/verilog/ip/RAM.xci delete mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl delete mode 100644 main/verilog/ip/clk_wiz_0.xci delete mode 100644 main/verilog/ip/cpuclk.xci delete mode 100644 main/verilog/ip/prgrom.xci delete mode 100644 main/verilog/ip/uart_bmpg_0.xci diff --git a/main/verilog/ip/RAM.xci b/main/verilog/ip/RAM.xci deleted file mode 100644 index 5497222..0000000 --- a/main/verilog/ip/RAM.xci +++ /dev/null @@ -1,267 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - RAM - - - 4096 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - OTHER - NONE - 8192 - 32 - READ_WRITE - OTHER - NONE - 8192 - 32 - READ_WRITE - - 100000000 - 0.000 - 14 - 14 - 1 - 4 - 0 - 1 - 9 - 0 - 1 - 14 - NONE - 0 - 0 - 0 - ./ - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Estimated Power for IP : 13.776802 mW - artix7 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RAM.mem - RAM.mif - 0 - 1 - 0 - 0 - 1 - 16384 - 16384 - 32 - 32 - 0 - 0 - CE - CE - ALL - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 16384 - 16384 - WRITE_FIRST - WRITE_FIRST - 32 - 32 - artix7 - 4 - Memory_Slave - AXI4_Full - false - Minimum_Area - false - 9 - NONE - ../../../../../main/mips/coe/dmem32.coe - ALL - RAM - false - false - false - false - false - false - false - false - false - Always_Enabled - Always_Enabled - Single_Bit_Error_Injection - false - Native - true - no_mem_loaded - Single_Port_RAM - WRITE_FIRST - WRITE_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 0 - 0 - 0 - 8kx2 - false - false - 32 - 32 - false - false - false - false - 0 - false - false - CE - CE - SYNC - false - false - false - false - false - false - false - 16384 - 32 - 32 - No_ECC - false - false - false - Stand_Alone - artix7 - - xc7a100t - fgg484 - VERILOG - - MIXED - -1 - - TRUE - TRUE - 1aa89aa0844684f9 - IP_Flow - 1 - TRUE - . - - . - 2017.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl deleted file mode 100644 index d789dd1..0000000 --- a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl +++ /dev/null @@ -1,71 +0,0 @@ -# Definitional proc to organize widgets for parameters. -proc init_gui { IPINST } { - ipgui::add_param $IPINST -name "Component_Name" - #Adding Page - set page [ipgui::add_page $IPINST -name "page"] - set_property tooltip {page} ${page} - ipgui::add_param $IPINST -name "Reset" -parent ${page} - ipgui::add_param $IPINST -name "Input_Clock_Freqency" -parent ${page} - ipgui::add_param $IPINST -name "Baud_Rate" -parent ${page} - ipgui::add_param $IPINST -name "Data_Bits" -parent ${page} - ipgui::add_param $IPINST -name "Parity" -parent ${page} - ipgui::add_param $IPINST -name "Stop_Bits" -parent ${page} - - -} - -proc update_PARAM_VALUE.Baud_Rate { PARAM_VALUE.Baud_Rate } { - # Procedure called to update Baud_Rate when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.Baud_Rate { PARAM_VALUE.Baud_Rate } { - # Procedure called to validate Baud_Rate - return true -} - -proc update_PARAM_VALUE.Data_Bits { PARAM_VALUE.Data_Bits } { - # Procedure called to update Data_Bits when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.Data_Bits { PARAM_VALUE.Data_Bits } { - # Procedure called to validate Data_Bits - return true -} - -proc update_PARAM_VALUE.Input_Clock_Freqency { PARAM_VALUE.Input_Clock_Freqency } { - # Procedure called to update Input_Clock_Freqency when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.Input_Clock_Freqency { PARAM_VALUE.Input_Clock_Freqency } { - # Procedure called to validate Input_Clock_Freqency - return true -} - -proc update_PARAM_VALUE.Parity { PARAM_VALUE.Parity } { - # Procedure called to update Parity when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.Parity { PARAM_VALUE.Parity } { - # Procedure called to validate Parity - return true -} - -proc update_PARAM_VALUE.Reset { PARAM_VALUE.Reset } { - # Procedure called to update Reset when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.Reset { PARAM_VALUE.Reset } { - # Procedure called to validate Reset - return true -} - -proc update_PARAM_VALUE.Stop_Bits { PARAM_VALUE.Stop_Bits } { - # Procedure called to update Stop_Bits when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.Stop_Bits { PARAM_VALUE.Stop_Bits } { - # Procedure called to validate Stop_Bits - return true -} - - diff --git a/main/verilog/ip/clk_wiz_0.xci b/main/verilog/ip/clk_wiz_0.xci deleted file mode 100644 index 7511ea8..0000000 --- a/main/verilog/ip/clk_wiz_0.xci +++ /dev/null @@ -1,677 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - clk_wiz_0 - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0.000 - - - - 100000000 - 0.000 - 1 - LEVEL_HIGH - - - - 100000000 - 0.000 - - 100000000 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 100.0 - 0000 - 0000 - 23.000 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 23.000 - 0.000 - 50.000 - 23 - 0.000 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - VCO - clk_in_sel - clk_out1 - clk_out2 - clk_out3 - clk_out4 - clk_out5 - clk_out6 - clk_out7 - CLK_VALID - NA - daddr - dclk - den - din - 0000 - 1 - 0.23 - 0.23 - 0.23 - 0.23 - 0.23 - 0.23 - dout - drdy - dwe - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - FDBK_AUTO - 0000 - 0000 - 0 - Input Clock Freq (MHz) Input Jitter (UI) - __primary_________100.000____________0.010 - no_secondary_input_clock - input_clk_stopped - 0 - Units_MHz - No_Jitter - locked - 0000 - 0000 - 0000 - false - false - false - false - false - false - false - false - OPTIMIZED - 46.000 - 0.000 - FALSE - 10.000 - 10.000 - 40.000 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - ZHOLD - 5 - None - 0.010 - 0.010 - FALSE - 1 - Output Output Phase Duty Cycle Pk-to-Pk Phase - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1____23.000______0.000______50.0______342.117____303.235 - no_CLK_OUT2_output - no_CLK_OUT3_output - no_CLK_OUT4_output - no_CLK_OUT5_output - no_CLK_OUT6_output - no_CLK_OUT7_output - 0 - 0 - WAVEFORM - UNKNOWN - false - false - false - false - false - OPTIMIZED - 1 - 0.000 - 1.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - No notes - 0.010 - power_down - 0000 - 1 - clk_in1 - PLL - AUTO - 100.000 - 0.010 - 10.000 - Single_ended_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - 0 - reset - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 4000 - 0.004 - STATUS - 11 - 32 - 100.0 - 100.0 - 100.0 - 100.0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - clk_wiz_0 - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 0.010 - 100.0 - 0.010 - BUFG - 342.117 - false - 303.235 - 50.000 - 23 - 0.000 - 1 - true - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - Custom - Custom - clk_in_sel - clk_out1 - false - clk_out2 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - clk_wiz_0 - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 46 - 0.000 - false - 10.000 - 10.000 - 40 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - ZHOLD - 5 - None - 0.010 - 0.010 - false - 1 - false - false - WAVEFORM - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 10.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - PLL - mmcm_adv - 100.000 - 0.010 - 10.000 - Single_ended_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - false - false - false - false - false - false - false - true - false - false - false - false - false - false - true - false - false - false - false - false - artix7 - - xc7a100t - fgg484 - VERILOG - - MIXED - -1 - - TRUE - TRUE - IP_Flow - 3 - TRUE - . - - . - 2017.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/main/verilog/ip/cpuclk.xci b/main/verilog/ip/cpuclk.xci deleted file mode 100644 index 037a865..0000000 --- a/main/verilog/ip/cpuclk.xci +++ /dev/null @@ -1,688 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - cpuclk - - - false - 100000000 - false - 100000000 - false - 100000000 - false - 100000000 - - - - 100000000 - 0.000 - - - - 100000000 - 0.000 - - - - 100000000 - 0.000 - 1 - LEVEL_HIGH - - - - 100000000 - 0.000 - - 100000000 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - MMCM - cddcdone - cddcreq - 0000 - 0000 - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 100.0 - 0000 - 0000 - 23.000 - 0000 - 0000 - 10.000 - BUFG - 50.0 - false - 23.000 - 0.000 - 50.000 - 23 - 0.000 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.0 - false - 10.000 - 0.000 - 50.000 - 10 - 0.000 - 1 - 1 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - 0000 - 0000 - 100.000 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - BUFG - 50.000 - false - 100.000 - 0.000 - 50.000 - 100.000 - 0.000 - 1 - 0 - VCO - clk_in_sel - clk_out1 - clk_out2 - clk_out3 - clk_out4 - clk_out5 - clk_out6 - clk_out7 - CLK_VALID - NA - daddr - dclk - den - din - 0000 - 1 - 2.3 - 0.23 - 0.23 - 0.23 - 0.23 - 0.23 - dout - drdy - dwe - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - FDBK_AUTO - 0000 - 0000 - 0 - Input Clock Freq (MHz) Input Jitter (UI) - __primary_________100.000____________0.010 - no_secondary_input_clock - input_clk_stopped - 0 - Units_MHz - No_Jitter - locked - 0000 - 0000 - 0000 - false - false - false - false - false - false - false - false - OPTIMIZED - 46.000 - 0.000 - FALSE - 10.000 - 10.000 - 40.000 - 0.500 - 0.000 - FALSE - 92 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - 1 - 0.500 - 0.000 - FALSE - FALSE - ZHOLD - 5 - None - 0.010 - 0.010 - FALSE - 2 - Output Output Phase Duty Cycle Pk-to-Pk Phase - Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - clk_out1____23.000______0.000______50.0______342.117____303.235 - clk_out2____10.000______0.000______50.0______391.228____303.235 - no_CLK_OUT3_output - no_CLK_OUT4_output - no_CLK_OUT5_output - no_CLK_OUT6_output - no_CLK_OUT7_output - 0 - 0 - WAVEFORM - UNKNOWN - false - false - false - false - false - OPTIMIZED - 1 - 0.000 - 1.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - No notes - 0.010 - power_down - 0000 - 1 - clk_in1 - PLL - AUTO - 100.000 - 0.010 - 10.000 - Single_ended_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - 0 - reset - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 4000 - 0.004 - STATUS - 11 - 32 - 100.0 - 100.0 - 100.0 - 100.0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - cpuclk - MMCM - false - empty - cddcdone - cddcreq - clkfb_in_n - clkfb_in - clkfb_in_p - SINGLE - clkfb_out_n - clkfb_out - clkfb_out_p - clkfb_stopped - 100.0 - 0.010 - 100.0 - 0.010 - BUFG - 342.117 - false - 303.235 - 50.000 - 23 - 0.000 - 1 - true - BUFG - 391.228 - false - 303.235 - 50.000 - 10 - 0.000 - 1 - true - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - BUFG - 0.0 - false - 0.0 - 50.000 - 100.000 - 0.000 - 1 - false - 600.000 - Custom - Custom - clk_in_sel - clk_out1 - false - clk_out2 - false - clk_out3 - false - clk_out4 - false - clk_out5 - false - clk_out6 - false - clk_out7 - false - CLK_VALID - auto - cpuclk - daddr - dclk - den - Custom - Custom - din - dout - drdy - dwe - false - false - false - false - false - false - false - false - false - FDBK_AUTO - input_clk_stopped - frequency - Enable_AXI - Units_MHz - Units_UI - UI - No_Jitter - locked - OPTIMIZED - 46 - 0.000 - false - 10.000 - 10.000 - 40 - 0.500 - 0.000 - false - 92 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - 1 - 0.500 - 0.000 - false - false - ZHOLD - 5 - None - 0.010 - 0.010 - false - 2 - false - false - WAVEFORM - false - UNKNOWN - OPTIMIZED - 4 - 0.000 - 10.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - 1 - 0.500 - 0.000 - CLKFBOUT - SYSTEM_SYNCHRONOUS - 1 - None - 0.010 - power_down - 1 - clk_in1 - PLL - mmcm_adv - 100.000 - 0.010 - 10.000 - Single_ended_clock_capable_pin - psclk - psdone - psen - psincdec - 100.0 - REL_PRIMARY - Custom - reset - ACTIVE_HIGH - 100.000 - 0.010 - 10.000 - clk_in2 - Single_ended_clock_capable_pin - CENTER_HIGH - 250 - 0.004 - STATUS - empty - 100.0 - 100.0 - 100.0 - 100.0 - false - false - false - false - false - false - false - true - false - false - false - false - false - false - true - false - false - false - false - false - artix7 - - xc7a100t - fgg484 - VERILOG - - MIXED - -1 - - TRUE - TRUE - IP_Flow - 3 - TRUE - . - - . - 2017.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/main/verilog/ip/prgrom.xci b/main/verilog/ip/prgrom.xci deleted file mode 100644 index 8a97daa..0000000 --- a/main/verilog/ip/prgrom.xci +++ /dev/null @@ -1,267 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - prgrom - - - 4096 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - OTHER - NONE - 8192 - 32 - READ_WRITE - OTHER - NONE - 8192 - 32 - READ_WRITE - - 100000000 - 0.000 - 14 - 14 - 1 - 4 - 0 - 1 - 9 - 0 - 1 - 14 - NONE - 0 - 0 - 0 - ./ - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Estimated Power for IP : 13.776802 mW - artix7 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - prgrom.mem - prgrom.mif - 0 - 1 - 0 - 0 - 1 - 16384 - 16384 - 32 - 32 - 0 - 0 - CE - CE - ALL - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 16384 - 16384 - WRITE_FIRST - WRITE_FIRST - 32 - 32 - artix7 - 4 - Memory_Slave - AXI4_Full - false - Minimum_Area - false - 9 - NONE - ../../../../../main/mips/coe/prgmip32.coe - ALL - prgrom - false - false - false - false - false - false - false - false - false - Always_Enabled - Always_Enabled - Single_Bit_Error_Injection - false - Native - true - no_mem_loaded - Single_Port_RAM - WRITE_FIRST - WRITE_FIRST - 0 - 0 - BRAM - 0 - 100 - 100 - 50 - 0 - 0 - 0 - 8kx2 - false - false - 32 - 32 - false - false - false - false - 0 - false - false - CE - CE - SYNC - false - false - false - false - false - false - false - 16384 - 32 - 32 - No_ECC - false - false - false - Stand_Alone - artix7 - - xc7a100t - fgg484 - VERILOG - - MIXED - -1 - - TRUE - TRUE - a14d160ef830f38c - IP_Flow - 1 - TRUE - . - - . - 2017.4 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - diff --git a/main/verilog/ip/uart_bmpg_0.xci b/main/verilog/ip/uart_bmpg_0.xci deleted file mode 100644 index 6d7acbc..0000000 --- a/main/verilog/ip/uart_bmpg_0.xci +++ /dev/null @@ -1,41 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - uart_bmpg_0 - - - 128000 bps - uart_bmpg_0 - 8 bits - 10 MHz - No - Active High - 1 bit(s) - artix7 - - xc7a100t - fgg484 - VERILOG - - MIXED - -1 - - TRUE - TRUE - IP_Flow - 8 - TRUE - . - - . - 2017.4 - OUT_OF_CONTEXT - - - - -- Gitee From 177d09b27e96311398bce341331814a25b87853d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 00:33:44 +0800 Subject: [PATCH 52/57] =?UTF-8?q?fix(verilog):=20=E4=BF=AE=E5=A4=8Dip?= =?UTF-8?q?=E6=A0=B8=E4=BD=8D=E7=BD=AE=EF=BC=8C=E5=88=86=E6=96=87=E4=BB=B6?= =?UTF-8?q?=E5=A4=B9=E5=AD=98=E5=82=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../component.xml | 345 - .../uart_bmpg.edif | 13965 ---------------- .../uart_bmpg.v | 37 - .../ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v | 51 - main/verilog/ip/cpuclk/.gitignore | 2 + main/verilog/ip/cpuclk/cpuclk.xci | 689 + main/verilog/ip/iart_bmpg_0/.gitignore | 2 + main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci | 41 + main/verilog/ip/prgrom/.gitignore | 2 + .../{blk_mem_gen_0.xci => prgrom/prgrom.xci} | 10 +- main/verilog/ip/ram/.gitignore | 2 + main/verilog/ip/ram/RAM.xci | 266 + 12 files changed, 1009 insertions(+), 14403 deletions(-) delete mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml delete mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif delete mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v delete mode 100644 main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v create mode 100644 main/verilog/ip/cpuclk/.gitignore create mode 100644 main/verilog/ip/cpuclk/cpuclk.xci create mode 100644 main/verilog/ip/iart_bmpg_0/.gitignore create mode 100644 main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci create mode 100644 main/verilog/ip/prgrom/.gitignore rename main/verilog/ip/{blk_mem_gen_0.xci => prgrom/prgrom.xci} (98%) create mode 100644 main/verilog/ip/ram/.gitignore create mode 100644 main/verilog/ip/ram/RAM.xci diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml deleted file mode 100644 index 8008995..0000000 --- a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/component.xml +++ /dev/null @@ -1,345 +0,0 @@ - - - SEU_CSE_507 - user - uart_bmpg - 1.3 - - - - xilinx_anylanguagesynthesis - Synthesis - :vivado.xilinx.com:synthesis - Verilog - upg - - xilinx_anylanguagesynthesis_view_fileset - - - - viewChecksum - 36acd76a - - - - - xilinx_anylanguagebehavioralsimulation - Simulation - :vivado.xilinx.com:simulation - Verilog - upg - - xilinx_anylanguagebehavioralsimulation_view_fileset - - - - viewChecksum - 6b59a370 - - - - - xilinx_xpgui - UI Layout - :vivado.xilinx.com:xgui.ui - - xilinx_xpgui_view_fileset - - - - viewChecksum - c3dd6d67 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - - xilinx_implementation_view_fileset - - - - viewChecksum - 995a2cc2 - - - - - - - upg_clk_i - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_rst_i - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_clk_o - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_wen_o - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_adr_o - - out - - 14 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_dat_o - - out - - 31 - 0 - - - - std_logic_vector - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_done_o - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_rx_i - - in - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - upg_tx_o - - out - - - std_logic - xilinx_anylanguagesynthesis - xilinx_anylanguagebehavioralsimulation - - - - - - - - - xilinx_anylanguagesynthesis_view_fileset - - uart_bmpg.edif - edn - - - uart_bmpg.v - verilogSource - CHECKSUM_3f5e0c86 - - - upg.v - verilogSource - CHECKSUM_049fde7b - - - - xilinx_anylanguagebehavioralsimulation_view_fileset - - uart_bmpg.v - verilogSource - - - upg.v - verilogSource - - - - xilinx_xpgui_view_fileset - - xgui/uart_bmpg_v1_3.tcl - tclSource - CHECKSUM_c3dd6d67 - XGUI_VERSION_2 - - - - xilinx_implementation_view_fileset - - uart_bmpg.edif - edn - - - - uart_bmpg_v1_3 - - - Component_Name - uart_bmpg_v1_3 - - - Input_Clock_Freqency - 10 MHz - - - - false - - - - - - Baud_Rate - 128000 bps - - - - false - - - - - - Data_Bits - 8 bits - - - - false - - - - - - Stop_Bits - Stop Bit(s) - 1 bit(s) - - - - false - - - - - - Parity - No - - - - false - - - - - - Reset - Active High - - - - false - - - - - - - - - artix7 - - - /UserIP - - uart_bmpg_v1_3 - package_project - 8 - 2018-07-14T12:11:51Z - - i:/uart_bmpg/uart_bmpg.srcs/sources_1/new - i:/uart_bmpg/uart_bmpg.srcs/sources_1/new - h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new - h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new - h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new - - - - 2017.4 - - - - - - diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif deleted file mode 100644 index e53e627..0000000 --- a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif +++ /dev/null @@ -1,13965 +0,0 @@ -(edif uart_bmpg - (edifversion 2 0 0) - (edifLevel 0) - (keywordmap (keywordlevel 0)) -(status - (written - (timeStamp 2018 07 14 20 08 21) - (program "Vivado" (version "2017.4")) - (comment "Built on 'Fri Dec 15 20:55:39 MST 2017'") - (comment "Built by 'xbuild'") - ) -) - (Library hdi_primitives - (edifLevel 0) - (technology (numberDefinition )) - (cell GND (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port G (direction OUTPUT)) - ) - ) - ) - (cell LUT5 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I0 (direction INPUT)) - (port I1 (direction INPUT)) - (port I2 (direction INPUT)) - (port I3 (direction INPUT)) - (port I4 (direction INPUT)) - ) - ) - ) - (cell LUT6 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I0 (direction INPUT)) - (port I1 (direction INPUT)) - (port I2 (direction INPUT)) - (port I3 (direction INPUT)) - (port I4 (direction INPUT)) - (port I5 (direction INPUT)) - ) - ) - ) - (cell FDCE (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port Q (direction OUTPUT)) - (port C (direction INPUT)) - (port CE (direction INPUT)) - (port CLR (direction INPUT)) - (port D (direction INPUT)) - ) - ) - ) - (cell VCC (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port P (direction OUTPUT)) - ) - ) - ) - (cell LUT2 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I0 (direction INPUT)) - (port I1 (direction INPUT)) - ) - ) - ) - (cell LUT4 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I0 (direction INPUT)) - (port I1 (direction INPUT)) - (port I2 (direction INPUT)) - (port I3 (direction INPUT)) - ) - ) - ) - (cell LUT3 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I0 (direction INPUT)) - (port I1 (direction INPUT)) - (port I2 (direction INPUT)) - ) - ) - ) - (cell FDRE (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port Q (direction OUTPUT)) - (port C (direction INPUT)) - (port CE (direction INPUT)) - (port D (direction INPUT)) - (port R (direction INPUT)) - ) - ) - ) - (cell SRL16E (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port Q (direction OUTPUT)) - (port A0 (direction INPUT)) - (port A1 (direction INPUT)) - (port A2 (direction INPUT)) - (port A3 (direction INPUT)) - (port CE (direction INPUT)) - (port CLK (direction INPUT)) - (port D (direction INPUT)) - ) - ) - ) - (cell LUT1 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I0 (direction INPUT)) - ) - ) - ) - (cell FDSE (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port Q (direction OUTPUT)) - (port C (direction INPUT)) - (port CE (direction INPUT)) - (port D (direction INPUT)) - (port S (direction INPUT)) - ) - ) - ) - (cell CARRY4 (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port CI (direction INPUT)) - (port CYINIT (direction INPUT)) - (port (array (rename CO "CO[3:0]") 4) (direction OUTPUT)) - (port (array (rename O "O[3:0]") 4) (direction OUTPUT)) - (port (array (rename DI "DI[3:0]") 4) (direction INPUT)) - (port (array (rename S "S[3:0]") 4) (direction INPUT)) - ) - ) - ) - (cell BUFG (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I (direction INPUT)) - ) - ) - ) - (cell FDPE (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port Q (direction OUTPUT)) - (port C (direction INPUT)) - (port CE (direction INPUT)) - (port D (direction INPUT)) - (port PRE (direction INPUT)) - ) - ) - ) - (cell OBUF (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I (direction INPUT)) - ) - ) - ) - (cell IBUF (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port O (direction OUTPUT)) - (port I (direction INPUT)) - ) - ) - ) - (cell INV (celltype GENERIC) - (view netlist (viewtype NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - ) - (Library work_library0_1 - (edifLevel 0) - (technology (numberDefinition )) - (cell axi_uart_pselect_f (celltype GENERIC) - (view pselect_f (viewtype NETLIST) - (interface - (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) - (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) - (port ce_expnd_i_3 (direction OUTPUT)) - ) - (contents - (instance CS (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h1")) - ) - (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined - (portref I0 (instanceref CS)) - (portref bus2ip_addr_i_reg_2_) - ) - ) - (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined - (portref I1 (instanceref CS)) - (portref bus2ip_addr_i_reg_3_) - ) - ) - (net ce_expnd_i_3 (joined - (portref O (instanceref CS)) - (portref ce_expnd_i_3) - ) - ) - ) - - (property ORIG_REF_NAME (string "pselect_f")) - ) - ) - (cell axi_uart_pselect_f__parameterized1 (celltype GENERIC) - (view pselect_f__parameterized1 (viewtype NETLIST) - (interface - (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) - (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) - (port ce_expnd_i_1 (direction OUTPUT)) - ) - (contents - (instance CS (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - ) - (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined - (portref I1 (instanceref CS)) - (portref bus2ip_addr_i_reg_2_) - ) - ) - (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined - (portref I0 (instanceref CS)) - (portref bus2ip_addr_i_reg_3_) - ) - ) - (net ce_expnd_i_1 (joined - (portref O (instanceref CS)) - (portref ce_expnd_i_1) - ) - ) - ) - - (property ORIG_REF_NAME (string "pselect_f")) - ) - ) - (cell axi_uart_address_decoder (celltype GENERIC) - (view address_decoder (viewtype NETLIST) - (interface - (port FIFO_Full_reg (direction OUTPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (direction OUTPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1") (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) - (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) - (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) - (port bus2ip_rnw_i (direction INPUT)) - (port enable_interrupts (direction INPUT)) - (port enable_interrupts_reg (direction OUTPUT)) - (port enable_interrupts_reg_0 (direction OUTPUT)) - (port fifo_wr (direction OUTPUT)) - (port ip2bus_error (direction OUTPUT)) - (port reset_RX_FIFO (direction OUTPUT)) - (port reset_TX_FIFO (direction OUTPUT)) - (port rx_Buffer_Full (direction INPUT)) - (port rx_Data_Present_Pre_reg (direction OUTPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port s_axi_arready (direction OUTPUT)) - (port s_axi_arvalid (direction INPUT)) - (port s_axi_awready (direction OUTPUT)) - (port s_axi_bready (direction INPUT)) - (port (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (direction OUTPUT)) - (port s_axi_bvalid_i_reg (direction OUTPUT)) - (port s_axi_bvalid_i_reg_0 (direction INPUT)) - (port s_axi_rready (direction INPUT)) - (port s_axi_rvalid_i_reg (direction OUTPUT)) - (port s_axi_rvalid_i_reg_0 (direction INPUT)) - (port s_axi_wvalid (direction INPUT)) - (port start2 (direction INPUT)) - (port (rename state_reg_0_ "state_reg[0]") (direction INPUT)) - (port (rename state_reg_1_ "state_reg[1]") (direction INPUT)) - (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) - (port tx_Buffer_Full (direction INPUT)) - (port (array (rename D "D[1:0]") 2) (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (direction INPUT)) - (port (array (rename Q "Q[1:0]") 2) (direction INPUT)) - (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) - (port (array (rename out "out[7:0]") 8) (direction INPUT)) - (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction INPUT)) - (port (array (rename s_axi_rdata_i_reg_7_ "s_axi_rdata_i_reg[7][7:0]") 8) (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) - (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) - ) - (contents - (instance Bus_RNW_reg_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hB8")) - (property SOFT_HLUTNM (string "soft_lutpair7")) - ) - (instance Bus_RNW_reg_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1 "GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair8")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_ "GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1 "GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFEFFFF")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2 "GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h8")) - (property SOFT_HLUTNM (string "soft_lutpair8")) - ) - (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance (rename INFERRED_GEN_cnt_i_3__i_2 "INFERRED_GEN.cnt_i[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hF7")) - (property SOFT_HLUTNM (string "soft_lutpair2")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_3 "INFERRED_GEN.cnt_i[4]_i_3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h7")) - (property SOFT_HLUTNM (string "soft_lutpair0")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_5 "INFERRED_GEN.cnt_i[4]_i_5") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hFD")) - (property SOFT_HLUTNM (string "soft_lutpair6")) - ) - (instance (rename INFERRED_GEN_data_reg_15__7__srl16_i_1 "INFERRED_GEN.data_reg[15][7]_srl16_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h10")) - (property SOFT_HLUTNM (string "soft_lutpair4")) - ) - (instance (rename MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I "MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I") (viewref pselect_f (cellref axi_uart_pselect_f (libraryref work_library0_1)))) - (instance (rename MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I "MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I") (viewref pselect_f__parameterized1 (cellref axi_uart_pselect_f__parameterized1 (libraryref work_library0_1)))) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance clr_Status_i_1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h8")) - (property SOFT_HLUTNM (string "soft_lutpair1")) - ) - (instance enable_interrupts_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFB08")) - (property SOFT_HLUTNM (string "soft_lutpair5")) - ) - (instance reset_RX_FIFO_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h40")) - (property SOFT_HLUTNM (string "soft_lutpair7")) - ) - (instance reset_TX_FIFO_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h40")) - (property SOFT_HLUTNM (string "soft_lutpair5")) - ) - (instance rx_Data_Present_Pre_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0444")) - ) - (instance s_axi_arready_INST_0 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hF0F0F0E0")) - (property SOFT_HLUTNM (string "soft_lutpair3")) - ) - (instance (rename s_axi_bresp_i_1__i_1 "s_axi_bresp_i[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFB08")) - ) - (instance s_axi_bvalid_i_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h40FF4040")) - ) - (instance (rename s_axi_rdata_i_0__i_1 "s_axi_rdata_i[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h5050C000")) - (property SOFT_HLUTNM (string "soft_lutpair2")) - ) - (instance (rename s_axi_rdata_i_1__i_1 "s_axi_rdata_i[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hA0A0C000")) - (property SOFT_HLUTNM (string "soft_lutpair0")) - ) - (instance (rename s_axi_rdata_i_2__i_1 "s_axi_rdata_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hA0A0C000")) - (property SOFT_HLUTNM (string "soft_lutpair1")) - ) - (instance (rename s_axi_rdata_i_3__i_1 "s_axi_rdata_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hA0A0C000")) - ) - (instance (rename s_axi_rdata_i_4__i_1 "s_axi_rdata_i[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hA0A0C000")) - ) - (instance (rename s_axi_rdata_i_5__i_1 "s_axi_rdata_i[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hA0A0C000")) - ) - (instance (rename s_axi_rdata_i_6__i_1 "s_axi_rdata_i[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hA0A0C000")) - ) - (instance (rename s_axi_rdata_i_7__i_2 "s_axi_rdata_i[7]_i_2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h4000")) - ) - (instance (rename s_axi_rresp_i_1__i_1 "s_axi_rresp_i[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hF0880088")) - (property SOFT_HLUTNM (string "soft_lutpair4")) - ) - (instance s_axi_rvalid_i_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h40FF4040")) - ) - (instance s_axi_wready_INST_0 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0F0F0F0E")) - (property SOFT_HLUTNM (string "soft_lutpair3")) - ) - (instance (rename state_0__i_1 "state[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hCFEFCFEC")) - ) - (instance (rename state_1__i_1 "state[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hCFECCFECCFEFCFEC")) - ) - (instance tx_Buffer_Empty_Pre_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h8808")) - (property SOFT_HLUTNM (string "soft_lutpair6")) - ) - (net (rename &_const0_ "") (joined - (portref G (instanceref GND)) - (portref R (instanceref Bus_RNW_reg_reg)) - ) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref Bus_RNW_reg_reg)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg_i_1_n_0 (joined - (portref D (instanceref Bus_RNW_reg_reg)) - (portref O (instanceref Bus_RNW_reg_i_1)) - ) - ) - (net (rename D_0_ "D[0]") (joined - (portref O (instanceref state_0__i_1)) - (portref (member D 1)) - ) - ) - (net (rename D_1_ "D[1]") (joined - (portref O (instanceref state_1__i_1)) - (portref (member D 0)) - ) - ) - (net FIFO_Full_reg (joined - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_3)) - (portref FIFO_Full_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (joined - (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_5)) - (portref I0 (instanceref s_axi_rresp_i_1__i_1)) - (portref I0 (instanceref s_axi_wready_INST_0)) - (portref I2 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) - (portref I2 (instanceref tx_Buffer_Empty_Pre_i_1)) - (portref I3 (instanceref s_axi_arready_INST_0)) - (portref Q (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_3)) - (portref I0 (instanceref s_axi_arready_INST_0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_2)) - (portref I1 (instanceref s_axi_rdata_i_7__i_2)) - (portref I2 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) - (portref I2 (instanceref s_axi_rresp_i_1__i_1)) - (portref I3 (instanceref rx_Data_Present_Pre_i_1)) - (portref I3 (instanceref s_axi_rdata_i_0__i_1)) - (portref I3 (instanceref s_axi_rdata_i_1__i_1)) - (portref I3 (instanceref s_axi_rdata_i_2__i_1)) - (portref I3 (instanceref s_axi_rdata_i_3__i_1)) - (portref I3 (instanceref s_axi_rdata_i_4__i_1)) - (portref I3 (instanceref s_axi_rdata_i_5__i_1)) - (portref I3 (instanceref s_axi_rdata_i_6__i_1)) - (portref I3 (instanceref s_axi_wready_INST_0)) - (portref Q (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg") (joined - (portref I0 (instanceref clr_Status_i_1)) - (portref I0 (instanceref s_axi_rdata_i_7__i_2)) - (portref I1 (instanceref s_axi_arready_INST_0)) - (portref I3 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) - (portref I4 (instanceref s_axi_rdata_i_0__i_1)) - (portref I4 (instanceref s_axi_rdata_i_1__i_1)) - (portref I4 (instanceref s_axi_rdata_i_2__i_1)) - (portref I4 (instanceref s_axi_rdata_i_3__i_1)) - (portref I4 (instanceref s_axi_rdata_i_4__i_1)) - (portref I4 (instanceref s_axi_rdata_i_5__i_1)) - (portref I4 (instanceref s_axi_rdata_i_6__i_1)) - (portref I4 (instanceref s_axi_wready_INST_0)) - (portref Q (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg") (joined - (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) - (portref I1 (instanceref enable_interrupts_i_1)) - (portref I1 (instanceref reset_RX_FIFO_i_1)) - (portref I1 (instanceref reset_TX_FIFO_i_1)) - (portref I1 (instanceref s_axi_wready_INST_0)) - (portref I4 (instanceref s_axi_arready_INST_0)) - (portref Q (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined - (portref O (instanceref INFERRED_GEN_cnt_i_3__i_2)) - (portref INFERRED_GEN_cnt_i_reg_2_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_5)) - (portref INFERRED_GEN_cnt_i_reg_2__0) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined - (portref I0 (instanceref rx_Data_Present_Pre_i_1)) - (portref I0 (instanceref s_axi_rdata_i_0__i_1)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_2)) - (portref I4 (instanceref s_axi_rresp_i_1__i_1)) - (portref INFERRED_GEN_cnt_i_reg_4__0_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (joined - (portref I0 (instanceref s_axi_rdata_i_2__i_1)) - (portref I1 (instanceref tx_Buffer_Empty_Pre_i_1)) - (portref INFERRED_GEN_cnt_i_reg_4__0_0_) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref I0 (instanceref s_axi_bvalid_i_i_1)) - (portref I1 (instanceref s_axi_rvalid_i_i_1)) - (portref I2 (instanceref s_axi_bresp_i_1__i_1)) - (portref I2 (instanceref state_1__i_1)) - (portref I3 (instanceref state_0__i_1)) - (portref (member Q 1)) - ) - ) - (net (rename Q_1_ "Q[1]") (joined - (portref I0 (instanceref s_axi_rvalid_i_i_1)) - (portref I1 (instanceref s_axi_bresp_i_1__i_1)) - (portref I1 (instanceref s_axi_bvalid_i_i_1)) - (portref I2 (instanceref state_0__i_1)) - (portref I3 (instanceref state_1__i_1)) - (portref (member Q 0)) - ) - ) - (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined - (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) - (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) - (portref bus2ip_addr_i_reg_2_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) - (portref bus2ip_addr_i_reg_2_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) - (portref bus2ip_addr_i_reg_2_) - ) - ) - (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined - (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) - (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) - (portref bus2ip_addr_i_reg_3_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) - (portref bus2ip_addr_i_reg_3_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) - (portref bus2ip_addr_i_reg_3_) - ) - ) - (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined - (portref O (instanceref clr_Status_i_1)) - (portref bus2ip_rdce_0_) - ) - ) - (net bus2ip_rnw_i (joined - (portref I0 (instanceref Bus_RNW_reg_i_1)) - (portref bus2ip_rnw_i) - ) - ) - (net ce_expnd_i_0 (joined - (portref D (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) - (portref O (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) - ) - ) - (net ce_expnd_i_1 (joined - (portref D (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) - (portref ce_expnd_i_1 (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) - ) - ) - (net ce_expnd_i_2 (joined - (portref D (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) - (portref O (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) - ) - ) - (net ce_expnd_i_3 (joined - (portref D (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) - (portref ce_expnd_i_3 (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) - ) - ) - (net cs_ce_clr (joined - (portref O (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) - (portref R (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) - (portref R (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) - (portref R (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) - (portref R (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) - ) - ) - (net enable_interrupts (joined - (portref I0 (instanceref s_axi_rdata_i_4__i_1)) - (portref I3 (instanceref enable_interrupts_i_1)) - (portref enable_interrupts) - ) - ) - (net enable_interrupts_reg (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_2)) - (portref I0 (instanceref reset_RX_FIFO_i_1)) - (portref I0 (instanceref reset_TX_FIFO_i_1)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_3)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_5)) - (portref I1 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) - (portref I1 (instanceref clr_Status_i_1)) - (portref I2 (instanceref Bus_RNW_reg_i_1)) - (portref I2 (instanceref enable_interrupts_i_1)) - (portref I2 (instanceref rx_Data_Present_Pre_i_1)) - (portref I2 (instanceref s_axi_arready_INST_0)) - (portref I2 (instanceref s_axi_rdata_i_0__i_1)) - (portref I2 (instanceref s_axi_rdata_i_1__i_1)) - (portref I2 (instanceref s_axi_rdata_i_2__i_1)) - (portref I2 (instanceref s_axi_rdata_i_3__i_1)) - (portref I2 (instanceref s_axi_rdata_i_4__i_1)) - (portref I2 (instanceref s_axi_rdata_i_5__i_1)) - (portref I2 (instanceref s_axi_rdata_i_6__i_1)) - (portref I2 (instanceref s_axi_rdata_i_7__i_2)) - (portref I2 (instanceref s_axi_wready_INST_0)) - (portref I3 (instanceref s_axi_rresp_i_1__i_1)) - (portref I3 (instanceref tx_Buffer_Empty_Pre_i_1)) - (portref Q (instanceref Bus_RNW_reg_reg)) - (portref enable_interrupts_reg) - ) - ) - (net enable_interrupts_reg_0 (joined - (portref O (instanceref enable_interrupts_i_1)) - (portref enable_interrupts_reg_0) - ) - ) - (net fifo_wr (joined - (portref O (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) - (portref fifo_wr) - ) - ) - (net ip2bus_error (joined - (portref I0 (instanceref s_axi_bresp_i_1__i_1)) - (portref O (instanceref s_axi_rresp_i_1__i_1)) - (portref ip2bus_error) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref I1 (instanceref s_axi_rdata_i_0__i_1)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref I1 (instanceref s_axi_rdata_i_1__i_1)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref I1 (instanceref s_axi_rdata_i_2__i_1)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref I1 (instanceref s_axi_rdata_i_3__i_1)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref I1 (instanceref s_axi_rdata_i_4__i_1)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref I1 (instanceref s_axi_rdata_i_5__i_1)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref I1 (instanceref s_axi_rdata_i_6__i_1)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref I3 (instanceref s_axi_rdata_i_7__i_2)) - (portref (member out 0)) - ) - ) - (net reset_RX_FIFO (joined - (portref O (instanceref reset_RX_FIFO_i_1)) - (portref reset_RX_FIFO) - ) - ) - (net reset_TX_FIFO (joined - (portref O (instanceref reset_TX_FIFO_i_1)) - (portref reset_TX_FIFO) - ) - ) - (net rx_Buffer_Full (joined - (portref I0 (instanceref s_axi_rdata_i_1__i_1)) - (portref rx_Buffer_Full) - ) - ) - (net rx_Data_Present_Pre_reg (joined - (portref O (instanceref rx_Data_Present_Pre_i_1)) - (portref rx_Data_Present_Pre_reg) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref Bus_RNW_reg_reg)) - (portref C (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) - (portref C (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) - (portref C (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) - (portref C (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I0 (instanceref tx_Buffer_Empty_Pre_i_1)) - (portref I1 (instanceref rx_Data_Present_Pre_i_1)) - (portref I4 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) - (portref s_axi_aresetn) - ) - ) - (net s_axi_arready (joined - (portref I0 (instanceref state_1__i_1)) - (portref I2 (instanceref s_axi_rvalid_i_i_1)) - (portref O (instanceref s_axi_arready_INST_0)) - (portref s_axi_arready) - ) - ) - (net s_axi_arvalid (joined - (portref I4 (instanceref state_0__i_1)) - (portref I5 (instanceref state_1__i_1)) - (portref s_axi_arvalid) - ) - ) - (net s_axi_awready (joined - (portref I0 (instanceref state_0__i_1)) - (portref I2 (instanceref s_axi_bvalid_i_i_1)) - (portref O (instanceref s_axi_wready_INST_0)) - (portref s_axi_awready) - ) - ) - (net s_axi_bready (joined - (portref I3 (instanceref s_axi_bvalid_i_i_1)) - (portref s_axi_bready) - ) - ) - (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined - (portref I3 (instanceref s_axi_bresp_i_1__i_1)) - (portref s_axi_bresp_0_) - ) - ) - (net (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (joined - (portref O (instanceref s_axi_bresp_i_1__i_1)) - (portref s_axi_bresp_i_reg_1_) - ) - ) - (net s_axi_bvalid_i_reg (joined - (portref O (instanceref s_axi_bvalid_i_i_1)) - (portref s_axi_bvalid_i_reg) - ) - ) - (net s_axi_bvalid_i_reg_0 (joined - (portref I4 (instanceref s_axi_bvalid_i_i_1)) - (portref s_axi_bvalid_i_reg_0) - ) - ) - (net (rename s_axi_rdata_i_reg_7__0_ "s_axi_rdata_i_reg[7][0]") (joined - (portref O (instanceref s_axi_rdata_i_0__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 7)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__1_ "s_axi_rdata_i_reg[7][1]") (joined - (portref O (instanceref s_axi_rdata_i_1__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 6)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__2_ "s_axi_rdata_i_reg[7][2]") (joined - (portref O (instanceref s_axi_rdata_i_2__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 5)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__3_ "s_axi_rdata_i_reg[7][3]") (joined - (portref O (instanceref s_axi_rdata_i_3__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 4)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__4_ "s_axi_rdata_i_reg[7][4]") (joined - (portref O (instanceref s_axi_rdata_i_4__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 3)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__5_ "s_axi_rdata_i_reg[7][5]") (joined - (portref O (instanceref s_axi_rdata_i_5__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 2)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__6_ "s_axi_rdata_i_reg[7][6]") (joined - (portref O (instanceref s_axi_rdata_i_6__i_1)) - (portref (member s_axi_rdata_i_reg_7_ 1)) - ) - ) - (net (rename s_axi_rdata_i_reg_7__7_ "s_axi_rdata_i_reg[7][7]") (joined - (portref O (instanceref s_axi_rdata_i_7__i_2)) - (portref (member s_axi_rdata_i_reg_7_ 0)) - ) - ) - (net s_axi_rready (joined - (portref I3 (instanceref s_axi_rvalid_i_i_1)) - (portref s_axi_rready) - ) - ) - (net s_axi_rvalid_i_reg (joined - (portref O (instanceref s_axi_rvalid_i_i_1)) - (portref s_axi_rvalid_i_reg) - ) - ) - (net s_axi_rvalid_i_reg_0 (joined - (portref I4 (instanceref s_axi_rvalid_i_i_1)) - (portref s_axi_rvalid_i_reg_0) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref I2 (instanceref reset_TX_FIFO_i_1)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref I2 (instanceref reset_RX_FIFO_i_1)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref I0 (instanceref enable_interrupts_i_1)) - (portref (member s_axi_wdata 0)) - ) - ) - (net s_axi_wvalid (joined - (portref I4 (instanceref state_1__i_1)) - (portref s_axi_wvalid) - ) - ) - (net start2 (joined - (portref CE (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) - (portref CE (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) - (portref CE (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) - (portref CE (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) - (portref I1 (instanceref Bus_RNW_reg_i_1)) - (portref start2) - ) - ) - (net (rename state_reg_0_ "state_reg[0]") (joined - (portref I1 (instanceref state_0__i_1)) - (portref state_reg_0_) - ) - ) - (net (rename state_reg_1_ "state_reg[1]") (joined - (portref I1 (instanceref state_1__i_1)) - (portref state_reg_1_) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref I0 (instanceref s_axi_rdata_i_5__i_1)) - (portref (member status_reg 1)) - ) - ) - (net (rename status_reg_1_ "status_reg[1]") (joined - (portref I0 (instanceref s_axi_rdata_i_6__i_1)) - (portref (member status_reg 0)) - ) - ) - (net tx_Buffer_Empty_Pre_reg (joined - (portref O (instanceref tx_Buffer_Empty_Pre_i_1)) - (portref tx_Buffer_Empty_Pre_reg) - ) - ) - (net tx_Buffer_Full (joined - (portref I0 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) - (portref I0 (instanceref s_axi_rdata_i_3__i_1)) - (portref I1 (instanceref s_axi_rresp_i_1__i_1)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_5)) - (portref tx_Buffer_Full) - ) - ) - ) - - (property ORIG_REF_NAME (string "address_decoder")) - ) - ) - (cell axi_uart_slave_attachment (celltype GENERIC) - (view slave_attachment (viewtype NETLIST) - (interface - (port FIFO_Full_reg (direction OUTPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction OUTPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) - (port bus2ip_reset (direction INPUT)) - (port enable_interrupts (direction INPUT)) - (port enable_interrupts_reg (direction OUTPUT)) - (port enable_interrupts_reg_0 (direction OUTPUT)) - (port fifo_wr (direction OUTPUT)) - (port reset_RX_FIFO (direction OUTPUT)) - (port reset_TX_FIFO (direction OUTPUT)) - (port rx_Buffer_Full (direction INPUT)) - (port rx_Data_Present_Pre_reg (direction OUTPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port s_axi_arready (direction OUTPUT)) - (port s_axi_arvalid (direction INPUT)) - (port s_axi_awready (direction OUTPUT)) - (port s_axi_awvalid (direction INPUT)) - (port s_axi_bready (direction INPUT)) - (port s_axi_bvalid (direction OUTPUT)) - (port s_axi_rready (direction INPUT)) - (port s_axi_rvalid (direction OUTPUT)) - (port s_axi_wvalid (direction INPUT)) - (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) - (port tx_Buffer_Full (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) - (port (rename Q_0_ "Q[0]") (direction INPUT)) - (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) - (port (array (rename out "out[7:0]") 8) (direction INPUT)) - (port (array (rename s_axi_araddr "s_axi_araddr[1:0]") 2) (direction INPUT)) - (port (array (rename s_axi_awaddr "s_axi_awaddr[1:0]") 2) (direction INPUT)) - (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction OUTPUT)) - (port (array (rename s_axi_rdata "s_axi_rdata[7:0]") 8) (direction OUTPUT)) - (port (rename s_axi_rresp_0_ "s_axi_rresp[0]") (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) - (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) - ) - (contents - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance I_DECODER (viewref address_decoder (cellref axi_uart_address_decoder (libraryref work_library0_1)))) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance (rename bus2ip_addr_i_2__i_1 "bus2ip_addr_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hB8FFB800")) - ) - (instance (rename bus2ip_addr_i_3__i_1 "bus2ip_addr_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hB8FFB800")) - ) - (instance (rename bus2ip_addr_i_3__i_2 "bus2ip_addr_i[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hEF")) - (property SOFT_HLUTNM (string "soft_lutpair9")) - ) - (instance (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance bus2ip_rnw_i_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFFF7000000F0")) - ) - (instance bus2ip_rnw_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rst_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance s_axi_bvalid_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_7__i_1 "s_axi_rdata_i[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - ) - (instance (rename s_axi_rdata_i_reg_0_ "s_axi_rdata_i_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_1_ "s_axi_rdata_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_2_ "s_axi_rdata_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_3_ "s_axi_rdata_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_4_ "s_axi_rdata_i_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_5_ "s_axi_rdata_i_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_6_ "s_axi_rdata_i_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rdata_i_reg_7_ "s_axi_rdata_i_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_rresp_i_reg_1_ "s_axi_rresp_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance s_axi_rvalid_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance start2_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h000000F8")) - (property SOFT_HLUTNM (string "soft_lutpair9")) - ) - (instance start2_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename state_0__i_2 "state[0]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h002A2A2A")) - ) - (instance (rename state_1__i_2 "state[1]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h002A2A2A")) - ) - (instance (rename state_1__i_3 "state[1]_i_3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h8")) - ) - (instance (rename state_reg_0_ "state_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename state_reg_1_ "state_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (net (rename &_const0_ "") (joined - (portref G (instanceref GND)) - (portref R (instanceref rst_reg)) - ) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref bus2ip_addr_i_reg_2_)) - (portref CE (instanceref bus2ip_addr_i_reg_3_)) - (portref CE (instanceref bus2ip_rnw_i_reg)) - (portref CE (instanceref rst_reg)) - (portref CE (instanceref s_axi_bresp_i_reg_1_)) - (portref CE (instanceref s_axi_bvalid_i_reg)) - (portref CE (instanceref s_axi_rvalid_i_reg)) - (portref CE (instanceref start2_reg)) - (portref CE (instanceref state_reg_0_)) - (portref CE (instanceref state_reg_1_)) - (portref P (instanceref VCC)) - ) - ) - (net FIFO_Full_reg (joined - (portref FIFO_Full_reg (instanceref I_DECODER)) - (portref FIFO_Full_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 (instanceref I_DECODER)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 (instanceref I_DECODER)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined - (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref I_DECODER)) - (portref INFERRED_GEN_cnt_i_reg_2_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined - (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref I_DECODER)) - (portref INFERRED_GEN_cnt_i_reg_2__0) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_0_ (instanceref I_DECODER)) - (portref INFERRED_GEN_cnt_i_reg_4__0_) - ) - ) - (net I_DECODER_n_26 (joined - (portref D (instanceref s_axi_rvalid_i_reg)) - (portref s_axi_rvalid_i_reg (instanceref I_DECODER)) - ) - ) - (net I_DECODER_n_27 (joined - (portref D (instanceref s_axi_bvalid_i_reg)) - (portref s_axi_bvalid_i_reg (instanceref I_DECODER)) - ) - ) - (net I_DECODER_n_28 (joined - (portref D (instanceref s_axi_bresp_i_reg_1_)) - (portref s_axi_bresp_i_reg_1_ (instanceref I_DECODER)) - ) - ) - (net I_DECODER_n_5 (joined - (portref D (instanceref state_reg_1_)) - (portref (member D 0) (instanceref I_DECODER)) - ) - ) - (net I_DECODER_n_6 (joined - (portref D (instanceref state_reg_0_)) - (portref (member D 1) (instanceref I_DECODER)) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_DECODER)) - (portref Q_0_) - ) - ) - (net (rename SIn_DBus_0_ "SIn_DBus[0]") (joined - (portref D (instanceref s_axi_rdata_i_reg_7_)) - (portref (member s_axi_rdata_i_reg_7_ 0) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_1_ "SIn_DBus[1]") (joined - (portref D (instanceref s_axi_rdata_i_reg_6_)) - (portref (member s_axi_rdata_i_reg_7_ 1) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_2_ "SIn_DBus[2]") (joined - (portref D (instanceref s_axi_rdata_i_reg_5_)) - (portref (member s_axi_rdata_i_reg_7_ 2) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_3_ "SIn_DBus[3]") (joined - (portref D (instanceref s_axi_rdata_i_reg_4_)) - (portref (member s_axi_rdata_i_reg_7_ 3) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_4_ "SIn_DBus[4]") (joined - (portref D (instanceref s_axi_rdata_i_reg_3_)) - (portref (member s_axi_rdata_i_reg_7_ 4) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_5_ "SIn_DBus[5]") (joined - (portref D (instanceref s_axi_rdata_i_reg_2_)) - (portref (member s_axi_rdata_i_reg_7_ 5) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_6_ "SIn_DBus[6]") (joined - (portref D (instanceref s_axi_rdata_i_reg_1_)) - (portref (member s_axi_rdata_i_reg_7_ 6) (instanceref I_DECODER)) - ) - ) - (net (rename SIn_DBus_7_ "SIn_DBus[7]") (joined - (portref D (instanceref s_axi_rdata_i_reg_0_)) - (portref (member s_axi_rdata_i_reg_7_ 7) (instanceref I_DECODER)) - ) - ) - (net (rename bus2ip_addr_i_2__i_1_n_0 "bus2ip_addr_i[2]_i_1_n_0") (joined - (portref D (instanceref bus2ip_addr_i_reg_2_)) - (portref O (instanceref bus2ip_addr_i_2__i_1)) - ) - ) - (net (rename bus2ip_addr_i_3__i_1_n_0 "bus2ip_addr_i[3]_i_1_n_0") (joined - (portref D (instanceref bus2ip_addr_i_reg_3_)) - (portref O (instanceref bus2ip_addr_i_3__i_1)) - ) - ) - (net (rename bus2ip_addr_i_3__i_2_n_0 "bus2ip_addr_i[3]_i_2_n_0") (joined - (portref I1 (instanceref bus2ip_addr_i_2__i_1)) - (portref I1 (instanceref bus2ip_addr_i_3__i_1)) - (portref O (instanceref bus2ip_addr_i_3__i_2)) - ) - ) - (net (rename bus2ip_addr_i_reg_n_0__2_ "bus2ip_addr_i_reg_n_0_[2]") (joined - (portref I4 (instanceref bus2ip_addr_i_2__i_1)) - (portref Q (instanceref bus2ip_addr_i_reg_2_)) - (portref bus2ip_addr_i_reg_2_ (instanceref I_DECODER)) - ) - ) - (net (rename bus2ip_addr_i_reg_n_0__3_ "bus2ip_addr_i_reg_n_0_[3]") (joined - (portref I4 (instanceref bus2ip_addr_i_3__i_1)) - (portref Q (instanceref bus2ip_addr_i_reg_3_)) - (portref bus2ip_addr_i_reg_3_ (instanceref I_DECODER)) - ) - ) - (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined - (portref bus2ip_rdce_0_ (instanceref I_DECODER)) - (portref bus2ip_rdce_0_) - ) - ) - (net bus2ip_reset (joined - (portref D (instanceref rst_reg)) - (portref bus2ip_reset) - ) - ) - (net bus2ip_rnw_i (joined - (portref I5 (instanceref bus2ip_rnw_i_i_1)) - (portref Q (instanceref bus2ip_rnw_i_reg)) - (portref bus2ip_rnw_i (instanceref I_DECODER)) - ) - ) - (net bus2ip_rnw_i_i_1_n_0 (joined - (portref D (instanceref bus2ip_rnw_i_reg)) - (portref O (instanceref bus2ip_rnw_i_i_1)) - ) - ) - (net enable_interrupts (joined - (portref enable_interrupts (instanceref I_DECODER)) - (portref enable_interrupts) - ) - ) - (net enable_interrupts_reg (joined - (portref enable_interrupts_reg (instanceref I_DECODER)) - (portref enable_interrupts_reg) - ) - ) - (net enable_interrupts_reg_0 (joined - (portref enable_interrupts_reg_0 (instanceref I_DECODER)) - (portref enable_interrupts_reg_0) - ) - ) - (net fifo_wr (joined - (portref fifo_wr (instanceref I_DECODER)) - (portref fifo_wr) - ) - ) - (net ip2bus_error (joined - (portref D (instanceref s_axi_rresp_i_reg_1_)) - (portref ip2bus_error (instanceref I_DECODER)) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref (member out 7) (instanceref I_DECODER)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref (member out 6) (instanceref I_DECODER)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref (member out 5) (instanceref I_DECODER)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref (member out 4) (instanceref I_DECODER)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref (member out 3) (instanceref I_DECODER)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref (member out 2) (instanceref I_DECODER)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref (member out 1) (instanceref I_DECODER)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref (member out 0) (instanceref I_DECODER)) - (portref (member out 0)) - ) - ) - (net reset_RX_FIFO (joined - (portref reset_RX_FIFO (instanceref I_DECODER)) - (portref reset_RX_FIFO) - ) - ) - (net reset_TX_FIFO (joined - (portref reset_TX_FIFO (instanceref I_DECODER)) - (portref reset_TX_FIFO) - ) - ) - (net rst (joined - (portref Q (instanceref rst_reg)) - (portref R (instanceref bus2ip_addr_i_reg_2_)) - (portref R (instanceref bus2ip_addr_i_reg_3_)) - (portref R (instanceref bus2ip_rnw_i_reg)) - (portref R (instanceref s_axi_bresp_i_reg_1_)) - (portref R (instanceref s_axi_bvalid_i_reg)) - (portref R (instanceref s_axi_rdata_i_reg_0_)) - (portref R (instanceref s_axi_rdata_i_reg_1_)) - (portref R (instanceref s_axi_rdata_i_reg_2_)) - (portref R (instanceref s_axi_rdata_i_reg_3_)) - (portref R (instanceref s_axi_rdata_i_reg_4_)) - (portref R (instanceref s_axi_rdata_i_reg_5_)) - (portref R (instanceref s_axi_rdata_i_reg_6_)) - (portref R (instanceref s_axi_rdata_i_reg_7_)) - (portref R (instanceref s_axi_rresp_i_reg_1_)) - (portref R (instanceref s_axi_rvalid_i_reg)) - (portref R (instanceref start2_reg)) - (portref R (instanceref state_reg_0_)) - (portref R (instanceref state_reg_1_)) - ) - ) - (net rx_Buffer_Full (joined - (portref rx_Buffer_Full (instanceref I_DECODER)) - (portref rx_Buffer_Full) - ) - ) - (net rx_Data_Present_Pre_reg (joined - (portref rx_Data_Present_Pre_reg (instanceref I_DECODER)) - (portref rx_Data_Present_Pre_reg) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref bus2ip_addr_i_reg_2_)) - (portref C (instanceref bus2ip_addr_i_reg_3_)) - (portref C (instanceref bus2ip_rnw_i_reg)) - (portref C (instanceref rst_reg)) - (portref C (instanceref s_axi_bresp_i_reg_1_)) - (portref C (instanceref s_axi_bvalid_i_reg)) - (portref C (instanceref s_axi_rdata_i_reg_0_)) - (portref C (instanceref s_axi_rdata_i_reg_1_)) - (portref C (instanceref s_axi_rdata_i_reg_2_)) - (portref C (instanceref s_axi_rdata_i_reg_3_)) - (portref C (instanceref s_axi_rdata_i_reg_4_)) - (portref C (instanceref s_axi_rdata_i_reg_5_)) - (portref C (instanceref s_axi_rdata_i_reg_6_)) - (portref C (instanceref s_axi_rdata_i_reg_7_)) - (portref C (instanceref s_axi_rresp_i_reg_1_)) - (portref C (instanceref s_axi_rvalid_i_reg)) - (portref C (instanceref start2_reg)) - (portref C (instanceref state_reg_0_)) - (portref C (instanceref state_reg_1_)) - (portref s_axi_aclk (instanceref I_DECODER)) - (portref s_axi_aclk) - ) - ) - (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined - (portref I2 (instanceref bus2ip_addr_i_2__i_1)) - (portref (member s_axi_araddr 1)) - ) - ) - (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined - (portref I2 (instanceref bus2ip_addr_i_3__i_1)) - (portref (member s_axi_araddr 0)) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref I_DECODER)) - (portref s_axi_aresetn) - ) - ) - (net s_axi_arready (joined - (portref s_axi_arready (instanceref I_DECODER)) - (portref s_axi_arready) - ) - ) - (net s_axi_arvalid (joined - (portref I2 (instanceref bus2ip_addr_i_3__i_2)) - (portref I2 (instanceref bus2ip_rnw_i_i_1)) - (portref I2 (instanceref start2_i_1)) - (portref s_axi_arvalid (instanceref I_DECODER)) - (portref s_axi_arvalid) - ) - ) - (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined - (portref I0 (instanceref bus2ip_addr_i_2__i_1)) - (portref (member s_axi_awaddr 1)) - ) - ) - (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined - (portref I0 (instanceref bus2ip_addr_i_3__i_1)) - (portref (member s_axi_awaddr 0)) - ) - ) - (net s_axi_awready (joined - (portref s_axi_awready (instanceref I_DECODER)) - (portref s_axi_awready) - ) - ) - (net s_axi_awvalid (joined - (portref I0 (instanceref bus2ip_rnw_i_i_1)) - (portref I0 (instanceref start2_i_1)) - (portref I0 (instanceref state_1__i_3)) - (portref s_axi_awvalid) - ) - ) - (net s_axi_bready (joined - (portref I3 (instanceref state_0__i_2)) - (portref I3 (instanceref state_1__i_2)) - (portref s_axi_bready (instanceref I_DECODER)) - (portref s_axi_bready) - ) - ) - (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined - (portref Q (instanceref s_axi_bresp_i_reg_1_)) - (portref s_axi_bresp_0_ (instanceref I_DECODER)) - (portref s_axi_bresp_0_) - ) - ) - (net s_axi_bvalid (joined - (portref I4 (instanceref state_0__i_2)) - (portref I4 (instanceref state_1__i_2)) - (portref Q (instanceref s_axi_bvalid_i_reg)) - (portref s_axi_bvalid_i_reg_0 (instanceref I_DECODER)) - (portref s_axi_bvalid) - ) - ) - (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_0_)) - (portref (member s_axi_rdata 7)) - ) - ) - (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_1_)) - (portref (member s_axi_rdata 6)) - ) - ) - (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_2_)) - (portref (member s_axi_rdata 5)) - ) - ) - (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_3_)) - (portref (member s_axi_rdata 4)) - ) - ) - (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_4_)) - (portref (member s_axi_rdata 3)) - ) - ) - (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_5_)) - (portref (member s_axi_rdata 2)) - ) - ) - (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_6_)) - (portref (member s_axi_rdata 1)) - ) - ) - (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined - (portref Q (instanceref s_axi_rdata_i_reg_7_)) - (portref (member s_axi_rdata 0)) - ) - ) - (net s_axi_rdata_i (joined - (portref CE (instanceref s_axi_rdata_i_reg_0_)) - (portref CE (instanceref s_axi_rdata_i_reg_1_)) - (portref CE (instanceref s_axi_rdata_i_reg_2_)) - (portref CE (instanceref s_axi_rdata_i_reg_3_)) - (portref CE (instanceref s_axi_rdata_i_reg_4_)) - (portref CE (instanceref s_axi_rdata_i_reg_5_)) - (portref CE (instanceref s_axi_rdata_i_reg_6_)) - (portref CE (instanceref s_axi_rdata_i_reg_7_)) - (portref CE (instanceref s_axi_rresp_i_reg_1_)) - (portref O (instanceref s_axi_rdata_i_7__i_1)) - ) - ) - (net s_axi_rready (joined - (portref I2 (instanceref state_0__i_2)) - (portref I2 (instanceref state_1__i_2)) - (portref s_axi_rready (instanceref I_DECODER)) - (portref s_axi_rready) - ) - ) - (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined - (portref Q (instanceref s_axi_rresp_i_reg_1_)) - (portref s_axi_rresp_0_) - ) - ) - (net s_axi_rvalid (joined - (portref I1 (instanceref state_0__i_2)) - (portref I1 (instanceref state_1__i_2)) - (portref Q (instanceref s_axi_rvalid_i_reg)) - (portref s_axi_rvalid_i_reg_0 (instanceref I_DECODER)) - (portref s_axi_rvalid) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 2) (instanceref I_DECODER)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 1) (instanceref I_DECODER)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 0) (instanceref I_DECODER)) - (portref (member s_axi_wdata 0)) - ) - ) - (net s_axi_wvalid (joined - (portref I1 (instanceref bus2ip_rnw_i_i_1)) - (portref I1 (instanceref start2_i_1)) - (portref I1 (instanceref state_1__i_3)) - (portref s_axi_wvalid) - ) - ) - (net start2 (joined - (portref Q (instanceref start2_reg)) - (portref start2 (instanceref I_DECODER)) - ) - ) - (net start2_i_1_n_0 (joined - (portref D (instanceref start2_reg)) - (portref I3 (instanceref bus2ip_addr_i_2__i_1)) - (portref I3 (instanceref bus2ip_addr_i_3__i_1)) - (portref O (instanceref start2_i_1)) - ) - ) - (net (rename state_0_ "state[0]") (joined - (portref I0 (instanceref s_axi_rdata_i_7__i_1)) - (portref I0 (instanceref state_0__i_2)) - (portref I1 (instanceref bus2ip_addr_i_3__i_2)) - (portref I3 (instanceref bus2ip_rnw_i_i_1)) - (portref I3 (instanceref start2_i_1)) - (portref Q (instanceref state_reg_0_)) - (portref (member Q 1) (instanceref I_DECODER)) - ) - ) - (net (rename state_0__i_2_n_0 "state[0]_i_2_n_0") (joined - (portref O (instanceref state_0__i_2)) - (portref state_reg_0_ (instanceref I_DECODER)) - ) - ) - (net (rename state_1_ "state[1]") (joined - (portref I0 (instanceref bus2ip_addr_i_3__i_2)) - (portref I0 (instanceref state_1__i_2)) - (portref I1 (instanceref s_axi_rdata_i_7__i_1)) - (portref I4 (instanceref bus2ip_rnw_i_i_1)) - (portref I4 (instanceref start2_i_1)) - (portref Q (instanceref state_reg_1_)) - (portref (member Q 0) (instanceref I_DECODER)) - ) - ) - (net (rename state_1__i_2_n_0 "state[1]_i_2_n_0") (joined - (portref O (instanceref state_1__i_2)) - (portref state_reg_1_ (instanceref I_DECODER)) - ) - ) - (net (rename state_1__i_3_n_0 "state[1]_i_3_n_0") (joined - (portref O (instanceref state_1__i_3)) - (portref s_axi_wvalid (instanceref I_DECODER)) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref (member status_reg 1) (instanceref I_DECODER)) - (portref (member status_reg 1)) - ) - ) - (net (rename status_reg_1_ "status_reg[1]") (joined - (portref (member status_reg 0) (instanceref I_DECODER)) - (portref (member status_reg 0)) - ) - ) - (net tx_Buffer_Empty_Pre_reg (joined - (portref tx_Buffer_Empty_Pre_reg (instanceref I_DECODER)) - (portref tx_Buffer_Empty_Pre_reg) - ) - ) - (net tx_Buffer_Full (joined - (portref tx_Buffer_Full (instanceref I_DECODER)) - (portref tx_Buffer_Full) - ) - ) - ) - - (property ORIG_REF_NAME (string "slave_attachment")) - ) - ) - (cell axi_uart_axi_lite_ipif (celltype GENERIC) - (view axi_lite_ipif (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction OUTPUT)) - (port FIFO_Full_reg (direction OUTPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction OUTPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) - (port bus2ip_reset (direction INPUT)) - (port enable_interrupts (direction INPUT)) - (port enable_interrupts_reg (direction OUTPUT)) - (port fifo_wr (direction OUTPUT)) - (port reset_RX_FIFO (direction OUTPUT)) - (port reset_TX_FIFO (direction OUTPUT)) - (port rx_Buffer_Full (direction INPUT)) - (port rx_Data_Present_Pre_reg (direction OUTPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port s_axi_arready (direction OUTPUT)) - (port s_axi_arvalid (direction INPUT)) - (port s_axi_awready (direction OUTPUT)) - (port s_axi_awvalid (direction INPUT)) - (port s_axi_bready (direction INPUT)) - (port s_axi_bvalid (direction OUTPUT)) - (port s_axi_rready (direction INPUT)) - (port s_axi_rvalid (direction OUTPUT)) - (port s_axi_wvalid (direction INPUT)) - (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) - (port tx_Buffer_Full (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) - (port (rename Q_0_ "Q[0]") (direction INPUT)) - (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) - (port (array (rename out "out[7:0]") 8) (direction INPUT)) - (port (array (rename s_axi_araddr "s_axi_araddr[1:0]") 2) (direction INPUT)) - (port (array (rename s_axi_awaddr "s_axi_awaddr[1:0]") 2) (direction INPUT)) - (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction OUTPUT)) - (port (array (rename s_axi_rdata "s_axi_rdata[7:0]") 8) (direction OUTPUT)) - (port (rename s_axi_rresp_0_ "s_axi_rresp[0]") (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) - (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) - ) - (contents - (instance I_SLAVE_ATTACHMENT (viewref slave_attachment (cellref axi_uart_slave_attachment (libraryref work_library0_1)))) - (net Bus_RNW_reg (joined - (portref enable_interrupts_reg (instanceref I_SLAVE_ATTACHMENT)) - (portref Bus_RNW_reg) - ) - ) - (net FIFO_Full_reg (joined - (portref FIFO_Full_reg (instanceref I_SLAVE_ATTACHMENT)) - (portref FIFO_Full_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 (instanceref I_SLAVE_ATTACHMENT)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref I_SLAVE_ATTACHMENT)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined - (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref I_SLAVE_ATTACHMENT)) - (portref INFERRED_GEN_cnt_i_reg_2_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined - (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref I_SLAVE_ATTACHMENT)) - (portref INFERRED_GEN_cnt_i_reg_2__0) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_SLAVE_ATTACHMENT)) - (portref INFERRED_GEN_cnt_i_reg_4__0_) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref Q_0_ (instanceref I_SLAVE_ATTACHMENT)) - (portref Q_0_) - ) - ) - (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined - (portref bus2ip_rdce_0_ (instanceref I_SLAVE_ATTACHMENT)) - (portref bus2ip_rdce_0_) - ) - ) - (net bus2ip_reset (joined - (portref bus2ip_reset (instanceref I_SLAVE_ATTACHMENT)) - (portref bus2ip_reset) - ) - ) - (net enable_interrupts (joined - (portref enable_interrupts (instanceref I_SLAVE_ATTACHMENT)) - (portref enable_interrupts) - ) - ) - (net enable_interrupts_reg (joined - (portref enable_interrupts_reg_0 (instanceref I_SLAVE_ATTACHMENT)) - (portref enable_interrupts_reg) - ) - ) - (net fifo_wr (joined - (portref fifo_wr (instanceref I_SLAVE_ATTACHMENT)) - (portref fifo_wr) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref (member out 7) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref (member out 6) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref (member out 5) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref (member out 4) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref (member out 3) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref (member out 2) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref (member out 1) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref (member out 0) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member out 0)) - ) - ) - (net reset_RX_FIFO (joined - (portref reset_RX_FIFO (instanceref I_SLAVE_ATTACHMENT)) - (portref reset_RX_FIFO) - ) - ) - (net reset_TX_FIFO (joined - (portref reset_TX_FIFO (instanceref I_SLAVE_ATTACHMENT)) - (portref reset_TX_FIFO) - ) - ) - (net rx_Buffer_Full (joined - (portref rx_Buffer_Full (instanceref I_SLAVE_ATTACHMENT)) - (portref rx_Buffer_Full) - ) - ) - (net rx_Data_Present_Pre_reg (joined - (portref rx_Data_Present_Pre_reg (instanceref I_SLAVE_ATTACHMENT)) - (portref rx_Data_Present_Pre_reg) - ) - ) - (net s_axi_aclk (joined - (portref s_axi_aclk (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_aclk) - ) - ) - (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined - (portref (member s_axi_araddr 1) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_araddr 1)) - ) - ) - (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined - (portref (member s_axi_araddr 0) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_araddr 0)) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_aresetn) - ) - ) - (net s_axi_arready (joined - (portref s_axi_arready (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_arready) - ) - ) - (net s_axi_arvalid (joined - (portref s_axi_arvalid (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_arvalid) - ) - ) - (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined - (portref (member s_axi_awaddr 1) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_awaddr 1)) - ) - ) - (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined - (portref (member s_axi_awaddr 0) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_awaddr 0)) - ) - ) - (net s_axi_awready (joined - (portref s_axi_awready (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_awready) - ) - ) - (net s_axi_awvalid (joined - (portref s_axi_awvalid (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_awvalid) - ) - ) - (net s_axi_bready (joined - (portref s_axi_bready (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_bready) - ) - ) - (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined - (portref s_axi_bresp_0_ (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_bresp_0_) - ) - ) - (net s_axi_bvalid (joined - (portref s_axi_bvalid (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_bvalid) - ) - ) - (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined - (portref (member s_axi_rdata 7) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 7)) - ) - ) - (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined - (portref (member s_axi_rdata 6) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 6)) - ) - ) - (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined - (portref (member s_axi_rdata 5) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 5)) - ) - ) - (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined - (portref (member s_axi_rdata 4) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 4)) - ) - ) - (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined - (portref (member s_axi_rdata 3) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 3)) - ) - ) - (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined - (portref (member s_axi_rdata 2) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 2)) - ) - ) - (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined - (portref (member s_axi_rdata 1) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 1)) - ) - ) - (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined - (portref (member s_axi_rdata 0) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_rdata 0)) - ) - ) - (net s_axi_rready (joined - (portref s_axi_rready (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_rready) - ) - ) - (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined - (portref s_axi_rresp_0_ (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_rresp_0_) - ) - ) - (net s_axi_rvalid (joined - (portref s_axi_rvalid (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_rvalid) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 2) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 1) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 0) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member s_axi_wdata 0)) - ) - ) - (net s_axi_wvalid (joined - (portref s_axi_wvalid (instanceref I_SLAVE_ATTACHMENT)) - (portref s_axi_wvalid) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref (member status_reg 1) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member status_reg 1)) - ) - ) - (net (rename status_reg_1_ "status_reg[1]") (joined - (portref (member status_reg 0) (instanceref I_SLAVE_ATTACHMENT)) - (portref (member status_reg 0)) - ) - ) - (net tx_Buffer_Empty_Pre_reg (joined - (portref tx_Buffer_Empty_Pre_reg (instanceref I_SLAVE_ATTACHMENT)) - (portref tx_Buffer_Empty_Pre_reg) - ) - ) - (net tx_Buffer_Full (joined - (portref tx_Buffer_Full (instanceref I_SLAVE_ATTACHMENT)) - (portref tx_Buffer_Full) - ) - ) - ) - - (property ORIG_REF_NAME (string "axi_lite_ipif")) - ) - ) - (cell axi_uart_baudrate (celltype GENERIC) - (view baudrate (viewtype NETLIST) - (interface - (port en_16x_Baud (direction OUTPUT)) - (port s_axi_aclk (direction INPUT)) - (port (rename SR_0_ "SR[0]") (direction INPUT)) - ) - (contents - (instance EN_16x_Baud_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h01")) - (property SOFT_HLUTNM (string "soft_lutpair10")) - ) - (instance EN_16x_Baud_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance (rename count_0__i_1 "count[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h32")) - (property SOFT_HLUTNM (string "soft_lutpair11")) - ) - (instance (rename count_1__i_1 "count[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hC2")) - (property SOFT_HLUTNM (string "soft_lutpair11")) - ) - (instance (rename count_2__i_1 "count[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA9")) - (property SOFT_HLUTNM (string "soft_lutpair10")) - ) - (instance (rename count_reg_0_ "count_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename count_reg_1_ "count_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename count_reg_2_ "count_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref EN_16x_Baud_reg)) - (portref CE (instanceref count_reg_0_)) - (portref CE (instanceref count_reg_1_)) - (portref CE (instanceref count_reg_2_)) - (portref P (instanceref VCC)) - ) - ) - (net EN_16x_Baud_i_1_n_0 (joined - (portref D (instanceref EN_16x_Baud_reg)) - (portref O (instanceref EN_16x_Baud_i_1)) - ) - ) - (net (rename SR_0_ "SR[0]") (joined - (portref R (instanceref EN_16x_Baud_reg)) - (portref R (instanceref count_reg_0_)) - (portref R (instanceref count_reg_1_)) - (portref R (instanceref count_reg_2_)) - (portref SR_0_) - ) - ) - (net (rename count_0_ "count[0]") (joined - (portref I1 (instanceref EN_16x_Baud_i_1)) - (portref I1 (instanceref count_0__i_1)) - (portref I1 (instanceref count_1__i_1)) - (portref I1 (instanceref count_2__i_1)) - (portref Q (instanceref count_reg_0_)) - ) - ) - (net (rename count_0__i_1_n_0 "count[0]_i_1_n_0") (joined - (portref D (instanceref count_reg_0_)) - (portref O (instanceref count_0__i_1)) - ) - ) - (net (rename count_1_ "count[1]") (joined - (portref I0 (instanceref EN_16x_Baud_i_1)) - (portref I2 (instanceref count_0__i_1)) - (portref I2 (instanceref count_1__i_1)) - (portref I2 (instanceref count_2__i_1)) - (portref Q (instanceref count_reg_1_)) - ) - ) - (net (rename count_1__i_1_n_0 "count[1]_i_1_n_0") (joined - (portref D (instanceref count_reg_1_)) - (portref O (instanceref count_1__i_1)) - ) - ) - (net (rename count_2_ "count[2]") (joined - (portref I0 (instanceref count_0__i_1)) - (portref I0 (instanceref count_1__i_1)) - (portref I0 (instanceref count_2__i_1)) - (portref I2 (instanceref EN_16x_Baud_i_1)) - (portref Q (instanceref count_reg_2_)) - ) - ) - (net (rename count_2__i_1_n_0 "count[2]_i_1_n_0") (joined - (portref D (instanceref count_reg_2_)) - (portref O (instanceref count_2__i_1)) - ) - ) - (net en_16x_Baud (joined - (portref Q (instanceref EN_16x_Baud_reg)) - (portref en_16x_Baud) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref EN_16x_Baud_reg)) - (portref C (instanceref count_reg_0_)) - (portref C (instanceref count_reg_1_)) - (portref C (instanceref count_reg_2_)) - (portref s_axi_aclk) - ) - ) - ) - - (property ORIG_REF_NAME (string "baudrate")) - ) - ) - (cell axi_uart_dynshreg_i_f (celltype GENERIC) - (view dynshreg_i_f (viewtype NETLIST) - (interface - (port (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (direction OUTPUT)) - (port clr_Status (direction INPUT)) - (port en_16x_Baud (direction INPUT)) - (port fifo_Write0 (direction OUTPUT)) - (port frame_err_ocrd (direction INPUT)) - (port frame_err_ocrd_reg (direction OUTPUT)) - (port p_11_out (direction OUTPUT)) - (port p_14_out (direction OUTPUT)) - (port p_17_out (direction OUTPUT)) - (port p_20_out (direction OUTPUT)) - (port p_2_out (direction OUTPUT)) - (port p_5_out (direction OUTPUT)) - (port p_8_out (direction OUTPUT)) - (port running_reg (direction OUTPUT)) - (port running_reg_0 (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port scndry_out (direction INPUT)) - (port start_Edge_Detected (direction INPUT)) - (port status_reg_reg0 (direction OUTPUT)) - (port stop_Bit_Position_reg (direction OUTPUT)) - (port stop_Bit_Position_reg_0 (direction INPUT)) - (port valid_rx (direction INPUT)) - (port (array (rename in "in[0:7]") 8) (direction INPUT)) - (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) - ) - (contents - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance (rename INFERRED_GEN_data_reg_14__0__srl15 "INFERRED_GEN.data_reg[14][0]_srl15") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 ")) - ) - (instance (rename INFERRED_GEN_data_reg_14__0__srl15_i_1 "INFERRED_GEN.data_reg[14][0]_srl15_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h4440")) - (property SOFT_HLUTNM (string "soft_lutpair14")) - ) - (instance (rename INFERRED_GEN_data_reg_15__0_ "INFERRED_GEN.data_reg[15][0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_2__fifo_din_2__i_1 "SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_3__fifo_din_3__i_1 "SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_4__fifo_din_4__i_1 "SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_5__fifo_din_5__i_1 "SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_6__fifo_din_6__i_1 "SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_7__fifo_din_7__i_1 "SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_8__i_1 "SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0A000C00")) - ) - (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_8__i_2 "SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hF7")) - (property SOFT_HLUTNM (string "soft_lutpair12")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance fifo_Write_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h8000")) - (property SOFT_HLUTNM (string "soft_lutpair13")) - ) - (instance frame_err_ocrd_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h00FF0080")) - (property SOFT_HLUTNM (string "soft_lutpair13")) - ) - (instance running_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hBFFFA0A0")) - (property SOFT_HLUTNM (string "soft_lutpair12")) - ) - (instance (rename status_reg_1__i_1 "status_reg[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0000F200")) - ) - (instance (rename status_reg_1__i_2 "status_reg[1]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h80")) - (property SOFT_HLUTNM (string "soft_lutpair14")) - ) - (instance stop_Bit_Position_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h2CCC")) - ) - (net (rename &_const0_ "") (joined - (portref A0 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref G (instanceref GND)) - (portref R (instanceref INFERRED_GEN_data_reg_15__0_)) - ) - ) - (net (rename &_const1_ "") (joined - (portref A1 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref A2 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref A3 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref P (instanceref VCC)) - ) - ) - (net (rename INFERRED_GEN_data_reg_14__0__srl15_n_0 "INFERRED_GEN.data_reg[14][0]_srl15_n_0") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__0_)) - (portref Q (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - ) - ) - (net (rename INFERRED_GEN_data_reg_15_ "INFERRED_GEN.data_reg[15]") (joined - (portref I0 (instanceref fifo_Write_i_1)) - (portref I0 (instanceref frame_err_ocrd_i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) - (portref I1 (instanceref running_i_1)) - (portref I2 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) - (portref I2 (instanceref status_reg_1__i_2)) - (portref I3 (instanceref stop_Bit_Position_i_1)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__0_)) - ) - ) - (net (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (joined - (portref I4 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) - (portref I4 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) - (portref I4 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) - (portref I4 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) - (portref I4 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) - (portref I4 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) - (portref I4 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) - (portref O (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) - (portref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_) - ) - ) - (net clr_Status (joined - (portref I4 (instanceref status_reg_1__i_1)) - (portref clr_Status) - ) - ) - (net en_16x_Baud (joined - (portref CE (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__0_)) - (portref I0 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) - (portref I1 (instanceref fifo_Write_i_1)) - (portref I1 (instanceref frame_err_ocrd_i_1)) - (portref I1 (instanceref status_reg_1__i_2)) - (portref I2 (instanceref running_i_1)) - (portref I2 (instanceref stop_Bit_Position_i_1)) - (portref en_16x_Baud) - ) - ) - (net fifo_Write0 (joined - (portref O (instanceref fifo_Write_i_1)) - (portref fifo_Write0) - ) - ) - (net frame_err_ocrd (joined - (portref I4 (instanceref frame_err_ocrd_i_1)) - (portref frame_err_ocrd) - ) - ) - (net frame_err_ocrd_reg (joined - (portref O (instanceref frame_err_ocrd_i_1)) - (portref frame_err_ocrd_reg) - ) - ) - (net (rename in_0_ "in[0]") (joined - (portref I1 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) - (portref (member in 0)) - ) - ) - (net (rename in_1_ "in[1]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) - (portref (member in 1)) - ) - ) - (net (rename in_2_ "in[2]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) - (portref (member in 2)) - ) - ) - (net (rename in_3_ "in[3]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) - (portref (member in 3)) - ) - ) - (net (rename in_4_ "in[4]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) - (portref (member in 4)) - ) - ) - (net (rename in_5_ "in[5]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) - (portref (member in 5)) - ) - ) - (net (rename in_6_ "in[6]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) - (portref I1 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) - (portref (member in 6)) - ) - ) - (net (rename in_7_ "in[7]") (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) - (portref I0 (instanceref stop_Bit_Position_i_1)) - (portref (member in 7)) - ) - ) - (net p_11_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) - (portref p_11_out) - ) - ) - (net p_14_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) - (portref p_14_out) - ) - ) - (net p_17_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) - (portref p_17_out) - ) - ) - (net p_20_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) - (portref p_20_out) - ) - ) - (net p_2_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) - (portref p_2_out) - ) - ) - (net p_5_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) - (portref p_5_out) - ) - ) - (net p_8_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) - (portref p_8_out) - ) - ) - (net recycle (joined - (portref D (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref O (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) - ) - ) - (net running_reg (joined - (portref O (instanceref running_i_1)) - (portref running_reg) - ) - ) - (net running_reg_0 (joined - (portref I4 (instanceref running_i_1)) - (portref running_reg_0) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref INFERRED_GEN_data_reg_15__0_)) - (portref CLK (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I3 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) - (portref I3 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) - (portref I3 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) - (portref I3 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) - (portref I3 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) - (portref I3 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) - (portref I3 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) - (portref I3 (instanceref status_reg_1__i_1)) - (portref s_axi_aresetn) - ) - ) - (net scndry_out (joined - (portref I1 (instanceref status_reg_1__i_1)) - (portref I3 (instanceref fifo_Write_i_1)) - (portref I3 (instanceref frame_err_ocrd_i_1)) - (portref scndry_out) - ) - ) - (net start_Edge_Detected (joined - (portref I0 (instanceref running_i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) - (portref I3 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) - (portref start_Edge_Detected) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref I2 (instanceref status_reg_1__i_1)) - (portref status_reg_0_) - ) - ) - (net (rename status_reg_1__i_2_n_0 "status_reg[1]_i_2_n_0") (joined - (portref I0 (instanceref status_reg_1__i_1)) - (portref O (instanceref status_reg_1__i_2)) - ) - ) - (net status_reg_reg0 (joined - (portref O (instanceref status_reg_1__i_1)) - (portref status_reg_reg0) - ) - ) - (net stop_Bit_Position_reg (joined - (portref O (instanceref stop_Bit_Position_i_1)) - (portref stop_Bit_Position_reg) - ) - ) - (net stop_Bit_Position_reg_0 (joined - (portref I0 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) - (portref I0 (instanceref status_reg_1__i_2)) - (portref I1 (instanceref stop_Bit_Position_i_1)) - (portref I2 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) - (portref I2 (instanceref fifo_Write_i_1)) - (portref I2 (instanceref frame_err_ocrd_i_1)) - (portref I3 (instanceref running_i_1)) - (portref stop_Bit_Position_reg_0) - ) - ) - (net valid_rx (joined - (portref I1 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) - (portref valid_rx) - ) - ) - ) - - (property ORIG_REF_NAME (string "dynshreg_i_f")) - ) - ) - (cell axi_uart_cdc_sync (celltype GENERIC) - (view cdc_sync (viewtype NETLIST) - (interface - (port EN_16x_Baud_reg (direction INPUT)) - (port p_26_out (direction OUTPUT)) - (port rx (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port scndry_out (direction OUTPUT)) - (port start_Edge_Detected (direction INPUT)) - (port (rename in_0_ "in[0]") (direction INPUT)) - ) - (contents - (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property ASYNC_REG (boolean (true))) - (property box_type (string "PRIMITIVE")) - (property XILINX_LEGACY_PRIM (string "FDR")) - (property INIT (string "1'b0")) - ) - (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property ASYNC_REG (boolean (true))) - (property box_type (string "PRIMITIVE")) - (property XILINX_LEGACY_PRIM (string "FDR")) - (property INIT (string "1'b0")) - ) - (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property ASYNC_REG (boolean (true))) - (property box_type (string "PRIMITIVE")) - (property XILINX_LEGACY_PRIM (string "FDR")) - (property INIT (string "1'b0")) - ) - (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property ASYNC_REG (boolean (true))) - (property box_type (string "PRIMITIVE")) - (property XILINX_LEGACY_PRIM (string "FDR")) - (property INIT (string "1'b0")) - ) - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance (rename SERIAL_TO_PARALLEL_1__fifo_din_1__i_1 "SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFE00CE00")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (net (rename &_const0_ "") (joined - (portref G (instanceref GND)) - (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) - (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) - (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) - (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) - ) - ) - (net EN_16x_Baud_reg (joined - (portref I2 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) - (portref EN_16x_Baud_reg) - ) - ) - (net VCC_1 (joined - (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) - (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) - (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) - (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) - (portref P (instanceref VCC)) - ) - ) - (net (rename in_0_ "in[0]") (joined - (portref I4 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) - (portref in_0_) - ) - ) - (net p_26_out (joined - (portref O (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) - (portref p_26_out) - ) - ) - (net rx (joined - (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) - (portref rx) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) - (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) - (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) - (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I3 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) - (portref s_axi_aresetn) - ) - ) - (net s_level_out_d1_cdc_to (joined - (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) - (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) - ) - ) - (net s_level_out_d2 (joined - (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) - (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) - ) - ) - (net s_level_out_d3 (joined - (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) - (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) - ) - ) - (net scndry_out (joined - (portref I0 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) - (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) - (portref scndry_out) - ) - ) - (net start_Edge_Detected (joined - (portref I1 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) - (portref start_Edge_Detected) - ) - ) - ) - - (property ORIG_REF_NAME (string "cdc_sync")) - ) - ) - (cell axi_uart_cntr_incr_decr_addn_f_2 (celltype GENERIC) - (view cntr_incr_decr_addn_f_2 (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port Bus_RNW_reg_reg (direction INPUT)) - (port FIFO_Full_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) - (port Interrupt0 (direction OUTPUT)) - (port enable_interrupts (direction INPUT)) - (port fifo_Write (direction INPUT)) - (port fifo_full_p1 (direction OUTPUT)) - (port reset_RX_FIFO_reg (direction INPUT)) - (port rx_Data_Present_Pre (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port tx_Buffer_Empty_Pre (direction INPUT)) - (port valid_rx (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (direction INPUT)) - (port (array (rename Q "Q[4:0]") 5) (direction OUTPUT)) - (port (rename SS_0_ "SS[0]") (direction OUTPUT)) - ) - (contents - (instance FIFO_Full_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000009040000")) - ) - (instance FIFO_Full_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h7")) - (property SOFT_HLUTNM (string "soft_lutpair15")) - ) - (instance (rename INFERRED_GEN_cnt_i_0__i_1 "INFERRED_GEN.cnt_i[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hF70808F7")) - ) - (instance (rename INFERRED_GEN_cnt_i_1__i_1 "INFERRED_GEN.cnt_i[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hAAAAAA6A5595AAAA")) - ) - (instance (rename INFERRED_GEN_cnt_i_2__i_1 "INFERRED_GEN.cnt_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFE017F80")) - (property SOFT_HLUTNM (string "soft_lutpair15")) - ) - (instance (rename INFERRED_GEN_cnt_i_3__i_1 "INFERRED_GEN.cnt_i[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hF0F0F0E178F0F0F0")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_1 "INFERRED_GEN.cnt_i[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'hB")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_2 "INFERRED_GEN.cnt_i[4]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hF0F0F4F4F00AF0F0")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_4 "INFERRED_GEN.cnt_i[4]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h01")) - (property SOFT_HLUTNM (string "soft_lutpair16")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_5__0 "INFERRED_GEN.cnt_i[4]_i_5__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h7F")) - (property SOFT_HLUTNM (string "soft_lutpair16")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_6 "INFERRED_GEN.cnt_i[4]_i_6") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hDF")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_0_ "INFERRED_GEN.cnt_i_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_1_ "INFERRED_GEN.cnt_i_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_3_ "INFERRED_GEN.cnt_i_reg[3]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance Interrupt_i_2 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h1010F010")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (net (rename &_const1_ "") (joined - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_0__i_1)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_1__i_1)) - (portref Bus_RNW_reg) - ) - ) - (net Bus_RNW_reg_reg (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_2__i_1)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_1)) - (portref Bus_RNW_reg_reg) - ) - ) - (net FIFO_Full_i_2_n_0 (joined - (portref I5 (instanceref FIFO_Full_i_1)) - (portref O (instanceref FIFO_Full_i_2)) - ) - ) - (net FIFO_Full_reg (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_6)) - (portref FIFO_Full_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_0__i_1)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_1__i_1)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_2)) - (portref I3 (instanceref FIFO_Full_i_1)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_4__i_4_n_0 "INFERRED_GEN.cnt_i[4]_i_4_n_0") (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_2)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_4)) - ) - ) - (net (rename INFERRED_GEN_cnt_i_4__i_5__0_n_0 "INFERRED_GEN.cnt_i[4]_i_5__0_n_0") (joined - (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_2)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) - ) - ) - (net (rename INFERRED_GEN_cnt_i_4__i_6_n_0 "INFERRED_GEN.cnt_i[4]_i_6_n_0") (joined - (portref I0 (instanceref FIFO_Full_i_1)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_0__i_1)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_2__i_1)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_1__i_1)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_3__i_1)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_4__i_2)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_6)) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (joined - (portref I3 (instanceref Interrupt_i_2)) - (portref INFERRED_GEN_cnt_i_reg_4__0_0_) - ) - ) - (net Interrupt0 (joined - (portref O (instanceref Interrupt_i_2)) - (portref Interrupt0) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_2__i_1)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_1)) - (portref I1 (instanceref FIFO_Full_i_1)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_0__i_1)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_1__i_1)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_4__i_2)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref (member Q 4)) - ) - ) - (net (rename Q_1_ "Q[1]") (joined - (portref I0 (instanceref FIFO_Full_i_2)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_1__i_1)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_4)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_2__i_1)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_3__i_1)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref (member Q 3)) - ) - ) - (net (rename Q_2_ "Q[2]") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_4)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) - (portref I1 (instanceref FIFO_Full_i_2)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_2__i_1)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_3__i_1)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref (member Q 2)) - ) - ) - (net (rename Q_3_ "Q[3]") (joined - (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_1)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_4)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) - (portref I4 (instanceref FIFO_Full_i_1)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref (member Q 1)) - ) - ) - (net (rename Q_4_ "Q[4]") (joined - (portref I1 (instanceref Interrupt_i_2)) - (portref I2 (instanceref FIFO_Full_i_1)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_0__i_1)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_2)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_1__i_1)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref (member Q 0)) - ) - ) - (net (rename SS_0_ "SS[0]") (joined - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_1)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref SS_0_) - ) - ) - (net (rename addr_i_p1_0_ "addr_i_p1[0]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref O (instanceref INFERRED_GEN_cnt_i_0__i_1)) - ) - ) - (net (rename addr_i_p1_1_ "addr_i_p1[1]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref O (instanceref INFERRED_GEN_cnt_i_1__i_1)) - ) - ) - (net (rename addr_i_p1_2_ "addr_i_p1[2]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref O (instanceref INFERRED_GEN_cnt_i_2__i_1)) - ) - ) - (net (rename addr_i_p1_3_ "addr_i_p1[3]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref O (instanceref INFERRED_GEN_cnt_i_3__i_1)) - ) - ) - (net (rename addr_i_p1_4_ "addr_i_p1[4]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_2)) - ) - ) - (net enable_interrupts (joined - (portref I2 (instanceref Interrupt_i_2)) - (portref enable_interrupts) - ) - ) - (net fifo_Write (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_6)) - (portref fifo_Write) - ) - ) - (net fifo_full_p1 (joined - (portref O (instanceref FIFO_Full_i_1)) - (portref fifo_full_p1) - ) - ) - (net reset_RX_FIFO_reg (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_1)) - (portref reset_RX_FIFO_reg) - ) - ) - (net rx_Data_Present_Pre (joined - (portref I0 (instanceref Interrupt_i_2)) - (portref rx_Data_Present_Pre) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_1)) - (portref s_axi_aresetn) - ) - ) - (net tx_Buffer_Empty_Pre (joined - (portref I4 (instanceref Interrupt_i_2)) - (portref tx_Buffer_Empty_Pre) - ) - ) - (net valid_rx (joined - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_6)) - (portref valid_rx) - ) - ) - ) - - (property ORIG_REF_NAME (string "cntr_incr_decr_addn_f")) - ) - ) - (cell axi_uart_dynshreg_f_3 (celltype GENERIC) - (view dynshreg_f_3 (viewtype NETLIST) - (interface - (port FIFO_Full_reg (direction INPUT)) - (port fifo_Write (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port valid_rx (direction INPUT)) - (port (array (rename Q "Q[3:0]") 4) (direction INPUT)) - (port (array (rename in "in[0:7]") 8) (direction INPUT)) - (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) - ) - (contents - (instance (rename INFERRED_GEN_data_reg_15__0__srl16 "INFERRED_GEN.data_reg[15][0]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__1__srl16 "INFERRED_GEN.data_reg[15][1]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__2__srl16 "INFERRED_GEN.data_reg[15][2]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__3__srl16 "INFERRED_GEN.data_reg[15][3]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__4__srl16 "INFERRED_GEN.data_reg[15][4]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__5__srl16 "INFERRED_GEN.data_reg[15][5]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__6__srl16 "INFERRED_GEN.data_reg[15][6]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__7__srl16 "INFERRED_GEN.data_reg[15][7]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__7__srl16_i_1__0 "INFERRED_GEN.data_reg[15][7]_srl16_i_1__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h20")) - ) - (net FIFO_Full_reg (joined - (portref I1 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) - (portref FIFO_Full_reg) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref A0 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 3)) - ) - ) - (net (rename Q_1_ "Q[1]") (joined - (portref A1 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 2)) - ) - ) - (net (rename Q_2_ "Q[2]") (joined - (portref A2 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 1)) - ) - ) - (net (rename Q_3_ "Q[3]") (joined - (portref A3 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 0)) - ) - ) - (net fifo_Write (joined - (portref I2 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) - (portref fifo_Write) - ) - ) - (net fifo_wr (joined - (portref CE (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref O (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) - ) - ) - (net (rename in_0_ "in[0]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref (member in 0)) - ) - ) - (net (rename in_1_ "in[1]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref (member in 1)) - ) - ) - (net (rename in_2_ "in[2]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref (member in 2)) - ) - ) - (net (rename in_3_ "in[3]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref (member in 3)) - ) - ) - (net (rename in_4_ "in[4]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref (member in 4)) - ) - ) - (net (rename in_5_ "in[5]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref (member in 5)) - ) - ) - (net (rename in_6_ "in[6]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref (member in 6)) - ) - ) - (net (rename in_7_ "in[7]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member in 7)) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref Q (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref (member out 0)) - ) - ) - (net s_axi_aclk (joined - (portref CLK (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref s_axi_aclk) - ) - ) - (net valid_rx (joined - (portref I0 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) - (portref valid_rx) - ) - ) - ) - - (property ORIG_REF_NAME (string "dynshreg_f")) - ) - ) - (cell axi_uart_srl_fifo_rbu_f_1 (celltype GENERIC) - (view srl_fifo_rbu_f_1 (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port Bus_RNW_reg_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) - (port Interrupt0 (direction OUTPUT)) - (port clr_Status (direction INPUT)) - (port enable_interrupts (direction INPUT)) - (port fifo_Write (direction INPUT)) - (port reset_RX_FIFO_reg (direction INPUT)) - (port rx_Data_Present_Pre (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) - (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) - (port tx_Buffer_Empty_Pre (direction INPUT)) - (port valid_rx (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (array (rename in "in[0:7]") 8) (direction INPUT)) - (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) - (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) - ) - (contents - (instance CNTR_INCR_DECR_ADDN_F_I (viewref cntr_incr_decr_addn_f_2 (cellref axi_uart_cntr_incr_decr_addn_f_2 (libraryref work_library0_1)))) - (instance DYNSHREG_F_I (viewref dynshreg_f_3 (cellref axi_uart_dynshreg_f_3 (libraryref work_library0_1)))) - (instance FIFO_Full_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance (rename status_reg_2__i_1 "status_reg[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h00EA0000")) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref FIFO_Full_reg)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref Bus_RNW_reg) - ) - ) - (net Bus_RNW_reg_reg (joined - (portref Bus_RNW_reg_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref Bus_RNW_reg_reg) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_3 (joined - (portref (member Q 1) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 0) (instanceref DYNSHREG_F_I)) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_4 (joined - (portref (member Q 2) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 1) (instanceref DYNSHREG_F_I)) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_5 (joined - (portref (member Q 3) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 2) (instanceref DYNSHREG_F_I)) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_6 (joined - (portref (member Q 4) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 3) (instanceref DYNSHREG_F_I)) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref INFERRED_GEN_cnt_i_reg_4__0_) - ) - ) - (net Interrupt0 (joined - (portref Interrupt0 (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref Interrupt0) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref (member Q 0) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref Q_0_) - ) - ) - (net RX_FIFO_Reset (joined - (portref R (instanceref FIFO_Full_reg)) - (portref SS_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) - ) - ) - (net clr_Status (joined - (portref I3 (instanceref status_reg_2__i_1)) - (portref clr_Status) - ) - ) - (net enable_interrupts (joined - (portref enable_interrupts (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref enable_interrupts) - ) - ) - (net fifo_Write (joined - (portref I1 (instanceref status_reg_2__i_1)) - (portref fifo_Write (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref fifo_Write (instanceref DYNSHREG_F_I)) - (portref fifo_Write) - ) - ) - (net fifo_full_p1 (joined - (portref D (instanceref FIFO_Full_reg)) - (portref fifo_full_p1 (instanceref CNTR_INCR_DECR_ADDN_F_I)) - ) - ) - (net (rename in_0_ "in[0]") (joined - (portref (member in 0) (instanceref DYNSHREG_F_I)) - (portref (member in 0)) - ) - ) - (net (rename in_1_ "in[1]") (joined - (portref (member in 1) (instanceref DYNSHREG_F_I)) - (portref (member in 1)) - ) - ) - (net (rename in_2_ "in[2]") (joined - (portref (member in 2) (instanceref DYNSHREG_F_I)) - (portref (member in 2)) - ) - ) - (net (rename in_3_ "in[3]") (joined - (portref (member in 3) (instanceref DYNSHREG_F_I)) - (portref (member in 3)) - ) - ) - (net (rename in_4_ "in[4]") (joined - (portref (member in 4) (instanceref DYNSHREG_F_I)) - (portref (member in 4)) - ) - ) - (net (rename in_5_ "in[5]") (joined - (portref (member in 5) (instanceref DYNSHREG_F_I)) - (portref (member in 5)) - ) - ) - (net (rename in_6_ "in[6]") (joined - (portref (member in 6) (instanceref DYNSHREG_F_I)) - (portref (member in 6)) - ) - ) - (net (rename in_7_ "in[7]") (joined - (portref (member in 7) (instanceref DYNSHREG_F_I)) - (portref (member in 7)) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref (member out 7) (instanceref DYNSHREG_F_I)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref (member out 6) (instanceref DYNSHREG_F_I)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref (member out 5) (instanceref DYNSHREG_F_I)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref (member out 4) (instanceref DYNSHREG_F_I)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref (member out 3) (instanceref DYNSHREG_F_I)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref (member out 2) (instanceref DYNSHREG_F_I)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref (member out 1) (instanceref DYNSHREG_F_I)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref (member out 0) (instanceref DYNSHREG_F_I)) - (portref (member out 0)) - ) - ) - (net reset_RX_FIFO_reg (joined - (portref reset_RX_FIFO_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref reset_RX_FIFO_reg) - ) - ) - (net rx_Data_Present_Pre (joined - (portref rx_Data_Present_Pre (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref rx_Data_Present_Pre) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref FIFO_Full_reg)) - (portref s_axi_aclk (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref s_axi_aclk (instanceref DYNSHREG_F_I)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I4 (instanceref status_reg_2__i_1)) - (portref s_axi_aresetn (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref s_axi_aresetn) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref I0 (instanceref status_reg_2__i_1)) - (portref status_reg_0_) - ) - ) - (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined - (portref FIFO_Full_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref FIFO_Full_reg (instanceref DYNSHREG_F_I)) - (portref I2 (instanceref status_reg_2__i_1)) - (portref Q (instanceref FIFO_Full_reg)) - (portref status_reg_reg_2_) - ) - ) - (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined - (portref O (instanceref status_reg_2__i_1)) - (portref status_reg_reg_2__0) - ) - ) - (net tx_Buffer_Empty_Pre (joined - (portref tx_Buffer_Empty_Pre (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref tx_Buffer_Empty_Pre) - ) - ) - (net valid_rx (joined - (portref valid_rx (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref valid_rx (instanceref DYNSHREG_F_I)) - (portref valid_rx) - ) - ) - ) - - (property ORIG_REF_NAME (string "srl_fifo_rbu_f")) - ) - ) - (cell axi_uart_srl_fifo_f_0 (celltype GENERIC) - (view srl_fifo_f_0 (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port Bus_RNW_reg_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) - (port Interrupt0 (direction OUTPUT)) - (port clr_Status (direction INPUT)) - (port enable_interrupts (direction INPUT)) - (port fifo_Write (direction INPUT)) - (port reset_RX_FIFO_reg (direction INPUT)) - (port rx_Data_Present_Pre (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) - (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) - (port tx_Buffer_Empty_Pre (direction INPUT)) - (port valid_rx (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (array (rename in "in[0:7]") 8) (direction INPUT)) - (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) - (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) - ) - (contents - (instance I_SRL_FIFO_RBU_F (viewref srl_fifo_rbu_f_1 (cellref axi_uart_srl_fifo_rbu_f_1 (libraryref work_library0_1)))) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref Bus_RNW_reg) - ) - ) - (net Bus_RNW_reg_reg (joined - (portref Bus_RNW_reg_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref Bus_RNW_reg_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_SRL_FIFO_RBU_F)) - (portref INFERRED_GEN_cnt_i_reg_4__0_) - ) - ) - (net Interrupt0 (joined - (portref Interrupt0 (instanceref I_SRL_FIFO_RBU_F)) - (portref Interrupt0) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref Q_0_ (instanceref I_SRL_FIFO_RBU_F)) - (portref Q_0_) - ) - ) - (net clr_Status (joined - (portref clr_Status (instanceref I_SRL_FIFO_RBU_F)) - (portref clr_Status) - ) - ) - (net enable_interrupts (joined - (portref enable_interrupts (instanceref I_SRL_FIFO_RBU_F)) - (portref enable_interrupts) - ) - ) - (net fifo_Write (joined - (portref fifo_Write (instanceref I_SRL_FIFO_RBU_F)) - (portref fifo_Write) - ) - ) - (net (rename in_0_ "in[0]") (joined - (portref (member in 0) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 0)) - ) - ) - (net (rename in_1_ "in[1]") (joined - (portref (member in 1) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 1)) - ) - ) - (net (rename in_2_ "in[2]") (joined - (portref (member in 2) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 2)) - ) - ) - (net (rename in_3_ "in[3]") (joined - (portref (member in 3) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 3)) - ) - ) - (net (rename in_4_ "in[4]") (joined - (portref (member in 4) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 4)) - ) - ) - (net (rename in_5_ "in[5]") (joined - (portref (member in 5) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 5)) - ) - ) - (net (rename in_6_ "in[6]") (joined - (portref (member in 6) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 6)) - ) - ) - (net (rename in_7_ "in[7]") (joined - (portref (member in 7) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member in 7)) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref (member out 7) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref (member out 6) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref (member out 5) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref (member out 4) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref (member out 3) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref (member out 2) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref (member out 1) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref (member out 0) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member out 0)) - ) - ) - (net reset_RX_FIFO_reg (joined - (portref reset_RX_FIFO_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref reset_RX_FIFO_reg) - ) - ) - (net rx_Data_Present_Pre (joined - (portref rx_Data_Present_Pre (instanceref I_SRL_FIFO_RBU_F)) - (portref rx_Data_Present_Pre) - ) - ) - (net s_axi_aclk (joined - (portref s_axi_aclk (instanceref I_SRL_FIFO_RBU_F)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref I_SRL_FIFO_RBU_F)) - (portref s_axi_aresetn) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref status_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) - (portref status_reg_0_) - ) - ) - (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined - (portref status_reg_reg_2_ (instanceref I_SRL_FIFO_RBU_F)) - (portref status_reg_reg_2_) - ) - ) - (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined - (portref status_reg_reg_2__0 (instanceref I_SRL_FIFO_RBU_F)) - (portref status_reg_reg_2__0) - ) - ) - (net tx_Buffer_Empty_Pre (joined - (portref tx_Buffer_Empty_Pre (instanceref I_SRL_FIFO_RBU_F)) - (portref tx_Buffer_Empty_Pre) - ) - ) - (net valid_rx (joined - (portref valid_rx (instanceref I_SRL_FIFO_RBU_F)) - (portref valid_rx) - ) - ) - ) - - (property ORIG_REF_NAME (string "srl_fifo_f")) - ) - ) - (cell axi_uart_uartlite_rx (celltype GENERIC) - (view uartlite_rx (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port Bus_RNW_reg_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) - (port Interrupt0 (direction OUTPUT)) - (port clr_Status (direction INPUT)) - (port en_16x_Baud (direction INPUT)) - (port enable_interrupts (direction INPUT)) - (port reset_RX_FIFO_reg (direction INPUT)) - (port rx (direction INPUT)) - (port rx_Data_Present_Pre (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port status_reg_reg0 (direction OUTPUT)) - (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) - (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) - (port tx_Buffer_Empty_Pre (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (rename SR_0_ "SR[0]") (direction OUTPUT)) - (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) - (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) - ) - (contents - (instance DELAY_16_I (viewref dynshreg_i_f (cellref axi_uart_dynshreg_i_f (libraryref work_library0_1)))) - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance INPUT_DOUBLE_REGS3 (viewref cdc_sync (cellref axi_uart_cdc_sync (libraryref work_library0_1)))) - (instance Interrupt_i_1 (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) - (property INIT (string "2'h1")) - ) - (instance (rename SERIAL_TO_PARALLEL_1__fifo_din_reg_1_ "SERIAL_TO_PARALLEL[1].fifo_din_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_3__fifo_din_reg_3_ "SERIAL_TO_PARALLEL[3].fifo_din_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_4__fifo_din_reg_4_ "SERIAL_TO_PARALLEL[4].fifo_din_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_5__fifo_din_reg_5_ "SERIAL_TO_PARALLEL[5].fifo_din_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_6__fifo_din_reg_6_ "SERIAL_TO_PARALLEL[6].fifo_din_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_7__fifo_din_reg_7_ "SERIAL_TO_PARALLEL[7].fifo_din_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_reg_8_ "SERIAL_TO_PARALLEL[8].fifo_din_reg[8]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance SRL_FIFO_I (viewref srl_fifo_f_0 (cellref axi_uart_srl_fifo_f_0 (libraryref work_library0_1)))) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance fifo_Write_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance frame_err_ocrd_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance running_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_1_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_2_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_3_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_4_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_5_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_6_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_7_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_8_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_9_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance start_Edge_Detected_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000000000010")) - ) - (instance start_Edge_Detected_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000000000010")) - ) - (instance start_Edge_Detected_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance stop_Bit_Position_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance valid_rx_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hBA")) - ) - (instance valid_rx_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (net (rename &_const0_ "") (joined - (portref G (instanceref GND)) - (portref R (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) - (portref R (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) - (portref R (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) - (portref R (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) - (portref R (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) - (portref R (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) - (portref R (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) - (portref R (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) - ) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) - (portref CE (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) - (portref CE (instanceref fifo_Write_reg)) - (portref CE (instanceref frame_err_ocrd_reg)) - (portref CE (instanceref running_reg)) - (portref CE (instanceref stop_Bit_Position_reg)) - (portref CE (instanceref valid_rx_reg)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref SRL_FIFO_I)) - (portref Bus_RNW_reg) - ) - ) - (net Bus_RNW_reg_reg (joined - (portref Bus_RNW_reg_reg (instanceref SRL_FIFO_I)) - (portref Bus_RNW_reg_reg) - ) - ) - (net DELAY_16_I_n_1 (joined - (portref EN_16x_Baud_reg (instanceref INPUT_DOUBLE_REGS3)) - (portref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ (instanceref DELAY_16_I)) - ) - ) - (net DELAY_16_I_n_10 (joined - (portref D (instanceref stop_Bit_Position_reg)) - (portref stop_Bit_Position_reg (instanceref DELAY_16_I)) - ) - ) - (net DELAY_16_I_n_11 (joined - (portref D (instanceref frame_err_ocrd_reg)) - (portref frame_err_ocrd_reg (instanceref DELAY_16_I)) - ) - ) - (net DELAY_16_I_n_12 (joined - (portref D (instanceref running_reg)) - (portref running_reg (instanceref DELAY_16_I)) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref SRL_FIFO_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref SRL_FIFO_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref SRL_FIFO_I)) - (portref INFERRED_GEN_cnt_i_reg_4__0_) - ) - ) - (net Interrupt0 (joined - (portref Interrupt0 (instanceref SRL_FIFO_I)) - (portref Interrupt0) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref Q_0_ (instanceref SRL_FIFO_I)) - (portref Q_0_) - ) - ) - (net RX_D2 (joined - (portref D (instanceref rx_1_reg)) - (portref scndry_out (instanceref DELAY_16_I)) - (portref scndry_out (instanceref INPUT_DOUBLE_REGS3)) - ) - ) - (net (rename SR_0_ "SR[0]") (joined - (portref O (instanceref Interrupt_i_1)) - (portref R (instanceref fifo_Write_reg)) - (portref R (instanceref frame_err_ocrd_reg)) - (portref R (instanceref running_reg)) - (portref R (instanceref rx_1_reg)) - (portref R (instanceref rx_2_reg)) - (portref R (instanceref rx_3_reg)) - (portref R (instanceref rx_4_reg)) - (portref R (instanceref rx_5_reg)) - (portref R (instanceref rx_6_reg)) - (portref R (instanceref rx_7_reg)) - (portref R (instanceref rx_8_reg)) - (portref R (instanceref rx_9_reg)) - (portref R (instanceref start_Edge_Detected_reg)) - (portref R (instanceref stop_Bit_Position_reg)) - (portref R (instanceref valid_rx_reg)) - (portref SR_0_) - ) - ) - (net clr_Status (joined - (portref clr_Status (instanceref DELAY_16_I)) - (portref clr_Status (instanceref SRL_FIFO_I)) - (portref clr_Status) - ) - ) - (net en_16x_Baud (joined - (portref CE (instanceref rx_1_reg)) - (portref CE (instanceref rx_2_reg)) - (portref CE (instanceref rx_3_reg)) - (portref CE (instanceref rx_4_reg)) - (portref CE (instanceref rx_5_reg)) - (portref CE (instanceref rx_6_reg)) - (portref CE (instanceref rx_7_reg)) - (portref CE (instanceref rx_8_reg)) - (portref CE (instanceref rx_9_reg)) - (portref CE (instanceref start_Edge_Detected_reg)) - (portref en_16x_Baud (instanceref DELAY_16_I)) - (portref en_16x_Baud) - ) - ) - (net enable_interrupts (joined - (portref enable_interrupts (instanceref SRL_FIFO_I)) - (portref enable_interrupts) - ) - ) - (net fifo_Write (joined - (portref I1 (instanceref valid_rx_i_1)) - (portref Q (instanceref fifo_Write_reg)) - (portref fifo_Write (instanceref SRL_FIFO_I)) - ) - ) - (net fifo_Write0 (joined - (portref D (instanceref fifo_Write_reg)) - (portref fifo_Write0 (instanceref DELAY_16_I)) - ) - ) - (net (rename fifo_din_1_ "fifo_din[1]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) - (portref (member in 0) (instanceref DELAY_16_I)) - (portref in_0_ (instanceref INPUT_DOUBLE_REGS3)) - (portref (member in 0) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_2_ "fifo_din[2]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) - (portref (member in 1) (instanceref DELAY_16_I)) - (portref (member in 1) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_3_ "fifo_din[3]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) - (portref (member in 2) (instanceref DELAY_16_I)) - (portref (member in 2) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_4_ "fifo_din[4]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) - (portref (member in 3) (instanceref DELAY_16_I)) - (portref (member in 3) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_5_ "fifo_din[5]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) - (portref (member in 4) (instanceref DELAY_16_I)) - (portref (member in 4) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_6_ "fifo_din[6]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) - (portref (member in 5) (instanceref DELAY_16_I)) - (portref (member in 5) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_7_ "fifo_din[7]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) - (portref (member in 6) (instanceref DELAY_16_I)) - (portref (member in 6) (instanceref SRL_FIFO_I)) - ) - ) - (net (rename fifo_din_8_ "fifo_din[8]") (joined - (portref Q (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) - (portref (member in 7) (instanceref DELAY_16_I)) - (portref (member in 7) (instanceref SRL_FIFO_I)) - ) - ) - (net frame_err_ocrd (joined - (portref I5 (instanceref start_Edge_Detected_i_1)) - (portref Q (instanceref frame_err_ocrd_reg)) - (portref frame_err_ocrd (instanceref DELAY_16_I)) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref (member out 7) (instanceref SRL_FIFO_I)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref (member out 6) (instanceref SRL_FIFO_I)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref (member out 5) (instanceref SRL_FIFO_I)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref (member out 4) (instanceref SRL_FIFO_I)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref (member out 3) (instanceref SRL_FIFO_I)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref (member out 2) (instanceref SRL_FIFO_I)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref (member out 1) (instanceref SRL_FIFO_I)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref (member out 0) (instanceref SRL_FIFO_I)) - (portref (member out 0)) - ) - ) - (net p_11_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) - (portref p_11_out (instanceref DELAY_16_I)) - ) - ) - (net p_14_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) - (portref p_14_out (instanceref DELAY_16_I)) - ) - ) - (net p_17_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) - (portref p_17_out (instanceref DELAY_16_I)) - ) - ) - (net p_20_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) - (portref p_20_out (instanceref DELAY_16_I)) - ) - ) - (net p_26_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) - (portref p_26_out (instanceref INPUT_DOUBLE_REGS3)) - ) - ) - (net p_2_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) - (portref p_2_out (instanceref DELAY_16_I)) - ) - ) - (net p_5_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) - (portref p_5_out (instanceref DELAY_16_I)) - ) - ) - (net p_8_out (joined - (portref D (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) - (portref p_8_out (instanceref DELAY_16_I)) - ) - ) - (net reset_RX_FIFO_reg (joined - (portref reset_RX_FIFO_reg (instanceref SRL_FIFO_I)) - (portref reset_RX_FIFO_reg) - ) - ) - (net running_reg_n_0 (joined - (portref I3 (instanceref start_Edge_Detected_i_2)) - (portref Q (instanceref running_reg)) - (portref running_reg_0 (instanceref DELAY_16_I)) - ) - ) - (net rx (joined - (portref rx (instanceref INPUT_DOUBLE_REGS3)) - (portref rx) - ) - ) - (net rx_1 (joined - (portref D (instanceref rx_2_reg)) - (portref I4 (instanceref start_Edge_Detected_i_1)) - (portref Q (instanceref rx_1_reg)) - ) - ) - (net rx_2 (joined - (portref D (instanceref rx_3_reg)) - (portref I1 (instanceref start_Edge_Detected_i_1)) - (portref Q (instanceref rx_2_reg)) - ) - ) - (net rx_3 (joined - (portref D (instanceref rx_4_reg)) - (portref I3 (instanceref start_Edge_Detected_i_1)) - (portref Q (instanceref rx_3_reg)) - ) - ) - (net rx_4 (joined - (portref D (instanceref rx_5_reg)) - (portref I5 (instanceref start_Edge_Detected_i_2)) - (portref Q (instanceref rx_4_reg)) - ) - ) - (net rx_5 (joined - (portref D (instanceref rx_6_reg)) - (portref I0 (instanceref start_Edge_Detected_i_2)) - (portref Q (instanceref rx_5_reg)) - ) - ) - (net rx_6 (joined - (portref D (instanceref rx_7_reg)) - (portref I4 (instanceref start_Edge_Detected_i_2)) - (portref Q (instanceref rx_6_reg)) - ) - ) - (net rx_7 (joined - (portref D (instanceref rx_8_reg)) - (portref I1 (instanceref start_Edge_Detected_i_2)) - (portref Q (instanceref rx_7_reg)) - ) - ) - (net rx_8 (joined - (portref D (instanceref rx_9_reg)) - (portref I0 (instanceref start_Edge_Detected_i_1)) - (portref Q (instanceref rx_8_reg)) - ) - ) - (net rx_9 (joined - (portref I2 (instanceref start_Edge_Detected_i_2)) - (portref Q (instanceref rx_9_reg)) - ) - ) - (net rx_Data_Present_Pre (joined - (portref rx_Data_Present_Pre (instanceref SRL_FIFO_I)) - (portref rx_Data_Present_Pre) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) - (portref C (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) - (portref C (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) - (portref C (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) - (portref C (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) - (portref C (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) - (portref C (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) - (portref C (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) - (portref C (instanceref fifo_Write_reg)) - (portref C (instanceref frame_err_ocrd_reg)) - (portref C (instanceref running_reg)) - (portref C (instanceref rx_1_reg)) - (portref C (instanceref rx_2_reg)) - (portref C (instanceref rx_3_reg)) - (portref C (instanceref rx_4_reg)) - (portref C (instanceref rx_5_reg)) - (portref C (instanceref rx_6_reg)) - (portref C (instanceref rx_7_reg)) - (portref C (instanceref rx_8_reg)) - (portref C (instanceref rx_9_reg)) - (portref C (instanceref start_Edge_Detected_reg)) - (portref C (instanceref stop_Bit_Position_reg)) - (portref C (instanceref valid_rx_reg)) - (portref s_axi_aclk (instanceref DELAY_16_I)) - (portref s_axi_aclk (instanceref INPUT_DOUBLE_REGS3)) - (portref s_axi_aclk (instanceref SRL_FIFO_I)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I0 (instanceref Interrupt_i_1)) - (portref s_axi_aresetn (instanceref DELAY_16_I)) - (portref s_axi_aresetn (instanceref INPUT_DOUBLE_REGS3)) - (portref s_axi_aresetn (instanceref SRL_FIFO_I)) - (portref s_axi_aresetn) - ) - ) - (net start_Edge_Detected (joined - (portref I0 (instanceref valid_rx_i_1)) - (portref Q (instanceref start_Edge_Detected_reg)) - (portref start_Edge_Detected (instanceref DELAY_16_I)) - (portref start_Edge_Detected (instanceref INPUT_DOUBLE_REGS3)) - ) - ) - (net start_Edge_Detected0 (joined - (portref D (instanceref start_Edge_Detected_reg)) - (portref O (instanceref start_Edge_Detected_i_1)) - ) - ) - (net start_Edge_Detected_i_2_n_0 (joined - (portref I2 (instanceref start_Edge_Detected_i_1)) - (portref O (instanceref start_Edge_Detected_i_2)) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref status_reg_0_ (instanceref SRL_FIFO_I)) - (portref (member status_reg 1)) - ) - ) - (net (rename status_reg_1_ "status_reg[1]") (joined - (portref status_reg_0_ (instanceref DELAY_16_I)) - (portref (member status_reg 0)) - ) - ) - (net status_reg_reg0 (joined - (portref status_reg_reg0 (instanceref DELAY_16_I)) - (portref status_reg_reg0) - ) - ) - (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined - (portref status_reg_reg_2_ (instanceref SRL_FIFO_I)) - (portref status_reg_reg_2_) - ) - ) - (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined - (portref status_reg_reg_2__0 (instanceref SRL_FIFO_I)) - (portref status_reg_reg_2__0) - ) - ) - (net stop_Bit_Position_reg_n_0 (joined - (portref Q (instanceref stop_Bit_Position_reg)) - (portref stop_Bit_Position_reg_0 (instanceref DELAY_16_I)) - ) - ) - (net tx_Buffer_Empty_Pre (joined - (portref tx_Buffer_Empty_Pre (instanceref SRL_FIFO_I)) - (portref tx_Buffer_Empty_Pre) - ) - ) - (net valid_rx (joined - (portref I2 (instanceref valid_rx_i_1)) - (portref Q (instanceref valid_rx_reg)) - (portref valid_rx (instanceref DELAY_16_I)) - (portref valid_rx (instanceref SRL_FIFO_I)) - ) - ) - (net valid_rx_i_1_n_0 (joined - (portref D (instanceref valid_rx_reg)) - (portref O (instanceref valid_rx_i_1)) - ) - ) - ) - - (property ORIG_REF_NAME (string "uartlite_rx")) - ) - ) - (cell axi_uart_dynshreg_i_f__parameterized0 (celltype GENERIC) - (view dynshreg_i_f__parameterized0 (viewtype NETLIST) - (interface - (port en_16x_Baud (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port tx_Data_Enable_reg (direction OUTPUT)) - (port tx_Data_Enable_reg_0 (direction INPUT)) - ) - (contents - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance (rename INFERRED_GEN_data_reg_14__0__srl15 "INFERRED_GEN.data_reg[14][0]_srl15") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0001")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__0_ "INFERRED_GEN.data_reg[15][0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance tx_Data_Enable_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h20")) - ) - (net (rename &_const0_ "") (joined - (portref A0 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref G (instanceref GND)) - (portref R (instanceref INFERRED_GEN_data_reg_15__0_)) - ) - ) - (net (rename &_const1_ "") (joined - (portref A1 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref A2 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref A3 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref P (instanceref VCC)) - ) - ) - (net (rename INFERRED_GEN_data_reg_14__0__srl15_n_0 "INFERRED_GEN.data_reg[14][0]_srl15_n_0") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__0_)) - (portref Q (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - ) - ) - (net (rename INFERRED_GEN_data_reg_n_0__15__0_ "INFERRED_GEN.data_reg_n_0_[15][0]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref I0 (instanceref tx_Data_Enable_i_1)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__0_)) - ) - ) - (net en_16x_Baud (joined - (portref CE (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__0_)) - (portref I2 (instanceref tx_Data_Enable_i_1)) - (portref en_16x_Baud) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref INFERRED_GEN_data_reg_15__0_)) - (portref CLK (instanceref INFERRED_GEN_data_reg_14__0__srl15)) - (portref s_axi_aclk) - ) - ) - (net tx_Data_Enable_reg (joined - (portref O (instanceref tx_Data_Enable_i_1)) - (portref tx_Data_Enable_reg) - ) - ) - (net tx_Data_Enable_reg_0 (joined - (portref I1 (instanceref tx_Data_Enable_i_1)) - (portref tx_Data_Enable_reg_0) - ) - ) - ) - - (property ORIG_REF_NAME (string "dynshreg_i_f")) - ) - ) - (cell axi_uart_cntr_incr_decr_addn_f (celltype GENERIC) - (view cntr_incr_decr_addn_f (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) - (port fifo_Read (direction INPUT)) - (port fifo_full_p1 (direction OUTPUT)) - (port reset_TX_FIFO_reg (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port tx_Buffer_Full (direction INPUT)) - (port tx_DataBits (direction INPUT)) - (port tx_Data_Enable_reg (direction INPUT)) - (port tx_Start (direction INPUT)) - (port tx_Start0 (direction OUTPUT)) - (port (array (rename Q "Q[4:0]") 5) (direction OUTPUT)) - (port (rename SS_0_ "SS[0]") (direction OUTPUT)) - ) - (contents - (instance FIFO_Full_i_1__0 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000004090000")) - ) - (instance FIFO_Full_i_2__0 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h7")) - ) - (instance (rename INFERRED_GEN_cnt_i_0__i_1__0 "INFERRED_GEN.cnt_i[0]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hBBB4BBBB444B4444")) - ) - (instance (rename INFERRED_GEN_cnt_i_1__i_1__0 "INFERRED_GEN.cnt_i[1]_i_1__0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hAA9A65AA")) - (property SOFT_HLUTNM (string "soft_lutpair17")) - ) - (instance (rename INFERRED_GEN_cnt_i_2__i_1__0 "INFERRED_GEN.cnt_i[2]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hF4FF0B00FFBF0040")) - ) - (instance (rename INFERRED_GEN_cnt_i_3__i_1__0 "INFERRED_GEN.cnt_i[3]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hAAAA6AAAAAA9AAAA")) - ) - (instance (rename INFERRED_GEN_cnt_i_3__i_2__0 "INFERRED_GEN.cnt_i[3]_i_2__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'hB")) - (property SOFT_HLUTNM (string "soft_lutpair17")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_1__0 "INFERRED_GEN.cnt_i[4]_i_1__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'hB")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_2__0 "INFERRED_GEN.cnt_i[4]_i_2__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hF0F0FAFAF003F0F0")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_3__0 "INFERRED_GEN.cnt_i[4]_i_3__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0004")) - (property SOFT_HLUTNM (string "soft_lutpair18")) - ) - (instance (rename INFERRED_GEN_cnt_i_4__i_4__0 "INFERRED_GEN.cnt_i[4]_i_4__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h7F")) - (property SOFT_HLUTNM (string "soft_lutpair18")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_0_ "INFERRED_GEN.cnt_i_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_1_ "INFERRED_GEN.cnt_i_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_3_ "INFERRED_GEN.cnt_i_reg[3]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance tx_Start_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0F02")) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref CE (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref I3 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - (portref Bus_RNW_reg) - ) - ) - (net FIFO_Full_i_2__0_n_0 (joined - (portref I5 (instanceref FIFO_Full_i_1__0)) - (portref O (instanceref FIFO_Full_i_2__0)) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref I4 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined - (portref I0 (instanceref FIFO_Full_i_1__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_3__i_2__0_n_0 "INFERRED_GEN.cnt_i[3]_i_2__0_n_0") (joined - (portref I3 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - (portref O (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) - ) - ) - (net (rename INFERRED_GEN_cnt_i_4__i_3__0_n_0 "INFERRED_GEN.cnt_i[4]_i_3__0_n_0") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) - ) - ) - (net (rename INFERRED_GEN_cnt_i_4__i_4__0_n_0 "INFERRED_GEN.cnt_i[4]_i_4__0_n_0") (joined - (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref I1 (instanceref FIFO_Full_i_1__0)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref (member Q 4)) - ) - ) - (net (rename Q_1_ "Q[1]") (joined - (portref I0 (instanceref FIFO_Full_i_2__0)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) - (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) - (portref I5 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref (member Q 3)) - ) - ) - (net (rename Q_2_ "Q[2]") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) - (portref I1 (instanceref FIFO_Full_i_2__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) - (portref I4 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref (member Q 2)) - ) - ) - (net (rename Q_3_ "Q[3]") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) - (portref I4 (instanceref FIFO_Full_i_1__0)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref (member Q 1)) - ) - ) - (net (rename Q_4_ "Q[4]") (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) - (portref I1 (instanceref tx_Start_i_1)) - (portref I2 (instanceref FIFO_Full_i_1__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - (portref Q (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref (member Q 0)) - ) - ) - (net (rename SS_0_ "SS[0]") (joined - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref S (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref SS_0_) - ) - ) - (net (rename addr_i_p1_0_ "addr_i_p1[0]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref O (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - ) - ) - (net (rename addr_i_p1_1_ "addr_i_p1[1]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref O (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) - ) - ) - (net (rename addr_i_p1_2_ "addr_i_p1[2]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref O (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - ) - ) - (net (rename addr_i_p1_3_ "addr_i_p1[3]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref O (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) - ) - ) - (net (rename addr_i_p1_4_ "addr_i_p1[4]") (joined - (portref D (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref O (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - ) - ) - (net fifo_Read (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) - (portref I2 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) - (portref I3 (instanceref FIFO_Full_i_1__0)) - (portref fifo_Read) - ) - ) - (net fifo_full_p1 (joined - (portref O (instanceref FIFO_Full_i_1__0)) - (portref fifo_full_p1) - ) - ) - (net reset_TX_FIFO_reg (joined - (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) - (portref reset_TX_FIFO_reg) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref INFERRED_GEN_cnt_i_reg_0_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_1_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_2_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_3_)) - (portref C (instanceref INFERRED_GEN_cnt_i_reg_4_)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) - (portref s_axi_aresetn) - ) - ) - (net tx_Buffer_Full (joined - (portref I2 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) - (portref tx_Buffer_Full) - ) - ) - (net tx_DataBits (joined - (portref I2 (instanceref tx_Start_i_1)) - (portref tx_DataBits) - ) - ) - (net tx_Data_Enable_reg (joined - (portref I0 (instanceref tx_Start_i_1)) - (portref tx_Data_Enable_reg) - ) - ) - (net tx_Start (joined - (portref I3 (instanceref tx_Start_i_1)) - (portref tx_Start) - ) - ) - (net tx_Start0 (joined - (portref O (instanceref tx_Start_i_1)) - (portref tx_Start0) - ) - ) - ) - - (property ORIG_REF_NAME (string "cntr_incr_decr_addn_f")) - ) - ) - (cell axi_uart_dynshreg_f (celltype GENERIC) - (view dynshreg_f (viewtype NETLIST) - (interface - (port fifo_wr (direction INPUT)) - (port mux_Out (direction OUTPUT)) - (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) - (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) - (port p_4_in (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port (array (rename Q "Q[3:0]") 4) (direction INPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) - ) - (contents - (instance (rename INFERRED_GEN_data_reg_15__0__srl16 "INFERRED_GEN.data_reg[15][0]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__1__srl16 "INFERRED_GEN.data_reg[15][1]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__2__srl16 "INFERRED_GEN.data_reg[15][2]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__3__srl16 "INFERRED_GEN.data_reg[15][3]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__4__srl16 "INFERRED_GEN.data_reg[15][4]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__5__srl16 "INFERRED_GEN.data_reg[15][5]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__6__srl16 "INFERRED_GEN.data_reg[15][6]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ")) - ) - (instance (rename INFERRED_GEN_data_reg_15__7__srl16 "INFERRED_GEN.data_reg[15][7]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) - (property INIT (string "16'h0000")) - (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) - (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ")) - ) - (instance serial_Data_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFFFE")) - ) - (instance serial_Data_i_2 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h44400040")) - ) - (instance serial_Data_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h88800080")) - ) - (instance serial_Data_i_4 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h44400040")) - ) - (instance serial_Data_i_5 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h000A000C")) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref A0 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A0 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 3)) - ) - ) - (net (rename Q_1_ "Q[1]") (joined - (portref A1 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A1 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 2)) - ) - ) - (net (rename Q_2_ "Q[2]") (joined - (portref A2 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A2 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 1)) - ) - ) - (net (rename Q_3_ "Q[3]") (joined - (portref A3 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref A3 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member Q 0)) - ) - ) - (net (rename fifo_DOut_0_ "fifo_DOut[0]") (joined - (portref I1 (instanceref serial_Data_i_5)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - ) - ) - (net (rename fifo_DOut_1_ "fifo_DOut[1]") (joined - (portref I2 (instanceref serial_Data_i_4)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - ) - ) - (net (rename fifo_DOut_2_ "fifo_DOut[2]") (joined - (portref I2 (instanceref serial_Data_i_2)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - ) - ) - (net (rename fifo_DOut_3_ "fifo_DOut[3]") (joined - (portref I4 (instanceref serial_Data_i_4)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - ) - ) - (net (rename fifo_DOut_4_ "fifo_DOut[4]") (joined - (portref I0 (instanceref serial_Data_i_5)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - ) - ) - (net (rename fifo_DOut_5_ "fifo_DOut[5]") (joined - (portref I2 (instanceref serial_Data_i_3)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - ) - ) - (net (rename fifo_DOut_6_ "fifo_DOut[6]") (joined - (portref I4 (instanceref serial_Data_i_2)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - ) - ) - (net (rename fifo_DOut_7_ "fifo_DOut[7]") (joined - (portref I4 (instanceref serial_Data_i_3)) - (portref Q (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - ) - ) - (net fifo_wr (joined - (portref CE (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref CE (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref fifo_wr) - ) - ) - (net mux_Out (joined - (portref O (instanceref serial_Data_i_1)) - (portref mux_Out) - ) - ) - (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined - (portref I0 (instanceref serial_Data_i_3)) - (portref I0 (instanceref serial_Data_i_4)) - (portref I3 (instanceref serial_Data_i_2)) - (portref I4 (instanceref serial_Data_i_5)) - (portref mux_sel_reg_0_) - ) - ) - (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined - (portref I0 (instanceref serial_Data_i_2)) - (portref I1 (instanceref serial_Data_i_3)) - (portref I1 (instanceref serial_Data_i_4)) - (portref I3 (instanceref serial_Data_i_5)) - (portref mux_sel_reg_2_) - ) - ) - (net p_4_in (joined - (portref I1 (instanceref serial_Data_i_2)) - (portref I2 (instanceref serial_Data_i_5)) - (portref I3 (instanceref serial_Data_i_3)) - (portref I3 (instanceref serial_Data_i_4)) - (portref p_4_in) - ) - ) - (net s_axi_aclk (joined - (portref CLK (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref CLK (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref s_axi_aclk) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__7__srl16)) - (portref (member s_axi_wdata 7)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__6__srl16)) - (portref (member s_axi_wdata 6)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__5__srl16)) - (portref (member s_axi_wdata 5)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__4__srl16)) - (portref (member s_axi_wdata 4)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__3__srl16)) - (portref (member s_axi_wdata 3)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__2__srl16)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__1__srl16)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref D (instanceref INFERRED_GEN_data_reg_15__0__srl16)) - (portref (member s_axi_wdata 0)) - ) - ) - (net serial_Data_i_2_n_0 (joined - (portref I0 (instanceref serial_Data_i_1)) - (portref O (instanceref serial_Data_i_2)) - ) - ) - (net serial_Data_i_3_n_0 (joined - (portref I1 (instanceref serial_Data_i_1)) - (portref O (instanceref serial_Data_i_3)) - ) - ) - (net serial_Data_i_4_n_0 (joined - (portref I2 (instanceref serial_Data_i_1)) - (portref O (instanceref serial_Data_i_4)) - ) - ) - (net serial_Data_i_5_n_0 (joined - (portref I3 (instanceref serial_Data_i_1)) - (portref O (instanceref serial_Data_i_5)) - ) - ) - ) - - (property ORIG_REF_NAME (string "dynshreg_f")) - ) - ) - (cell axi_uart_srl_fifo_rbu_f (celltype GENERIC) - (view srl_fifo_rbu_f (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) - (port fifo_Read (direction INPUT)) - (port fifo_wr (direction INPUT)) - (port mux_Out (direction OUTPUT)) - (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) - (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) - (port p_4_in (direction INPUT)) - (port reset_TX_FIFO_reg (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port tx_Buffer_Full (direction OUTPUT)) - (port tx_DataBits (direction INPUT)) - (port tx_Data_Enable_reg (direction INPUT)) - (port tx_Start (direction INPUT)) - (port tx_Start0 (direction OUTPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) - ) - (contents - (instance CNTR_INCR_DECR_ADDN_F_I (viewref cntr_incr_decr_addn_f (cellref axi_uart_cntr_incr_decr_addn_f (libraryref work_library0_1)))) - (instance DYNSHREG_F_I (viewref dynshreg_f (cellref axi_uart_dynshreg_f (libraryref work_library0_1)))) - (instance FIFO_Full_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (net (rename &_const1_ "") (joined - (portref CE (instanceref FIFO_Full_reg)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref Bus_RNW_reg) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_2 (joined - (portref (member Q 1) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 0) (instanceref DYNSHREG_F_I)) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_3 (joined - (portref (member Q 2) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 1) (instanceref DYNSHREG_F_I)) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_4 (joined - (portref (member Q 3) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 2) (instanceref DYNSHREG_F_I)) - ) - ) - (net CNTR_INCR_DECR_ADDN_F_I_n_5 (joined - (portref (member Q 4) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref (member Q 3) (instanceref DYNSHREG_F_I)) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref (member Q 0) (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref Q_0_) - ) - ) - (net TX_FIFO_Reset (joined - (portref R (instanceref FIFO_Full_reg)) - (portref SS_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) - ) - ) - (net fifo_Read (joined - (portref fifo_Read (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref fifo_Read) - ) - ) - (net fifo_full_p1 (joined - (portref D (instanceref FIFO_Full_reg)) - (portref fifo_full_p1 (instanceref CNTR_INCR_DECR_ADDN_F_I)) - ) - ) - (net fifo_wr (joined - (portref fifo_wr (instanceref DYNSHREG_F_I)) - (portref fifo_wr) - ) - ) - (net mux_Out (joined - (portref mux_Out (instanceref DYNSHREG_F_I)) - (portref mux_Out) - ) - ) - (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined - (portref mux_sel_reg_0_ (instanceref DYNSHREG_F_I)) - (portref mux_sel_reg_0_) - ) - ) - (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined - (portref mux_sel_reg_2_ (instanceref DYNSHREG_F_I)) - (portref mux_sel_reg_2_) - ) - ) - (net p_4_in (joined - (portref p_4_in (instanceref DYNSHREG_F_I)) - (portref p_4_in) - ) - ) - (net reset_TX_FIFO_reg (joined - (portref reset_TX_FIFO_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref reset_TX_FIFO_reg) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref FIFO_Full_reg)) - (portref s_axi_aclk (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref s_axi_aclk (instanceref DYNSHREG_F_I)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref s_axi_aresetn) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 7) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 7)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 6) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 6)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 5) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 5)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref (member s_axi_wdata 4) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 4)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref (member s_axi_wdata 3) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 3)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref (member s_axi_wdata 2) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref (member s_axi_wdata 1) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref (member s_axi_wdata 0) (instanceref DYNSHREG_F_I)) - (portref (member s_axi_wdata 0)) - ) - ) - (net tx_Buffer_Full (joined - (portref Q (instanceref FIFO_Full_reg)) - (portref tx_Buffer_Full (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref tx_Buffer_Full) - ) - ) - (net tx_DataBits (joined - (portref tx_DataBits (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref tx_DataBits) - ) - ) - (net tx_Data_Enable_reg (joined - (portref tx_Data_Enable_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref tx_Data_Enable_reg) - ) - ) - (net tx_Start (joined - (portref tx_Start (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref tx_Start) - ) - ) - (net tx_Start0 (joined - (portref tx_Start0 (instanceref CNTR_INCR_DECR_ADDN_F_I)) - (portref tx_Start0) - ) - ) - ) - - (property ORIG_REF_NAME (string "srl_fifo_rbu_f")) - ) - ) - (cell axi_uart_srl_fifo_f (celltype GENERIC) - (view srl_fifo_f (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) - (port fifo_Read (direction INPUT)) - (port fifo_wr (direction INPUT)) - (port mux_Out (direction OUTPUT)) - (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) - (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) - (port p_4_in (direction INPUT)) - (port reset_TX_FIFO_reg (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port tx_Buffer_Full (direction OUTPUT)) - (port tx_DataBits (direction INPUT)) - (port tx_Data_Enable_reg (direction INPUT)) - (port tx_Start (direction INPUT)) - (port tx_Start0 (direction OUTPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) - ) - (contents - (instance I_SRL_FIFO_RBU_F (viewref srl_fifo_rbu_f (cellref axi_uart_srl_fifo_rbu_f (libraryref work_library0_1)))) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref Bus_RNW_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref I_SRL_FIFO_RBU_F)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref Q_0_ (instanceref I_SRL_FIFO_RBU_F)) - (portref Q_0_) - ) - ) - (net fifo_Read (joined - (portref fifo_Read (instanceref I_SRL_FIFO_RBU_F)) - (portref fifo_Read) - ) - ) - (net fifo_wr (joined - (portref fifo_wr (instanceref I_SRL_FIFO_RBU_F)) - (portref fifo_wr) - ) - ) - (net mux_Out (joined - (portref mux_Out (instanceref I_SRL_FIFO_RBU_F)) - (portref mux_Out) - ) - ) - (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined - (portref mux_sel_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) - (portref mux_sel_reg_0_) - ) - ) - (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined - (portref mux_sel_reg_2_ (instanceref I_SRL_FIFO_RBU_F)) - (portref mux_sel_reg_2_) - ) - ) - (net p_4_in (joined - (portref p_4_in (instanceref I_SRL_FIFO_RBU_F)) - (portref p_4_in) - ) - ) - (net reset_TX_FIFO_reg (joined - (portref reset_TX_FIFO_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref reset_TX_FIFO_reg) - ) - ) - (net s_axi_aclk (joined - (portref s_axi_aclk (instanceref I_SRL_FIFO_RBU_F)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref I_SRL_FIFO_RBU_F)) - (portref s_axi_aresetn) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 7) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 7)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 6) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 6)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 5) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 5)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref (member s_axi_wdata 4) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 4)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref (member s_axi_wdata 3) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 3)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref (member s_axi_wdata 2) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref (member s_axi_wdata 1) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref (member s_axi_wdata 0) (instanceref I_SRL_FIFO_RBU_F)) - (portref (member s_axi_wdata 0)) - ) - ) - (net tx_Buffer_Full (joined - (portref tx_Buffer_Full (instanceref I_SRL_FIFO_RBU_F)) - (portref tx_Buffer_Full) - ) - ) - (net tx_DataBits (joined - (portref tx_DataBits (instanceref I_SRL_FIFO_RBU_F)) - (portref tx_DataBits) - ) - ) - (net tx_Data_Enable_reg (joined - (portref tx_Data_Enable_reg (instanceref I_SRL_FIFO_RBU_F)) - (portref tx_Data_Enable_reg) - ) - ) - (net tx_Start (joined - (portref tx_Start (instanceref I_SRL_FIFO_RBU_F)) - (portref tx_Start) - ) - ) - (net tx_Start0 (joined - (portref tx_Start0 (instanceref I_SRL_FIFO_RBU_F)) - (portref tx_Start0) - ) - ) - ) - - (property ORIG_REF_NAME (string "srl_fifo_f")) - ) - ) - (cell axi_uart_uartlite_tx (celltype GENERIC) - (view uartlite_tx (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) - (port en_16x_Baud (direction INPUT)) - (port fifo_wr (direction INPUT)) - (port reset_TX_FIFO_reg (direction INPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port tx (direction OUTPUT)) - (port tx_Buffer_Full (direction OUTPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (rename SR_0_ "SR[0]") (direction INPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) - ) - (contents - (instance MID_START_BIT_SRL16_I (viewref dynshreg_i_f__parameterized0 (cellref axi_uart_dynshreg_i_f__parameterized0 (libraryref work_library0_1)))) - (instance SRL_FIFO_I (viewref srl_fifo_f (cellref axi_uart_srl_fifo_f (libraryref work_library0_1)))) - (instance TX_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h31")) - ) - (instance TX_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance fifo_Read_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0100")) - ) - (instance fifo_Read_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename mux_sel_0__i_1 "mux_sel[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hE1F0F1F0")) - (property SOFT_HLUTNM (string "soft_lutpair19")) - ) - (instance (rename mux_sel_1__i_1 "mux_sel[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h99AAABAA")) - (property SOFT_HLUTNM (string "soft_lutpair19")) - ) - (instance (rename mux_sel_2__i_1 "mux_sel[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h7777888C")) - ) - (instance (rename mux_sel_reg_0_ "mux_sel_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename mux_sel_reg_1_ "mux_sel_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename mux_sel_reg_2_ "mux_sel_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance serial_Data_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance tx_DataBits_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0F08")) - ) - (instance tx_DataBits_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance tx_Data_Enable_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance tx_Start_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref TX_reg)) - (portref CE (instanceref fifo_Read_reg)) - (portref CE (instanceref mux_sel_reg_0_)) - (portref CE (instanceref mux_sel_reg_1_)) - (portref CE (instanceref mux_sel_reg_2_)) - (portref CE (instanceref serial_Data_reg)) - (portref CE (instanceref tx_DataBits_reg)) - (portref CE (instanceref tx_Data_Enable_reg)) - (portref CE (instanceref tx_Start_reg)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref SRL_FIFO_I)) - (portref Bus_RNW_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref SRL_FIFO_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref SRL_FIFO_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) - ) - ) - (net MID_START_BIT_SRL16_I_n_0 (joined - (portref D (instanceref tx_Data_Enable_reg)) - (portref tx_Data_Enable_reg (instanceref MID_START_BIT_SRL16_I)) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref Q_0_ (instanceref SRL_FIFO_I)) - (portref Q_0_) - ) - ) - (net (rename SR_0_ "SR[0]") (joined - (portref R (instanceref fifo_Read_reg)) - (portref R (instanceref serial_Data_reg)) - (portref R (instanceref tx_DataBits_reg)) - (portref R (instanceref tx_Data_Enable_reg)) - (portref R (instanceref tx_Start_reg)) - (portref S (instanceref TX_reg)) - (portref S (instanceref mux_sel_reg_0_)) - (portref S (instanceref mux_sel_reg_1_)) - (portref S (instanceref mux_sel_reg_2_)) - (portref SR_0_) - ) - ) - (net TX0 (joined - (portref D (instanceref TX_reg)) - (portref O (instanceref TX_i_1)) - ) - ) - (net en_16x_Baud (joined - (portref en_16x_Baud (instanceref MID_START_BIT_SRL16_I)) - (portref en_16x_Baud) - ) - ) - (net fifo_Read (joined - (portref I2 (instanceref tx_DataBits_i_1)) - (portref Q (instanceref fifo_Read_reg)) - (portref fifo_Read (instanceref SRL_FIFO_I)) - ) - ) - (net fifo_Read0 (joined - (portref D (instanceref fifo_Read_reg)) - (portref O (instanceref fifo_Read_i_1)) - ) - ) - (net fifo_wr (joined - (portref fifo_wr (instanceref SRL_FIFO_I)) - (portref fifo_wr) - ) - ) - (net mux_Out (joined - (portref D (instanceref serial_Data_reg)) - (portref mux_Out (instanceref SRL_FIFO_I)) - ) - ) - (net (rename mux_sel_0__i_1_n_0 "mux_sel[0]_i_1_n_0") (joined - (portref D (instanceref mux_sel_reg_0_)) - (portref O (instanceref mux_sel_0__i_1)) - ) - ) - (net (rename mux_sel_1__i_1_n_0 "mux_sel[1]_i_1_n_0") (joined - (portref D (instanceref mux_sel_reg_1_)) - (portref O (instanceref mux_sel_1__i_1)) - ) - ) - (net (rename mux_sel_2__i_1_n_0 "mux_sel[2]_i_1_n_0") (joined - (portref D (instanceref mux_sel_reg_2_)) - (portref O (instanceref mux_sel_2__i_1)) - ) - ) - (net (rename mux_sel_reg_n_0__0_ "mux_sel_reg_n_0_[0]") (joined - (portref I0 (instanceref fifo_Read_i_1)) - (portref I2 (instanceref mux_sel_0__i_1)) - (portref I2 (instanceref mux_sel_1__i_1)) - (portref I2 (instanceref mux_sel_2__i_1)) - (portref Q (instanceref mux_sel_reg_0_)) - (portref mux_sel_reg_0_ (instanceref SRL_FIFO_I)) - ) - ) - (net (rename mux_sel_reg_n_0__2_ "mux_sel_reg_n_0_[2]") (joined - (portref I1 (instanceref fifo_Read_i_1)) - (portref I1 (instanceref mux_sel_0__i_1)) - (portref I1 (instanceref mux_sel_1__i_1)) - (portref I4 (instanceref mux_sel_2__i_1)) - (portref Q (instanceref mux_sel_reg_2_)) - (portref mux_sel_reg_2_ (instanceref SRL_FIFO_I)) - ) - ) - (net p_4_in (joined - (portref I0 (instanceref mux_sel_0__i_1)) - (portref I0 (instanceref mux_sel_1__i_1)) - (portref I2 (instanceref fifo_Read_i_1)) - (portref I3 (instanceref mux_sel_2__i_1)) - (portref Q (instanceref mux_sel_reg_1_)) - (portref p_4_in (instanceref SRL_FIFO_I)) - ) - ) - (net reset_TX_FIFO_reg (joined - (portref reset_TX_FIFO_reg (instanceref SRL_FIFO_I)) - (portref reset_TX_FIFO_reg) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref TX_reg)) - (portref C (instanceref fifo_Read_reg)) - (portref C (instanceref mux_sel_reg_0_)) - (portref C (instanceref mux_sel_reg_1_)) - (portref C (instanceref mux_sel_reg_2_)) - (portref C (instanceref serial_Data_reg)) - (portref C (instanceref tx_DataBits_reg)) - (portref C (instanceref tx_Data_Enable_reg)) - (portref C (instanceref tx_Start_reg)) - (portref s_axi_aclk (instanceref MID_START_BIT_SRL16_I)) - (portref s_axi_aclk (instanceref SRL_FIFO_I)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref SRL_FIFO_I)) - (portref s_axi_aresetn) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 7) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 7)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 6) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 6)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 5) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 5)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref (member s_axi_wdata 4) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 4)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref (member s_axi_wdata 3) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 3)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref (member s_axi_wdata 2) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref (member s_axi_wdata 1) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref (member s_axi_wdata 0) (instanceref SRL_FIFO_I)) - (portref (member s_axi_wdata 0)) - ) - ) - (net serial_Data (joined - (portref I2 (instanceref TX_i_1)) - (portref Q (instanceref serial_Data_reg)) - ) - ) - (net tx (joined - (portref Q (instanceref TX_reg)) - (portref tx) - ) - ) - (net tx_Buffer_Full (joined - (portref tx_Buffer_Full (instanceref SRL_FIFO_I)) - (portref tx_Buffer_Full) - ) - ) - (net tx_DataBits (joined - (portref I0 (instanceref TX_i_1)) - (portref I0 (instanceref mux_sel_2__i_1)) - (portref I3 (instanceref tx_DataBits_i_1)) - (portref I4 (instanceref mux_sel_0__i_1)) - (portref I4 (instanceref mux_sel_1__i_1)) - (portref Q (instanceref tx_DataBits_reg)) - (portref tx_DataBits (instanceref SRL_FIFO_I)) - ) - ) - (net tx_DataBits0 (joined - (portref D (instanceref tx_DataBits_reg)) - (portref O (instanceref tx_DataBits_i_1)) - ) - ) - (net tx_Data_Enable_reg_n_0 (joined - (portref I1 (instanceref mux_sel_2__i_1)) - (portref I1 (instanceref tx_DataBits_i_1)) - (portref I3 (instanceref fifo_Read_i_1)) - (portref I3 (instanceref mux_sel_0__i_1)) - (portref I3 (instanceref mux_sel_1__i_1)) - (portref Q (instanceref tx_Data_Enable_reg)) - (portref tx_Data_Enable_reg (instanceref SRL_FIFO_I)) - (portref tx_Data_Enable_reg_0 (instanceref MID_START_BIT_SRL16_I)) - ) - ) - (net tx_Start (joined - (portref I0 (instanceref tx_DataBits_i_1)) - (portref I1 (instanceref TX_i_1)) - (portref Q (instanceref tx_Start_reg)) - (portref tx_Start (instanceref SRL_FIFO_I)) - ) - ) - (net tx_Start0 (joined - (portref D (instanceref tx_Start_reg)) - (portref tx_Start0 (instanceref SRL_FIFO_I)) - ) - ) - ) - - (property ORIG_REF_NAME (string "uartlite_tx")) - ) - ) - (cell axi_uart_uartlite_core (celltype GENERIC) - (view uartlite_core (viewtype NETLIST) - (interface - (port Bus_RNW_reg (direction INPUT)) - (port Bus_RNW_reg_reg (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) - (port (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (direction INPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_4__0 "INFERRED_GEN.cnt_i_reg[4]_0") (direction INPUT)) - (port bus2ip_reset (direction OUTPUT)) - (port enable_interrupts (direction OUTPUT)) - (port fifo_wr (direction INPUT)) - (port interrupt (direction OUTPUT)) - (port reset_RX_FIFO (direction INPUT)) - (port reset_TX_FIFO (direction INPUT)) - (port rx (direction INPUT)) - (port rx_Buffer_Full (direction OUTPUT)) - (port s_axi_aclk (direction INPUT)) - (port s_axi_aresetn (direction INPUT)) - (port tx (direction OUTPUT)) - (port tx_Buffer_Full (direction OUTPUT)) - (port (rename INFERRED_GEN_cnt_i_reg_2__0_ "INFERRED_GEN.cnt_i_reg[2][0]") (direction OUTPUT)) - (port (rename Q_0_ "Q[0]") (direction OUTPUT)) - (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction INPUT)) - (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) - (port (array (rename status_reg "status_reg[1:0]") 2) (direction OUTPUT)) - ) - (contents - (instance BAUD_RATE_I (viewref baudrate (cellref axi_uart_baudrate (libraryref work_library0_1)))) - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance Interrupt_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance UARTLITE_RX_I (viewref uartlite_rx (cellref axi_uart_uartlite_rx (libraryref work_library0_1)))) - (instance UARTLITE_TX_I (viewref uartlite_tx (cellref axi_uart_uartlite_tx (libraryref work_library0_1)))) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance clr_Status_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance enable_interrupts_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance reset_RX_FIFO_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance reset_TX_FIFO_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance rx_Data_Present_Pre_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename status_reg_reg_1_ "status_reg_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename status_reg_reg_2_ "status_reg_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance tx_Buffer_Empty_Pre_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (net (rename &_const0_ "") (joined - (portref G (instanceref GND)) - (portref R (instanceref rx_Data_Present_Pre_reg)) - (portref R (instanceref status_reg_reg_1_)) - (portref R (instanceref status_reg_reg_2_)) - (portref R (instanceref tx_Buffer_Empty_Pre_reg)) - ) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref Interrupt_reg)) - (portref CE (instanceref clr_Status_reg)) - (portref CE (instanceref enable_interrupts_reg)) - (portref CE (instanceref reset_RX_FIFO_reg)) - (portref CE (instanceref reset_TX_FIFO_reg)) - (portref CE (instanceref rx_Data_Present_Pre_reg)) - (portref CE (instanceref status_reg_reg_1_)) - (portref CE (instanceref status_reg_reg_2_)) - (portref CE (instanceref tx_Buffer_Empty_Pre_reg)) - (portref P (instanceref VCC)) - ) - ) - (net Bus_RNW_reg (joined - (portref Bus_RNW_reg (instanceref UARTLITE_RX_I)) - (portref Bus_RNW_reg (instanceref UARTLITE_TX_I)) - (portref Bus_RNW_reg) - ) - ) - (net Bus_RNW_reg_reg (joined - (portref Bus_RNW_reg_reg (instanceref UARTLITE_RX_I)) - (portref Bus_RNW_reg_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref UARTLITE_RX_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref UARTLITE_RX_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref UARTLITE_TX_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref UARTLITE_TX_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) - ) - ) - (net (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (joined - (portref D (instanceref enable_interrupts_reg)) - (portref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_2__0_ "INFERRED_GEN.cnt_i_reg[2][0]") (joined - (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref UARTLITE_RX_I)) - (portref Q_0_ (instanceref UARTLITE_TX_I)) - (portref INFERRED_GEN_cnt_i_reg_2__0_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (joined - (portref D (instanceref tx_Buffer_Empty_Pre_reg)) - (portref INFERRED_GEN_cnt_i_reg_4_) - ) - ) - (net (rename INFERRED_GEN_cnt_i_reg_4__0 "INFERRED_GEN.cnt_i_reg[4]_0") (joined - (portref D (instanceref rx_Data_Present_Pre_reg)) - (portref INFERRED_GEN_cnt_i_reg_4__0) - ) - ) - (net Interrupt0 (joined - (portref D (instanceref Interrupt_reg)) - (portref Interrupt0 (instanceref UARTLITE_RX_I)) - ) - ) - (net (rename Q_0_ "Q[0]") (joined - (portref Q_0_ (instanceref UARTLITE_RX_I)) - (portref Q_0_) - ) - ) - (net UARTLITE_RX_I_n_4 (joined - (portref D (instanceref status_reg_reg_2_)) - (portref status_reg_reg_2__0 (instanceref UARTLITE_RX_I)) - ) - ) - (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined - (portref D (instanceref clr_Status_reg)) - (portref bus2ip_rdce_0_) - ) - ) - (net bus2ip_reset (joined - (portref R (instanceref Interrupt_reg)) - (portref R (instanceref clr_Status_reg)) - (portref R (instanceref enable_interrupts_reg)) - (portref S (instanceref reset_RX_FIFO_reg)) - (portref S (instanceref reset_TX_FIFO_reg)) - (portref SR_0_ (instanceref BAUD_RATE_I)) - (portref SR_0_ (instanceref UARTLITE_RX_I)) - (portref SR_0_ (instanceref UARTLITE_TX_I)) - (portref bus2ip_reset) - ) - ) - (net clr_Status (joined - (portref Q (instanceref clr_Status_reg)) - (portref clr_Status (instanceref UARTLITE_RX_I)) - ) - ) - (net en_16x_Baud (joined - (portref en_16x_Baud (instanceref BAUD_RATE_I)) - (portref en_16x_Baud (instanceref UARTLITE_RX_I)) - (portref en_16x_Baud (instanceref UARTLITE_TX_I)) - ) - ) - (net enable_interrupts (joined - (portref Q (instanceref enable_interrupts_reg)) - (portref enable_interrupts (instanceref UARTLITE_RX_I)) - (portref enable_interrupts) - ) - ) - (net fifo_wr (joined - (portref fifo_wr (instanceref UARTLITE_TX_I)) - (portref fifo_wr) - ) - ) - (net interrupt (joined - (portref Q (instanceref Interrupt_reg)) - (portref interrupt) - ) - ) - (net (rename out_0_ "out[0]") (joined - (portref (member out 7) (instanceref UARTLITE_RX_I)) - (portref (member out 7)) - ) - ) - (net (rename out_1_ "out[1]") (joined - (portref (member out 6) (instanceref UARTLITE_RX_I)) - (portref (member out 6)) - ) - ) - (net (rename out_2_ "out[2]") (joined - (portref (member out 5) (instanceref UARTLITE_RX_I)) - (portref (member out 5)) - ) - ) - (net (rename out_3_ "out[3]") (joined - (portref (member out 4) (instanceref UARTLITE_RX_I)) - (portref (member out 4)) - ) - ) - (net (rename out_4_ "out[4]") (joined - (portref (member out 3) (instanceref UARTLITE_RX_I)) - (portref (member out 3)) - ) - ) - (net (rename out_5_ "out[5]") (joined - (portref (member out 2) (instanceref UARTLITE_RX_I)) - (portref (member out 2)) - ) - ) - (net (rename out_6_ "out[6]") (joined - (portref (member out 1) (instanceref UARTLITE_RX_I)) - (portref (member out 1)) - ) - ) - (net (rename out_7_ "out[7]") (joined - (portref (member out 0) (instanceref UARTLITE_RX_I)) - (portref (member out 0)) - ) - ) - (net reset_RX_FIFO (joined - (portref D (instanceref reset_RX_FIFO_reg)) - (portref reset_RX_FIFO) - ) - ) - (net reset_RX_FIFO_reg_n_0 (joined - (portref Q (instanceref reset_RX_FIFO_reg)) - (portref reset_RX_FIFO_reg (instanceref UARTLITE_RX_I)) - ) - ) - (net reset_TX_FIFO (joined - (portref D (instanceref reset_TX_FIFO_reg)) - (portref reset_TX_FIFO) - ) - ) - (net reset_TX_FIFO_reg_n_0 (joined - (portref Q (instanceref reset_TX_FIFO_reg)) - (portref reset_TX_FIFO_reg (instanceref UARTLITE_TX_I)) - ) - ) - (net rx (joined - (portref rx (instanceref UARTLITE_RX_I)) - (portref rx) - ) - ) - (net rx_Buffer_Full (joined - (portref status_reg_reg_2_ (instanceref UARTLITE_RX_I)) - (portref rx_Buffer_Full) - ) - ) - (net rx_Data_Present_Pre (joined - (portref Q (instanceref rx_Data_Present_Pre_reg)) - (portref rx_Data_Present_Pre (instanceref UARTLITE_RX_I)) - ) - ) - (net s_axi_aclk (joined - (portref C (instanceref Interrupt_reg)) - (portref C (instanceref clr_Status_reg)) - (portref C (instanceref enable_interrupts_reg)) - (portref C (instanceref reset_RX_FIFO_reg)) - (portref C (instanceref reset_TX_FIFO_reg)) - (portref C (instanceref rx_Data_Present_Pre_reg)) - (portref C (instanceref status_reg_reg_1_)) - (portref C (instanceref status_reg_reg_2_)) - (portref C (instanceref tx_Buffer_Empty_Pre_reg)) - (portref s_axi_aclk (instanceref BAUD_RATE_I)) - (portref s_axi_aclk (instanceref UARTLITE_RX_I)) - (portref s_axi_aclk (instanceref UARTLITE_TX_I)) - (portref s_axi_aclk) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref UARTLITE_RX_I)) - (portref s_axi_aresetn (instanceref UARTLITE_TX_I)) - (portref s_axi_aresetn) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 7) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 7)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 6) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 6)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 5) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 5)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref (member s_axi_wdata 4) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 4)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref (member s_axi_wdata 3) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 3)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref (member s_axi_wdata 2) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref (member s_axi_wdata 1) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref (member s_axi_wdata 0) (instanceref UARTLITE_TX_I)) - (portref (member s_axi_wdata 0)) - ) - ) - (net (rename status_reg_0_ "status_reg[0]") (joined - (portref Q (instanceref status_reg_reg_2_)) - (portref (member status_reg 1) (instanceref UARTLITE_RX_I)) - (portref (member status_reg 1)) - ) - ) - (net (rename status_reg_1_ "status_reg[1]") (joined - (portref Q (instanceref status_reg_reg_1_)) - (portref (member status_reg 0) (instanceref UARTLITE_RX_I)) - (portref (member status_reg 0)) - ) - ) - (net status_reg_reg0 (joined - (portref D (instanceref status_reg_reg_1_)) - (portref status_reg_reg0 (instanceref UARTLITE_RX_I)) - ) - ) - (net tx (joined - (portref tx (instanceref UARTLITE_TX_I)) - (portref tx) - ) - ) - (net tx_Buffer_Empty_Pre (joined - (portref Q (instanceref tx_Buffer_Empty_Pre_reg)) - (portref tx_Buffer_Empty_Pre (instanceref UARTLITE_RX_I)) - ) - ) - (net tx_Buffer_Full (joined - (portref tx_Buffer_Full (instanceref UARTLITE_TX_I)) - (portref tx_Buffer_Full) - ) - ) - ) - - (property ORIG_REF_NAME (string "uartlite_core")) - ) - ) - (cell axi_uart_axi_uartlite (celltype GENERIC) - (view axi_uartlite (viewtype NETLIST) - (interface - (port interrupt (direction OUTPUT)) - (port rx (direction INPUT)) - (port s_axi_aclk (direction INPUT) - (property max_fanout (string "10000")) - ) - (port s_axi_aresetn (direction INPUT) - (property max_fanout (string "10000")) - ) - (port s_axi_arready (direction OUTPUT)) - (port s_axi_arvalid (direction INPUT)) - (port s_axi_awready (direction OUTPUT)) - (port s_axi_awvalid (direction INPUT)) - (port s_axi_bready (direction INPUT)) - (port s_axi_bvalid (direction OUTPUT)) - (port s_axi_rready (direction INPUT)) - (port s_axi_rvalid (direction OUTPUT)) - (port s_axi_wready (direction OUTPUT)) - (port s_axi_wvalid (direction INPUT)) - (port tx (direction OUTPUT)) - (port (array (rename s_axi_araddr "s_axi_araddr[3:0]") 4) (direction INPUT)) - (port (array (rename s_axi_awaddr "s_axi_awaddr[3:0]") 4) (direction INPUT)) - (port (array (rename s_axi_bresp "s_axi_bresp[1:0]") 2) (direction OUTPUT)) - (port (array (rename s_axi_rdata "s_axi_rdata[31:0]") 32) (direction OUTPUT)) - (port (array (rename s_axi_rresp "s_axi_rresp[1:0]") 2) (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[31:0]") 32) (direction INPUT)) - (port (array (rename s_axi_wstrb "s_axi_wstrb[3:0]") 4) (direction INPUT)) - ) - (contents - (instance AXI_LITE_IPIF_I (viewref axi_lite_ipif (cellref axi_uart_axi_lite_ipif (libraryref work_library0_1)))) - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance UARTLITE_CORE_I (viewref uartlite_core (cellref axi_uart_uartlite_core (libraryref work_library0_1)))) - (net (rename &_const0_ "") (joined - (portref G (instanceref GND)) - (portref (member s_axi_bresp 1)) - (portref (member s_axi_rdata 21)) - (portref (member s_axi_rdata 20)) - (portref (member s_axi_rdata 19)) - (portref (member s_axi_rdata 18)) - (portref (member s_axi_rdata 17)) - (portref (member s_axi_rdata 16)) - (portref (member s_axi_rdata 15)) - (portref (member s_axi_rdata 14)) - (portref (member s_axi_rdata 13)) - (portref (member s_axi_rdata 12)) - (portref (member s_axi_rdata 11)) - (portref (member s_axi_rdata 10)) - (portref (member s_axi_rdata 9)) - (portref (member s_axi_rdata 8)) - (portref (member s_axi_rdata 7)) - (portref (member s_axi_rdata 6)) - (portref (member s_axi_rdata 5)) - (portref (member s_axi_rdata 4)) - (portref (member s_axi_rdata 3)) - (portref (member s_axi_rdata 2)) - (portref (member s_axi_rdata 1)) - (portref (member s_axi_rdata 0)) - (portref (member s_axi_rdata 23)) - (portref (member s_axi_rdata 22)) - (portref (member s_axi_rresp 1)) - ) - ) - (net AXI_LITE_IPIF_I_n_11 (joined - (portref Bus_RNW_reg_reg (instanceref UARTLITE_CORE_I)) - (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref AXI_LITE_IPIF_I)) - ) - ) - (net AXI_LITE_IPIF_I_n_12 (joined - (portref INFERRED_GEN_cnt_i_reg_4__0 (instanceref UARTLITE_CORE_I)) - (portref rx_Data_Present_Pre_reg (instanceref AXI_LITE_IPIF_I)) - ) - ) - (net AXI_LITE_IPIF_I_n_13 (joined - (portref FIFO_Full_reg (instanceref AXI_LITE_IPIF_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref UARTLITE_CORE_I)) - ) - ) - (net AXI_LITE_IPIF_I_n_16 (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref UARTLITE_CORE_I)) - (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref AXI_LITE_IPIF_I)) - ) - ) - (net AXI_LITE_IPIF_I_n_17 (joined - (portref INFERRED_GEN_cnt_i_reg_4_ (instanceref UARTLITE_CORE_I)) - (portref tx_Buffer_Empty_Pre_reg (instanceref AXI_LITE_IPIF_I)) - ) - ) - (net AXI_LITE_IPIF_I_n_18 (joined - (portref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ (instanceref UARTLITE_CORE_I)) - (portref enable_interrupts_reg (instanceref AXI_LITE_IPIF_I)) - ) - ) - (net (rename I_SLAVE_ATTACHMENT_I_DECODER_Bus_RNW_reg "I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg") (joined - (portref Bus_RNW_reg (instanceref AXI_LITE_IPIF_I)) - (portref Bus_RNW_reg (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename I_SLAVE_ATTACHMENT_I_DECODER_GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref AXI_LITE_IPIF_I)) - (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename I_SLAVE_ATTACHMENT_I_DECODER_GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref AXI_LITE_IPIF_I)) - (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename UARTLITE_RX_I_rx_Data_Empty "UARTLITE_RX_I/rx_Data_Empty") (joined - (portref Q_0_ (instanceref AXI_LITE_IPIF_I)) - (portref Q_0_ (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename UARTLITE_TX_I_fifo_wr "UARTLITE_TX_I/fifo_wr") (joined - (portref fifo_wr (instanceref AXI_LITE_IPIF_I)) - (portref fifo_wr (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename bus2ip_rdce_1_ "bus2ip_rdce[1]") (joined - (portref bus2ip_rdce_0_ (instanceref AXI_LITE_IPIF_I)) - (portref bus2ip_rdce_0_ (instanceref UARTLITE_CORE_I)) - ) - ) - (net bus2ip_reset (joined - (portref bus2ip_reset (instanceref AXI_LITE_IPIF_I)) - (portref bus2ip_reset (instanceref UARTLITE_CORE_I)) - ) - ) - (net enable_interrupts (joined - (portref enable_interrupts (instanceref AXI_LITE_IPIF_I)) - (portref enable_interrupts (instanceref UARTLITE_CORE_I)) - ) - ) - (net interrupt (joined - (portref interrupt (instanceref UARTLITE_CORE_I)) - (portref interrupt) - ) - ) - (net reset_RX_FIFO (joined - (portref reset_RX_FIFO (instanceref AXI_LITE_IPIF_I)) - (portref reset_RX_FIFO (instanceref UARTLITE_CORE_I)) - ) - ) - (net reset_TX_FIFO (joined - (portref reset_TX_FIFO (instanceref AXI_LITE_IPIF_I)) - (portref reset_TX_FIFO (instanceref UARTLITE_CORE_I)) - ) - ) - (net rx (joined - (portref rx (instanceref UARTLITE_CORE_I)) - (portref rx) - ) - ) - (net rx_Buffer_Full (joined - (portref rx_Buffer_Full (instanceref AXI_LITE_IPIF_I)) - (portref rx_Buffer_Full (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_0_ "rx_Data[0]") (joined - (portref (member out 0) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 0) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_1_ "rx_Data[1]") (joined - (portref (member out 1) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 1) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_2_ "rx_Data[2]") (joined - (portref (member out 2) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 2) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_3_ "rx_Data[3]") (joined - (portref (member out 3) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 3) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_4_ "rx_Data[4]") (joined - (portref (member out 4) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 4) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_5_ "rx_Data[5]") (joined - (portref (member out 5) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 5) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_6_ "rx_Data[6]") (joined - (portref (member out 6) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 6) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename rx_Data_7_ "rx_Data[7]") (joined - (portref (member out 7) (instanceref AXI_LITE_IPIF_I)) - (portref (member out 7) (instanceref UARTLITE_CORE_I)) - ) - ) - (net s_axi_aclk (joined - (portref s_axi_aclk (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_aclk (instanceref UARTLITE_CORE_I)) - (portref s_axi_aclk) - ) - - (property RTL_MAX_FANOUT (string "found")) - (property MAX_FANOUT (string "10000")) - ) - (net (rename s_axi_araddr_2_ "s_axi_araddr[2]") (joined - (portref (member s_axi_araddr 1) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_araddr 1)) - ) - ) - (net (rename s_axi_araddr_3_ "s_axi_araddr[3]") (joined - (portref (member s_axi_araddr 0) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_araddr 0)) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_aresetn (instanceref UARTLITE_CORE_I)) - (portref s_axi_aresetn) - ) - - (property RTL_MAX_FANOUT (string "found")) - (property MAX_FANOUT (string "10000")) - ) - (net s_axi_arready (joined - (portref s_axi_arready (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_arready) - ) - ) - (net s_axi_arvalid (joined - (portref s_axi_arvalid (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_arvalid) - ) - ) - (net (rename s_axi_awaddr_2_ "s_axi_awaddr[2]") (joined - (portref (member s_axi_awaddr 1) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_awaddr 1)) - ) - ) - (net (rename s_axi_awaddr_3_ "s_axi_awaddr[3]") (joined - (portref (member s_axi_awaddr 0) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_awaddr 0)) - ) - ) - (net s_axi_awready (joined - (portref s_axi_awready (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_awready) - (portref s_axi_wready) - ) - ) - (net s_axi_awvalid (joined - (portref s_axi_awvalid (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_awvalid) - ) - ) - (net s_axi_bready (joined - (portref s_axi_bready (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_bready) - ) - ) - (net (rename s_axi_bresp_1_ "s_axi_bresp[1]") (joined - (portref s_axi_bresp_0_ (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_bresp 0)) - ) - ) - (net s_axi_bvalid (joined - (portref s_axi_bvalid (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_bvalid) - ) - ) - (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined - (portref (member s_axi_rdata 7) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 31)) - ) - ) - (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined - (portref (member s_axi_rdata 6) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 30)) - ) - ) - (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined - (portref (member s_axi_rdata 5) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 29)) - ) - ) - (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined - (portref (member s_axi_rdata 4) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 28)) - ) - ) - (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined - (portref (member s_axi_rdata 3) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 27)) - ) - ) - (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined - (portref (member s_axi_rdata 2) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 26)) - ) - ) - (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined - (portref (member s_axi_rdata 1) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 25)) - ) - ) - (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined - (portref (member s_axi_rdata 0) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rdata 24)) - ) - ) - (net s_axi_rready (joined - (portref s_axi_rready (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_rready) - ) - ) - (net (rename s_axi_rresp_1_ "s_axi_rresp[1]") (joined - (portref s_axi_rresp_0_ (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_rresp 0)) - ) - ) - (net s_axi_rvalid (joined - (portref s_axi_rvalid (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_rvalid) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 2) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_wdata 7) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 31)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 1) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_wdata 6) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 30)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 5) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 29)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref (member s_axi_wdata 4) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 28)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref (member s_axi_wdata 0) (instanceref AXI_LITE_IPIF_I)) - (portref (member s_axi_wdata 3) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 27)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref (member s_axi_wdata 2) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 26)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref (member s_axi_wdata 1) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 25)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref (member s_axi_wdata 0) (instanceref UARTLITE_CORE_I)) - (portref (member s_axi_wdata 24)) - ) - ) - (net s_axi_wvalid (joined - (portref s_axi_wvalid (instanceref AXI_LITE_IPIF_I)) - (portref s_axi_wvalid) - ) - ) - (net (rename status_reg_1_ "status_reg[1]") (joined - (portref (member status_reg 0) (instanceref AXI_LITE_IPIF_I)) - (portref (member status_reg 0) (instanceref UARTLITE_CORE_I)) - ) - ) - (net (rename status_reg_2_ "status_reg[2]") (joined - (portref (member status_reg 1) (instanceref AXI_LITE_IPIF_I)) - (portref (member status_reg 1) (instanceref UARTLITE_CORE_I)) - ) - ) - (net tx (joined - (portref tx (instanceref UARTLITE_CORE_I)) - (portref tx) - ) - ) - (net tx_Buffer_Empty (joined - (portref INFERRED_GEN_cnt_i_reg_2__0_ (instanceref UARTLITE_CORE_I)) - (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref AXI_LITE_IPIF_I)) - ) - ) - (net tx_Buffer_Full (joined - (portref tx_Buffer_Full (instanceref AXI_LITE_IPIF_I)) - (portref tx_Buffer_Full (instanceref UARTLITE_CORE_I)) - ) - ) - ) - - (property C_FAMILY (string "artix7")) - (property C_S_AXI_ACLK_FREQ_HZ (integer 10000000)) - (property C_S_AXI_ADDR_WIDTH (integer 4)) - (property C_S_AXI_DATA_WIDTH (integer 32)) - (property C_BAUDRATE (integer 128000)) - (property C_DATA_BITS (integer 8)) - (property C_USE_PARITY (integer 0)) - (property C_ODD_PARITY (integer 0)) - (property downgradeipidentifiedwarnings (string "yes")) - (property ORIG_REF_NAME (string "axi_uartlite")) - ) - ) - (cell axi_uart (celltype GENERIC) - (view axi_uart (viewtype NETLIST) - (interface - (port interrupt (direction OUTPUT) - (property x_interface_parameter (string "XIL_INTERFACENAME INTERRUPT, SENSITIVITY EDGE_RISING, PortWidth 1")) - (property x_interface_info (string "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT")) - ) - (port rx (direction INPUT) - (property x_interface_parameter (string "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UARTLITE_BOARD_INTERFACE")) - (property x_interface_info (string "xilinx.com:interface:uart:1.0 UART RxD")) - ) - (port s_axi_aclk (direction INPUT) - (property x_interface_parameter (string "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000")) - (property x_interface_info (string "xilinx.com:signal:clock:1.0 ACLK CLK")) - ) - (port s_axi_aresetn (direction INPUT) - (property x_interface_parameter (string "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW")) - (property x_interface_info (string "xilinx.com:signal:reset:1.0 ARESETN RST")) - ) - (port s_axi_arready (direction OUTPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI ARREADY")) - ) - (port s_axi_arvalid (direction INPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI ARVALID")) - ) - (port s_axi_awready (direction OUTPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI AWREADY")) - ) - (port s_axi_awvalid (direction INPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI AWVALID")) - ) - (port s_axi_bready (direction INPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI BREADY")) - ) - (port s_axi_bvalid (direction OUTPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI BVALID")) - ) - (port s_axi_rready (direction INPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI RREADY")) - ) - (port s_axi_rvalid (direction OUTPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI RVALID")) - ) - (port s_axi_wready (direction OUTPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI WREADY")) - ) - (port s_axi_wvalid (direction INPUT) - (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI WVALID")) - ) - (port tx (direction OUTPUT) - (property x_interface_info (string "xilinx.com:interface:uart:1.0 UART TxD")) - ) - (port (array (rename s_axi_araddr "s_axi_araddr[3:0]") 4) (direction INPUT)) - (port (array (rename s_axi_awaddr "s_axi_awaddr[3:0]") 4) (direction INPUT)) - (port (array (rename s_axi_bresp "s_axi_bresp[1:0]") 2) (direction OUTPUT)) - (port (array (rename s_axi_rdata "s_axi_rdata[31:0]") 32) (direction OUTPUT)) - (port (array (rename s_axi_rresp "s_axi_rresp[1:0]") 2) (direction OUTPUT)) - (port (array (rename s_axi_wdata "s_axi_wdata[31:0]") 32) (direction INPUT)) - (port (array (rename s_axi_wstrb "s_axi_wstrb[3:0]") 4) (direction INPUT)) - ) - (contents - (instance U0 (viewref axi_uartlite (cellref axi_uart_axi_uartlite (libraryref work_library0_1))) - (property C_BAUDRATE (integer 128000)) - (property C_DATA_BITS (integer 8)) - (property C_FAMILY (string "artix7")) - (property C_ODD_PARITY (integer 0)) - (property C_S_AXI_ACLK_FREQ_HZ (integer 10000000)) - (property C_S_AXI_ADDR_WIDTH (integer 4)) - (property C_S_AXI_DATA_WIDTH (integer 32)) - (property C_USE_PARITY (integer 0)) - (property downgradeipidentifiedwarnings (string "yes")) - ) - (net interrupt (joined - (portref interrupt (instanceref U0)) - (portref interrupt) - ) - ) - (net rx (joined - (portref rx (instanceref U0)) - (portref rx) - ) - ) - (net s_axi_aclk (joined - (portref s_axi_aclk (instanceref U0)) - (portref s_axi_aclk) - ) - ) - (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined - (portref (member s_axi_araddr 3) (instanceref U0)) - (portref (member s_axi_araddr 3)) - ) - ) - (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined - (portref (member s_axi_araddr 2) (instanceref U0)) - (portref (member s_axi_araddr 2)) - ) - ) - (net (rename s_axi_araddr_2_ "s_axi_araddr[2]") (joined - (portref (member s_axi_araddr 1) (instanceref U0)) - (portref (member s_axi_araddr 1)) - ) - ) - (net (rename s_axi_araddr_3_ "s_axi_araddr[3]") (joined - (portref (member s_axi_araddr 0) (instanceref U0)) - (portref (member s_axi_araddr 0)) - ) - ) - (net s_axi_aresetn (joined - (portref s_axi_aresetn (instanceref U0)) - (portref s_axi_aresetn) - ) - ) - (net s_axi_arready (joined - (portref s_axi_arready (instanceref U0)) - (portref s_axi_arready) - ) - ) - (net s_axi_arvalid (joined - (portref s_axi_arvalid (instanceref U0)) - (portref s_axi_arvalid) - ) - ) - (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined - (portref (member s_axi_awaddr 3) (instanceref U0)) - (portref (member s_axi_awaddr 3)) - ) - ) - (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined - (portref (member s_axi_awaddr 2) (instanceref U0)) - (portref (member s_axi_awaddr 2)) - ) - ) - (net (rename s_axi_awaddr_2_ "s_axi_awaddr[2]") (joined - (portref (member s_axi_awaddr 1) (instanceref U0)) - (portref (member s_axi_awaddr 1)) - ) - ) - (net (rename s_axi_awaddr_3_ "s_axi_awaddr[3]") (joined - (portref (member s_axi_awaddr 0) (instanceref U0)) - (portref (member s_axi_awaddr 0)) - ) - ) - (net s_axi_awready (joined - (portref s_axi_awready (instanceref U0)) - (portref s_axi_awready) - ) - ) - (net s_axi_awvalid (joined - (portref s_axi_awvalid (instanceref U0)) - (portref s_axi_awvalid) - ) - ) - (net s_axi_bready (joined - (portref s_axi_bready (instanceref U0)) - (portref s_axi_bready) - ) - ) - (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined - (portref (member s_axi_bresp 1) (instanceref U0)) - (portref (member s_axi_bresp 1)) - ) - ) - (net (rename s_axi_bresp_1_ "s_axi_bresp[1]") (joined - (portref (member s_axi_bresp 0) (instanceref U0)) - (portref (member s_axi_bresp 0)) - ) - ) - (net s_axi_bvalid (joined - (portref s_axi_bvalid (instanceref U0)) - (portref s_axi_bvalid) - ) - ) - (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined - (portref (member s_axi_rdata 31) (instanceref U0)) - (portref (member s_axi_rdata 31)) - ) - ) - (net (rename s_axi_rdata_10_ "s_axi_rdata[10]") (joined - (portref (member s_axi_rdata 21) (instanceref U0)) - (portref (member s_axi_rdata 21)) - ) - ) - (net (rename s_axi_rdata_11_ "s_axi_rdata[11]") (joined - (portref (member s_axi_rdata 20) (instanceref U0)) - (portref (member s_axi_rdata 20)) - ) - ) - (net (rename s_axi_rdata_12_ "s_axi_rdata[12]") (joined - (portref (member s_axi_rdata 19) (instanceref U0)) - (portref (member s_axi_rdata 19)) - ) - ) - (net (rename s_axi_rdata_13_ "s_axi_rdata[13]") (joined - (portref (member s_axi_rdata 18) (instanceref U0)) - (portref (member s_axi_rdata 18)) - ) - ) - (net (rename s_axi_rdata_14_ "s_axi_rdata[14]") (joined - (portref (member s_axi_rdata 17) (instanceref U0)) - (portref (member s_axi_rdata 17)) - ) - ) - (net (rename s_axi_rdata_15_ "s_axi_rdata[15]") (joined - (portref (member s_axi_rdata 16) (instanceref U0)) - (portref (member s_axi_rdata 16)) - ) - ) - (net (rename s_axi_rdata_16_ "s_axi_rdata[16]") (joined - (portref (member s_axi_rdata 15) (instanceref U0)) - (portref (member s_axi_rdata 15)) - ) - ) - (net (rename s_axi_rdata_17_ "s_axi_rdata[17]") (joined - (portref (member s_axi_rdata 14) (instanceref U0)) - (portref (member s_axi_rdata 14)) - ) - ) - (net (rename s_axi_rdata_18_ "s_axi_rdata[18]") (joined - (portref (member s_axi_rdata 13) (instanceref U0)) - (portref (member s_axi_rdata 13)) - ) - ) - (net (rename s_axi_rdata_19_ "s_axi_rdata[19]") (joined - (portref (member s_axi_rdata 12) (instanceref U0)) - (portref (member s_axi_rdata 12)) - ) - ) - (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined - (portref (member s_axi_rdata 30) (instanceref U0)) - (portref (member s_axi_rdata 30)) - ) - ) - (net (rename s_axi_rdata_20_ "s_axi_rdata[20]") (joined - (portref (member s_axi_rdata 11) (instanceref U0)) - (portref (member s_axi_rdata 11)) - ) - ) - (net (rename s_axi_rdata_21_ "s_axi_rdata[21]") (joined - (portref (member s_axi_rdata 10) (instanceref U0)) - (portref (member s_axi_rdata 10)) - ) - ) - (net (rename s_axi_rdata_22_ "s_axi_rdata[22]") (joined - (portref (member s_axi_rdata 9) (instanceref U0)) - (portref (member s_axi_rdata 9)) - ) - ) - (net (rename s_axi_rdata_23_ "s_axi_rdata[23]") (joined - (portref (member s_axi_rdata 8) (instanceref U0)) - (portref (member s_axi_rdata 8)) - ) - ) - (net (rename s_axi_rdata_24_ "s_axi_rdata[24]") (joined - (portref (member s_axi_rdata 7) (instanceref U0)) - (portref (member s_axi_rdata 7)) - ) - ) - (net (rename s_axi_rdata_25_ "s_axi_rdata[25]") (joined - (portref (member s_axi_rdata 6) (instanceref U0)) - (portref (member s_axi_rdata 6)) - ) - ) - (net (rename s_axi_rdata_26_ "s_axi_rdata[26]") (joined - (portref (member s_axi_rdata 5) (instanceref U0)) - (portref (member s_axi_rdata 5)) - ) - ) - (net (rename s_axi_rdata_27_ "s_axi_rdata[27]") (joined - (portref (member s_axi_rdata 4) (instanceref U0)) - (portref (member s_axi_rdata 4)) - ) - ) - (net (rename s_axi_rdata_28_ "s_axi_rdata[28]") (joined - (portref (member s_axi_rdata 3) (instanceref U0)) - (portref (member s_axi_rdata 3)) - ) - ) - (net (rename s_axi_rdata_29_ "s_axi_rdata[29]") (joined - (portref (member s_axi_rdata 2) (instanceref U0)) - (portref (member s_axi_rdata 2)) - ) - ) - (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined - (portref (member s_axi_rdata 29) (instanceref U0)) - (portref (member s_axi_rdata 29)) - ) - ) - (net (rename s_axi_rdata_30_ "s_axi_rdata[30]") (joined - (portref (member s_axi_rdata 1) (instanceref U0)) - (portref (member s_axi_rdata 1)) - ) - ) - (net (rename s_axi_rdata_31_ "s_axi_rdata[31]") (joined - (portref (member s_axi_rdata 0) (instanceref U0)) - (portref (member s_axi_rdata 0)) - ) - ) - (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined - (portref (member s_axi_rdata 28) (instanceref U0)) - (portref (member s_axi_rdata 28)) - ) - ) - (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined - (portref (member s_axi_rdata 27) (instanceref U0)) - (portref (member s_axi_rdata 27)) - ) - ) - (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined - (portref (member s_axi_rdata 26) (instanceref U0)) - (portref (member s_axi_rdata 26)) - ) - ) - (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined - (portref (member s_axi_rdata 25) (instanceref U0)) - (portref (member s_axi_rdata 25)) - ) - ) - (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined - (portref (member s_axi_rdata 24) (instanceref U0)) - (portref (member s_axi_rdata 24)) - ) - ) - (net (rename s_axi_rdata_8_ "s_axi_rdata[8]") (joined - (portref (member s_axi_rdata 23) (instanceref U0)) - (portref (member s_axi_rdata 23)) - ) - ) - (net (rename s_axi_rdata_9_ "s_axi_rdata[9]") (joined - (portref (member s_axi_rdata 22) (instanceref U0)) - (portref (member s_axi_rdata 22)) - ) - ) - (net s_axi_rready (joined - (portref s_axi_rready (instanceref U0)) - (portref s_axi_rready) - ) - ) - (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined - (portref (member s_axi_rresp 1) (instanceref U0)) - (portref (member s_axi_rresp 1)) - ) - ) - (net (rename s_axi_rresp_1_ "s_axi_rresp[1]") (joined - (portref (member s_axi_rresp 0) (instanceref U0)) - (portref (member s_axi_rresp 0)) - ) - ) - (net s_axi_rvalid (joined - (portref s_axi_rvalid (instanceref U0)) - (portref s_axi_rvalid) - ) - ) - (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined - (portref (member s_axi_wdata 31) (instanceref U0)) - (portref (member s_axi_wdata 31)) - ) - ) - (net (rename s_axi_wdata_10_ "s_axi_wdata[10]") (joined - (portref (member s_axi_wdata 21) (instanceref U0)) - (portref (member s_axi_wdata 21)) - ) - ) - (net (rename s_axi_wdata_11_ "s_axi_wdata[11]") (joined - (portref (member s_axi_wdata 20) (instanceref U0)) - (portref (member s_axi_wdata 20)) - ) - ) - (net (rename s_axi_wdata_12_ "s_axi_wdata[12]") (joined - (portref (member s_axi_wdata 19) (instanceref U0)) - (portref (member s_axi_wdata 19)) - ) - ) - (net (rename s_axi_wdata_13_ "s_axi_wdata[13]") (joined - (portref (member s_axi_wdata 18) (instanceref U0)) - (portref (member s_axi_wdata 18)) - ) - ) - (net (rename s_axi_wdata_14_ "s_axi_wdata[14]") (joined - (portref (member s_axi_wdata 17) (instanceref U0)) - (portref (member s_axi_wdata 17)) - ) - ) - (net (rename s_axi_wdata_15_ "s_axi_wdata[15]") (joined - (portref (member s_axi_wdata 16) (instanceref U0)) - (portref (member s_axi_wdata 16)) - ) - ) - (net (rename s_axi_wdata_16_ "s_axi_wdata[16]") (joined - (portref (member s_axi_wdata 15) (instanceref U0)) - (portref (member s_axi_wdata 15)) - ) - ) - (net (rename s_axi_wdata_17_ "s_axi_wdata[17]") (joined - (portref (member s_axi_wdata 14) (instanceref U0)) - (portref (member s_axi_wdata 14)) - ) - ) - (net (rename s_axi_wdata_18_ "s_axi_wdata[18]") (joined - (portref (member s_axi_wdata 13) (instanceref U0)) - (portref (member s_axi_wdata 13)) - ) - ) - (net (rename s_axi_wdata_19_ "s_axi_wdata[19]") (joined - (portref (member s_axi_wdata 12) (instanceref U0)) - (portref (member s_axi_wdata 12)) - ) - ) - (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined - (portref (member s_axi_wdata 30) (instanceref U0)) - (portref (member s_axi_wdata 30)) - ) - ) - (net (rename s_axi_wdata_20_ "s_axi_wdata[20]") (joined - (portref (member s_axi_wdata 11) (instanceref U0)) - (portref (member s_axi_wdata 11)) - ) - ) - (net (rename s_axi_wdata_21_ "s_axi_wdata[21]") (joined - (portref (member s_axi_wdata 10) (instanceref U0)) - (portref (member s_axi_wdata 10)) - ) - ) - (net (rename s_axi_wdata_22_ "s_axi_wdata[22]") (joined - (portref (member s_axi_wdata 9) (instanceref U0)) - (portref (member s_axi_wdata 9)) - ) - ) - (net (rename s_axi_wdata_23_ "s_axi_wdata[23]") (joined - (portref (member s_axi_wdata 8) (instanceref U0)) - (portref (member s_axi_wdata 8)) - ) - ) - (net (rename s_axi_wdata_24_ "s_axi_wdata[24]") (joined - (portref (member s_axi_wdata 7) (instanceref U0)) - (portref (member s_axi_wdata 7)) - ) - ) - (net (rename s_axi_wdata_25_ "s_axi_wdata[25]") (joined - (portref (member s_axi_wdata 6) (instanceref U0)) - (portref (member s_axi_wdata 6)) - ) - ) - (net (rename s_axi_wdata_26_ "s_axi_wdata[26]") (joined - (portref (member s_axi_wdata 5) (instanceref U0)) - (portref (member s_axi_wdata 5)) - ) - ) - (net (rename s_axi_wdata_27_ "s_axi_wdata[27]") (joined - (portref (member s_axi_wdata 4) (instanceref U0)) - (portref (member s_axi_wdata 4)) - ) - ) - (net (rename s_axi_wdata_28_ "s_axi_wdata[28]") (joined - (portref (member s_axi_wdata 3) (instanceref U0)) - (portref (member s_axi_wdata 3)) - ) - ) - (net (rename s_axi_wdata_29_ "s_axi_wdata[29]") (joined - (portref (member s_axi_wdata 2) (instanceref U0)) - (portref (member s_axi_wdata 2)) - ) - ) - (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined - (portref (member s_axi_wdata 29) (instanceref U0)) - (portref (member s_axi_wdata 29)) - ) - ) - (net (rename s_axi_wdata_30_ "s_axi_wdata[30]") (joined - (portref (member s_axi_wdata 1) (instanceref U0)) - (portref (member s_axi_wdata 1)) - ) - ) - (net (rename s_axi_wdata_31_ "s_axi_wdata[31]") (joined - (portref (member s_axi_wdata 0) (instanceref U0)) - (portref (member s_axi_wdata 0)) - ) - ) - (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined - (portref (member s_axi_wdata 28) (instanceref U0)) - (portref (member s_axi_wdata 28)) - ) - ) - (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined - (portref (member s_axi_wdata 27) (instanceref U0)) - (portref (member s_axi_wdata 27)) - ) - ) - (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined - (portref (member s_axi_wdata 26) (instanceref U0)) - (portref (member s_axi_wdata 26)) - ) - ) - (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined - (portref (member s_axi_wdata 25) (instanceref U0)) - (portref (member s_axi_wdata 25)) - ) - ) - (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined - (portref (member s_axi_wdata 24) (instanceref U0)) - (portref (member s_axi_wdata 24)) - ) - ) - (net (rename s_axi_wdata_8_ "s_axi_wdata[8]") (joined - (portref (member s_axi_wdata 23) (instanceref U0)) - (portref (member s_axi_wdata 23)) - ) - ) - (net (rename s_axi_wdata_9_ "s_axi_wdata[9]") (joined - (portref (member s_axi_wdata 22) (instanceref U0)) - (portref (member s_axi_wdata 22)) - ) - ) - (net s_axi_wready (joined - (portref s_axi_wready (instanceref U0)) - (portref s_axi_wready) - ) - ) - (net (rename s_axi_wstrb_0_ "s_axi_wstrb[0]") (joined - (portref (member s_axi_wstrb 3) (instanceref U0)) - (portref (member s_axi_wstrb 3)) - ) - ) - (net (rename s_axi_wstrb_1_ "s_axi_wstrb[1]") (joined - (portref (member s_axi_wstrb 2) (instanceref U0)) - (portref (member s_axi_wstrb 2)) - ) - ) - (net (rename s_axi_wstrb_2_ "s_axi_wstrb[2]") (joined - (portref (member s_axi_wstrb 1) (instanceref U0)) - (portref (member s_axi_wstrb 1)) - ) - ) - (net (rename s_axi_wstrb_3_ "s_axi_wstrb[3]") (joined - (portref (member s_axi_wstrb 0) (instanceref U0)) - (portref (member s_axi_wstrb 0)) - ) - ) - (net s_axi_wvalid (joined - (portref s_axi_wvalid (instanceref U0)) - (portref s_axi_wvalid) - ) - ) - (net tx (joined - (portref tx (instanceref U0)) - (portref tx) - ) - ) - ) - - (property downgradeipidentifiedwarnings (string "yes")) - (property x_core_info (string "axi_uartlite,Vivado 2017.4")) - (property CHECK_LICENSE_TYPE (string "axi_uart,axi_uartlite,{}")) - (property core_generation_info (string "axi_uart,axi_uartlite,{x_ipProduct=Vivado 2017.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=10000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=128000,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}")) - ) - ) - ) - (Library work - (edifLevel 0) - (technology (numberDefinition )) - (cell uart_bmpg (celltype GENERIC) - (view uart_bmpg (viewtype NETLIST) - (interface - (port upg_clk_i (direction INPUT)) - (port upg_clk_o (direction OUTPUT)) - (port upg_done_o (direction OUTPUT)) - (port upg_rst_i (direction INPUT)) - (port upg_rx_i (direction INPUT)) - (port upg_tx_o (direction OUTPUT)) - (port upg_wen_o (direction OUTPUT)) - (port (array (rename upg_adr_o "upg_adr_o[14:0]") 15) (direction OUTPUT)) - (port (array (rename upg_dat_o "upg_dat_o[31:0]") 32) (direction OUTPUT)) - ) - (contents - (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) - (instance (rename RCS_0__i_1 "RCS[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFF0050CF")) - (property SOFT_HLUTNM (string "soft_lutpair3")) - ) - (instance (rename RCS_1__i_1 "RCS[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFF00FF0055FCFF00")) - ) - (instance (rename RCS_2__i_1 "RCS[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFF5C000")) - ) - (instance (rename RCS_reg_0_ "RCS_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename RCS_reg_1_ "RCS_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename RCS_reg_2_ "RCS_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) - (instance (rename WCS_0__i_1 "WCS[0]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFF0000FF0F080F")) - ) - (instance (rename WCS_0__i_2 "WCS[0]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h8")) - (property SOFT_HLUTNM (string "soft_lutpair18")) - ) - (instance (rename WCS_1__i_1 "WCS[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFF7700F0F0F0")) - ) - (instance (rename WCS_2__i_1 "WCS[2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFF00FF88FF000F00")) - ) - (instance (rename WCS_2__i_2 "WCS[2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000000000001")) - ) - (instance (rename WCS_2__i_3 "WCS[2]_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hEFFF")) - ) - (instance (rename WCS_2__i_4 "WCS[2]_i_4") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFF7FFF")) - (property SOFT_HLUTNM (string "soft_lutpair11")) - ) - (instance (rename WCS_2__i_5 "WCS[2]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hEFFF")) - ) - (instance (rename WCS_reg_0_ "WCS_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename WCS_reg_1_ "WCS_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename WCS_reg_2_ "WCS_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance axi_uart_inst (viewref axi_uart (cellref axi_uart (libraryref work_library0_1))) - (property x_core_info (string "axi_uartlite,Vivado 2017.4")) - ) - (instance axi_uart_inst_i_1 (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) - (property INIT (string "2'h1")) - ) - (instance (rename bn_ascii_0__i_1 "bn_ascii[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair21")) - ) - (instance (rename bn_ascii_10__i_1 "bn_ascii[10]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair23")) - ) - (instance (rename bn_ascii_11__i_1 "bn_ascii[11]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair22")) - ) - (instance (rename bn_ascii_13__i_1 "bn_ascii[13]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair24")) - ) - (instance (rename bn_ascii_14__i_1 "bn_ascii[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - ) - (instance (rename bn_ascii_16__i_1 "bn_ascii[16]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair25")) - ) - (instance (rename bn_ascii_17__i_1 "bn_ascii[17]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair25")) - ) - (instance (rename bn_ascii_18__i_1 "bn_ascii[18]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair26")) - ) - (instance (rename bn_ascii_19__i_1 "bn_ascii[19]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair26")) - ) - (instance (rename bn_ascii_1__i_1 "bn_ascii[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair20")) - ) - (instance (rename bn_ascii_21__i_1 "bn_ascii[21]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair41")) - ) - (instance (rename bn_ascii_22__i_1 "bn_ascii[22]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair41")) - ) - (instance (rename bn_ascii_24__i_1 "bn_ascii[24]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair27")) - ) - (instance (rename bn_ascii_25__i_1 "bn_ascii[25]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair17")) - ) - (instance (rename bn_ascii_26__i_1 "bn_ascii[26]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair17")) - ) - (instance (rename bn_ascii_27__i_1 "bn_ascii[27]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair27")) - ) - (instance (rename bn_ascii_29__i_1 "bn_ascii[29]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair36")) - ) - (instance (rename bn_ascii_2__i_1 "bn_ascii[2]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair20")) - ) - (instance (rename bn_ascii_30__i_1 "bn_ascii[30]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair36")) - ) - (instance (rename bn_ascii_32__i_1 "bn_ascii[32]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair29")) - ) - (instance (rename bn_ascii_33__i_1 "bn_ascii[33]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair29")) - ) - (instance (rename bn_ascii_34__i_1 "bn_ascii[34]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair30")) - ) - (instance (rename bn_ascii_35__i_1 "bn_ascii[35]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair30")) - ) - (instance (rename bn_ascii_37__i_1 "bn_ascii[37]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair39")) - ) - (instance (rename bn_ascii_38__i_1 "bn_ascii[38]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair39")) - ) - (instance (rename bn_ascii_3__i_1 "bn_ascii[3]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair21")) - ) - (instance (rename bn_ascii_40__i_1 "bn_ascii[40]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair31")) - ) - (instance (rename bn_ascii_41__i_1 "bn_ascii[41]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair28")) - ) - (instance (rename bn_ascii_42__i_1 "bn_ascii[42]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair28")) - ) - (instance (rename bn_ascii_43__i_1 "bn_ascii[43]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair31")) - ) - (instance (rename bn_ascii_45__i_1 "bn_ascii[45]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair35")) - ) - (instance (rename bn_ascii_46__i_1 "bn_ascii[46]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair35")) - ) - (instance (rename bn_ascii_48__i_1 "bn_ascii[48]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair32")) - ) - (instance (rename bn_ascii_49__i_1 "bn_ascii[49]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair32")) - ) - (instance (rename bn_ascii_50__i_1 "bn_ascii[50]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair33")) - ) - (instance (rename bn_ascii_51__i_1 "bn_ascii[51]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair33")) - ) - (instance (rename bn_ascii_53__i_1 "bn_ascii[53]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair40")) - ) - (instance (rename bn_ascii_54__i_1 "bn_ascii[54]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair40")) - ) - (instance (rename bn_ascii_56__i_1 "bn_ascii[56]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair16")) - ) - (instance (rename bn_ascii_57__i_1 "bn_ascii[57]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair16")) - ) - (instance (rename bn_ascii_58__i_1 "bn_ascii[58]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hCC8C")) - (property SOFT_HLUTNM (string "soft_lutpair34")) - ) - (instance (rename bn_ascii_59__i_1 "bn_ascii[59]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h02")) - (property SOFT_HLUTNM (string "soft_lutpair34")) - ) - (instance (rename bn_ascii_5__i_1 "bn_ascii[5]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair37")) - ) - (instance (rename bn_ascii_61__i_1 "bn_ascii[61]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h1F")) - (property SOFT_HLUTNM (string "soft_lutpair38")) - ) - (instance (rename bn_ascii_62__i_1 "bn_ascii[62]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h4000")) - ) - (instance (rename bn_ascii_62__i_2 "bn_ascii[62]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair38")) - ) - (instance (rename bn_ascii_6__i_1 "bn_ascii[6]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hA8")) - (property SOFT_HLUTNM (string "soft_lutpair37")) - ) - (instance (rename bn_ascii_8__i_1 "bn_ascii[8]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h56AA")) - (property SOFT_HLUTNM (string "soft_lutpair24")) - ) - (instance (rename bn_ascii_9__i_1 "bn_ascii[9]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hBB40")) - (property SOFT_HLUTNM (string "soft_lutpair23")) - ) - (instance (rename bn_ascii_reg_0_ "bn_ascii_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_10_ "bn_ascii_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_11_ "bn_ascii_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_13_ "bn_ascii_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_14_ "bn_ascii_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_16_ "bn_ascii_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_17_ "bn_ascii_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_18_ "bn_ascii_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_19_ "bn_ascii_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_1_ "bn_ascii_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_21_ "bn_ascii_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_22_ "bn_ascii_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_24_ "bn_ascii_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_25_ "bn_ascii_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_26_ "bn_ascii_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_27_ "bn_ascii_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_29_ "bn_ascii_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_2_ "bn_ascii_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_30_ "bn_ascii_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_32_ "bn_ascii_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_33_ "bn_ascii_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_34_ "bn_ascii_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_35_ "bn_ascii_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_37_ "bn_ascii_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_38_ "bn_ascii_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_3_ "bn_ascii_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_40_ "bn_ascii_reg[40]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_41_ "bn_ascii_reg[41]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_42_ "bn_ascii_reg[42]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_43_ "bn_ascii_reg[43]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_45_ "bn_ascii_reg[45]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_46_ "bn_ascii_reg[46]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_48_ "bn_ascii_reg[48]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_49_ "bn_ascii_reg[49]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_50_ "bn_ascii_reg[50]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_51_ "bn_ascii_reg[51]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_53_ "bn_ascii_reg[53]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_54_ "bn_ascii_reg[54]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_56_ "bn_ascii_reg[56]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_57_ "bn_ascii_reg[57]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_58_ "bn_ascii_reg[58]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_59_ "bn_ascii_reg[59]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_5_ "bn_ascii_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_61_ "bn_ascii_reg[61]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_62_ "bn_ascii_reg[62]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_6_ "bn_ascii_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_8_ "bn_ascii_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename bn_ascii_reg_9_ "bn_ascii_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_0__i_1 "byte_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) - (property INIT (string "2'h1")) - ) - (instance (rename byte_cnt_31__i_1 "byte_cnt[31]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0040")) - ) - (instance (rename byte_cnt_reg_0_ "byte_cnt_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_10_ "byte_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_11_ "byte_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_12_ "byte_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_12__i_1 "byte_cnt_reg[12]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_13_ "byte_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_14_ "byte_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_15_ "byte_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_16_ "byte_cnt_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_16__i_1 "byte_cnt_reg[16]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_17_ "byte_cnt_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_18_ "byte_cnt_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_19_ "byte_cnt_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_1_ "byte_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_20_ "byte_cnt_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_20__i_1 "byte_cnt_reg[20]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_21_ "byte_cnt_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_22_ "byte_cnt_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_23_ "byte_cnt_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_24_ "byte_cnt_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_24__i_1 "byte_cnt_reg[24]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_25_ "byte_cnt_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_26_ "byte_cnt_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_27_ "byte_cnt_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_28_ "byte_cnt_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_28__i_1 "byte_cnt_reg[28]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_29_ "byte_cnt_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_2_ "byte_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_30_ "byte_cnt_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_31_ "byte_cnt_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_31__i_2 "byte_cnt_reg[31]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_3_ "byte_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_4_ "byte_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_4__i_1 "byte_cnt_reg[4]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_5_ "byte_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_6_ "byte_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_7_ "byte_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_8_ "byte_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_cnt_reg_8__i_1 "byte_cnt_reg[8]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename byte_cnt_reg_9_ "byte_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_7__i_1 "byte_len[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h8")) - ) - (instance (rename byte_len_reg_0_ "byte_len_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_1_ "byte_len_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_2_ "byte_len_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_3_ "byte_len_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_4_ "byte_len_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_5_ "byte_len_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_6_ "byte_len_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_len_reg_7_ "byte_len_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_31__i_1 "byte_num[31]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h08")) - ) - (instance (rename byte_num_reg_0_ "byte_num_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_10_ "byte_num_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_11_ "byte_num_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_12_ "byte_num_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_13_ "byte_num_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_14_ "byte_num_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_15_ "byte_num_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_16_ "byte_num_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_17_ "byte_num_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_18_ "byte_num_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_19_ "byte_num_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_1_ "byte_num_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_20_ "byte_num_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_21_ "byte_num_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_22_ "byte_num_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_23_ "byte_num_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_24_ "byte_num_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_25_ "byte_num_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_26_ "byte_num_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_27_ "byte_num_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_28_ "byte_num_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_29_ "byte_num_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_2_ "byte_num_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_30_ "byte_num_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_31_ "byte_num_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_3_ "byte_num_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_4_ "byte_num_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_5_ "byte_num_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_6_ "byte_num_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_7_ "byte_num_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_8_ "byte_num_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename byte_num_reg_9_ "byte_num_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_0_ "dbuf_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_10_ "dbuf_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_11_ "dbuf_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_12_ "dbuf_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_13_ "dbuf_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_14_ "dbuf_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_15_ "dbuf_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_16_ "dbuf_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_17_ "dbuf_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_18_ "dbuf_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_19_ "dbuf_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_1_ "dbuf_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_20_ "dbuf_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_21_ "dbuf_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_22_ "dbuf_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_23_ "dbuf_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_2_ "dbuf_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_3_ "dbuf_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_4_ "dbuf_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_5_ "dbuf_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_6_ "dbuf_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_7_ "dbuf_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_8_ "dbuf_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename dbuf_reg_9_ "dbuf_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_0__i_1 "disp[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h5595")) - ) - (instance (rename disp_1__i_1 "disp[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h55556555")) - (property SOFT_HLUTNM (string "soft_lutpair5")) - ) - (instance (rename disp_1__i_2 "disp[1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFEFF0000EFFFFFFF")) - ) - (instance (rename disp_1__i_3 "disp[1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000FF00FFFFEFFF")) - ) - (instance (rename disp_2__i_1 "disp[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h82882222")) - ) - (instance (rename disp_2__i_2 "disp[2]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFFEFFF")) - (property SOFT_HLUTNM (string "soft_lutpair5")) - ) - (instance (rename disp_3__i_1 "disp[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFF0000007F807F80")) - ) - (instance (rename disp_3__i_2 "disp[3]_i_2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h00A2")) - (property SOFT_HLUTNM (string "soft_lutpair6")) - ) - (instance (rename disp_4__i_1 "disp[4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFF0000007F807F80")) - ) - (instance (rename disp_5__i_1 "disp[5]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h00000000BFFF4000")) - ) - (instance (rename disp_5__i_2 "disp[5]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'hB")) - (property SOFT_HLUTNM (string "soft_lutpair10")) - ) - (instance (rename disp_5__i_3 "disp[5]_i_3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h20220000")) - (property SOFT_HLUTNM (string "soft_lutpair6")) - ) - (instance (rename disp_5__i_4 "disp[5]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair1")) - ) - (instance (rename disp_6__i_1 "disp[6]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hB000B00000F0B000")) - ) - (instance (rename disp_6__i_2 "disp[6]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFDFFFF")) - (property SOFT_HLUTNM (string "soft_lutpair10")) - ) - (instance (rename disp_6__i_3 "disp[6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hF7F7F7F7F7F7D7F7")) - ) - (instance (rename disp_7__i_1 "disp[7]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hD02FD0D0D0D0D0D0")) - ) - (instance (rename disp_7__i_2 "disp[7]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFDFFFFFFFFFFFFFF")) - ) - (instance (rename disp_7__i_3 "disp[7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFAAEFFFFFFFFFFF")) - ) - (instance (rename disp_7__i_4 "disp[7]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'hE")) - (property SOFT_HLUTNM (string "soft_lutpair0")) - ) - (instance (rename disp_reg_0_ "disp_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_1_ "disp_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_2_ "disp_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_3_ "disp_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_4_ "disp_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_5_ "disp_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_6_ "disp_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename disp_reg_7_ "disp_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance initFlag_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hAAAE")) - (property SOFT_HLUTNM (string "soft_lutpair18")) - ) - (instance initFlag_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename len_cnt_0__i_1 "len_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) - (property INIT (string "2'h1")) - (property SOFT_HLUTNM (string "soft_lutpair52")) - ) - (instance (rename len_cnt_1__i_1 "len_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h6")) - (property SOFT_HLUTNM (string "soft_lutpair52")) - ) - (instance (rename len_cnt_2__i_1 "len_cnt[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h6A")) - (property SOFT_HLUTNM (string "soft_lutpair13")) - ) - (instance (rename len_cnt_3__i_1 "len_cnt[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h6AAA")) - (property SOFT_HLUTNM (string "soft_lutpair13")) - ) - (instance (rename len_cnt_reg_0_ "len_cnt_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename len_cnt_reg_1_ "len_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename len_cnt_reg_2_ "len_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename len_cnt_reg_3_ "len_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_0__i_1 "msg_indx[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) - (property INIT (string "2'h1")) - ) - (instance (rename msg_indx_1__i_1 "msg_indx[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h6")) - (property SOFT_HLUTNM (string "soft_lutpair12")) - ) - (instance (rename msg_indx_2__i_1 "msg_indx[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h6A")) - (property SOFT_HLUTNM (string "soft_lutpair7")) - ) - (instance (rename msg_indx_3__i_1 "msg_indx[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h6AAA")) - (property SOFT_HLUTNM (string "soft_lutpair2")) - ) - (instance (rename msg_indx_4__i_1 "msg_indx[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h6AAAAAAA")) - (property SOFT_HLUTNM (string "soft_lutpair2")) - ) - (instance (rename msg_indx_5__i_1 "msg_indx[5]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h6AAAAAAAAAAAAAAA")) - ) - (instance (rename msg_indx_6__i_1 "msg_indx[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h6")) - ) - (instance (rename msg_indx_7__i_1 "msg_indx[7]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0008")) - ) - (instance (rename msg_indx_7__i_2 "msg_indx[7]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h6A")) - (property SOFT_HLUTNM (string "soft_lutpair15")) - ) - (instance (rename msg_indx_7__i_3 "msg_indx[7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h8000000000000000")) - ) - (instance (rename msg_indx_reg_0_ "msg_indx_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_1_ "msg_indx_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_2_ "msg_indx_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_3_ "msg_indx_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_4_ "msg_indx_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_5_ "msg_indx_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_6_ "msg_indx_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename msg_indx_reg_7_ "msg_indx_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance oldInitF_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFF0200")) - ) - (instance oldInitF_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rdStat_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives)))) - (instance rdStat_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hF708F708FF00FF0A")) - ) - (instance rdStat_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance recv_done_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFF2000")) - ) - (instance recv_done_i_10 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_11 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_13 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_14 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_15 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_16 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_17 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_18 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_19 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_20 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_22 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_23 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_24 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_25 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_26 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_27 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_28 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_29 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_30 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_31 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_32 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_33 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h222B")) - ) - (instance recv_done_i_34 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_35 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_36 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_37 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h6006")) - ) - (instance recv_done_i_4 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_5 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_6 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_7 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h22B2")) - ) - (instance recv_done_i_8 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_i_9 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h9009")) - ) - (instance recv_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance recv_done_reg_i_12 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance recv_done_reg_i_2 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance recv_done_reg_i_21 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance recv_done_reg_i_3 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename rwait_cnt_0__i_1 "rwait_cnt[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h1")) - ) - (instance (rename rwait_cnt_10__i_1 "rwait_cnt[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair47")) - ) - (instance (rename rwait_cnt_11__i_1 "rwait_cnt[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair54")) - ) - (instance (rename rwait_cnt_12__i_1 "rwait_cnt[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair42")) - ) - (instance (rename rwait_cnt_13__i_1 "rwait_cnt[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair56")) - ) - (instance (rename rwait_cnt_14__i_1 "rwait_cnt[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair56")) - ) - (instance (rename rwait_cnt_15__i_1 "rwait_cnt[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h10")) - ) - (instance (rename rwait_cnt_15__i_2 "rwait_cnt[15]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - ) - (instance (rename rwait_cnt_15__i_4 "rwait_cnt[15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000000004000")) - ) - (instance (rename rwait_cnt_15__i_5 "rwait_cnt[15]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFFFD")) - ) - (instance (rename rwait_cnt_15__i_6 "rwait_cnt[15]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFFFBFF")) - ) - (instance (rename rwait_cnt_15__i_7 "rwait_cnt[15]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFFEF")) - ) - (instance (rename rwait_cnt_1__i_1 "rwait_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair42")) - ) - (instance (rename rwait_cnt_2__i_1 "rwait_cnt[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair43")) - ) - (instance (rename rwait_cnt_3__i_1 "rwait_cnt[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair43")) - ) - (instance (rename rwait_cnt_4__i_1 "rwait_cnt[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair44")) - ) - (instance (rename rwait_cnt_5__i_1 "rwait_cnt[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair46")) - ) - (instance (rename rwait_cnt_6__i_1 "rwait_cnt[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair46")) - ) - (instance (rename rwait_cnt_7__i_1 "rwait_cnt[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair47")) - ) - (instance (rename rwait_cnt_8__i_1 "rwait_cnt[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair44")) - ) - (instance (rename rwait_cnt_9__i_1 "rwait_cnt[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair54")) - ) - (instance (rename rwait_cnt_reg_0_ "rwait_cnt_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename rwait_cnt_reg_10_ "rwait_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_11_ "rwait_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_12_ "rwait_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_12__i_2 "rwait_cnt_reg[12]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename rwait_cnt_reg_13_ "rwait_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_14_ "rwait_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_15_ "rwait_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_15__i_3 "rwait_cnt_reg[15]_i_3") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename rwait_cnt_reg_1_ "rwait_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_2_ "rwait_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_3_ "rwait_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_4_ "rwait_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_4__i_2 "rwait_cnt_reg[4]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename rwait_cnt_reg_5_ "rwait_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_6_ "rwait_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_7_ "rwait_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_8_ "rwait_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename rwait_cnt_reg_8__i_2 "rwait_cnt_reg[8]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename rwait_cnt_reg_9_ "rwait_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance rx_done_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h38")) - ) - (instance rx_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_araddr_3__i_1 "s_axi_araddr[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFFFE00000002")) - ) - (instance (rename s_axi_araddr_reg_3_ "s_axi_araddr_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance s_axi_arvalid_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFF7373000C4040")) - ) - (instance s_axi_arvalid_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h1")) - ) - (instance s_axi_arvalid_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h1")) - (property SOFT_HLUTNM (string "soft_lutpair9")) - ) - (instance s_axi_arvalid_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_awaddr_3__i_1 "s_axi_awaddr[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFFFD00000001")) - ) - (instance (rename s_axi_awaddr_reg_3_ "s_axi_awaddr_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance s_axi_awvalid_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFF558A00")) - ) - (instance s_axi_awvalid_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000F0008000F")) - ) - (instance s_axi_awvalid_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_0__i_1 "s_axi_wdata[0]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h20AA2020AAAAAAAA")) - ) - (instance (rename s_axi_wdata_0__i_2 "s_axi_wdata[0]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000004B560AB000")) - ) - (instance (rename s_axi_wdata_0__i_3 "s_axi_wdata[0]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hABEFABEFABEF0000")) - ) - (instance (rename s_axi_wdata_0__i_4 "s_axi_wdata[0]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h000037F7FFFF37F7")) - ) - (instance (rename s_axi_wdata_0__i_5 "s_axi_wdata[0]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hAFA0CFCFAFA0C0C0")) - ) - (instance (rename s_axi_wdata_1__i_1 "s_axi_wdata[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h20AA2020AAAAAAAA")) - ) - (instance (rename s_axi_wdata_1__i_2 "s_axi_wdata[1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h000F008800441500")) - ) - (instance (rename s_axi_wdata_1__i_3 "s_axi_wdata[1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hABEFABEFABEF0000")) - ) - (instance (rename s_axi_wdata_1__i_4 "s_axi_wdata[1]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0001")) - (property SOFT_HLUTNM (string "soft_lutpair15")) - ) - (instance (rename s_axi_wdata_1__i_5 "s_axi_wdata[1]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFF000057F757F7")) - ) - (instance (rename s_axi_wdata_1__i_6 "s_axi_wdata[1]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h05F5030305F5F3F3")) - ) - (instance (rename s_axi_wdata_2__i_1 "s_axi_wdata[2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h4F4F4FFF44444444")) - ) - (instance (rename s_axi_wdata_2__i_2 "s_axi_wdata[2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h00000047C6526000")) - ) - (instance (rename s_axi_wdata_2__i_3 "s_axi_wdata[2]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFF4FFF7FFFFFFFF")) - ) - (instance (rename s_axi_wdata_2__i_4 "s_axi_wdata[2]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h000037F7FFFF37F7")) - ) - (instance (rename s_axi_wdata_2__i_5 "s_axi_wdata[2]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hAFA0CFCFAFA0C0C0")) - ) - (instance (rename s_axi_wdata_3__i_1 "s_axi_wdata[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h4F4F4FFF44444444")) - ) - (instance (rename s_axi_wdata_3__i_2 "s_axi_wdata[3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000046431202")) - ) - (instance (rename s_axi_wdata_3__i_3 "s_axi_wdata[3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFF35FFFFFFFF")) - ) - (instance (rename s_axi_wdata_3__i_4 "s_axi_wdata[3]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h000037F7FFFF37F7")) - ) - (instance (rename s_axi_wdata_3__i_5 "s_axi_wdata[3]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hAFA0CFCFAFA0C0C0")) - ) - (instance (rename s_axi_wdata_4__i_1 "s_axi_wdata[4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0100010101010101")) - ) - (instance (rename s_axi_wdata_4__i_2 "s_axi_wdata[4]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hAA20AAAA")) - ) - (instance (rename s_axi_wdata_4__i_3 "s_axi_wdata[4]_i_3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h54")) - (property SOFT_HLUTNM (string "soft_lutpair4")) - ) - (instance (rename s_axi_wdata_4__i_4 "s_axi_wdata[4]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h02A8")) - (property SOFT_HLUTNM (string "soft_lutpair14")) - ) - (instance (rename s_axi_wdata_4__i_5 "s_axi_wdata[4]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000009D584FF")) - ) - (instance (rename s_axi_wdata_4__i_6 "s_axi_wdata[4]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h88888888AAA888A8")) - ) - (instance (rename s_axi_wdata_4__i_7 "s_axi_wdata[4]_i_7") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h45")) - (property SOFT_HLUTNM (string "soft_lutpair8")) - ) - (instance (rename s_axi_wdata_4__i_8 "s_axi_wdata[4]_i_8") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'hFD")) - (property SOFT_HLUTNM (string "soft_lutpair14")) - ) - (instance (rename s_axi_wdata_5__i_1 "s_axi_wdata[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFF4F4444")) - ) - (instance (rename s_axi_wdata_5__i_2 "s_axi_wdata[5]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000FFF7FFFFF")) - ) - (instance (rename s_axi_wdata_5__i_3 "s_axi_wdata[5]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFF35FFFFFFFF")) - ) - (instance (rename s_axi_wdata_5__i_4 "s_axi_wdata[5]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0455")) - (property SOFT_HLUTNM (string "soft_lutpair19")) - ) - (instance (rename s_axi_wdata_5__i_5 "s_axi_wdata[5]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h05F5030305F5F3F3")) - ) - (instance (rename s_axi_wdata_5__i_6 "s_axi_wdata[5]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFF47FF")) - (property SOFT_HLUTNM (string "soft_lutpair12")) - ) - (instance (rename s_axi_wdata_6__i_1 "s_axi_wdata[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h00010101")) - ) - (instance (rename s_axi_wdata_6__i_2 "s_axi_wdata[6]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h3A3A3A0A")) - ) - (instance (rename s_axi_wdata_6__i_3 "s_axi_wdata[6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h00DF00F8009E0704")) - ) - (instance (rename s_axi_wdata_6__i_4 "s_axi_wdata[6]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000005300000000")) - ) - (instance (rename s_axi_wdata_6__i_5 "s_axi_wdata[6]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h00000000AAAAFEAE")) - ) - (instance (rename s_axi_wdata_6__i_6 "s_axi_wdata[6]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h8A80FFFF")) - (property SOFT_HLUTNM (string "soft_lutpair8")) - ) - (instance (rename s_axi_wdata_6__i_7 "s_axi_wdata[6]_i_7") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h00103010")) - (property SOFT_HLUTNM (string "soft_lutpair7")) - ) - (instance (rename s_axi_wdata_reg_0_ "s_axi_wdata_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_reg_1_ "s_axi_wdata_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_reg_2_ "s_axi_wdata_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_reg_3_ "s_axi_wdata_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_reg_4_ "s_axi_wdata_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_reg_5_ "s_axi_wdata_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wdata_reg_6_ "s_axi_wdata_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename s_axi_wstrb_3__i_1 "s_axi_wstrb[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h2220AAAA")) - (property SOFT_HLUTNM (string "soft_lutpair4")) - ) - (instance (rename s_axi_wstrb_reg_3_ "s_axi_wstrb_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename statReg_0__i_1 "statReg[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFBF0080")) - (property SOFT_HLUTNM (string "soft_lutpair9")) - ) - (instance (rename statReg_0__i_2 "statReg[0]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h80")) - (property SOFT_HLUTNM (string "soft_lutpair3")) - ) - (instance (rename statReg_reg_0_ "statReg_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_7__i_1 "uart_rdat[7]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000000000080")) - ) - (instance (rename uart_rdat_reg_0_ "uart_rdat_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_1_ "uart_rdat_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_2_ "uart_rdat_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_3_ "uart_rdat_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_4_ "uart_rdat_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_5_ "uart_rdat_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_6_ "uart_rdat_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename uart_rdat_reg_7_ "uart_rdat_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance uart_wen_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFFEF00000020")) - ) - (instance uart_wen_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_14__i_1 "upg_adr_o[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h01")) - ) - (instance (rename upg_adr_o_OBUF_0__inst "upg_adr_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_10__inst "upg_adr_o_OBUF[10]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_11__inst "upg_adr_o_OBUF[11]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_12__inst "upg_adr_o_OBUF[12]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_13__inst "upg_adr_o_OBUF[13]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_14__inst "upg_adr_o_OBUF[14]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_1__inst "upg_adr_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_2__inst "upg_adr_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_3__inst "upg_adr_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_4__inst "upg_adr_o_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_5__inst "upg_adr_o_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_6__inst "upg_adr_o_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_7__inst "upg_adr_o_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_8__inst "upg_adr_o_OBUF[8]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_OBUF_9__inst "upg_adr_o_OBUF[9]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_adr_o_reg_0_ "upg_adr_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_10_ "upg_adr_o_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_11_ "upg_adr_o_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_12_ "upg_adr_o_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_13_ "upg_adr_o_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_14_ "upg_adr_o_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_1_ "upg_adr_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_2_ "upg_adr_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_3_ "upg_adr_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_4_ "upg_adr_o_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_5_ "upg_adr_o_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_6_ "upg_adr_o_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_7_ "upg_adr_o_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_8_ "upg_adr_o_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_adr_o_reg_9_ "upg_adr_o_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance upg_clk_i_IBUF_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives)))) - (instance upg_clk_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) - (instance upg_clk_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance upg_clk_o_OBUF_inst_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFFFFFB")) - (property SOFT_HLUTNM (string "soft_lutpair0")) - ) - (instance upg_clk_o_OBUF_inst_i_2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0001")) - ) - (instance (rename upg_dat_o_OBUF_0__inst "upg_dat_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_10__inst "upg_dat_o_OBUF[10]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_11__inst "upg_dat_o_OBUF[11]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_12__inst "upg_dat_o_OBUF[12]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_13__inst "upg_dat_o_OBUF[13]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_14__inst "upg_dat_o_OBUF[14]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_15__inst "upg_dat_o_OBUF[15]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_16__inst "upg_dat_o_OBUF[16]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_17__inst "upg_dat_o_OBUF[17]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_18__inst "upg_dat_o_OBUF[18]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_19__inst "upg_dat_o_OBUF[19]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_1__inst "upg_dat_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_20__inst "upg_dat_o_OBUF[20]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_21__inst "upg_dat_o_OBUF[21]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_22__inst "upg_dat_o_OBUF[22]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_23__inst "upg_dat_o_OBUF[23]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_24__inst "upg_dat_o_OBUF[24]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_25__inst "upg_dat_o_OBUF[25]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_26__inst "upg_dat_o_OBUF[26]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_27__inst "upg_dat_o_OBUF[27]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_28__inst "upg_dat_o_OBUF[28]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_29__inst "upg_dat_o_OBUF[29]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_2__inst "upg_dat_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_30__inst "upg_dat_o_OBUF[30]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_31__inst "upg_dat_o_OBUF[31]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_3__inst "upg_dat_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_4__inst "upg_dat_o_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_5__inst "upg_dat_o_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_6__inst "upg_dat_o_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_7__inst "upg_dat_o_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_8__inst "upg_dat_o_OBUF[8]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_OBUF_9__inst "upg_dat_o_OBUF[9]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance (rename upg_dat_o_reg_0_ "upg_dat_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_10_ "upg_dat_o_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_11_ "upg_dat_o_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_12_ "upg_dat_o_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_13_ "upg_dat_o_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_14_ "upg_dat_o_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_15_ "upg_dat_o_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_16_ "upg_dat_o_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_17_ "upg_dat_o_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_18_ "upg_dat_o_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_19_ "upg_dat_o_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_1_ "upg_dat_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_20_ "upg_dat_o_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_21_ "upg_dat_o_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_22_ "upg_dat_o_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_23_ "upg_dat_o_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_24_ "upg_dat_o_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_25_ "upg_dat_o_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_26_ "upg_dat_o_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_27_ "upg_dat_o_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_28_ "upg_dat_o_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_29_ "upg_dat_o_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_2_ "upg_dat_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_30_ "upg_dat_o_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_31_ "upg_dat_o_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_3_ "upg_dat_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_4_ "upg_dat_o_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_5_ "upg_dat_o_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_6_ "upg_dat_o_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_7_ "upg_dat_o_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_8_ "upg_dat_o_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename upg_dat_o_reg_9_ "upg_dat_o_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance upg_done_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance upg_done_o_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h0008")) - ) - (instance upg_done_o_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFEFEFEFEFEEEEEEE")) - ) - (instance upg_done_o_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'hE")) - (property SOFT_HLUTNM (string "soft_lutpair19")) - ) - (instance upg_done_o_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance upg_rst_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) - (instance upg_rx_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) - (instance upg_tx_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance upg_wen_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) - (instance upg_wen_o_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hAAAB")) - ) - (instance upg_wen_o_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h1")) - ) - (instance upg_wen_o_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'h0000AAA8")) - ) - (instance upg_wen_o_i_4 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFFBBB0")) - (property SOFT_HLUTNM (string "soft_lutpair1")) - ) - (instance upg_wen_o_i_5 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000002800000000")) - ) - (instance upg_wen_o_i_6 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFF00FFFFFE00FEFE")) - ) - (instance upg_wen_o_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance wr_byte_len_done_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h5555555555555554")) - ) - (instance wr_byte_len_done_i_2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFFFE")) - (property SOFT_HLUTNM (string "soft_lutpair22")) - ) - (instance wr_byte_len_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance wr_byte_num_done_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h000000006AAA9555")) - ) - (instance wr_byte_num_done_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFFFFF96F6FF6")) - ) - (instance wr_byte_num_done_i_3 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'hFFFFFFFEFFFEFFFF")) - ) - (instance wr_byte_num_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_0__i_1 "wwait_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) - (property INIT (string "2'h1")) - (property SOFT_HLUTNM (string "soft_lutpair11")) - ) - (instance (rename wwait_cnt_10__i_1 "wwait_cnt[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair55")) - ) - (instance (rename wwait_cnt_11__i_1 "wwait_cnt[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair50")) - ) - (instance (rename wwait_cnt_12__i_1 "wwait_cnt[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair49")) - ) - (instance (rename wwait_cnt_13__i_1 "wwait_cnt[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair48")) - ) - (instance (rename wwait_cnt_14__i_1 "wwait_cnt[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - ) - (instance (rename wwait_cnt_15__i_1 "wwait_cnt[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) - (property INIT (string "8'h10")) - ) - (instance (rename wwait_cnt_15__i_2 "wwait_cnt[15]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair45")) - ) - (instance (rename wwait_cnt_15__i_4 "wwait_cnt[15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) - (property INIT (string "64'h0000000040000000")) - ) - (instance (rename wwait_cnt_15__i_5 "wwait_cnt[15]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'h7FFF")) - ) - (instance (rename wwait_cnt_15__i_6 "wwait_cnt[15]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) - (property INIT (string "32'hFFFFFFFE")) - ) - (instance (rename wwait_cnt_15__i_7 "wwait_cnt[15]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) - (property INIT (string "16'hFFFE")) - ) - (instance (rename wwait_cnt_1__i_1 "wwait_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair45")) - ) - (instance (rename wwait_cnt_2__i_1 "wwait_cnt[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair48")) - ) - (instance (rename wwait_cnt_3__i_1 "wwait_cnt[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair49")) - ) - (instance (rename wwait_cnt_4__i_1 "wwait_cnt[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair50")) - ) - (instance (rename wwait_cnt_5__i_1 "wwait_cnt[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair51")) - ) - (instance (rename wwait_cnt_6__i_1 "wwait_cnt[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair53")) - ) - (instance (rename wwait_cnt_7__i_1 "wwait_cnt[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair55")) - ) - (instance (rename wwait_cnt_8__i_1 "wwait_cnt[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair53")) - ) - (instance (rename wwait_cnt_9__i_1 "wwait_cnt[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) - (property INIT (string "4'h2")) - (property SOFT_HLUTNM (string "soft_lutpair51")) - ) - (instance (rename wwait_cnt_reg_0_ "wwait_cnt_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) - (property INIT (string "1'b1")) - ) - (instance (rename wwait_cnt_reg_10_ "wwait_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_11_ "wwait_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_12_ "wwait_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_12__i_2 "wwait_cnt_reg[12]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename wwait_cnt_reg_13_ "wwait_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_14_ "wwait_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_15_ "wwait_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_15__i_3 "wwait_cnt_reg[15]_i_3") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename wwait_cnt_reg_1_ "wwait_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_2_ "wwait_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_3_ "wwait_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_4_ "wwait_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_4__i_2 "wwait_cnt_reg[4]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename wwait_cnt_reg_5_ "wwait_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_6_ "wwait_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_7_ "wwait_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_8_ "wwait_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (instance (rename wwait_cnt_reg_8__i_2 "wwait_cnt_reg[8]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) - (instance (rename wwait_cnt_reg_9_ "wwait_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) - (property INIT (string "1'b0")) - ) - (net (rename &_const0_ "") (joined - (portref CI (instanceref byte_cnt_reg_4__i_1)) - (portref CI (instanceref recv_done_reg_i_21)) - (portref CI (instanceref rwait_cnt_reg_4__i_2)) - (portref CI (instanceref wwait_cnt_reg_4__i_2)) - (portref CYINIT (instanceref byte_cnt_reg_12__i_1)) - (portref CYINIT (instanceref byte_cnt_reg_16__i_1)) - (portref CYINIT (instanceref byte_cnt_reg_20__i_1)) - (portref CYINIT (instanceref byte_cnt_reg_24__i_1)) - (portref CYINIT (instanceref byte_cnt_reg_28__i_1)) - (portref CYINIT (instanceref byte_cnt_reg_31__i_2)) - (portref CYINIT (instanceref byte_cnt_reg_8__i_1)) - (portref CYINIT (instanceref recv_done_reg_i_12)) - (portref CYINIT (instanceref recv_done_reg_i_2)) - (portref CYINIT (instanceref recv_done_reg_i_3)) - (portref CYINIT (instanceref rwait_cnt_reg_12__i_2)) - (portref CYINIT (instanceref rwait_cnt_reg_15__i_3)) - (portref CYINIT (instanceref rwait_cnt_reg_8__i_2)) - (portref CYINIT (instanceref wwait_cnt_reg_12__i_2)) - (portref CYINIT (instanceref wwait_cnt_reg_15__i_3)) - (portref CYINIT (instanceref wwait_cnt_reg_8__i_2)) - (portref (member DI 3) (instanceref byte_cnt_reg_12__i_1)) - (portref (member DI 3) (instanceref byte_cnt_reg_16__i_1)) - (portref (member DI 3) (instanceref byte_cnt_reg_20__i_1)) - (portref (member DI 3) (instanceref byte_cnt_reg_24__i_1)) - (portref (member DI 3) (instanceref byte_cnt_reg_28__i_1)) - (portref (member DI 3) (instanceref byte_cnt_reg_31__i_2)) - (portref (member DI 3) (instanceref byte_cnt_reg_4__i_1)) - (portref (member DI 3) (instanceref byte_cnt_reg_8__i_1)) - (portref (member DI 3) (instanceref rwait_cnt_reg_12__i_2)) - (portref (member DI 3) (instanceref rwait_cnt_reg_15__i_3)) - (portref (member DI 3) (instanceref rwait_cnt_reg_4__i_2)) - (portref (member DI 3) (instanceref rwait_cnt_reg_8__i_2)) - (portref (member DI 3) (instanceref wwait_cnt_reg_12__i_2)) - (portref (member DI 3) (instanceref wwait_cnt_reg_15__i_3)) - (portref (member DI 3) (instanceref wwait_cnt_reg_4__i_2)) - (portref (member DI 3) (instanceref wwait_cnt_reg_8__i_2)) - (portref (member DI 2) (instanceref byte_cnt_reg_12__i_1)) - (portref (member DI 2) (instanceref byte_cnt_reg_16__i_1)) - (portref (member DI 2) (instanceref byte_cnt_reg_20__i_1)) - (portref (member DI 2) (instanceref byte_cnt_reg_24__i_1)) - (portref (member DI 2) (instanceref byte_cnt_reg_28__i_1)) - (portref (member DI 2) (instanceref byte_cnt_reg_31__i_2)) - (portref (member DI 2) (instanceref byte_cnt_reg_4__i_1)) - (portref (member DI 2) (instanceref byte_cnt_reg_8__i_1)) - (portref (member DI 2) (instanceref rwait_cnt_reg_12__i_2)) - (portref (member DI 2) (instanceref rwait_cnt_reg_15__i_3)) - (portref (member DI 2) (instanceref rwait_cnt_reg_4__i_2)) - (portref (member DI 2) (instanceref rwait_cnt_reg_8__i_2)) - (portref (member DI 2) (instanceref wwait_cnt_reg_12__i_2)) - (portref (member DI 2) (instanceref wwait_cnt_reg_15__i_3)) - (portref (member DI 2) (instanceref wwait_cnt_reg_4__i_2)) - (portref (member DI 2) (instanceref wwait_cnt_reg_8__i_2)) - (portref (member DI 1) (instanceref byte_cnt_reg_12__i_1)) - (portref (member DI 1) (instanceref byte_cnt_reg_16__i_1)) - (portref (member DI 1) (instanceref byte_cnt_reg_20__i_1)) - (portref (member DI 1) (instanceref byte_cnt_reg_24__i_1)) - (portref (member DI 1) (instanceref byte_cnt_reg_28__i_1)) - (portref (member DI 1) (instanceref byte_cnt_reg_31__i_2)) - (portref (member DI 1) (instanceref byte_cnt_reg_4__i_1)) - (portref (member DI 1) (instanceref byte_cnt_reg_8__i_1)) - (portref (member DI 1) (instanceref rwait_cnt_reg_12__i_2)) - (portref (member DI 1) (instanceref rwait_cnt_reg_15__i_3)) - (portref (member DI 1) (instanceref rwait_cnt_reg_4__i_2)) - (portref (member DI 1) (instanceref rwait_cnt_reg_8__i_2)) - (portref (member DI 1) (instanceref wwait_cnt_reg_12__i_2)) - (portref (member DI 1) (instanceref wwait_cnt_reg_15__i_3)) - (portref (member DI 1) (instanceref wwait_cnt_reg_4__i_2)) - (portref (member DI 1) (instanceref wwait_cnt_reg_8__i_2)) - (portref (member DI 0) (instanceref byte_cnt_reg_12__i_1)) - (portref (member DI 0) (instanceref byte_cnt_reg_16__i_1)) - (portref (member DI 0) (instanceref byte_cnt_reg_20__i_1)) - (portref (member DI 0) (instanceref byte_cnt_reg_24__i_1)) - (portref (member DI 0) (instanceref byte_cnt_reg_28__i_1)) - (portref (member DI 0) (instanceref byte_cnt_reg_31__i_2)) - (portref (member DI 0) (instanceref byte_cnt_reg_4__i_1)) - (portref (member DI 0) (instanceref byte_cnt_reg_8__i_1)) - (portref (member DI 0) (instanceref rwait_cnt_reg_12__i_2)) - (portref (member DI 0) (instanceref rwait_cnt_reg_15__i_3)) - (portref (member DI 0) (instanceref rwait_cnt_reg_4__i_2)) - (portref (member DI 0) (instanceref rwait_cnt_reg_8__i_2)) - (portref (member DI 0) (instanceref wwait_cnt_reg_12__i_2)) - (portref (member DI 0) (instanceref wwait_cnt_reg_15__i_3)) - (portref (member DI 0) (instanceref wwait_cnt_reg_4__i_2)) - (portref (member DI 0) (instanceref wwait_cnt_reg_8__i_2)) - (portref G (instanceref GND)) - (portref R (instanceref s_axi_araddr_reg_3_)) - (portref R (instanceref s_axi_arvalid_reg)) - (portref R (instanceref s_axi_awaddr_reg_3_)) - (portref R (instanceref s_axi_awvalid_reg)) - (portref R (instanceref s_axi_wdata_reg_0_)) - (portref R (instanceref s_axi_wdata_reg_1_)) - (portref R (instanceref s_axi_wdata_reg_4_)) - (portref R (instanceref s_axi_wstrb_reg_3_)) - (portref R (instanceref uart_rdat_reg_0_)) - (portref R (instanceref uart_rdat_reg_1_)) - (portref R (instanceref uart_rdat_reg_2_)) - (portref R (instanceref uart_rdat_reg_3_)) - (portref R (instanceref uart_rdat_reg_4_)) - (portref R (instanceref uart_rdat_reg_5_)) - (portref R (instanceref uart_rdat_reg_6_)) - (portref R (instanceref uart_rdat_reg_7_)) - (portref (member S 0) (instanceref byte_cnt_reg_31__i_2)) - (portref (member S 0) (instanceref rwait_cnt_reg_15__i_3)) - (portref (member S 0) (instanceref wwait_cnt_reg_15__i_3)) - (portref (member s_axi_araddr 3) (instanceref axi_uart_inst)) - (portref (member s_axi_araddr 2) (instanceref axi_uart_inst)) - (portref (member s_axi_araddr 1) (instanceref axi_uart_inst)) - (portref (member s_axi_awaddr 3) (instanceref axi_uart_inst)) - (portref (member s_axi_awaddr 2) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 21) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 20) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 19) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 18) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 17) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 16) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 15) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 14) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 13) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 12) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 11) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 10) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 9) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 8) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 7) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 6) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 5) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 4) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 3) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 2) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 1) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 0) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 24) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 23) (instanceref axi_uart_inst)) - (portref (member s_axi_wdata 22) (instanceref axi_uart_inst)) - ) - ) - (net (rename &_const1_ "") (joined - (portref CE (instanceref RCS_reg_0_)) - (portref CE (instanceref RCS_reg_1_)) - (portref CE (instanceref RCS_reg_2_)) - (portref CE (instanceref WCS_reg_0_)) - (portref CE (instanceref WCS_reg_1_)) - (portref CE (instanceref WCS_reg_2_)) - (portref CE (instanceref initFlag_reg)) - (portref CE (instanceref oldInitF_reg)) - (portref CE (instanceref rdStat_reg)) - (portref CE (instanceref recv_done_reg)) - (portref CE (instanceref rx_done_reg)) - (portref CE (instanceref s_axi_araddr_reg_3_)) - (portref CE (instanceref s_axi_arvalid_reg)) - (portref CE (instanceref s_axi_awaddr_reg_3_)) - (portref CE (instanceref s_axi_awvalid_reg)) - (portref CE (instanceref statReg_reg_0_)) - (portref CE (instanceref uart_wen_reg)) - (portref CYINIT (instanceref recv_done_reg_i_21)) - (portref P (instanceref VCC)) - (portref (member s_axi_awaddr 1) (instanceref axi_uart_inst)) - (portref s_axi_bready (instanceref axi_uart_inst)) - (portref s_axi_rready (instanceref axi_uart_inst)) - ) - ) - (net (rename RCS_0__i_1_n_0 "RCS[0]_i_1_n_0") (joined - (portref D (instanceref RCS_reg_0_)) - (portref O (instanceref RCS_0__i_1)) - ) - ) - (net (rename RCS_1__i_1_n_0 "RCS[1]_i_1_n_0") (joined - (portref D (instanceref RCS_reg_1_)) - (portref O (instanceref RCS_1__i_1)) - ) - ) - (net (rename RCS_2__i_1_n_0 "RCS[2]_i_1_n_0") (joined - (portref D (instanceref RCS_reg_2_)) - (portref O (instanceref RCS_2__i_1)) - ) - ) - (net (rename RCS_reg_n_0__0_ "RCS_reg_n_0_[0]") (joined - (portref I0 (instanceref rdStat_i_1)) - (portref I0 (instanceref statReg_0__i_2)) - (portref I1 (instanceref rwait_cnt_15__i_1)) - (portref I2 (instanceref uart_rdat_7__i_1)) - (portref I3 (instanceref RCS_0__i_1)) - (portref I3 (instanceref RCS_2__i_1)) - (portref I4 (instanceref RCS_1__i_1)) - (portref I4 (instanceref s_axi_araddr_3__i_1)) - (portref I4 (instanceref s_axi_arvalid_i_1)) - (portref Q (instanceref RCS_reg_0_)) - ) - ) - (net (rename RCS_reg_n_0__1_ "RCS_reg_n_0_[1]") (joined - (portref I0 (instanceref rwait_cnt_15__i_1)) - (portref I1 (instanceref statReg_0__i_2)) - (portref I1 (instanceref uart_rdat_7__i_1)) - (portref I2 (instanceref RCS_0__i_1)) - (portref I2 (instanceref RCS_2__i_1)) - (portref I2 (instanceref s_axi_arvalid_i_1)) - (portref I3 (instanceref RCS_1__i_1)) - (portref I3 (instanceref s_axi_araddr_3__i_1)) - (portref I5 (instanceref rdStat_i_1)) - (portref Q (instanceref RCS_reg_1_)) - ) - ) - (net (rename RCS_reg_n_0__2_ "RCS_reg_n_0_[2]") (joined - (portref I1 (instanceref s_axi_araddr_3__i_1)) - (portref I1 (instanceref s_axi_arvalid_i_2)) - (portref I2 (instanceref rdStat_i_1)) - (portref I2 (instanceref rwait_cnt_15__i_1)) - (portref I3 (instanceref statReg_0__i_1)) - (portref I4 (instanceref RCS_0__i_1)) - (portref I4 (instanceref RCS_2__i_1)) - (portref I4 (instanceref uart_rdat_7__i_1)) - (portref I5 (instanceref RCS_1__i_1)) - (portref Q (instanceref RCS_reg_2_)) - ) - ) - (net (rename WCS_0__i_1_n_0 "WCS[0]_i_1_n_0") (joined - (portref D (instanceref WCS_reg_0_)) - (portref O (instanceref WCS_0__i_1)) - ) - ) - (net (rename WCS_0__i_2_n_0 "WCS[0]_i_2_n_0") (joined - (portref I0 (instanceref WCS_0__i_1)) - (portref O (instanceref WCS_0__i_2)) - ) - ) - (net (rename WCS_1__i_1_n_0 "WCS[1]_i_1_n_0") (joined - (portref D (instanceref WCS_reg_1_)) - (portref O (instanceref WCS_1__i_1)) - ) - ) - (net (rename WCS_2__i_1_n_0 "WCS[2]_i_1_n_0") (joined - (portref D (instanceref WCS_reg_2_)) - (portref O (instanceref WCS_2__i_1)) - ) - ) - (net (rename WCS_2__i_2_n_0 "WCS[2]_i_2_n_0") (joined - (portref I1 (instanceref WCS_0__i_1)) - (portref I2 (instanceref WCS_2__i_1)) - (portref I3 (instanceref oldInitF_i_1)) - (portref O (instanceref WCS_2__i_2)) - ) - ) - (net (rename WCS_2__i_3_n_0 "WCS[2]_i_3_n_0") (joined - (portref I0 (instanceref WCS_2__i_2)) - (portref O (instanceref WCS_2__i_3)) - ) - ) - (net (rename WCS_2__i_4_n_0 "WCS[2]_i_4_n_0") (joined - (portref I5 (instanceref WCS_2__i_2)) - (portref O (instanceref WCS_2__i_4)) - ) - ) - (net (rename WCS_2__i_5_n_0 "WCS[2]_i_5_n_0") (joined - (portref I4 (instanceref WCS_2__i_4)) - (portref O (instanceref WCS_2__i_5)) - ) - ) - (net (rename WCS_reg_n_0__0_ "WCS_reg_n_0_[0]") (joined - (portref I0 (instanceref s_axi_wdata_0__i_1)) - (portref I0 (instanceref s_axi_wdata_1__i_1)) - (portref I0 (instanceref s_axi_wdata_4__i_2)) - (portref I0 (instanceref s_axi_wstrb_3__i_1)) - (portref I0 (instanceref wwait_cnt_15__i_1)) - (portref I1 (instanceref initFlag_i_1)) - (portref I1 (instanceref msg_indx_7__i_1)) - (portref I1 (instanceref upg_done_o_i_1)) - (portref I2 (instanceref oldInitF_i_1)) - (portref I2 (instanceref uart_wen_i_1)) - (portref I3 (instanceref s_axi_awaddr_3__i_1)) - (portref I3 (instanceref s_axi_awvalid_i_1)) - (portref I3 (instanceref s_axi_wdata_6__i_1)) - (portref I4 (instanceref WCS_0__i_1)) - (portref I4 (instanceref WCS_1__i_1)) - (portref I4 (instanceref WCS_2__i_1)) - (portref I5 (instanceref s_axi_awvalid_i_2)) - (portref I5 (instanceref s_axi_wdata_4__i_1)) - (portref Q (instanceref WCS_reg_0_)) - ) - ) - (net (rename WCS_reg_n_0__1_ "WCS_reg_n_0_[1]") (joined - (portref I0 (instanceref s_axi_wdata_4__i_1)) - (portref I1 (instanceref oldInitF_i_1)) - (portref I1 (instanceref wwait_cnt_15__i_1)) - (portref I2 (instanceref initFlag_i_1)) - (portref I2 (instanceref msg_indx_7__i_1)) - (portref I2 (instanceref s_axi_wdata_6__i_1)) - (portref I2 (instanceref upg_done_o_i_1)) - (portref I3 (instanceref uart_wen_i_1)) - (portref I4 (instanceref s_axi_awaddr_3__i_1)) - (portref I4 (instanceref s_axi_awvalid_i_2)) - (portref I5 (instanceref WCS_0__i_1)) - (portref I5 (instanceref WCS_1__i_1)) - (portref I5 (instanceref WCS_2__i_1)) - (portref Q (instanceref WCS_reg_1_)) - ) - ) - (net (rename WCS_reg_n_0__2_ "WCS_reg_n_0_[2]") (joined - (portref I0 (instanceref oldInitF_i_1)) - (portref I0 (instanceref s_axi_wdata_6__i_1)) - (portref I1 (instanceref s_axi_awaddr_3__i_1)) - (portref I2 (instanceref s_axi_wdata_4__i_1)) - (portref I2 (instanceref wwait_cnt_15__i_1)) - (portref I3 (instanceref WCS_0__i_1)) - (portref I3 (instanceref WCS_1__i_1)) - (portref I3 (instanceref WCS_2__i_1)) - (portref I3 (instanceref initFlag_i_1)) - (portref I3 (instanceref msg_indx_7__i_1)) - (portref I3 (instanceref s_axi_awvalid_i_2)) - (portref I3 (instanceref upg_done_o_i_1)) - (portref I4 (instanceref uart_wen_i_1)) - (portref Q (instanceref WCS_reg_2_)) - ) - ) - (net (rename bn_ascii_reg_n_0__0_ "bn_ascii_reg_n_0_[0]") (joined - (portref I2 (instanceref s_axi_wdata_0__i_3)) - (portref Q (instanceref bn_ascii_reg_0_)) - ) - ) - (net (rename bn_ascii_reg_n_0__1_ "bn_ascii_reg_n_0_[1]") (joined - (portref I2 (instanceref s_axi_wdata_1__i_3)) - (portref Q (instanceref bn_ascii_reg_1_)) - ) - ) - (net (rename bn_ascii_reg_n_0__2_ "bn_ascii_reg_n_0_[2]") (joined - (portref I0 (instanceref s_axi_wdata_2__i_3)) - (portref Q (instanceref bn_ascii_reg_2_)) - ) - ) - (net (rename bn_ascii_reg_n_0__3_ "bn_ascii_reg_n_0_[3]") (joined - (portref I1 (instanceref s_axi_wdata_3__i_3)) - (portref Q (instanceref bn_ascii_reg_3_)) - ) - ) - (net (rename bn_ascii_reg_n_0__48_ "bn_ascii_reg_n_0_[48]") (joined - (portref I3 (instanceref s_axi_wdata_0__i_4)) - (portref Q (instanceref bn_ascii_reg_48_)) - ) - ) - (net (rename bn_ascii_reg_n_0__49_ "bn_ascii_reg_n_0_[49]") (joined - (portref I3 (instanceref s_axi_wdata_1__i_5)) - (portref Q (instanceref bn_ascii_reg_49_)) - ) - ) - (net (rename bn_ascii_reg_n_0__50_ "bn_ascii_reg_n_0_[50]") (joined - (portref I3 (instanceref s_axi_wdata_2__i_4)) - (portref Q (instanceref bn_ascii_reg_50_)) - ) - ) - (net (rename bn_ascii_reg_n_0__51_ "bn_ascii_reg_n_0_[51]") (joined - (portref I3 (instanceref s_axi_wdata_3__i_4)) - (portref Q (instanceref bn_ascii_reg_51_)) - ) - ) - (net (rename bn_ascii_reg_n_0__53_ "bn_ascii_reg_n_0_[53]") (joined - (portref I0 (instanceref s_axi_wdata_5__i_6)) - (portref Q (instanceref bn_ascii_reg_53_)) - ) - ) - (net (rename bn_ascii_reg_n_0__54_ "bn_ascii_reg_n_0_[54]") (joined - (portref I4 (instanceref s_axi_wdata_6__i_7)) - (portref Q (instanceref bn_ascii_reg_54_)) - ) - ) - (net (rename bn_ascii_reg_n_0__56_ "bn_ascii_reg_n_0_[56]") (joined - (portref I0 (instanceref s_axi_wdata_0__i_4)) - (portref Q (instanceref bn_ascii_reg_56_)) - ) - ) - (net (rename bn_ascii_reg_n_0__57_ "bn_ascii_reg_n_0_[57]") (joined - (portref I1 (instanceref s_axi_wdata_1__i_5)) - (portref Q (instanceref bn_ascii_reg_57_)) - ) - ) - (net (rename bn_ascii_reg_n_0__58_ "bn_ascii_reg_n_0_[58]") (joined - (portref I0 (instanceref s_axi_wdata_2__i_4)) - (portref Q (instanceref bn_ascii_reg_58_)) - ) - ) - (net (rename bn_ascii_reg_n_0__59_ "bn_ascii_reg_n_0_[59]") (joined - (portref I0 (instanceref s_axi_wdata_3__i_4)) - (portref Q (instanceref bn_ascii_reg_59_)) - ) - ) - (net (rename bn_ascii_reg_n_0__5_ "bn_ascii_reg_n_0_[5]") (joined - (portref I1 (instanceref s_axi_wdata_5__i_3)) - (portref I2 (instanceref s_axi_wdata_4__i_6)) - (portref Q (instanceref bn_ascii_reg_5_)) - ) - ) - (net (rename bn_ascii_reg_n_0__61_ "bn_ascii_reg_n_0_[61]") (joined - (portref I2 (instanceref s_axi_wdata_5__i_6)) - (portref Q (instanceref bn_ascii_reg_61_)) - ) - ) - (net (rename bn_ascii_reg_n_0__62_ "bn_ascii_reg_n_0_[62]") (joined - (portref I0 (instanceref s_axi_wdata_6__i_7)) - (portref Q (instanceref bn_ascii_reg_62_)) - ) - ) - (net (rename bn_ascii_reg_n_0__6_ "bn_ascii_reg_n_0_[6]") (joined - (portref I0 (instanceref s_axi_wdata_6__i_4)) - (portref Q (instanceref bn_ascii_reg_6_)) - ) - ) - (net byte_cnt (joined - (portref CE (instanceref byte_cnt_reg_0_)) - (portref CE (instanceref byte_cnt_reg_10_)) - (portref CE (instanceref byte_cnt_reg_11_)) - (portref CE (instanceref byte_cnt_reg_12_)) - (portref CE (instanceref byte_cnt_reg_13_)) - (portref CE (instanceref byte_cnt_reg_14_)) - (portref CE (instanceref byte_cnt_reg_15_)) - (portref CE (instanceref byte_cnt_reg_16_)) - (portref CE (instanceref byte_cnt_reg_17_)) - (portref CE (instanceref byte_cnt_reg_18_)) - (portref CE (instanceref byte_cnt_reg_19_)) - (portref CE (instanceref byte_cnt_reg_1_)) - (portref CE (instanceref byte_cnt_reg_20_)) - (portref CE (instanceref byte_cnt_reg_21_)) - (portref CE (instanceref byte_cnt_reg_22_)) - (portref CE (instanceref byte_cnt_reg_23_)) - (portref CE (instanceref byte_cnt_reg_24_)) - (portref CE (instanceref byte_cnt_reg_25_)) - (portref CE (instanceref byte_cnt_reg_26_)) - (portref CE (instanceref byte_cnt_reg_27_)) - (portref CE (instanceref byte_cnt_reg_28_)) - (portref CE (instanceref byte_cnt_reg_29_)) - (portref CE (instanceref byte_cnt_reg_2_)) - (portref CE (instanceref byte_cnt_reg_30_)) - (portref CE (instanceref byte_cnt_reg_31_)) - (portref CE (instanceref byte_cnt_reg_3_)) - (portref CE (instanceref byte_cnt_reg_4_)) - (portref CE (instanceref byte_cnt_reg_5_)) - (portref CE (instanceref byte_cnt_reg_6_)) - (portref CE (instanceref byte_cnt_reg_7_)) - (portref CE (instanceref byte_cnt_reg_8_)) - (portref CE (instanceref byte_cnt_reg_9_)) - (portref CE (instanceref dbuf_reg_0_)) - (portref CE (instanceref dbuf_reg_10_)) - (portref CE (instanceref dbuf_reg_11_)) - (portref CE (instanceref dbuf_reg_12_)) - (portref CE (instanceref dbuf_reg_13_)) - (portref CE (instanceref dbuf_reg_14_)) - (portref CE (instanceref dbuf_reg_15_)) - (portref CE (instanceref dbuf_reg_16_)) - (portref CE (instanceref dbuf_reg_17_)) - (portref CE (instanceref dbuf_reg_18_)) - (portref CE (instanceref dbuf_reg_19_)) - (portref CE (instanceref dbuf_reg_1_)) - (portref CE (instanceref dbuf_reg_20_)) - (portref CE (instanceref dbuf_reg_21_)) - (portref CE (instanceref dbuf_reg_22_)) - (portref CE (instanceref dbuf_reg_23_)) - (portref CE (instanceref dbuf_reg_2_)) - (portref CE (instanceref dbuf_reg_3_)) - (portref CE (instanceref dbuf_reg_4_)) - (portref CE (instanceref dbuf_reg_5_)) - (portref CE (instanceref dbuf_reg_6_)) - (portref CE (instanceref dbuf_reg_7_)) - (portref CE (instanceref dbuf_reg_8_)) - (portref CE (instanceref dbuf_reg_9_)) - (portref O (instanceref byte_cnt_31__i_1)) - ) - ) - (net (rename byte_cnt_reg_12__i_1_n_0 "byte_cnt_reg[12]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_16__i_1)) - (portref (member CO 0) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename byte_cnt_reg_12__i_1_n_1 "byte_cnt_reg[12]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename byte_cnt_reg_12__i_1_n_2 "byte_cnt_reg[12]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename byte_cnt_reg_12__i_1_n_3 "byte_cnt_reg[12]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename byte_cnt_reg_16__i_1_n_0 "byte_cnt_reg[16]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_20__i_1)) - (portref (member CO 0) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename byte_cnt_reg_16__i_1_n_1 "byte_cnt_reg[16]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename byte_cnt_reg_16__i_1_n_2 "byte_cnt_reg[16]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename byte_cnt_reg_16__i_1_n_3 "byte_cnt_reg[16]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename byte_cnt_reg_20__i_1_n_0 "byte_cnt_reg[20]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_24__i_1)) - (portref (member CO 0) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_20__i_1_n_1 "byte_cnt_reg[20]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_20__i_1_n_2 "byte_cnt_reg[20]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_20__i_1_n_3 "byte_cnt_reg[20]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_24__i_1_n_0 "byte_cnt_reg[24]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_28__i_1)) - (portref (member CO 0) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_24__i_1_n_1 "byte_cnt_reg[24]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_24__i_1_n_2 "byte_cnt_reg[24]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_24__i_1_n_3 "byte_cnt_reg[24]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_28__i_1_n_0 "byte_cnt_reg[28]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_31__i_2)) - (portref (member CO 0) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_28__i_1_n_1 "byte_cnt_reg[28]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_28__i_1_n_2 "byte_cnt_reg[28]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_28__i_1_n_3 "byte_cnt_reg[28]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_31__i_2_n_2 "byte_cnt_reg[31]_i_2_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename byte_cnt_reg_31__i_2_n_3 "byte_cnt_reg[31]_i_2_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename byte_cnt_reg_4__i_1_n_0 "byte_cnt_reg[4]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_8__i_1)) - (portref (member CO 0) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename byte_cnt_reg_4__i_1_n_1 "byte_cnt_reg[4]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename byte_cnt_reg_4__i_1_n_2 "byte_cnt_reg[4]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename byte_cnt_reg_4__i_1_n_3 "byte_cnt_reg[4]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename byte_cnt_reg_8__i_1_n_0 "byte_cnt_reg[8]_i_1_n_0") (joined - (portref CI (instanceref byte_cnt_reg_12__i_1)) - (portref (member CO 0) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename byte_cnt_reg_8__i_1_n_1 "byte_cnt_reg[8]_i_1_n_1") (joined - (portref (member CO 1) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename byte_cnt_reg_8__i_1_n_2 "byte_cnt_reg[8]_i_1_n_2") (joined - (portref (member CO 2) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename byte_cnt_reg_8__i_1_n_3 "byte_cnt_reg[8]_i_1_n_3") (joined - (portref (member CO 3) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__0_ "byte_cnt_reg_n_0_[0]") (joined - (portref CYINIT (instanceref byte_cnt_reg_4__i_1)) - (portref I0 (instanceref byte_cnt_0__i_1)) - (portref I1 (instanceref recv_done_i_37)) - (portref I2 (instanceref recv_done_i_33)) - (portref Q (instanceref byte_cnt_reg_0_)) - ) - ) - (net (rename byte_cnt_reg_n_0__17_ "byte_cnt_reg_n_0_[17]") (joined - (portref Q (instanceref byte_cnt_reg_17_)) - (portref (member S 3) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__18_ "byte_cnt_reg_n_0_[18]") (joined - (portref Q (instanceref byte_cnt_reg_18_)) - (portref (member S 2) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__19_ "byte_cnt_reg_n_0_[19]") (joined - (portref Q (instanceref byte_cnt_reg_19_)) - (portref (member S 1) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__1_ "byte_cnt_reg_n_0_[1]") (joined - (portref Q (instanceref byte_cnt_reg_1_)) - (portref (member S 3) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__20_ "byte_cnt_reg_n_0_[20]") (joined - (portref Q (instanceref byte_cnt_reg_20_)) - (portref (member S 0) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__21_ "byte_cnt_reg_n_0_[21]") (joined - (portref Q (instanceref byte_cnt_reg_21_)) - (portref (member S 3) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__22_ "byte_cnt_reg_n_0_[22]") (joined - (portref Q (instanceref byte_cnt_reg_22_)) - (portref (member S 2) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__23_ "byte_cnt_reg_n_0_[23]") (joined - (portref Q (instanceref byte_cnt_reg_23_)) - (portref (member S 1) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__24_ "byte_cnt_reg_n_0_[24]") (joined - (portref Q (instanceref byte_cnt_reg_24_)) - (portref (member S 0) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__25_ "byte_cnt_reg_n_0_[25]") (joined - (portref Q (instanceref byte_cnt_reg_25_)) - (portref (member S 3) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__26_ "byte_cnt_reg_n_0_[26]") (joined - (portref Q (instanceref byte_cnt_reg_26_)) - (portref (member S 2) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__27_ "byte_cnt_reg_n_0_[27]") (joined - (portref Q (instanceref byte_cnt_reg_27_)) - (portref (member S 1) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__28_ "byte_cnt_reg_n_0_[28]") (joined - (portref Q (instanceref byte_cnt_reg_28_)) - (portref (member S 0) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename byte_cnt_reg_n_0__29_ "byte_cnt_reg_n_0_[29]") (joined - (portref Q (instanceref byte_cnt_reg_29_)) - (portref (member S 3) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename byte_cnt_reg_n_0__30_ "byte_cnt_reg_n_0_[30]") (joined - (portref Q (instanceref byte_cnt_reg_30_)) - (portref (member S 2) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename byte_cnt_reg_n_0__31_ "byte_cnt_reg_n_0_[31]") (joined - (portref Q (instanceref byte_cnt_reg_31_)) - (portref (member S 1) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename byte_len_7__i_1_n_0 "byte_len[7]_i_1_n_0") (joined - (portref CE (instanceref byte_len_reg_0_)) - (portref CE (instanceref byte_len_reg_1_)) - (portref CE (instanceref byte_len_reg_2_)) - (portref CE (instanceref byte_len_reg_3_)) - (portref CE (instanceref byte_len_reg_4_)) - (portref CE (instanceref byte_len_reg_5_)) - (portref CE (instanceref byte_len_reg_6_)) - (portref CE (instanceref byte_len_reg_7_)) - (portref CE (instanceref wr_byte_len_done_reg)) - (portref O (instanceref byte_len_7__i_1)) - ) - ) - (net (rename byte_len_reg_n_0__0_ "byte_len_reg_n_0_[0]") (joined - (portref I4 (instanceref wr_byte_num_done_i_3)) - (portref Q (instanceref byte_len_reg_0_)) - ) - ) - (net (rename byte_len_reg_n_0__1_ "byte_len_reg_n_0_[1]") (joined - (portref I2 (instanceref wr_byte_num_done_i_2)) - (portref Q (instanceref byte_len_reg_1_)) - ) - ) - (net (rename byte_len_reg_n_0__2_ "byte_len_reg_n_0_[2]") (joined - (portref I1 (instanceref wr_byte_num_done_i_2)) - (portref Q (instanceref byte_len_reg_2_)) - ) - ) - (net (rename byte_len_reg_n_0__3_ "byte_len_reg_n_0_[3]") (joined - (portref I4 (instanceref wr_byte_num_done_i_1)) - (portref Q (instanceref byte_len_reg_3_)) - ) - ) - (net (rename byte_len_reg_n_0__4_ "byte_len_reg_n_0_[4]") (joined - (portref I1 (instanceref wr_byte_num_done_i_3)) - (portref Q (instanceref byte_len_reg_4_)) - ) - ) - (net (rename byte_len_reg_n_0__5_ "byte_len_reg_n_0_[5]") (joined - (portref I0 (instanceref wr_byte_num_done_i_3)) - (portref Q (instanceref byte_len_reg_5_)) - ) - ) - (net (rename byte_len_reg_n_0__6_ "byte_len_reg_n_0_[6]") (joined - (portref I3 (instanceref wr_byte_num_done_i_3)) - (portref Q (instanceref byte_len_reg_6_)) - ) - ) - (net (rename byte_len_reg_n_0__7_ "byte_len_reg_n_0_[7]") (joined - (portref I2 (instanceref wr_byte_num_done_i_3)) - (portref Q (instanceref byte_len_reg_7_)) - ) - ) - (net byte_num (joined - (portref CE (instanceref byte_num_reg_0_)) - (portref CE (instanceref byte_num_reg_10_)) - (portref CE (instanceref byte_num_reg_11_)) - (portref CE (instanceref byte_num_reg_12_)) - (portref CE (instanceref byte_num_reg_13_)) - (portref CE (instanceref byte_num_reg_14_)) - (portref CE (instanceref byte_num_reg_15_)) - (portref CE (instanceref byte_num_reg_16_)) - (portref CE (instanceref byte_num_reg_17_)) - (portref CE (instanceref byte_num_reg_18_)) - (portref CE (instanceref byte_num_reg_19_)) - (portref CE (instanceref byte_num_reg_1_)) - (portref CE (instanceref byte_num_reg_20_)) - (portref CE (instanceref byte_num_reg_21_)) - (portref CE (instanceref byte_num_reg_22_)) - (portref CE (instanceref byte_num_reg_23_)) - (portref CE (instanceref byte_num_reg_24_)) - (portref CE (instanceref byte_num_reg_25_)) - (portref CE (instanceref byte_num_reg_26_)) - (portref CE (instanceref byte_num_reg_27_)) - (portref CE (instanceref byte_num_reg_28_)) - (portref CE (instanceref byte_num_reg_29_)) - (portref CE (instanceref byte_num_reg_2_)) - (portref CE (instanceref byte_num_reg_30_)) - (portref CE (instanceref byte_num_reg_31_)) - (portref CE (instanceref byte_num_reg_3_)) - (portref CE (instanceref byte_num_reg_4_)) - (portref CE (instanceref byte_num_reg_5_)) - (portref CE (instanceref byte_num_reg_6_)) - (portref CE (instanceref byte_num_reg_7_)) - (portref CE (instanceref byte_num_reg_8_)) - (portref CE (instanceref byte_num_reg_9_)) - (portref CE (instanceref len_cnt_reg_0_)) - (portref CE (instanceref len_cnt_reg_1_)) - (portref CE (instanceref len_cnt_reg_2_)) - (portref CE (instanceref len_cnt_reg_3_)) - (portref O (instanceref byte_num_31__i_1)) - ) - ) - (net (rename byte_num_reg_n_0__24_ "byte_num_reg_n_0_[24]") (joined - (portref I2 (instanceref recv_done_i_11)) - (portref I3 (instanceref recv_done_i_7)) - (portref Q (instanceref byte_num_reg_24_)) - ) - ) - (net (rename byte_num_reg_n_0__25_ "byte_num_reg_n_0_[25]") (joined - (portref I0 (instanceref recv_done_i_11)) - (portref I1 (instanceref recv_done_i_7)) - (portref Q (instanceref byte_num_reg_25_)) - ) - ) - (net (rename byte_num_reg_n_0__26_ "byte_num_reg_n_0_[26]") (joined - (portref I2 (instanceref recv_done_i_10)) - (portref I3 (instanceref recv_done_i_6)) - (portref Q (instanceref byte_num_reg_26_)) - ) - ) - (net (rename byte_num_reg_n_0__27_ "byte_num_reg_n_0_[27]") (joined - (portref I0 (instanceref recv_done_i_10)) - (portref I1 (instanceref recv_done_i_6)) - (portref Q (instanceref byte_num_reg_27_)) - ) - ) - (net (rename byte_num_reg_n_0__28_ "byte_num_reg_n_0_[28]") (joined - (portref I2 (instanceref recv_done_i_9)) - (portref I3 (instanceref recv_done_i_5)) - (portref Q (instanceref byte_num_reg_28_)) - ) - ) - (net (rename byte_num_reg_n_0__29_ "byte_num_reg_n_0_[29]") (joined - (portref I0 (instanceref recv_done_i_9)) - (portref I1 (instanceref recv_done_i_5)) - (portref Q (instanceref byte_num_reg_29_)) - ) - ) - (net (rename byte_num_reg_n_0__30_ "byte_num_reg_n_0_[30]") (joined - (portref I2 (instanceref recv_done_i_8)) - (portref I3 (instanceref recv_done_i_4)) - (portref Q (instanceref byte_num_reg_30_)) - ) - ) - (net (rename byte_num_reg_n_0__31_ "byte_num_reg_n_0_[31]") (joined - (portref I0 (instanceref recv_done_i_8)) - (portref I1 (instanceref recv_done_i_4)) - (portref Q (instanceref byte_num_reg_31_)) - ) - ) - (net (rename data2_0_ "data2[0]") (joined - (portref I5 (instanceref s_axi_wdata_0__i_5)) - (portref Q (instanceref bn_ascii_reg_40_)) - ) - ) - (net (rename data2_1_ "data2[1]") (joined - (portref I1 (instanceref s_axi_wdata_1__i_6)) - (portref Q (instanceref bn_ascii_reg_41_)) - ) - ) - (net (rename data2_2_ "data2[2]") (joined - (portref I5 (instanceref s_axi_wdata_2__i_5)) - (portref Q (instanceref bn_ascii_reg_42_)) - ) - ) - (net (rename data2_3_ "data2[3]") (joined - (portref I5 (instanceref s_axi_wdata_3__i_5)) - (portref Q (instanceref bn_ascii_reg_43_)) - ) - ) - (net (rename data2_5_ "data2[5]") (joined - (portref I1 (instanceref s_axi_wdata_5__i_5)) - (portref Q (instanceref bn_ascii_reg_45_)) - ) - ) - (net (rename data2_6_ "data2[6]") (joined - (portref I1 (instanceref s_axi_wdata_6__i_5)) - (portref Q (instanceref bn_ascii_reg_46_)) - ) - ) - (net (rename data3_0_ "data3[0]") (joined - (portref I3 (instanceref s_axi_wdata_0__i_5)) - (portref Q (instanceref bn_ascii_reg_32_)) - ) - ) - (net (rename data3_1_ "data3[1]") (joined - (portref I0 (instanceref s_axi_wdata_1__i_6)) - (portref Q (instanceref bn_ascii_reg_33_)) - ) - ) - (net (rename data3_2_ "data3[2]") (joined - (portref I3 (instanceref s_axi_wdata_2__i_5)) - (portref Q (instanceref bn_ascii_reg_34_)) - ) - ) - (net (rename data3_3_ "data3[3]") (joined - (portref I3 (instanceref s_axi_wdata_3__i_5)) - (portref Q (instanceref bn_ascii_reg_35_)) - ) - ) - (net (rename data3_5_ "data3[5]") (joined - (portref I0 (instanceref s_axi_wdata_5__i_5)) - (portref Q (instanceref bn_ascii_reg_37_)) - ) - ) - (net (rename data3_6_ "data3[6]") (joined - (portref I3 (instanceref s_axi_wdata_6__i_5)) - (portref Q (instanceref bn_ascii_reg_38_)) - ) - ) - (net (rename data4_0_ "data4[0]") (joined - (portref I1 (instanceref s_axi_wdata_0__i_5)) - (portref Q (instanceref bn_ascii_reg_24_)) - ) - ) - (net (rename data4_1_ "data4[1]") (joined - (portref I5 (instanceref s_axi_wdata_1__i_6)) - (portref Q (instanceref bn_ascii_reg_25_)) - ) - ) - (net (rename data4_2_ "data4[2]") (joined - (portref I1 (instanceref s_axi_wdata_2__i_5)) - (portref Q (instanceref bn_ascii_reg_26_)) - ) - ) - (net (rename data4_3_ "data4[3]") (joined - (portref I1 (instanceref s_axi_wdata_3__i_5)) - (portref Q (instanceref bn_ascii_reg_27_)) - ) - ) - (net (rename data4_5_ "data4[5]") (joined - (portref I5 (instanceref s_axi_wdata_5__i_5)) - (portref Q (instanceref bn_ascii_reg_29_)) - ) - ) - (net (rename data4_6_ "data4[6]") (joined - (portref I3 (instanceref s_axi_wdata_6__i_6)) - (portref Q (instanceref bn_ascii_reg_30_)) - ) - ) - (net (rename data5_0_ "data5[0]") (joined - (portref I0 (instanceref s_axi_wdata_0__i_5)) - (portref Q (instanceref bn_ascii_reg_16_)) - ) - ) - (net (rename data5_1_ "data5[1]") (joined - (portref I3 (instanceref s_axi_wdata_1__i_6)) - (portref Q (instanceref bn_ascii_reg_17_)) - ) - ) - (net (rename data5_2_ "data5[2]") (joined - (portref I0 (instanceref s_axi_wdata_2__i_5)) - (portref Q (instanceref bn_ascii_reg_18_)) - ) - ) - (net (rename data5_3_ "data5[3]") (joined - (portref I0 (instanceref s_axi_wdata_3__i_5)) - (portref Q (instanceref bn_ascii_reg_19_)) - ) - ) - (net (rename data5_5_ "data5[5]") (joined - (portref I3 (instanceref s_axi_wdata_5__i_5)) - (portref Q (instanceref bn_ascii_reg_21_)) - ) - ) - (net (rename data5_6_ "data5[6]") (joined - (portref I1 (instanceref s_axi_wdata_6__i_6)) - (portref Q (instanceref bn_ascii_reg_22_)) - ) - ) - (net (rename data6_0_ "data6[0]") (joined - (portref I3 (instanceref s_axi_wdata_0__i_3)) - (portref Q (instanceref bn_ascii_reg_8_)) - ) - ) - (net (rename data6_1_ "data6[1]") (joined - (portref I3 (instanceref s_axi_wdata_1__i_3)) - (portref Q (instanceref bn_ascii_reg_9_)) - ) - ) - (net (rename data6_2_ "data6[2]") (joined - (portref I4 (instanceref s_axi_wdata_2__i_3)) - (portref Q (instanceref bn_ascii_reg_10_)) - ) - ) - (net (rename data6_3_ "data6[3]") (joined - (portref I0 (instanceref s_axi_wdata_3__i_3)) - (portref Q (instanceref bn_ascii_reg_11_)) - ) - ) - (net (rename data6_5_ "data6[5]") (joined - (portref I0 (instanceref s_axi_wdata_5__i_3)) - (portref I4 (instanceref s_axi_wdata_4__i_6)) - (portref Q (instanceref bn_ascii_reg_13_)) - ) - ) - (net (rename data6_6_ "data6[6]") (joined - (portref I1 (instanceref s_axi_wdata_6__i_4)) - (portref Q (instanceref bn_ascii_reg_14_)) - ) - ) - (net (rename dbuf_0_ "dbuf[0]") (joined - (portref D (instanceref dbuf_reg_8_)) - (portref D (instanceref upg_dat_o_reg_8_)) - (portref Q (instanceref dbuf_reg_0_)) - ) - ) - (net (rename dbuf_10_ "dbuf[10]") (joined - (portref D (instanceref dbuf_reg_18_)) - (portref D (instanceref upg_dat_o_reg_18_)) - (portref Q (instanceref dbuf_reg_10_)) - ) - ) - (net (rename dbuf_11_ "dbuf[11]") (joined - (portref D (instanceref dbuf_reg_19_)) - (portref D (instanceref upg_dat_o_reg_19_)) - (portref Q (instanceref dbuf_reg_11_)) - ) - ) - (net (rename dbuf_12_ "dbuf[12]") (joined - (portref D (instanceref dbuf_reg_20_)) - (portref D (instanceref upg_dat_o_reg_20_)) - (portref Q (instanceref dbuf_reg_12_)) - ) - ) - (net (rename dbuf_13_ "dbuf[13]") (joined - (portref D (instanceref dbuf_reg_21_)) - (portref D (instanceref upg_dat_o_reg_21_)) - (portref Q (instanceref dbuf_reg_13_)) - ) - ) - (net (rename dbuf_14_ "dbuf[14]") (joined - (portref D (instanceref dbuf_reg_22_)) - (portref D (instanceref upg_dat_o_reg_22_)) - (portref Q (instanceref dbuf_reg_14_)) - ) - ) - (net (rename dbuf_15_ "dbuf[15]") (joined - (portref D (instanceref dbuf_reg_23_)) - (portref D (instanceref upg_dat_o_reg_23_)) - (portref Q (instanceref dbuf_reg_15_)) - ) - ) - (net (rename dbuf_16_ "dbuf[16]") (joined - (portref D (instanceref upg_dat_o_reg_24_)) - (portref Q (instanceref dbuf_reg_16_)) - ) - ) - (net (rename dbuf_17_ "dbuf[17]") (joined - (portref D (instanceref upg_dat_o_reg_25_)) - (portref Q (instanceref dbuf_reg_17_)) - ) - ) - (net (rename dbuf_18_ "dbuf[18]") (joined - (portref D (instanceref upg_dat_o_reg_26_)) - (portref Q (instanceref dbuf_reg_18_)) - ) - ) - (net (rename dbuf_19_ "dbuf[19]") (joined - (portref D (instanceref upg_dat_o_reg_27_)) - (portref Q (instanceref dbuf_reg_19_)) - ) - ) - (net (rename dbuf_1_ "dbuf[1]") (joined - (portref D (instanceref dbuf_reg_9_)) - (portref D (instanceref upg_dat_o_reg_9_)) - (portref Q (instanceref dbuf_reg_1_)) - ) - ) - (net (rename dbuf_20_ "dbuf[20]") (joined - (portref D (instanceref upg_dat_o_reg_28_)) - (portref Q (instanceref dbuf_reg_20_)) - ) - ) - (net (rename dbuf_21_ "dbuf[21]") (joined - (portref D (instanceref upg_dat_o_reg_29_)) - (portref Q (instanceref dbuf_reg_21_)) - ) - ) - (net (rename dbuf_22_ "dbuf[22]") (joined - (portref D (instanceref upg_dat_o_reg_30_)) - (portref Q (instanceref dbuf_reg_22_)) - ) - ) - (net (rename dbuf_23_ "dbuf[23]") (joined - (portref D (instanceref upg_dat_o_reg_31_)) - (portref Q (instanceref dbuf_reg_23_)) - ) - ) - (net (rename dbuf_2_ "dbuf[2]") (joined - (portref D (instanceref dbuf_reg_10_)) - (portref D (instanceref upg_dat_o_reg_10_)) - (portref Q (instanceref dbuf_reg_2_)) - ) - ) - (net (rename dbuf_3_ "dbuf[3]") (joined - (portref D (instanceref dbuf_reg_11_)) - (portref D (instanceref upg_dat_o_reg_11_)) - (portref Q (instanceref dbuf_reg_3_)) - ) - ) - (net (rename dbuf_4_ "dbuf[4]") (joined - (portref D (instanceref dbuf_reg_12_)) - (portref D (instanceref upg_dat_o_reg_12_)) - (portref Q (instanceref dbuf_reg_4_)) - ) - ) - (net (rename dbuf_5_ "dbuf[5]") (joined - (portref D (instanceref dbuf_reg_13_)) - (portref D (instanceref upg_dat_o_reg_13_)) - (portref Q (instanceref dbuf_reg_5_)) - ) - ) - (net (rename dbuf_6_ "dbuf[6]") (joined - (portref D (instanceref dbuf_reg_14_)) - (portref D (instanceref upg_dat_o_reg_14_)) - (portref Q (instanceref dbuf_reg_6_)) - ) - ) - (net (rename dbuf_7_ "dbuf[7]") (joined - (portref D (instanceref dbuf_reg_15_)) - (portref D (instanceref upg_dat_o_reg_15_)) - (portref Q (instanceref dbuf_reg_7_)) - ) - ) - (net (rename dbuf_8_ "dbuf[8]") (joined - (portref D (instanceref dbuf_reg_16_)) - (portref D (instanceref upg_dat_o_reg_16_)) - (portref Q (instanceref dbuf_reg_8_)) - ) - ) - (net (rename dbuf_9_ "dbuf[9]") (joined - (portref D (instanceref dbuf_reg_17_)) - (portref D (instanceref upg_dat_o_reg_17_)) - (portref Q (instanceref dbuf_reg_9_)) - ) - ) - (net disp1 (joined - (portref I2 (instanceref disp_6__i_3)) - (portref I2 (instanceref disp_7__i_2)) - (portref I3 (instanceref disp_7__i_3)) - (portref I4 (instanceref disp_1__i_2)) - (portref I5 (instanceref disp_5__i_1)) - (portref I5 (instanceref upg_wen_o_i_5)) - (portref O (instanceref disp_5__i_4)) - ) - ) - (net (rename disp_0__i_1_n_0 "disp[0]_i_1_n_0") (joined - (portref D (instanceref disp_reg_0_)) - (portref O (instanceref disp_0__i_1)) - ) - ) - (net (rename disp_1__i_1_n_0 "disp[1]_i_1_n_0") (joined - (portref D (instanceref disp_reg_1_)) - (portref O (instanceref disp_1__i_1)) - ) - ) - (net (rename disp_1__i_2_n_0 "disp[1]_i_2_n_0") (joined - (portref I0 (instanceref disp_1__i_1)) - (portref I0 (instanceref disp_2__i_2)) - (portref O (instanceref disp_1__i_2)) - ) - ) - (net (rename disp_1__i_3_n_0 "disp[1]_i_3_n_0") (joined - (portref I0 (instanceref disp_0__i_1)) - (portref I1 (instanceref disp_1__i_1)) - (portref I1 (instanceref disp_2__i_2)) - (portref O (instanceref disp_1__i_3)) - ) - ) - (net (rename disp_2__i_1_n_0 "disp[2]_i_1_n_0") (joined - (portref D (instanceref disp_reg_2_)) - (portref O (instanceref disp_2__i_1)) - ) - ) - (net (rename disp_2__i_2_n_0 "disp[2]_i_2_n_0") (joined - (portref I0 (instanceref upg_adr_o_14__i_1)) - (portref I1 (instanceref disp_2__i_1)) - (portref I1 (instanceref upg_wen_o_i_2)) - (portref I3 (instanceref upg_wen_o_i_1)) - (portref O (instanceref disp_2__i_2)) - ) - ) - (net (rename disp_3__i_1_n_0 "disp[3]_i_1_n_0") (joined - (portref D (instanceref disp_reg_3_)) - (portref O (instanceref disp_3__i_1)) - ) - ) - (net (rename disp_3__i_2_n_0 "disp[3]_i_2_n_0") (joined - (portref I1 (instanceref disp_3__i_1)) - (portref O (instanceref disp_3__i_2)) - ) - ) - (net (rename disp_4__i_1_n_0 "disp[4]_i_1_n_0") (joined - (portref D (instanceref disp_reg_4_)) - (portref O (instanceref disp_4__i_1)) - ) - ) - (net (rename disp_5__i_1_n_0 "disp[5]_i_1_n_0") (joined - (portref D (instanceref disp_reg_5_)) - (portref O (instanceref disp_5__i_1)) - ) - ) - (net (rename disp_5__i_2_n_0 "disp[5]_i_2_n_0") (joined - (portref I0 (instanceref disp_5__i_1)) - (portref I0 (instanceref disp_7__i_3)) - (portref O (instanceref disp_5__i_2)) - ) - ) - (net (rename disp_5__i_3_n_0 "disp[5]_i_3_n_0") (joined - (portref I1 (instanceref disp_4__i_1)) - (portref I1 (instanceref disp_5__i_1)) - (portref O (instanceref disp_5__i_3)) - ) - ) - (net (rename disp_6__i_1_n_0 "disp[6]_i_1_n_0") (joined - (portref D (instanceref disp_reg_6_)) - (portref O (instanceref disp_6__i_1)) - ) - ) - (net (rename disp_6__i_2_n_0 "disp[6]_i_2_n_0") (joined - (portref I0 (instanceref disp_2__i_1)) - (portref I2 (instanceref disp_6__i_1)) - (portref O (instanceref disp_6__i_2)) - ) - ) - (net (rename disp_6__i_3_n_0 "disp[6]_i_3_n_0") (joined - (portref I1 (instanceref disp_5__i_3)) - (portref I2 (instanceref disp_6__i_2)) - (portref I3 (instanceref disp_3__i_2)) - (portref O (instanceref disp_6__i_3)) - ) - ) - (net (rename disp_7__i_1_n_0 "disp[7]_i_1_n_0") (joined - (portref D (instanceref disp_reg_7_)) - (portref O (instanceref disp_7__i_1)) - ) - ) - (net (rename disp_7__i_2_n_0 "disp[7]_i_2_n_0") (joined - (portref I3 (instanceref disp_7__i_1)) - (portref I5 (instanceref disp_6__i_1)) - (portref O (instanceref disp_7__i_2)) - ) - ) - (net (rename disp_7__i_3_n_0 "disp[7]_i_3_n_0") (joined - (portref I1 (instanceref disp_7__i_2)) - (portref O (instanceref disp_7__i_3)) - ) - ) - (net (rename disp_7__i_4_n_0 "disp[7]_i_4_n_0") (joined - (portref I1 (instanceref disp_7__i_3)) - (portref O (instanceref disp_7__i_4)) - ) - ) - (net (rename disp_reg_n_0__0_ "disp_reg_n_0_[0]") (joined - (portref I1 (instanceref disp_6__i_3)) - (portref I1 (instanceref upg_wen_o_i_3)) - (portref I1 (instanceref upg_wen_o_i_5)) - (portref I2 (instanceref disp_1__i_2)) - (portref I2 (instanceref upg_clk_o_OBUF_inst_i_1)) - (portref I4 (instanceref disp_7__i_3)) - (portref I5 (instanceref disp_1__i_3)) - (portref Q (instanceref disp_reg_0_)) - ) - ) - (net (rename disp_reg_n_0__1_ "disp_reg_n_0_[1]") (joined - (portref I0 (instanceref disp_6__i_3)) - (portref I0 (instanceref upg_clk_o_OBUF_inst_i_1)) - (portref I2 (instanceref upg_wen_o_i_5)) - (portref I5 (instanceref disp_1__i_2)) - (portref I5 (instanceref disp_7__i_3)) - (portref Q (instanceref disp_reg_1_)) - ) - ) - (net (rename disp_reg_n_0__2_ "disp_reg_n_0_[2]") (joined - (portref I0 (instanceref disp_3__i_2)) - (portref I1 (instanceref upg_clk_o_OBUF_inst_i_2)) - (portref I2 (instanceref upg_wen_o_i_4)) - (portref I3 (instanceref disp_7__i_2)) - (portref I4 (instanceref disp_2__i_1)) - (portref I4 (instanceref disp_5__i_3)) - (portref Q (instanceref disp_reg_2_)) - ) - ) - (net (rename disp_reg_n_0__3_ "disp_reg_n_0_[3]") (joined - (portref I0 (instanceref disp_5__i_3)) - (portref I0 (instanceref disp_7__i_2)) - (portref I3 (instanceref disp_3__i_1)) - (portref I3 (instanceref upg_clk_o_OBUF_inst_i_2)) - (portref I3 (instanceref upg_wen_o_i_4)) - (portref Q (instanceref disp_reg_3_)) - ) - ) - (net (rename disp_reg_n_0__4_ "disp_reg_n_0_[4]") (joined - (portref I1 (instanceref upg_wen_o_i_6)) - (portref I2 (instanceref disp_5__i_1)) - (portref I2 (instanceref upg_clk_o_OBUF_inst_i_2)) - (portref I3 (instanceref disp_4__i_1)) - (portref I4 (instanceref disp_7__i_2)) - (portref Q (instanceref disp_reg_4_)) - ) - ) - (net (rename disp_reg_n_0__5_ "disp_reg_n_0_[5]") (joined - (portref I0 (instanceref upg_clk_o_OBUF_inst_i_2)) - (portref I4 (instanceref disp_5__i_1)) - (portref I5 (instanceref disp_7__i_2)) - (portref I5 (instanceref upg_wen_o_i_6)) - (portref Q (instanceref disp_reg_5_)) - ) - ) - (net (rename disp_reg_n_0__6_ "disp_reg_n_0_[6]") (joined - (portref I0 (instanceref disp_1__i_2)) - (portref I0 (instanceref disp_1__i_3)) - (portref I0 (instanceref disp_7__i_4)) - (portref I2 (instanceref upg_wen_o_i_6)) - (portref I3 (instanceref disp_6__i_1)) - (portref I3 (instanceref upg_wen_o_i_3)) - (portref I4 (instanceref upg_clk_o_OBUF_inst_i_1)) - (portref I4 (instanceref upg_wen_o_i_5)) - (portref I5 (instanceref disp_6__i_3)) - (portref I5 (instanceref disp_7__i_1)) - (portref Q (instanceref disp_reg_6_)) - ) - ) - (net (rename disp_reg_n_0__7_ "disp_reg_n_0_[7]") (joined - (portref I0 (instanceref upg_wen_o_i_6)) - (portref I1 (instanceref disp_1__i_2)) - (portref I1 (instanceref disp_1__i_3)) - (portref I1 (instanceref disp_7__i_4)) - (portref I2 (instanceref disp_7__i_1)) - (portref I2 (instanceref upg_wen_o_i_3)) - (portref I3 (instanceref upg_clk_o_OBUF_inst_i_1)) - (portref I3 (instanceref upg_wen_o_i_5)) - (portref I4 (instanceref disp_6__i_3)) - (portref Q (instanceref disp_reg_7_)) - ) - ) - (net (rename hex0_10_ "hex0[10]") (joined - (portref D (instanceref byte_num_reg_10_)) - (portref I1 (instanceref bn_ascii_18__i_1)) - (portref I1 (instanceref bn_ascii_19__i_1)) - (portref I1 (instanceref bn_ascii_21__i_1)) - (portref I1 (instanceref bn_ascii_22__i_1)) - (portref I2 (instanceref bn_ascii_16__i_1)) - (portref I2 (instanceref bn_ascii_17__i_1)) - (portref I2 (instanceref recv_done_i_36)) - (portref I3 (instanceref recv_done_i_32)) - (portref Q (instanceref byte_num_reg_2_)) - ) - ) - (net (rename hex0_11_ "hex0[11]") (joined - (portref D (instanceref byte_num_reg_11_)) - (portref I0 (instanceref bn_ascii_19__i_1)) - (portref I0 (instanceref bn_ascii_22__i_1)) - (portref I0 (instanceref recv_done_i_36)) - (portref I1 (instanceref bn_ascii_17__i_1)) - (portref I1 (instanceref recv_done_i_32)) - (portref I2 (instanceref bn_ascii_18__i_1)) - (portref I2 (instanceref bn_ascii_21__i_1)) - (portref I3 (instanceref bn_ascii_16__i_1)) - (portref Q (instanceref byte_num_reg_3_)) - ) - ) - (net (rename hex0_12_ "hex0[12]") (joined - (portref D (instanceref byte_num_reg_12_)) - (portref I0 (instanceref bn_ascii_24__i_1)) - (portref I0 (instanceref bn_ascii_25__i_1)) - (portref I2 (instanceref recv_done_i_35)) - (portref I3 (instanceref bn_ascii_26__i_1)) - (portref I3 (instanceref recv_done_i_31)) - (portref Q (instanceref byte_num_reg_4_)) - ) - ) - (net (rename hex0_13_ "hex0[13]") (joined - (portref D (instanceref byte_num_reg_13_)) - (portref I0 (instanceref bn_ascii_26__i_1)) - (portref I0 (instanceref bn_ascii_29__i_1)) - (portref I0 (instanceref recv_done_i_35)) - (portref I1 (instanceref bn_ascii_24__i_1)) - (portref I1 (instanceref recv_done_i_31)) - (portref I2 (instanceref bn_ascii_27__i_1)) - (portref I2 (instanceref bn_ascii_30__i_1)) - (portref I3 (instanceref bn_ascii_25__i_1)) - (portref Q (instanceref byte_num_reg_5_)) - ) - ) - (net (rename hex0_14_ "hex0[14]") (joined - (portref D (instanceref byte_num_reg_14_)) - (portref I1 (instanceref bn_ascii_26__i_1)) - (portref I1 (instanceref bn_ascii_27__i_1)) - (portref I1 (instanceref bn_ascii_29__i_1)) - (portref I1 (instanceref bn_ascii_30__i_1)) - (portref I2 (instanceref bn_ascii_24__i_1)) - (portref I2 (instanceref bn_ascii_25__i_1)) - (portref I2 (instanceref recv_done_i_34)) - (portref I3 (instanceref recv_done_i_30)) - (portref Q (instanceref byte_num_reg_6_)) - ) - ) - (net (rename hex0_15_ "hex0[15]") (joined - (portref D (instanceref byte_num_reg_15_)) - (portref I0 (instanceref bn_ascii_27__i_1)) - (portref I0 (instanceref bn_ascii_30__i_1)) - (portref I0 (instanceref recv_done_i_34)) - (portref I1 (instanceref bn_ascii_25__i_1)) - (portref I1 (instanceref recv_done_i_30)) - (portref I2 (instanceref bn_ascii_26__i_1)) - (portref I2 (instanceref bn_ascii_29__i_1)) - (portref I3 (instanceref bn_ascii_24__i_1)) - (portref Q (instanceref byte_num_reg_7_)) - ) - ) - (net (rename hex0_16_ "hex0[16]") (joined - (portref D (instanceref byte_num_reg_16_)) - (portref I0 (instanceref bn_ascii_32__i_1)) - (portref I0 (instanceref bn_ascii_33__i_1)) - (portref I2 (instanceref recv_done_i_29)) - (portref I3 (instanceref bn_ascii_34__i_1)) - (portref I3 (instanceref recv_done_i_25)) - (portref Q (instanceref byte_num_reg_8_)) - ) - ) - (net (rename hex0_17_ "hex0[17]") (joined - (portref D (instanceref byte_num_reg_17_)) - (portref I0 (instanceref bn_ascii_34__i_1)) - (portref I0 (instanceref bn_ascii_37__i_1)) - (portref I0 (instanceref recv_done_i_29)) - (portref I1 (instanceref bn_ascii_32__i_1)) - (portref I1 (instanceref recv_done_i_25)) - (portref I2 (instanceref bn_ascii_35__i_1)) - (portref I2 (instanceref bn_ascii_38__i_1)) - (portref I3 (instanceref bn_ascii_33__i_1)) - (portref Q (instanceref byte_num_reg_9_)) - ) - ) - (net (rename hex0_18_ "hex0[18]") (joined - (portref D (instanceref byte_num_reg_18_)) - (portref I1 (instanceref bn_ascii_34__i_1)) - (portref I1 (instanceref bn_ascii_35__i_1)) - (portref I1 (instanceref bn_ascii_37__i_1)) - (portref I1 (instanceref bn_ascii_38__i_1)) - (portref I2 (instanceref bn_ascii_32__i_1)) - (portref I2 (instanceref bn_ascii_33__i_1)) - (portref I2 (instanceref recv_done_i_28)) - (portref I3 (instanceref recv_done_i_24)) - (portref Q (instanceref byte_num_reg_10_)) - ) - ) - (net (rename hex0_19_ "hex0[19]") (joined - (portref D (instanceref byte_num_reg_19_)) - (portref I0 (instanceref bn_ascii_35__i_1)) - (portref I0 (instanceref bn_ascii_38__i_1)) - (portref I0 (instanceref recv_done_i_28)) - (portref I1 (instanceref bn_ascii_33__i_1)) - (portref I1 (instanceref recv_done_i_24)) - (portref I2 (instanceref bn_ascii_34__i_1)) - (portref I2 (instanceref bn_ascii_37__i_1)) - (portref I3 (instanceref bn_ascii_32__i_1)) - (portref Q (instanceref byte_num_reg_11_)) - ) - ) - (net (rename hex0_20_ "hex0[20]") (joined - (portref D (instanceref byte_num_reg_20_)) - (portref I0 (instanceref bn_ascii_40__i_1)) - (portref I0 (instanceref bn_ascii_41__i_1)) - (portref I2 (instanceref recv_done_i_27)) - (portref I3 (instanceref bn_ascii_42__i_1)) - (portref I3 (instanceref recv_done_i_23)) - (portref Q (instanceref byte_num_reg_12_)) - ) - ) - (net (rename hex0_21_ "hex0[21]") (joined - (portref D (instanceref byte_num_reg_21_)) - (portref I0 (instanceref bn_ascii_42__i_1)) - (portref I0 (instanceref bn_ascii_45__i_1)) - (portref I0 (instanceref recv_done_i_27)) - (portref I1 (instanceref bn_ascii_40__i_1)) - (portref I1 (instanceref recv_done_i_23)) - (portref I2 (instanceref bn_ascii_43__i_1)) - (portref I2 (instanceref bn_ascii_46__i_1)) - (portref I3 (instanceref bn_ascii_41__i_1)) - (portref Q (instanceref byte_num_reg_13_)) - ) - ) - (net (rename hex0_22_ "hex0[22]") (joined - (portref D (instanceref byte_num_reg_22_)) - (portref I1 (instanceref bn_ascii_42__i_1)) - (portref I1 (instanceref bn_ascii_43__i_1)) - (portref I1 (instanceref bn_ascii_45__i_1)) - (portref I1 (instanceref bn_ascii_46__i_1)) - (portref I2 (instanceref bn_ascii_40__i_1)) - (portref I2 (instanceref bn_ascii_41__i_1)) - (portref I2 (instanceref recv_done_i_26)) - (portref I3 (instanceref recv_done_i_22)) - (portref Q (instanceref byte_num_reg_14_)) - ) - ) - (net (rename hex0_23_ "hex0[23]") (joined - (portref D (instanceref byte_num_reg_23_)) - (portref I0 (instanceref bn_ascii_43__i_1)) - (portref I0 (instanceref bn_ascii_46__i_1)) - (portref I0 (instanceref recv_done_i_26)) - (portref I1 (instanceref bn_ascii_41__i_1)) - (portref I1 (instanceref recv_done_i_22)) - (portref I2 (instanceref bn_ascii_42__i_1)) - (portref I2 (instanceref bn_ascii_45__i_1)) - (portref I3 (instanceref bn_ascii_40__i_1)) - (portref Q (instanceref byte_num_reg_15_)) - ) - ) - (net (rename hex0_24_ "hex0[24]") (joined - (portref D (instanceref byte_num_reg_24_)) - (portref I0 (instanceref bn_ascii_48__i_1)) - (portref I0 (instanceref bn_ascii_49__i_1)) - (portref I2 (instanceref recv_done_i_20)) - (portref I3 (instanceref bn_ascii_50__i_1)) - (portref I3 (instanceref recv_done_i_16)) - (portref Q (instanceref byte_num_reg_16_)) - ) - ) - (net (rename hex0_25_ "hex0[25]") (joined - (portref D (instanceref byte_num_reg_25_)) - (portref I0 (instanceref bn_ascii_50__i_1)) - (portref I0 (instanceref bn_ascii_53__i_1)) - (portref I0 (instanceref recv_done_i_20)) - (portref I1 (instanceref bn_ascii_48__i_1)) - (portref I1 (instanceref recv_done_i_16)) - (portref I2 (instanceref bn_ascii_51__i_1)) - (portref I2 (instanceref bn_ascii_54__i_1)) - (portref I3 (instanceref bn_ascii_49__i_1)) - (portref Q (instanceref byte_num_reg_17_)) - ) - ) - (net (rename hex0_26_ "hex0[26]") (joined - (portref D (instanceref byte_num_reg_26_)) - (portref I1 (instanceref bn_ascii_50__i_1)) - (portref I1 (instanceref bn_ascii_51__i_1)) - (portref I1 (instanceref bn_ascii_53__i_1)) - (portref I1 (instanceref bn_ascii_54__i_1)) - (portref I2 (instanceref bn_ascii_48__i_1)) - (portref I2 (instanceref bn_ascii_49__i_1)) - (portref I2 (instanceref recv_done_i_19)) - (portref I3 (instanceref recv_done_i_15)) - (portref Q (instanceref byte_num_reg_18_)) - ) - ) - (net (rename hex0_27_ "hex0[27]") (joined - (portref D (instanceref byte_num_reg_27_)) - (portref I0 (instanceref bn_ascii_51__i_1)) - (portref I0 (instanceref bn_ascii_54__i_1)) - (portref I0 (instanceref recv_done_i_19)) - (portref I1 (instanceref bn_ascii_49__i_1)) - (portref I1 (instanceref recv_done_i_15)) - (portref I2 (instanceref bn_ascii_50__i_1)) - (portref I2 (instanceref bn_ascii_53__i_1)) - (portref I3 (instanceref bn_ascii_48__i_1)) - (portref Q (instanceref byte_num_reg_19_)) - ) - ) - (net (rename hex0_28_ "hex0[28]") (joined - (portref D (instanceref byte_num_reg_28_)) - (portref I0 (instanceref bn_ascii_56__i_1)) - (portref I0 (instanceref bn_ascii_57__i_1)) - (portref I2 (instanceref recv_done_i_18)) - (portref I3 (instanceref bn_ascii_58__i_1)) - (portref I3 (instanceref recv_done_i_14)) - (portref Q (instanceref byte_num_reg_20_)) - ) - ) - (net (rename hex0_29_ "hex0[29]") (joined - (portref D (instanceref byte_num_reg_29_)) - (portref I0 (instanceref bn_ascii_58__i_1)) - (portref I0 (instanceref bn_ascii_61__i_1)) - (portref I0 (instanceref recv_done_i_18)) - (portref I1 (instanceref bn_ascii_56__i_1)) - (portref I1 (instanceref recv_done_i_14)) - (portref I2 (instanceref bn_ascii_59__i_1)) - (portref I2 (instanceref bn_ascii_62__i_2)) - (portref I3 (instanceref bn_ascii_57__i_1)) - (portref Q (instanceref byte_num_reg_21_)) - ) - ) - (net (rename hex0_30_ "hex0[30]") (joined - (portref D (instanceref byte_num_reg_30_)) - (portref I1 (instanceref bn_ascii_58__i_1)) - (portref I1 (instanceref bn_ascii_59__i_1)) - (portref I1 (instanceref bn_ascii_61__i_1)) - (portref I1 (instanceref bn_ascii_62__i_2)) - (portref I2 (instanceref bn_ascii_56__i_1)) - (portref I2 (instanceref bn_ascii_57__i_1)) - (portref I2 (instanceref recv_done_i_17)) - (portref I3 (instanceref recv_done_i_13)) - (portref Q (instanceref byte_num_reg_22_)) - ) - ) - (net (rename hex0_31_ "hex0[31]") (joined - (portref D (instanceref byte_num_reg_31_)) - (portref I0 (instanceref bn_ascii_59__i_1)) - (portref I0 (instanceref bn_ascii_62__i_2)) - (portref I0 (instanceref recv_done_i_17)) - (portref I1 (instanceref bn_ascii_57__i_1)) - (portref I1 (instanceref recv_done_i_13)) - (portref I2 (instanceref bn_ascii_58__i_1)) - (portref I2 (instanceref bn_ascii_61__i_1)) - (portref I3 (instanceref bn_ascii_56__i_1)) - (portref Q (instanceref byte_num_reg_23_)) - ) - ) - (net (rename hex0_8_ "hex0[8]") (joined - (portref D (instanceref byte_num_reg_8_)) - (portref I0 (instanceref bn_ascii_16__i_1)) - (portref I0 (instanceref bn_ascii_17__i_1)) - (portref I0 (instanceref recv_done_i_37)) - (portref I3 (instanceref bn_ascii_18__i_1)) - (portref I3 (instanceref recv_done_i_33)) - (portref Q (instanceref byte_num_reg_0_)) - ) - ) - (net (rename hex0_9_ "hex0[9]") (joined - (portref D (instanceref byte_num_reg_9_)) - (portref I0 (instanceref bn_ascii_18__i_1)) - (portref I0 (instanceref bn_ascii_21__i_1)) - (portref I1 (instanceref bn_ascii_16__i_1)) - (portref I1 (instanceref recv_done_i_33)) - (portref I2 (instanceref bn_ascii_19__i_1)) - (portref I2 (instanceref bn_ascii_22__i_1)) - (portref I2 (instanceref recv_done_i_37)) - (portref I3 (instanceref bn_ascii_17__i_1)) - (portref Q (instanceref byte_num_reg_1_)) - ) - ) - (net (rename hex2ascii_return0_0_ "hex2ascii_return0[0]") (joined - (portref D (instanceref bn_ascii_reg_56_)) - (portref O (instanceref bn_ascii_56__i_1)) - ) - ) - (net (rename hex2ascii_return0_1_ "hex2ascii_return0[1]") (joined - (portref D (instanceref bn_ascii_reg_57_)) - (portref O (instanceref bn_ascii_57__i_1)) - ) - ) - (net (rename hex2ascii_return0_2_ "hex2ascii_return0[2]") (joined - (portref D (instanceref bn_ascii_reg_58_)) - (portref O (instanceref bn_ascii_58__i_1)) - ) - ) - (net (rename hex2ascii_return0_3_ "hex2ascii_return0[3]") (joined - (portref D (instanceref bn_ascii_reg_59_)) - (portref O (instanceref bn_ascii_59__i_1)) - ) - ) - (net (rename hex2ascii_return0_5_ "hex2ascii_return0[5]") (joined - (portref D (instanceref bn_ascii_reg_61_)) - (portref O (instanceref bn_ascii_61__i_1)) - ) - ) - (net (rename hex2ascii_return0_6_ "hex2ascii_return0[6]") (joined - (portref D (instanceref bn_ascii_reg_62_)) - (portref O (instanceref bn_ascii_62__i_2)) - ) - ) - (net (rename hex2ascii_return_0_ "hex2ascii_return[0]") (joined - (portref D (instanceref bn_ascii_reg_0_)) - (portref O (instanceref bn_ascii_0__i_1)) - ) - ) - (net (rename hex2ascii_return_10_ "hex2ascii_return[10]") (joined - (portref D (instanceref bn_ascii_reg_10_)) - (portref O (instanceref bn_ascii_10__i_1)) - ) - ) - (net (rename hex2ascii_return_11_ "hex2ascii_return[11]") (joined - (portref D (instanceref bn_ascii_reg_11_)) - (portref O (instanceref bn_ascii_11__i_1)) - ) - ) - (net (rename hex2ascii_return_13_ "hex2ascii_return[13]") (joined - (portref D (instanceref bn_ascii_reg_13_)) - (portref O (instanceref bn_ascii_13__i_1)) - ) - ) - (net (rename hex2ascii_return_14_ "hex2ascii_return[14]") (joined - (portref D (instanceref bn_ascii_reg_14_)) - (portref O (instanceref bn_ascii_14__i_1)) - ) - ) - (net (rename hex2ascii_return_16_ "hex2ascii_return[16]") (joined - (portref D (instanceref bn_ascii_reg_16_)) - (portref O (instanceref bn_ascii_16__i_1)) - ) - ) - (net (rename hex2ascii_return_17_ "hex2ascii_return[17]") (joined - (portref D (instanceref bn_ascii_reg_17_)) - (portref O (instanceref bn_ascii_17__i_1)) - ) - ) - (net (rename hex2ascii_return_18_ "hex2ascii_return[18]") (joined - (portref D (instanceref bn_ascii_reg_18_)) - (portref O (instanceref bn_ascii_18__i_1)) - ) - ) - (net (rename hex2ascii_return_19_ "hex2ascii_return[19]") (joined - (portref D (instanceref bn_ascii_reg_19_)) - (portref O (instanceref bn_ascii_19__i_1)) - ) - ) - (net (rename hex2ascii_return_1_ "hex2ascii_return[1]") (joined - (portref D (instanceref bn_ascii_reg_1_)) - (portref O (instanceref bn_ascii_1__i_1)) - ) - ) - (net (rename hex2ascii_return_21_ "hex2ascii_return[21]") (joined - (portref D (instanceref bn_ascii_reg_21_)) - (portref O (instanceref bn_ascii_21__i_1)) - ) - ) - (net (rename hex2ascii_return_22_ "hex2ascii_return[22]") (joined - (portref D (instanceref bn_ascii_reg_22_)) - (portref O (instanceref bn_ascii_22__i_1)) - ) - ) - (net (rename hex2ascii_return_24_ "hex2ascii_return[24]") (joined - (portref D (instanceref bn_ascii_reg_24_)) - (portref O (instanceref bn_ascii_24__i_1)) - ) - ) - (net (rename hex2ascii_return_25_ "hex2ascii_return[25]") (joined - (portref D (instanceref bn_ascii_reg_25_)) - (portref O (instanceref bn_ascii_25__i_1)) - ) - ) - (net (rename hex2ascii_return_26_ "hex2ascii_return[26]") (joined - (portref D (instanceref bn_ascii_reg_26_)) - (portref O (instanceref bn_ascii_26__i_1)) - ) - ) - (net (rename hex2ascii_return_27_ "hex2ascii_return[27]") (joined - (portref D (instanceref bn_ascii_reg_27_)) - (portref O (instanceref bn_ascii_27__i_1)) - ) - ) - (net (rename hex2ascii_return_29_ "hex2ascii_return[29]") (joined - (portref D (instanceref bn_ascii_reg_29_)) - (portref O (instanceref bn_ascii_29__i_1)) - ) - ) - (net (rename hex2ascii_return_2_ "hex2ascii_return[2]") (joined - (portref D (instanceref bn_ascii_reg_2_)) - (portref O (instanceref bn_ascii_2__i_1)) - ) - ) - (net (rename hex2ascii_return_30_ "hex2ascii_return[30]") (joined - (portref D (instanceref bn_ascii_reg_30_)) - (portref O (instanceref bn_ascii_30__i_1)) - ) - ) - (net (rename hex2ascii_return_32_ "hex2ascii_return[32]") (joined - (portref D (instanceref bn_ascii_reg_32_)) - (portref O (instanceref bn_ascii_32__i_1)) - ) - ) - (net (rename hex2ascii_return_33_ "hex2ascii_return[33]") (joined - (portref D (instanceref bn_ascii_reg_33_)) - (portref O (instanceref bn_ascii_33__i_1)) - ) - ) - (net (rename hex2ascii_return_34_ "hex2ascii_return[34]") (joined - (portref D (instanceref bn_ascii_reg_34_)) - (portref O (instanceref bn_ascii_34__i_1)) - ) - ) - (net (rename hex2ascii_return_35_ "hex2ascii_return[35]") (joined - (portref D (instanceref bn_ascii_reg_35_)) - (portref O (instanceref bn_ascii_35__i_1)) - ) - ) - (net (rename hex2ascii_return_37_ "hex2ascii_return[37]") (joined - (portref D (instanceref bn_ascii_reg_37_)) - (portref O (instanceref bn_ascii_37__i_1)) - ) - ) - (net (rename hex2ascii_return_38_ "hex2ascii_return[38]") (joined - (portref D (instanceref bn_ascii_reg_38_)) - (portref O (instanceref bn_ascii_38__i_1)) - ) - ) - (net (rename hex2ascii_return_3_ "hex2ascii_return[3]") (joined - (portref D (instanceref bn_ascii_reg_3_)) - (portref O (instanceref bn_ascii_3__i_1)) - ) - ) - (net (rename hex2ascii_return_40_ "hex2ascii_return[40]") (joined - (portref D (instanceref bn_ascii_reg_40_)) - (portref O (instanceref bn_ascii_40__i_1)) - ) - ) - (net (rename hex2ascii_return_41_ "hex2ascii_return[41]") (joined - (portref D (instanceref bn_ascii_reg_41_)) - (portref O (instanceref bn_ascii_41__i_1)) - ) - ) - (net (rename hex2ascii_return_42_ "hex2ascii_return[42]") (joined - (portref D (instanceref bn_ascii_reg_42_)) - (portref O (instanceref bn_ascii_42__i_1)) - ) - ) - (net (rename hex2ascii_return_43_ "hex2ascii_return[43]") (joined - (portref D (instanceref bn_ascii_reg_43_)) - (portref O (instanceref bn_ascii_43__i_1)) - ) - ) - (net (rename hex2ascii_return_45_ "hex2ascii_return[45]") (joined - (portref D (instanceref bn_ascii_reg_45_)) - (portref O (instanceref bn_ascii_45__i_1)) - ) - ) - (net (rename hex2ascii_return_46_ "hex2ascii_return[46]") (joined - (portref D (instanceref bn_ascii_reg_46_)) - (portref O (instanceref bn_ascii_46__i_1)) - ) - ) - (net (rename hex2ascii_return_48_ "hex2ascii_return[48]") (joined - (portref D (instanceref bn_ascii_reg_48_)) - (portref O (instanceref bn_ascii_48__i_1)) - ) - ) - (net (rename hex2ascii_return_49_ "hex2ascii_return[49]") (joined - (portref D (instanceref bn_ascii_reg_49_)) - (portref O (instanceref bn_ascii_49__i_1)) - ) - ) - (net (rename hex2ascii_return_50_ "hex2ascii_return[50]") (joined - (portref D (instanceref bn_ascii_reg_50_)) - (portref O (instanceref bn_ascii_50__i_1)) - ) - ) - (net (rename hex2ascii_return_51_ "hex2ascii_return[51]") (joined - (portref D (instanceref bn_ascii_reg_51_)) - (portref O (instanceref bn_ascii_51__i_1)) - ) - ) - (net (rename hex2ascii_return_53_ "hex2ascii_return[53]") (joined - (portref D (instanceref bn_ascii_reg_53_)) - (portref O (instanceref bn_ascii_53__i_1)) - ) - ) - (net (rename hex2ascii_return_54_ "hex2ascii_return[54]") (joined - (portref D (instanceref bn_ascii_reg_54_)) - (portref O (instanceref bn_ascii_54__i_1)) - ) - ) - (net (rename hex2ascii_return_5_ "hex2ascii_return[5]") (joined - (portref D (instanceref bn_ascii_reg_5_)) - (portref O (instanceref bn_ascii_5__i_1)) - ) - ) - (net (rename hex2ascii_return_6_ "hex2ascii_return[6]") (joined - (portref D (instanceref bn_ascii_reg_6_)) - (portref O (instanceref bn_ascii_6__i_1)) - ) - ) - (net (rename hex2ascii_return_8_ "hex2ascii_return[8]") (joined - (portref D (instanceref bn_ascii_reg_8_)) - (portref O (instanceref bn_ascii_8__i_1)) - ) - ) - (net (rename hex2ascii_return_9_ "hex2ascii_return[9]") (joined - (portref D (instanceref bn_ascii_reg_9_)) - (portref O (instanceref bn_ascii_9__i_1)) - ) - ) - (net initFlag (joined - (portref I0 (instanceref WCS_0__i_2)) - (portref I0 (instanceref initFlag_i_1)) - (portref I0 (instanceref s_axi_awaddr_3__i_1)) - (portref I2 (instanceref s_axi_awvalid_i_1)) - (portref I4 (instanceref s_axi_wdata_4__i_1)) - (portref I4 (instanceref s_axi_wdata_4__i_2)) - (portref I4 (instanceref s_axi_wdata_6__i_1)) - (portref I4 (instanceref s_axi_wstrb_3__i_1)) - (portref I5 (instanceref s_axi_wdata_0__i_1)) - (portref I5 (instanceref s_axi_wdata_1__i_1)) - (portref Q (instanceref initFlag_reg)) - ) - ) - (net initFlag_i_1_n_0 (joined - (portref D (instanceref initFlag_reg)) - (portref O (instanceref initFlag_i_1)) - ) - ) - (net (rename len_cnt_0__i_1_n_0 "len_cnt[0]_i_1_n_0") (joined - (portref D (instanceref len_cnt_reg_0_)) - (portref O (instanceref len_cnt_0__i_1)) - ) - ) - (net (rename len_cnt_1__i_1_n_0 "len_cnt[1]_i_1_n_0") (joined - (portref D (instanceref len_cnt_reg_1_)) - (portref O (instanceref len_cnt_1__i_1)) - ) - ) - (net (rename len_cnt_2__i_1_n_0 "len_cnt[2]_i_1_n_0") (joined - (portref D (instanceref len_cnt_reg_2_)) - (portref O (instanceref len_cnt_2__i_1)) - ) - ) - (net (rename len_cnt_3__i_1_n_0 "len_cnt[3]_i_1_n_0") (joined - (portref D (instanceref len_cnt_reg_3_)) - (portref O (instanceref len_cnt_3__i_1)) - ) - ) - (net (rename len_cnt_reg__0_0_ "len_cnt_reg__0[0]") (joined - (portref I0 (instanceref len_cnt_0__i_1)) - (portref I0 (instanceref len_cnt_1__i_1)) - (portref I1 (instanceref len_cnt_3__i_1)) - (portref I1 (instanceref wr_byte_num_done_i_1)) - (portref I2 (instanceref len_cnt_2__i_1)) - (portref I4 (instanceref wr_byte_num_done_i_2)) - (portref I5 (instanceref wr_byte_num_done_i_3)) - (portref Q (instanceref len_cnt_reg_0_)) - ) - ) - (net (rename len_cnt_reg__0_1_ "len_cnt_reg__0[1]") (joined - (portref I1 (instanceref len_cnt_1__i_1)) - (portref I1 (instanceref len_cnt_2__i_1)) - (portref I2 (instanceref len_cnt_3__i_1)) - (portref I2 (instanceref wr_byte_num_done_i_1)) - (portref I3 (instanceref wr_byte_num_done_i_2)) - (portref Q (instanceref len_cnt_reg_1_)) - ) - ) - (net (rename len_cnt_reg__0_2_ "len_cnt_reg__0[2]") (joined - (portref I0 (instanceref len_cnt_2__i_1)) - (portref I0 (instanceref wr_byte_num_done_i_2)) - (portref I3 (instanceref len_cnt_3__i_1)) - (portref I3 (instanceref wr_byte_num_done_i_1)) - (portref Q (instanceref len_cnt_reg_2_)) - ) - ) - (net (rename len_cnt_reg__0_3_ "len_cnt_reg__0[3]") (joined - (portref I0 (instanceref len_cnt_3__i_1)) - (portref I0 (instanceref wr_byte_num_done_i_1)) - (portref Q (instanceref len_cnt_reg_3_)) - ) - ) - (net (rename msg_indx_7__i_1_n_0 "msg_indx[7]_i_1_n_0") (joined - (portref CE (instanceref msg_indx_reg_0_)) - (portref CE (instanceref msg_indx_reg_1_)) - (portref CE (instanceref msg_indx_reg_2_)) - (portref CE (instanceref msg_indx_reg_3_)) - (portref CE (instanceref msg_indx_reg_4_)) - (portref CE (instanceref msg_indx_reg_5_)) - (portref CE (instanceref msg_indx_reg_6_)) - (portref CE (instanceref msg_indx_reg_7_)) - (portref O (instanceref msg_indx_7__i_1)) - ) - ) - (net (rename msg_indx_7__i_3_n_0 "msg_indx[7]_i_3_n_0") (joined - (portref I1 (instanceref msg_indx_6__i_1)) - (portref I1 (instanceref msg_indx_7__i_2)) - (portref O (instanceref msg_indx_7__i_3)) - ) - ) - (net (rename msg_indx_reg__0_0_ "msg_indx_reg__0[0]") (joined - (portref I0 (instanceref msg_indx_0__i_1)) - (portref I0 (instanceref msg_indx_1__i_1)) - (portref I0 (instanceref s_axi_wdata_5__i_2)) - (portref I1 (instanceref s_axi_wdata_0__i_2)) - (portref I1 (instanceref s_axi_wdata_1__i_2)) - (portref I1 (instanceref s_axi_wdata_2__i_2)) - (portref I1 (instanceref s_axi_wdata_2__i_3)) - (portref I1 (instanceref s_axi_wdata_4__i_5)) - (portref I1 (instanceref s_axi_wdata_5__i_6)) - (portref I1 (instanceref s_axi_wdata_6__i_3)) - (portref I2 (instanceref msg_indx_2__i_1)) - (portref I2 (instanceref msg_indx_4__i_1)) - (portref I2 (instanceref msg_indx_7__i_3)) - (portref I2 (instanceref s_axi_wdata_0__i_4)) - (portref I2 (instanceref s_axi_wdata_1__i_5)) - (portref I2 (instanceref s_axi_wdata_2__i_4)) - (portref I2 (instanceref s_axi_wdata_3__i_3)) - (portref I2 (instanceref s_axi_wdata_3__i_4)) - (portref I2 (instanceref s_axi_wdata_4__i_7)) - (portref I2 (instanceref s_axi_wdata_5__i_3)) - (portref I2 (instanceref s_axi_wdata_6__i_4)) - (portref I2 (instanceref s_axi_wdata_6__i_5)) - (portref I2 (instanceref s_axi_wdata_6__i_6)) - (portref I3 (instanceref msg_indx_3__i_1)) - (portref I3 (instanceref msg_indx_5__i_1)) - (portref I3 (instanceref s_axi_wdata_6__i_7)) - (portref I4 (instanceref s_axi_wdata_0__i_5)) - (portref I4 (instanceref s_axi_wdata_1__i_6)) - (portref I4 (instanceref s_axi_wdata_2__i_5)) - (portref I4 (instanceref s_axi_wdata_3__i_2)) - (portref I4 (instanceref s_axi_wdata_3__i_5)) - (portref I4 (instanceref s_axi_wdata_5__i_5)) - (portref Q (instanceref msg_indx_reg_0_)) - ) - ) - (net (rename msg_indx_reg__0_1_ "msg_indx_reg__0[1]") (joined - (portref I0 (instanceref msg_indx_7__i_3)) - (portref I0 (instanceref s_axi_wdata_0__i_2)) - (portref I0 (instanceref s_axi_wdata_1__i_2)) - (portref I0 (instanceref s_axi_wdata_1__i_5)) - (portref I0 (instanceref s_axi_wdata_2__i_2)) - (portref I0 (instanceref s_axi_wdata_4__i_5)) - (portref I0 (instanceref s_axi_wdata_6__i_3)) - (portref I0 (instanceref s_axi_wdata_6__i_6)) - (portref I1 (instanceref msg_indx_1__i_1)) - (portref I1 (instanceref msg_indx_2__i_1)) - (portref I1 (instanceref msg_indx_3__i_1)) - (portref I1 (instanceref msg_indx_5__i_1)) - (portref I1 (instanceref s_axi_wdata_0__i_4)) - (portref I1 (instanceref s_axi_wdata_2__i_4)) - (portref I1 (instanceref s_axi_wdata_3__i_4)) - (portref I1 (instanceref s_axi_wdata_4__i_4)) - (portref I1 (instanceref s_axi_wdata_4__i_7)) - (portref I1 (instanceref s_axi_wdata_5__i_2)) - (portref I2 (instanceref s_axi_wdata_0__i_5)) - (portref I2 (instanceref s_axi_wdata_1__i_6)) - (portref I2 (instanceref s_axi_wdata_2__i_3)) - (portref I2 (instanceref s_axi_wdata_2__i_5)) - (portref I2 (instanceref s_axi_wdata_3__i_5)) - (portref I2 (instanceref s_axi_wdata_4__i_8)) - (portref I2 (instanceref s_axi_wdata_5__i_5)) - (portref I2 (instanceref s_axi_wdata_6__i_7)) - (portref I3 (instanceref s_axi_wdata_3__i_3)) - (portref I3 (instanceref s_axi_wdata_5__i_3)) - (portref I3 (instanceref s_axi_wdata_5__i_6)) - (portref I3 (instanceref s_axi_wdata_6__i_4)) - (portref I4 (instanceref msg_indx_4__i_1)) - (portref I4 (instanceref s_axi_wdata_6__i_5)) - (portref I4 (instanceref upg_done_o_i_2)) - (portref I5 (instanceref s_axi_wdata_3__i_2)) - (portref Q (instanceref msg_indx_reg_1_)) - ) - ) - (net (rename msg_indx_reg__0_2_ "msg_indx_reg__0[2]") (joined - (portref I0 (instanceref msg_indx_2__i_1)) - (portref I0 (instanceref s_axi_wdata_4__i_7)) - (portref I1 (instanceref msg_indx_7__i_3)) - (portref I1 (instanceref s_axi_wdata_4__i_8)) - (portref I1 (instanceref s_axi_wdata_5__i_4)) - (portref I1 (instanceref s_axi_wdata_6__i_7)) - (portref I2 (instanceref msg_indx_3__i_1)) - (portref I2 (instanceref msg_indx_5__i_1)) - (portref I2 (instanceref s_axi_wdata_0__i_2)) - (portref I2 (instanceref s_axi_wdata_1__i_2)) - (portref I2 (instanceref s_axi_wdata_2__i_2)) - (portref I2 (instanceref s_axi_wdata_4__i_4)) - (portref I2 (instanceref s_axi_wdata_4__i_5)) - (portref I2 (instanceref s_axi_wdata_5__i_2)) - (portref I2 (instanceref s_axi_wdata_6__i_3)) - (portref I3 (instanceref msg_indx_4__i_1)) - (portref I3 (instanceref s_axi_wdata_2__i_3)) - (portref I3 (instanceref s_axi_wdata_3__i_2)) - (portref I3 (instanceref upg_done_o_i_2)) - (portref I4 (instanceref s_axi_wdata_0__i_4)) - (portref I4 (instanceref s_axi_wdata_2__i_4)) - (portref I4 (instanceref s_axi_wdata_3__i_3)) - (portref I4 (instanceref s_axi_wdata_3__i_4)) - (portref I4 (instanceref s_axi_wdata_5__i_3)) - (portref I4 (instanceref s_axi_wdata_5__i_6)) - (portref I4 (instanceref s_axi_wdata_6__i_4)) - (portref I4 (instanceref s_axi_wdata_6__i_6)) - (portref I5 (instanceref s_axi_wdata_1__i_5)) - (portref Q (instanceref msg_indx_reg_2_)) - ) - ) - (net (rename msg_indx_reg__0_3_ "msg_indx_reg__0[3]") (joined - (portref I0 (instanceref msg_indx_3__i_1)) - (portref I0 (instanceref s_axi_wdata_4__i_8)) - (portref I0 (instanceref s_axi_wdata_5__i_4)) - (portref I0 (instanceref upg_done_o_i_3)) - (portref I1 (instanceref msg_indx_4__i_1)) - (portref I2 (instanceref s_axi_wdata_3__i_2)) - (portref I3 (instanceref msg_indx_7__i_3)) - (portref I3 (instanceref s_axi_wdata_0__i_2)) - (portref I3 (instanceref s_axi_wdata_2__i_2)) - (portref I3 (instanceref s_axi_wdata_4__i_4)) - (portref I3 (instanceref s_axi_wdata_5__i_2)) - (portref I3 (instanceref s_axi_wdata_6__i_2)) - (portref I4 (instanceref msg_indx_5__i_1)) - (portref I4 (instanceref s_axi_wdata_2__i_1)) - (portref I4 (instanceref s_axi_wdata_3__i_1)) - (portref I4 (instanceref s_axi_wdata_4__i_5)) - (portref I5 (instanceref s_axi_wdata_0__i_3)) - (portref I5 (instanceref s_axi_wdata_1__i_2)) - (portref I5 (instanceref s_axi_wdata_1__i_3)) - (portref I5 (instanceref s_axi_wdata_2__i_3)) - (portref I5 (instanceref s_axi_wdata_3__i_3)) - (portref I5 (instanceref s_axi_wdata_5__i_3)) - (portref I5 (instanceref s_axi_wdata_6__i_3)) - (portref I5 (instanceref s_axi_wdata_6__i_4)) - (portref Q (instanceref msg_indx_reg_3_)) - ) - ) - (net (rename msg_indx_reg__0_4_ "msg_indx_reg__0[4]") (joined - (portref I0 (instanceref msg_indx_4__i_1)) - (portref I1 (instanceref s_axi_wdata_3__i_2)) - (portref I1 (instanceref upg_done_o_i_3)) - (portref I3 (instanceref s_axi_wdata_1__i_4)) - (portref I3 (instanceref s_axi_wdata_4__i_5)) - (portref I4 (instanceref msg_indx_7__i_3)) - (portref I4 (instanceref s_axi_wdata_0__i_2)) - (portref I4 (instanceref s_axi_wdata_1__i_2)) - (portref I4 (instanceref s_axi_wdata_2__i_2)) - (portref I4 (instanceref s_axi_wdata_5__i_2)) - (portref I4 (instanceref s_axi_wdata_6__i_3)) - (portref I5 (instanceref msg_indx_5__i_1)) - (portref Q (instanceref msg_indx_reg_4_)) - ) - ) - (net (rename msg_indx_reg__0_5_ "msg_indx_reg__0[5]") (joined - (portref I0 (instanceref msg_indx_5__i_1)) - (portref I0 (instanceref s_axi_wdata_3__i_2)) - (portref I2 (instanceref s_axi_wdata_1__i_4)) - (portref I2 (instanceref upg_done_o_i_2)) - (portref I3 (instanceref s_axi_wdata_1__i_2)) - (portref I3 (instanceref s_axi_wdata_6__i_3)) - (portref I5 (instanceref msg_indx_7__i_3)) - (portref I5 (instanceref s_axi_wdata_0__i_2)) - (portref I5 (instanceref s_axi_wdata_2__i_2)) - (portref I5 (instanceref s_axi_wdata_4__i_5)) - (portref I5 (instanceref s_axi_wdata_5__i_2)) - (portref Q (instanceref msg_indx_reg_5_)) - ) - ) - (net (rename msg_indx_reg__1_6_ "msg_indx_reg__1[6]") (joined - (portref I0 (instanceref msg_indx_6__i_1)) - (portref I1 (instanceref s_axi_wdata_1__i_4)) - (portref I1 (instanceref upg_done_o_i_2)) - (portref I2 (instanceref msg_indx_7__i_2)) - (portref Q (instanceref msg_indx_reg_6_)) - ) - ) - (net (rename msg_indx_reg__1_7_ "msg_indx_reg__1[7]") (joined - (portref I0 (instanceref msg_indx_7__i_2)) - (portref I0 (instanceref s_axi_wdata_1__i_4)) - (portref I0 (instanceref upg_done_o_i_2)) - (portref Q (instanceref msg_indx_reg_7_)) - ) - ) - (net oldInitF_i_1_n_0 (joined - (portref D (instanceref oldInitF_reg)) - (portref O (instanceref oldInitF_i_1)) - ) - ) - (net oldInitF_reg_n_0 (joined - (portref I1 (instanceref WCS_0__i_2)) - (portref I4 (instanceref oldInitF_i_1)) - (portref Q (instanceref oldInitF_reg)) - ) - ) - (net (rename p_0_in_0_ "p_0_in[0]") (joined - (portref D (instanceref upg_adr_o_reg_0_)) - (portref Q (instanceref byte_cnt_reg_2_)) - (portref (member S 2) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename p_0_in_10_ "p_0_in[10]") (joined - (portref D (instanceref upg_adr_o_reg_10_)) - (portref Q (instanceref byte_cnt_reg_12_)) - (portref (member S 0) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename p_0_in_11_ "p_0_in[11]") (joined - (portref D (instanceref upg_adr_o_reg_11_)) - (portref Q (instanceref byte_cnt_reg_13_)) - (portref (member S 3) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename p_0_in_12_ "p_0_in[12]") (joined - (portref D (instanceref upg_adr_o_reg_12_)) - (portref Q (instanceref byte_cnt_reg_14_)) - (portref (member S 2) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename p_0_in_13_ "p_0_in[13]") (joined - (portref D (instanceref upg_adr_o_reg_13_)) - (portref Q (instanceref byte_cnt_reg_15_)) - (portref (member S 1) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename p_0_in_14_ "p_0_in[14]") (joined - (portref D (instanceref upg_adr_o_reg_14_)) - (portref Q (instanceref byte_cnt_reg_16_)) - (portref (member S 0) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename p_0_in_1_ "p_0_in[1]") (joined - (portref D (instanceref upg_adr_o_reg_1_)) - (portref Q (instanceref byte_cnt_reg_3_)) - (portref (member S 1) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename p_0_in_2_ "p_0_in[2]") (joined - (portref D (instanceref upg_adr_o_reg_2_)) - (portref Q (instanceref byte_cnt_reg_4_)) - (portref (member S 0) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename p_0_in_3_ "p_0_in[3]") (joined - (portref D (instanceref upg_adr_o_reg_3_)) - (portref Q (instanceref byte_cnt_reg_5_)) - (portref (member S 3) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename p_0_in_4_ "p_0_in[4]") (joined - (portref D (instanceref upg_adr_o_reg_4_)) - (portref Q (instanceref byte_cnt_reg_6_)) - (portref (member S 2) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename p_0_in_5_ "p_0_in[5]") (joined - (portref D (instanceref upg_adr_o_reg_5_)) - (portref Q (instanceref byte_cnt_reg_7_)) - (portref (member S 1) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename p_0_in_6_ "p_0_in[6]") (joined - (portref D (instanceref upg_adr_o_reg_6_)) - (portref Q (instanceref byte_cnt_reg_8_)) - (portref (member S 0) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename p_0_in_7_ "p_0_in[7]") (joined - (portref D (instanceref upg_adr_o_reg_7_)) - (portref Q (instanceref byte_cnt_reg_9_)) - (portref (member S 3) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename p_0_in_8_ "p_0_in[8]") (joined - (portref D (instanceref upg_adr_o_reg_8_)) - (portref Q (instanceref byte_cnt_reg_10_)) - (portref (member S 2) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename p_0_in_9_ "p_0_in[9]") (joined - (portref D (instanceref upg_adr_o_reg_9_)) - (portref Q (instanceref byte_cnt_reg_11_)) - (portref (member S 1) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename p_0_in__0_0_ "p_0_in__0[0]") (joined - (portref D (instanceref msg_indx_reg_0_)) - (portref O (instanceref msg_indx_0__i_1)) - ) - ) - (net (rename p_0_in__0_1_ "p_0_in__0[1]") (joined - (portref D (instanceref msg_indx_reg_1_)) - (portref O (instanceref msg_indx_1__i_1)) - ) - ) - (net (rename p_0_in__0_2_ "p_0_in__0[2]") (joined - (portref D (instanceref msg_indx_reg_2_)) - (portref O (instanceref msg_indx_2__i_1)) - ) - ) - (net (rename p_0_in__0_3_ "p_0_in__0[3]") (joined - (portref D (instanceref msg_indx_reg_3_)) - (portref O (instanceref msg_indx_3__i_1)) - ) - ) - (net (rename p_0_in__0_4_ "p_0_in__0[4]") (joined - (portref D (instanceref msg_indx_reg_4_)) - (portref O (instanceref msg_indx_4__i_1)) - ) - ) - (net (rename p_0_in__0_5_ "p_0_in__0[5]") (joined - (portref D (instanceref msg_indx_reg_5_)) - (portref O (instanceref msg_indx_5__i_1)) - ) - ) - (net (rename p_0_in__0_6_ "p_0_in__0[6]") (joined - (portref D (instanceref msg_indx_reg_6_)) - (portref O (instanceref msg_indx_6__i_1)) - ) - ) - (net (rename p_0_in__0_7_ "p_0_in__0[7]") (joined - (portref D (instanceref msg_indx_reg_7_)) - (portref O (instanceref msg_indx_7__i_2)) - ) - ) - (net rdStat (joined - (portref I (instanceref rdStat_BUFG_inst)) - (portref I0 (instanceref s_axi_araddr_3__i_1)) - (portref I0 (instanceref s_axi_arvalid_i_3)) - (portref I2 (instanceref RCS_1__i_1)) - (portref I2 (instanceref statReg_0__i_1)) - (portref I3 (instanceref rdStat_i_1)) - (portref I5 (instanceref uart_rdat_7__i_1)) - (portref Q (instanceref rdStat_reg)) - ) - ) - (net rdStat_BUFG (joined - (portref C (instanceref bn_ascii_reg_0_)) - (portref C (instanceref bn_ascii_reg_10_)) - (portref C (instanceref bn_ascii_reg_11_)) - (portref C (instanceref bn_ascii_reg_13_)) - (portref C (instanceref bn_ascii_reg_14_)) - (portref C (instanceref bn_ascii_reg_16_)) - (portref C (instanceref bn_ascii_reg_17_)) - (portref C (instanceref bn_ascii_reg_18_)) - (portref C (instanceref bn_ascii_reg_19_)) - (portref C (instanceref bn_ascii_reg_1_)) - (portref C (instanceref bn_ascii_reg_21_)) - (portref C (instanceref bn_ascii_reg_22_)) - (portref C (instanceref bn_ascii_reg_24_)) - (portref C (instanceref bn_ascii_reg_25_)) - (portref C (instanceref bn_ascii_reg_26_)) - (portref C (instanceref bn_ascii_reg_27_)) - (portref C (instanceref bn_ascii_reg_29_)) - (portref C (instanceref bn_ascii_reg_2_)) - (portref C (instanceref bn_ascii_reg_30_)) - (portref C (instanceref bn_ascii_reg_32_)) - (portref C (instanceref bn_ascii_reg_33_)) - (portref C (instanceref bn_ascii_reg_34_)) - (portref C (instanceref bn_ascii_reg_35_)) - (portref C (instanceref bn_ascii_reg_37_)) - (portref C (instanceref bn_ascii_reg_38_)) - (portref C (instanceref bn_ascii_reg_3_)) - (portref C (instanceref bn_ascii_reg_40_)) - (portref C (instanceref bn_ascii_reg_41_)) - (portref C (instanceref bn_ascii_reg_42_)) - (portref C (instanceref bn_ascii_reg_43_)) - (portref C (instanceref bn_ascii_reg_45_)) - (portref C (instanceref bn_ascii_reg_46_)) - (portref C (instanceref bn_ascii_reg_48_)) - (portref C (instanceref bn_ascii_reg_49_)) - (portref C (instanceref bn_ascii_reg_50_)) - (portref C (instanceref bn_ascii_reg_51_)) - (portref C (instanceref bn_ascii_reg_53_)) - (portref C (instanceref bn_ascii_reg_54_)) - (portref C (instanceref bn_ascii_reg_56_)) - (portref C (instanceref bn_ascii_reg_57_)) - (portref C (instanceref bn_ascii_reg_58_)) - (portref C (instanceref bn_ascii_reg_59_)) - (portref C (instanceref bn_ascii_reg_5_)) - (portref C (instanceref bn_ascii_reg_61_)) - (portref C (instanceref bn_ascii_reg_62_)) - (portref C (instanceref bn_ascii_reg_6_)) - (portref C (instanceref bn_ascii_reg_8_)) - (portref C (instanceref bn_ascii_reg_9_)) - (portref C (instanceref byte_cnt_reg_0_)) - (portref C (instanceref byte_cnt_reg_10_)) - (portref C (instanceref byte_cnt_reg_11_)) - (portref C (instanceref byte_cnt_reg_12_)) - (portref C (instanceref byte_cnt_reg_13_)) - (portref C (instanceref byte_cnt_reg_14_)) - (portref C (instanceref byte_cnt_reg_15_)) - (portref C (instanceref byte_cnt_reg_16_)) - (portref C (instanceref byte_cnt_reg_17_)) - (portref C (instanceref byte_cnt_reg_18_)) - (portref C (instanceref byte_cnt_reg_19_)) - (portref C (instanceref byte_cnt_reg_1_)) - (portref C (instanceref byte_cnt_reg_20_)) - (portref C (instanceref byte_cnt_reg_21_)) - (portref C (instanceref byte_cnt_reg_22_)) - (portref C (instanceref byte_cnt_reg_23_)) - (portref C (instanceref byte_cnt_reg_24_)) - (portref C (instanceref byte_cnt_reg_25_)) - (portref C (instanceref byte_cnt_reg_26_)) - (portref C (instanceref byte_cnt_reg_27_)) - (portref C (instanceref byte_cnt_reg_28_)) - (portref C (instanceref byte_cnt_reg_29_)) - (portref C (instanceref byte_cnt_reg_2_)) - (portref C (instanceref byte_cnt_reg_30_)) - (portref C (instanceref byte_cnt_reg_31_)) - (portref C (instanceref byte_cnt_reg_3_)) - (portref C (instanceref byte_cnt_reg_4_)) - (portref C (instanceref byte_cnt_reg_5_)) - (portref C (instanceref byte_cnt_reg_6_)) - (portref C (instanceref byte_cnt_reg_7_)) - (portref C (instanceref byte_cnt_reg_8_)) - (portref C (instanceref byte_cnt_reg_9_)) - (portref C (instanceref byte_len_reg_0_)) - (portref C (instanceref byte_len_reg_1_)) - (portref C (instanceref byte_len_reg_2_)) - (portref C (instanceref byte_len_reg_3_)) - (portref C (instanceref byte_len_reg_4_)) - (portref C (instanceref byte_len_reg_5_)) - (portref C (instanceref byte_len_reg_6_)) - (portref C (instanceref byte_len_reg_7_)) - (portref C (instanceref byte_num_reg_0_)) - (portref C (instanceref byte_num_reg_10_)) - (portref C (instanceref byte_num_reg_11_)) - (portref C (instanceref byte_num_reg_12_)) - (portref C (instanceref byte_num_reg_13_)) - (portref C (instanceref byte_num_reg_14_)) - (portref C (instanceref byte_num_reg_15_)) - (portref C (instanceref byte_num_reg_16_)) - (portref C (instanceref byte_num_reg_17_)) - (portref C (instanceref byte_num_reg_18_)) - (portref C (instanceref byte_num_reg_19_)) - (portref C (instanceref byte_num_reg_1_)) - (portref C (instanceref byte_num_reg_20_)) - (portref C (instanceref byte_num_reg_21_)) - (portref C (instanceref byte_num_reg_22_)) - (portref C (instanceref byte_num_reg_23_)) - (portref C (instanceref byte_num_reg_24_)) - (portref C (instanceref byte_num_reg_25_)) - (portref C (instanceref byte_num_reg_26_)) - (portref C (instanceref byte_num_reg_27_)) - (portref C (instanceref byte_num_reg_28_)) - (portref C (instanceref byte_num_reg_29_)) - (portref C (instanceref byte_num_reg_2_)) - (portref C (instanceref byte_num_reg_30_)) - (portref C (instanceref byte_num_reg_31_)) - (portref C (instanceref byte_num_reg_3_)) - (portref C (instanceref byte_num_reg_4_)) - (portref C (instanceref byte_num_reg_5_)) - (portref C (instanceref byte_num_reg_6_)) - (portref C (instanceref byte_num_reg_7_)) - (portref C (instanceref byte_num_reg_8_)) - (portref C (instanceref byte_num_reg_9_)) - (portref C (instanceref dbuf_reg_0_)) - (portref C (instanceref dbuf_reg_10_)) - (portref C (instanceref dbuf_reg_11_)) - (portref C (instanceref dbuf_reg_12_)) - (portref C (instanceref dbuf_reg_13_)) - (portref C (instanceref dbuf_reg_14_)) - (portref C (instanceref dbuf_reg_15_)) - (portref C (instanceref dbuf_reg_16_)) - (portref C (instanceref dbuf_reg_17_)) - (portref C (instanceref dbuf_reg_18_)) - (portref C (instanceref dbuf_reg_19_)) - (portref C (instanceref dbuf_reg_1_)) - (portref C (instanceref dbuf_reg_20_)) - (portref C (instanceref dbuf_reg_21_)) - (portref C (instanceref dbuf_reg_22_)) - (portref C (instanceref dbuf_reg_23_)) - (portref C (instanceref dbuf_reg_2_)) - (portref C (instanceref dbuf_reg_3_)) - (portref C (instanceref dbuf_reg_4_)) - (portref C (instanceref dbuf_reg_5_)) - (portref C (instanceref dbuf_reg_6_)) - (portref C (instanceref dbuf_reg_7_)) - (portref C (instanceref dbuf_reg_8_)) - (portref C (instanceref dbuf_reg_9_)) - (portref C (instanceref disp_reg_0_)) - (portref C (instanceref disp_reg_1_)) - (portref C (instanceref disp_reg_2_)) - (portref C (instanceref disp_reg_3_)) - (portref C (instanceref disp_reg_4_)) - (portref C (instanceref disp_reg_5_)) - (portref C (instanceref disp_reg_6_)) - (portref C (instanceref disp_reg_7_)) - (portref C (instanceref len_cnt_reg_0_)) - (portref C (instanceref len_cnt_reg_1_)) - (portref C (instanceref len_cnt_reg_2_)) - (portref C (instanceref len_cnt_reg_3_)) - (portref C (instanceref recv_done_reg)) - (portref C (instanceref rx_done_reg)) - (portref C (instanceref upg_adr_o_reg_0_)) - (portref C (instanceref upg_adr_o_reg_10_)) - (portref C (instanceref upg_adr_o_reg_11_)) - (portref C (instanceref upg_adr_o_reg_12_)) - (portref C (instanceref upg_adr_o_reg_13_)) - (portref C (instanceref upg_adr_o_reg_14_)) - (portref C (instanceref upg_adr_o_reg_1_)) - (portref C (instanceref upg_adr_o_reg_2_)) - (portref C (instanceref upg_adr_o_reg_3_)) - (portref C (instanceref upg_adr_o_reg_4_)) - (portref C (instanceref upg_adr_o_reg_5_)) - (portref C (instanceref upg_adr_o_reg_6_)) - (portref C (instanceref upg_adr_o_reg_7_)) - (portref C (instanceref upg_adr_o_reg_8_)) - (portref C (instanceref upg_adr_o_reg_9_)) - (portref C (instanceref upg_dat_o_reg_0_)) - (portref C (instanceref upg_dat_o_reg_10_)) - (portref C (instanceref upg_dat_o_reg_11_)) - (portref C (instanceref upg_dat_o_reg_12_)) - (portref C (instanceref upg_dat_o_reg_13_)) - (portref C (instanceref upg_dat_o_reg_14_)) - (portref C (instanceref upg_dat_o_reg_15_)) - (portref C (instanceref upg_dat_o_reg_16_)) - (portref C (instanceref upg_dat_o_reg_17_)) - (portref C (instanceref upg_dat_o_reg_18_)) - (portref C (instanceref upg_dat_o_reg_19_)) - (portref C (instanceref upg_dat_o_reg_1_)) - (portref C (instanceref upg_dat_o_reg_20_)) - (portref C (instanceref upg_dat_o_reg_21_)) - (portref C (instanceref upg_dat_o_reg_22_)) - (portref C (instanceref upg_dat_o_reg_23_)) - (portref C (instanceref upg_dat_o_reg_24_)) - (portref C (instanceref upg_dat_o_reg_25_)) - (portref C (instanceref upg_dat_o_reg_26_)) - (portref C (instanceref upg_dat_o_reg_27_)) - (portref C (instanceref upg_dat_o_reg_28_)) - (portref C (instanceref upg_dat_o_reg_29_)) - (portref C (instanceref upg_dat_o_reg_2_)) - (portref C (instanceref upg_dat_o_reg_30_)) - (portref C (instanceref upg_dat_o_reg_31_)) - (portref C (instanceref upg_dat_o_reg_3_)) - (portref C (instanceref upg_dat_o_reg_4_)) - (portref C (instanceref upg_dat_o_reg_5_)) - (portref C (instanceref upg_dat_o_reg_6_)) - (portref C (instanceref upg_dat_o_reg_7_)) - (portref C (instanceref upg_dat_o_reg_8_)) - (portref C (instanceref upg_dat_o_reg_9_)) - (portref C (instanceref upg_wen_o_reg)) - (portref C (instanceref wr_byte_len_done_reg)) - (portref C (instanceref wr_byte_num_done_reg)) - (portref O (instanceref rdStat_BUFG_inst)) - ) - ) - (net rdStat_i_1_n_0 (joined - (portref D (instanceref rdStat_reg)) - (portref O (instanceref rdStat_i_1)) - ) - ) - (net recv_done0 (joined - (portref (member CO 0) (instanceref recv_done_reg_i_2)) - (portref I0 (instanceref recv_done_i_1)) - ) - ) - (net (rename recv_done1_0_ "recv_done1[0]") (joined - (portref D (instanceref byte_cnt_reg_0_)) - (portref O (instanceref byte_cnt_0__i_1)) - ) - ) - (net (rename recv_done1_10_ "recv_done1[10]") (joined - (portref D (instanceref byte_cnt_reg_10_)) - (portref I2 (instanceref recv_done_i_24)) - (portref I3 (instanceref recv_done_i_28)) - (portref (member O 2) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename recv_done1_11_ "recv_done1[11]") (joined - (portref D (instanceref byte_cnt_reg_11_)) - (portref I0 (instanceref recv_done_i_24)) - (portref I1 (instanceref recv_done_i_28)) - (portref (member O 1) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename recv_done1_12_ "recv_done1[12]") (joined - (portref D (instanceref byte_cnt_reg_12_)) - (portref I2 (instanceref recv_done_i_23)) - (portref I3 (instanceref recv_done_i_27)) - (portref (member O 0) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net (rename recv_done1_13_ "recv_done1[13]") (joined - (portref D (instanceref byte_cnt_reg_13_)) - (portref I0 (instanceref recv_done_i_23)) - (portref I1 (instanceref recv_done_i_27)) - (portref (member O 3) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename recv_done1_14_ "recv_done1[14]") (joined - (portref D (instanceref byte_cnt_reg_14_)) - (portref I2 (instanceref recv_done_i_22)) - (portref I3 (instanceref recv_done_i_26)) - (portref (member O 2) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename recv_done1_15_ "recv_done1[15]") (joined - (portref D (instanceref byte_cnt_reg_15_)) - (portref I0 (instanceref recv_done_i_22)) - (portref I1 (instanceref recv_done_i_26)) - (portref (member O 1) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename recv_done1_16_ "recv_done1[16]") (joined - (portref D (instanceref byte_cnt_reg_16_)) - (portref I2 (instanceref recv_done_i_16)) - (portref I3 (instanceref recv_done_i_20)) - (portref (member O 0) (instanceref byte_cnt_reg_16__i_1)) - ) - ) - (net (rename recv_done1_17_ "recv_done1[17]") (joined - (portref D (instanceref byte_cnt_reg_17_)) - (portref I0 (instanceref recv_done_i_16)) - (portref I1 (instanceref recv_done_i_20)) - (portref (member O 3) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename recv_done1_18_ "recv_done1[18]") (joined - (portref D (instanceref byte_cnt_reg_18_)) - (portref I2 (instanceref recv_done_i_15)) - (portref I3 (instanceref recv_done_i_19)) - (portref (member O 2) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename recv_done1_19_ "recv_done1[19]") (joined - (portref D (instanceref byte_cnt_reg_19_)) - (portref I0 (instanceref recv_done_i_15)) - (portref I1 (instanceref recv_done_i_19)) - (portref (member O 1) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename recv_done1_1_ "recv_done1[1]") (joined - (portref D (instanceref byte_cnt_reg_1_)) - (portref I0 (instanceref recv_done_i_33)) - (portref I3 (instanceref recv_done_i_37)) - (portref (member O 3) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename recv_done1_20_ "recv_done1[20]") (joined - (portref D (instanceref byte_cnt_reg_20_)) - (portref I2 (instanceref recv_done_i_14)) - (portref I3 (instanceref recv_done_i_18)) - (portref (member O 0) (instanceref byte_cnt_reg_20__i_1)) - ) - ) - (net (rename recv_done1_21_ "recv_done1[21]") (joined - (portref D (instanceref byte_cnt_reg_21_)) - (portref I0 (instanceref recv_done_i_14)) - (portref I1 (instanceref recv_done_i_18)) - (portref (member O 3) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename recv_done1_22_ "recv_done1[22]") (joined - (portref D (instanceref byte_cnt_reg_22_)) - (portref I2 (instanceref recv_done_i_13)) - (portref I3 (instanceref recv_done_i_17)) - (portref (member O 2) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename recv_done1_23_ "recv_done1[23]") (joined - (portref D (instanceref byte_cnt_reg_23_)) - (portref I0 (instanceref recv_done_i_13)) - (portref I1 (instanceref recv_done_i_17)) - (portref (member O 1) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename recv_done1_24_ "recv_done1[24]") (joined - (portref D (instanceref byte_cnt_reg_24_)) - (portref I2 (instanceref recv_done_i_7)) - (portref I3 (instanceref recv_done_i_11)) - (portref (member O 0) (instanceref byte_cnt_reg_24__i_1)) - ) - ) - (net (rename recv_done1_25_ "recv_done1[25]") (joined - (portref D (instanceref byte_cnt_reg_25_)) - (portref I0 (instanceref recv_done_i_7)) - (portref I1 (instanceref recv_done_i_11)) - (portref (member O 3) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename recv_done1_26_ "recv_done1[26]") (joined - (portref D (instanceref byte_cnt_reg_26_)) - (portref I2 (instanceref recv_done_i_6)) - (portref I3 (instanceref recv_done_i_10)) - (portref (member O 2) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename recv_done1_27_ "recv_done1[27]") (joined - (portref D (instanceref byte_cnt_reg_27_)) - (portref I0 (instanceref recv_done_i_6)) - (portref I1 (instanceref recv_done_i_10)) - (portref (member O 1) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename recv_done1_28_ "recv_done1[28]") (joined - (portref D (instanceref byte_cnt_reg_28_)) - (portref I2 (instanceref recv_done_i_5)) - (portref I3 (instanceref recv_done_i_9)) - (portref (member O 0) (instanceref byte_cnt_reg_28__i_1)) - ) - ) - (net (rename recv_done1_29_ "recv_done1[29]") (joined - (portref D (instanceref byte_cnt_reg_29_)) - (portref I0 (instanceref recv_done_i_5)) - (portref I1 (instanceref recv_done_i_9)) - (portref (member O 3) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename recv_done1_2_ "recv_done1[2]") (joined - (portref D (instanceref byte_cnt_reg_2_)) - (portref I2 (instanceref recv_done_i_32)) - (portref I3 (instanceref recv_done_i_36)) - (portref (member O 2) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename recv_done1_30_ "recv_done1[30]") (joined - (portref D (instanceref byte_cnt_reg_30_)) - (portref I2 (instanceref recv_done_i_4)) - (portref I3 (instanceref recv_done_i_8)) - (portref (member O 2) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename recv_done1_31_ "recv_done1[31]") (joined - (portref D (instanceref byte_cnt_reg_31_)) - (portref I0 (instanceref recv_done_i_4)) - (portref I1 (instanceref recv_done_i_8)) - (portref (member O 1) (instanceref byte_cnt_reg_31__i_2)) - ) - ) - (net (rename recv_done1_3_ "recv_done1[3]") (joined - (portref D (instanceref byte_cnt_reg_3_)) - (portref I0 (instanceref recv_done_i_32)) - (portref I1 (instanceref recv_done_i_36)) - (portref (member O 1) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename recv_done1_4_ "recv_done1[4]") (joined - (portref D (instanceref byte_cnt_reg_4_)) - (portref I2 (instanceref recv_done_i_31)) - (portref I3 (instanceref recv_done_i_35)) - (portref (member O 0) (instanceref byte_cnt_reg_4__i_1)) - ) - ) - (net (rename recv_done1_5_ "recv_done1[5]") (joined - (portref D (instanceref byte_cnt_reg_5_)) - (portref I0 (instanceref recv_done_i_31)) - (portref I1 (instanceref recv_done_i_35)) - (portref (member O 3) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename recv_done1_6_ "recv_done1[6]") (joined - (portref D (instanceref byte_cnt_reg_6_)) - (portref I2 (instanceref recv_done_i_30)) - (portref I3 (instanceref recv_done_i_34)) - (portref (member O 2) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename recv_done1_7_ "recv_done1[7]") (joined - (portref D (instanceref byte_cnt_reg_7_)) - (portref I0 (instanceref recv_done_i_30)) - (portref I1 (instanceref recv_done_i_34)) - (portref (member O 1) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename recv_done1_8_ "recv_done1[8]") (joined - (portref D (instanceref byte_cnt_reg_8_)) - (portref I2 (instanceref recv_done_i_25)) - (portref I3 (instanceref recv_done_i_29)) - (portref (member O 0) (instanceref byte_cnt_reg_8__i_1)) - ) - ) - (net (rename recv_done1_9_ "recv_done1[9]") (joined - (portref D (instanceref byte_cnt_reg_9_)) - (portref I0 (instanceref recv_done_i_25)) - (portref I1 (instanceref recv_done_i_29)) - (portref (member O 3) (instanceref byte_cnt_reg_12__i_1)) - ) - ) - (net recv_done_i_10_n_0 (joined - (portref O (instanceref recv_done_i_10)) - (portref (member S 2) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_i_11_n_0 (joined - (portref O (instanceref recv_done_i_11)) - (portref (member S 3) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_i_13_n_0 (joined - (portref (member DI 0) (instanceref recv_done_reg_i_3)) - (portref O (instanceref recv_done_i_13)) - ) - ) - (net recv_done_i_14_n_0 (joined - (portref (member DI 1) (instanceref recv_done_reg_i_3)) - (portref O (instanceref recv_done_i_14)) - ) - ) - (net recv_done_i_15_n_0 (joined - (portref (member DI 2) (instanceref recv_done_reg_i_3)) - (portref O (instanceref recv_done_i_15)) - ) - ) - (net recv_done_i_16_n_0 (joined - (portref (member DI 3) (instanceref recv_done_reg_i_3)) - (portref O (instanceref recv_done_i_16)) - ) - ) - (net recv_done_i_17_n_0 (joined - (portref O (instanceref recv_done_i_17)) - (portref (member S 0) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_i_18_n_0 (joined - (portref O (instanceref recv_done_i_18)) - (portref (member S 1) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_i_19_n_0 (joined - (portref O (instanceref recv_done_i_19)) - (portref (member S 2) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_i_1_n_0 (joined - (portref D (instanceref recv_done_reg)) - (portref O (instanceref recv_done_i_1)) - ) - ) - (net recv_done_i_20_n_0 (joined - (portref O (instanceref recv_done_i_20)) - (portref (member S 3) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_i_22_n_0 (joined - (portref (member DI 0) (instanceref recv_done_reg_i_12)) - (portref O (instanceref recv_done_i_22)) - ) - ) - (net recv_done_i_23_n_0 (joined - (portref (member DI 1) (instanceref recv_done_reg_i_12)) - (portref O (instanceref recv_done_i_23)) - ) - ) - (net recv_done_i_24_n_0 (joined - (portref (member DI 2) (instanceref recv_done_reg_i_12)) - (portref O (instanceref recv_done_i_24)) - ) - ) - (net recv_done_i_25_n_0 (joined - (portref (member DI 3) (instanceref recv_done_reg_i_12)) - (portref O (instanceref recv_done_i_25)) - ) - ) - (net recv_done_i_26_n_0 (joined - (portref O (instanceref recv_done_i_26)) - (portref (member S 0) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_i_27_n_0 (joined - (portref O (instanceref recv_done_i_27)) - (portref (member S 1) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_i_28_n_0 (joined - (portref O (instanceref recv_done_i_28)) - (portref (member S 2) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_i_29_n_0 (joined - (portref O (instanceref recv_done_i_29)) - (portref (member S 3) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_i_30_n_0 (joined - (portref (member DI 0) (instanceref recv_done_reg_i_21)) - (portref O (instanceref recv_done_i_30)) - ) - ) - (net recv_done_i_31_n_0 (joined - (portref (member DI 1) (instanceref recv_done_reg_i_21)) - (portref O (instanceref recv_done_i_31)) - ) - ) - (net recv_done_i_32_n_0 (joined - (portref (member DI 2) (instanceref recv_done_reg_i_21)) - (portref O (instanceref recv_done_i_32)) - ) - ) - (net recv_done_i_33_n_0 (joined - (portref (member DI 3) (instanceref recv_done_reg_i_21)) - (portref O (instanceref recv_done_i_33)) - ) - ) - (net recv_done_i_34_n_0 (joined - (portref O (instanceref recv_done_i_34)) - (portref (member S 0) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_i_35_n_0 (joined - (portref O (instanceref recv_done_i_35)) - (portref (member S 1) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_i_36_n_0 (joined - (portref O (instanceref recv_done_i_36)) - (portref (member S 2) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_i_37_n_0 (joined - (portref O (instanceref recv_done_i_37)) - (portref (member S 3) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_i_4_n_0 (joined - (portref (member DI 0) (instanceref recv_done_reg_i_2)) - (portref O (instanceref recv_done_i_4)) - ) - ) - (net recv_done_i_5_n_0 (joined - (portref (member DI 1) (instanceref recv_done_reg_i_2)) - (portref O (instanceref recv_done_i_5)) - ) - ) - (net recv_done_i_6_n_0 (joined - (portref (member DI 2) (instanceref recv_done_reg_i_2)) - (portref O (instanceref recv_done_i_6)) - ) - ) - (net recv_done_i_7_n_0 (joined - (portref (member DI 3) (instanceref recv_done_reg_i_2)) - (portref O (instanceref recv_done_i_7)) - ) - ) - (net recv_done_i_8_n_0 (joined - (portref O (instanceref recv_done_i_8)) - (portref (member S 0) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_i_9_n_0 (joined - (portref O (instanceref recv_done_i_9)) - (portref (member S 1) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_reg_i_12_n_0 (joined - (portref CI (instanceref recv_done_reg_i_3)) - (portref (member CO 0) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_reg_i_12_n_1 (joined - (portref (member CO 1) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_reg_i_12_n_2 (joined - (portref (member CO 2) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_reg_i_12_n_3 (joined - (portref (member CO 3) (instanceref recv_done_reg_i_12)) - ) - ) - (net recv_done_reg_i_21_n_0 (joined - (portref CI (instanceref recv_done_reg_i_12)) - (portref (member CO 0) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_reg_i_21_n_1 (joined - (portref (member CO 1) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_reg_i_21_n_2 (joined - (portref (member CO 2) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_reg_i_21_n_3 (joined - (portref (member CO 3) (instanceref recv_done_reg_i_21)) - ) - ) - (net recv_done_reg_i_2_n_1 (joined - (portref (member CO 1) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_reg_i_2_n_2 (joined - (portref (member CO 2) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_reg_i_2_n_3 (joined - (portref (member CO 3) (instanceref recv_done_reg_i_2)) - ) - ) - (net recv_done_reg_i_3_n_0 (joined - (portref CI (instanceref recv_done_reg_i_2)) - (portref (member CO 0) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_reg_i_3_n_1 (joined - (portref (member CO 1) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_reg_i_3_n_2 (joined - (portref (member CO 2) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_reg_i_3_n_3 (joined - (portref (member CO 3) (instanceref recv_done_reg_i_3)) - ) - ) - (net recv_done_reg_n_0 (joined - (portref I0 (instanceref byte_cnt_31__i_1)) - (portref I0 (instanceref disp_5__i_2)) - (portref I0 (instanceref disp_5__i_4)) - (portref I0 (instanceref disp_7__i_1)) - (portref I0 (instanceref rx_done_i_1)) - (portref I1 (instanceref disp_3__i_2)) - (portref I1 (instanceref disp_6__i_1)) - (portref I1 (instanceref disp_6__i_2)) - (portref I1 (instanceref upg_wen_o_i_4)) - (portref I3 (instanceref disp_0__i_1)) - (portref I3 (instanceref disp_1__i_3)) - (portref I3 (instanceref disp_2__i_1)) - (portref I3 (instanceref disp_5__i_3)) - (portref I4 (instanceref disp_1__i_1)) - (portref I4 (instanceref disp_2__i_2)) - (portref I4 (instanceref recv_done_i_1)) - (portref I4 (instanceref upg_wen_o_i_6)) - (portref I5 (instanceref disp_3__i_1)) - (portref I5 (instanceref disp_4__i_1)) - (portref Q (instanceref recv_done_reg)) - ) - ) - (net (rename rwait_cnt_0_ "rwait_cnt[0]") (joined - (portref D (instanceref rwait_cnt_reg_0_)) - (portref O (instanceref rwait_cnt_0__i_1)) - ) - ) - (net (rename rwait_cnt_10_ "rwait_cnt[10]") (joined - (portref D (instanceref rwait_cnt_reg_10_)) - (portref O (instanceref rwait_cnt_10__i_1)) - ) - ) - (net (rename rwait_cnt_11_ "rwait_cnt[11]") (joined - (portref D (instanceref rwait_cnt_reg_11_)) - (portref O (instanceref rwait_cnt_11__i_1)) - ) - ) - (net (rename rwait_cnt_12_ "rwait_cnt[12]") (joined - (portref D (instanceref rwait_cnt_reg_12_)) - (portref O (instanceref rwait_cnt_12__i_1)) - ) - ) - (net (rename rwait_cnt_13_ "rwait_cnt[13]") (joined - (portref D (instanceref rwait_cnt_reg_13_)) - (portref O (instanceref rwait_cnt_13__i_1)) - ) - ) - (net (rename rwait_cnt_14_ "rwait_cnt[14]") (joined - (portref D (instanceref rwait_cnt_reg_14_)) - (portref O (instanceref rwait_cnt_14__i_1)) - ) - ) - (net (rename rwait_cnt_15_ "rwait_cnt[15]") (joined - (portref D (instanceref rwait_cnt_reg_15_)) - (portref O (instanceref rwait_cnt_15__i_2)) - ) - ) - (net (rename rwait_cnt_15__i_1_n_0 "rwait_cnt[15]_i_1_n_0") (joined - (portref CE (instanceref rwait_cnt_reg_0_)) - (portref CE (instanceref rwait_cnt_reg_10_)) - (portref CE (instanceref rwait_cnt_reg_11_)) - (portref CE (instanceref rwait_cnt_reg_12_)) - (portref CE (instanceref rwait_cnt_reg_13_)) - (portref CE (instanceref rwait_cnt_reg_14_)) - (portref CE (instanceref rwait_cnt_reg_15_)) - (portref CE (instanceref rwait_cnt_reg_1_)) - (portref CE (instanceref rwait_cnt_reg_2_)) - (portref CE (instanceref rwait_cnt_reg_3_)) - (portref CE (instanceref rwait_cnt_reg_4_)) - (portref CE (instanceref rwait_cnt_reg_5_)) - (portref CE (instanceref rwait_cnt_reg_6_)) - (portref CE (instanceref rwait_cnt_reg_7_)) - (portref CE (instanceref rwait_cnt_reg_8_)) - (portref CE (instanceref rwait_cnt_reg_9_)) - (portref O (instanceref rwait_cnt_15__i_1)) - ) - ) - (net (rename rwait_cnt_15__i_4_n_0 "rwait_cnt[15]_i_4_n_0") (joined - (portref I0 (instanceref RCS_2__i_1)) - (portref I1 (instanceref rwait_cnt_0__i_1)) - (portref I1 (instanceref rwait_cnt_10__i_1)) - (portref I1 (instanceref rwait_cnt_11__i_1)) - (portref I1 (instanceref rwait_cnt_12__i_1)) - (portref I1 (instanceref rwait_cnt_13__i_1)) - (portref I1 (instanceref rwait_cnt_14__i_1)) - (portref I1 (instanceref rwait_cnt_15__i_2)) - (portref I1 (instanceref rwait_cnt_1__i_1)) - (portref I1 (instanceref rwait_cnt_2__i_1)) - (portref I1 (instanceref rwait_cnt_3__i_1)) - (portref I1 (instanceref rwait_cnt_4__i_1)) - (portref I1 (instanceref rwait_cnt_5__i_1)) - (portref I1 (instanceref rwait_cnt_6__i_1)) - (portref I1 (instanceref rwait_cnt_7__i_1)) - (portref I1 (instanceref rwait_cnt_8__i_1)) - (portref I1 (instanceref rwait_cnt_9__i_1)) - (portref O (instanceref rwait_cnt_15__i_4)) - ) - ) - (net (rename rwait_cnt_15__i_5_n_0 "rwait_cnt[15]_i_5_n_0") (joined - (portref I0 (instanceref rwait_cnt_15__i_4)) - (portref O (instanceref rwait_cnt_15__i_5)) - ) - ) - (net (rename rwait_cnt_15__i_6_n_0 "rwait_cnt[15]_i_6_n_0") (joined - (portref I5 (instanceref rwait_cnt_15__i_4)) - (portref O (instanceref rwait_cnt_15__i_6)) - ) - ) - (net (rename rwait_cnt_15__i_7_n_0 "rwait_cnt[15]_i_7_n_0") (joined - (portref I4 (instanceref rwait_cnt_15__i_6)) - (portref O (instanceref rwait_cnt_15__i_7)) - ) - ) - (net (rename rwait_cnt_1_ "rwait_cnt[1]") (joined - (portref D (instanceref rwait_cnt_reg_1_)) - (portref O (instanceref rwait_cnt_1__i_1)) - ) - ) - (net (rename rwait_cnt_2_ "rwait_cnt[2]") (joined - (portref D (instanceref rwait_cnt_reg_2_)) - (portref O (instanceref rwait_cnt_2__i_1)) - ) - ) - (net (rename rwait_cnt_3_ "rwait_cnt[3]") (joined - (portref D (instanceref rwait_cnt_reg_3_)) - (portref O (instanceref rwait_cnt_3__i_1)) - ) - ) - (net (rename rwait_cnt_4_ "rwait_cnt[4]") (joined - (portref D (instanceref rwait_cnt_reg_4_)) - (portref O (instanceref rwait_cnt_4__i_1)) - ) - ) - (net (rename rwait_cnt_5_ "rwait_cnt[5]") (joined - (portref D (instanceref rwait_cnt_reg_5_)) - (portref O (instanceref rwait_cnt_5__i_1)) - ) - ) - (net (rename rwait_cnt_6_ "rwait_cnt[6]") (joined - (portref D (instanceref rwait_cnt_reg_6_)) - (portref O (instanceref rwait_cnt_6__i_1)) - ) - ) - (net (rename rwait_cnt_7_ "rwait_cnt[7]") (joined - (portref D (instanceref rwait_cnt_reg_7_)) - (portref O (instanceref rwait_cnt_7__i_1)) - ) - ) - (net (rename rwait_cnt_8_ "rwait_cnt[8]") (joined - (portref D (instanceref rwait_cnt_reg_8_)) - (portref O (instanceref rwait_cnt_8__i_1)) - ) - ) - (net (rename rwait_cnt_9_ "rwait_cnt[9]") (joined - (portref D (instanceref rwait_cnt_reg_9_)) - (portref O (instanceref rwait_cnt_9__i_1)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_0 "rwait_cnt_reg[12]_i_2_n_0") (joined - (portref CI (instanceref rwait_cnt_reg_15__i_3)) - (portref (member CO 0) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_1 "rwait_cnt_reg[12]_i_2_n_1") (joined - (portref (member CO 1) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_2 "rwait_cnt_reg[12]_i_2_n_2") (joined - (portref (member CO 2) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_3 "rwait_cnt_reg[12]_i_2_n_3") (joined - (portref (member CO 3) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_4 "rwait_cnt_reg[12]_i_2_n_4") (joined - (portref I0 (instanceref rwait_cnt_12__i_1)) - (portref (member O 0) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_5 "rwait_cnt_reg[12]_i_2_n_5") (joined - (portref I0 (instanceref rwait_cnt_11__i_1)) - (portref (member O 1) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_6 "rwait_cnt_reg[12]_i_2_n_6") (joined - (portref I0 (instanceref rwait_cnt_10__i_1)) - (portref (member O 2) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_12__i_2_n_7 "rwait_cnt_reg[12]_i_2_n_7") (joined - (portref I0 (instanceref rwait_cnt_9__i_1)) - (portref (member O 3) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_15__i_3_n_2 "rwait_cnt_reg[15]_i_3_n_2") (joined - (portref (member CO 2) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_15__i_3_n_3 "rwait_cnt_reg[15]_i_3_n_3") (joined - (portref (member CO 3) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_15__i_3_n_5 "rwait_cnt_reg[15]_i_3_n_5") (joined - (portref I0 (instanceref rwait_cnt_15__i_2)) - (portref (member O 1) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_15__i_3_n_6 "rwait_cnt_reg[15]_i_3_n_6") (joined - (portref I0 (instanceref rwait_cnt_14__i_1)) - (portref (member O 2) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_15__i_3_n_7 "rwait_cnt_reg[15]_i_3_n_7") (joined - (portref I0 (instanceref rwait_cnt_13__i_1)) - (portref (member O 3) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_0 "rwait_cnt_reg[4]_i_2_n_0") (joined - (portref CI (instanceref rwait_cnt_reg_8__i_2)) - (portref (member CO 0) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_1 "rwait_cnt_reg[4]_i_2_n_1") (joined - (portref (member CO 1) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_2 "rwait_cnt_reg[4]_i_2_n_2") (joined - (portref (member CO 2) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_3 "rwait_cnt_reg[4]_i_2_n_3") (joined - (portref (member CO 3) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_4 "rwait_cnt_reg[4]_i_2_n_4") (joined - (portref I0 (instanceref rwait_cnt_4__i_1)) - (portref (member O 0) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_5 "rwait_cnt_reg[4]_i_2_n_5") (joined - (portref I0 (instanceref rwait_cnt_3__i_1)) - (portref (member O 1) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_6 "rwait_cnt_reg[4]_i_2_n_6") (joined - (portref I0 (instanceref rwait_cnt_2__i_1)) - (portref (member O 2) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_4__i_2_n_7 "rwait_cnt_reg[4]_i_2_n_7") (joined - (portref I0 (instanceref rwait_cnt_1__i_1)) - (portref (member O 3) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_0 "rwait_cnt_reg[8]_i_2_n_0") (joined - (portref CI (instanceref rwait_cnt_reg_12__i_2)) - (portref (member CO 0) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_1 "rwait_cnt_reg[8]_i_2_n_1") (joined - (portref (member CO 1) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_2 "rwait_cnt_reg[8]_i_2_n_2") (joined - (portref (member CO 2) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_3 "rwait_cnt_reg[8]_i_2_n_3") (joined - (portref (member CO 3) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_4 "rwait_cnt_reg[8]_i_2_n_4") (joined - (portref I0 (instanceref rwait_cnt_8__i_1)) - (portref (member O 0) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_5 "rwait_cnt_reg[8]_i_2_n_5") (joined - (portref I0 (instanceref rwait_cnt_7__i_1)) - (portref (member O 1) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_6 "rwait_cnt_reg[8]_i_2_n_6") (joined - (portref I0 (instanceref rwait_cnt_6__i_1)) - (portref (member O 2) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_8__i_2_n_7 "rwait_cnt_reg[8]_i_2_n_7") (joined - (portref I0 (instanceref rwait_cnt_5__i_1)) - (portref (member O 3) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__0_ "rwait_cnt_reg_n_0_[0]") (joined - (portref CYINIT (instanceref rwait_cnt_reg_4__i_2)) - (portref I0 (instanceref rwait_cnt_0__i_1)) - (portref I2 (instanceref rwait_cnt_15__i_6)) - (portref Q (instanceref rwait_cnt_reg_0_)) - ) - ) - (net (rename rwait_cnt_reg_n_0__10_ "rwait_cnt_reg_n_0_[10]") (joined - (portref I1 (instanceref rwait_cnt_15__i_5)) - (portref Q (instanceref rwait_cnt_reg_10_)) - (portref (member S 2) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__11_ "rwait_cnt_reg_n_0_[11]") (joined - (portref I4 (instanceref rwait_cnt_15__i_4)) - (portref Q (instanceref rwait_cnt_reg_11_)) - (portref (member S 1) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__12_ "rwait_cnt_reg_n_0_[12]") (joined - (portref I0 (instanceref rwait_cnt_15__i_6)) - (portref Q (instanceref rwait_cnt_reg_12_)) - (portref (member S 0) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__13_ "rwait_cnt_reg_n_0_[13]") (joined - (portref I1 (instanceref rwait_cnt_15__i_7)) - (portref Q (instanceref rwait_cnt_reg_13_)) - (portref (member S 3) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_n_0__14_ "rwait_cnt_reg_n_0_[14]") (joined - (portref I0 (instanceref rwait_cnt_15__i_7)) - (portref Q (instanceref rwait_cnt_reg_14_)) - (portref (member S 2) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_n_0__15_ "rwait_cnt_reg_n_0_[15]") (joined - (portref I3 (instanceref rwait_cnt_15__i_5)) - (portref Q (instanceref rwait_cnt_reg_15_)) - (portref (member S 1) (instanceref rwait_cnt_reg_15__i_3)) - ) - ) - (net (rename rwait_cnt_reg_n_0__1_ "rwait_cnt_reg_n_0_[1]") (joined - (portref I1 (instanceref rwait_cnt_15__i_6)) - (portref Q (instanceref rwait_cnt_reg_1_)) - (portref (member S 3) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__2_ "rwait_cnt_reg_n_0_[2]") (joined - (portref I1 (instanceref rwait_cnt_15__i_4)) - (portref Q (instanceref rwait_cnt_reg_2_)) - (portref (member S 2) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__3_ "rwait_cnt_reg_n_0_[3]") (joined - (portref I2 (instanceref rwait_cnt_15__i_7)) - (portref Q (instanceref rwait_cnt_reg_3_)) - (portref (member S 1) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__4_ "rwait_cnt_reg_n_0_[4]") (joined - (portref I0 (instanceref rwait_cnt_15__i_5)) - (portref Q (instanceref rwait_cnt_reg_4_)) - (portref (member S 0) (instanceref rwait_cnt_reg_4__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__5_ "rwait_cnt_reg_n_0_[5]") (joined - (portref I2 (instanceref rwait_cnt_15__i_4)) - (portref Q (instanceref rwait_cnt_reg_5_)) - (portref (member S 3) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__6_ "rwait_cnt_reg_n_0_[6]") (joined - (portref I3 (instanceref rwait_cnt_15__i_6)) - (portref Q (instanceref rwait_cnt_reg_6_)) - (portref (member S 2) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__7_ "rwait_cnt_reg_n_0_[7]") (joined - (portref I2 (instanceref rwait_cnt_15__i_5)) - (portref Q (instanceref rwait_cnt_reg_7_)) - (portref (member S 1) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__8_ "rwait_cnt_reg_n_0_[8]") (joined - (portref I3 (instanceref rwait_cnt_15__i_4)) - (portref Q (instanceref rwait_cnt_reg_8_)) - (portref (member S 0) (instanceref rwait_cnt_reg_8__i_2)) - ) - ) - (net (rename rwait_cnt_reg_n_0__9_ "rwait_cnt_reg_n_0_[9]") (joined - (portref I3 (instanceref rwait_cnt_15__i_7)) - (portref Q (instanceref rwait_cnt_reg_9_)) - (portref (member S 3) (instanceref rwait_cnt_reg_12__i_2)) - ) - ) - (net rx_done (joined - (portref I0 (instanceref upg_wen_o_i_1)) - (portref I1 (instanceref rx_done_i_1)) - (portref O (instanceref upg_wen_o_i_3)) - ) - ) - (net rx_done_i_1_n_0 (joined - (portref D (instanceref rx_done_reg)) - (portref O (instanceref rx_done_i_1)) - ) - ) - (net rx_done_reg_n_0 (joined - (portref I0 (instanceref disp_6__i_1)) - (portref I0 (instanceref upg_wen_o_i_4)) - (portref I1 (instanceref disp_5__i_4)) - (portref I1 (instanceref disp_7__i_1)) - (portref I2 (instanceref disp_2__i_1)) - (portref I2 (instanceref disp_3__i_2)) - (portref I2 (instanceref disp_5__i_3)) - (portref I2 (instanceref rx_done_i_1)) - (portref I2 (instanceref s_axi_wdata_4__i_3)) - (portref I3 (instanceref s_axi_wstrb_3__i_1)) - (portref I3 (instanceref upg_wen_o_i_6)) - (portref I4 (instanceref disp_1__i_3)) - (portref I4 (instanceref disp_3__i_1)) - (portref I4 (instanceref disp_4__i_1)) - (portref Q (instanceref rx_done_reg)) - ) - ) - (net (rename s_axi_araddr_3__i_1_n_0 "s_axi_araddr[3]_i_1_n_0") (joined - (portref D (instanceref s_axi_araddr_reg_3_)) - (portref O (instanceref s_axi_araddr_3__i_1)) - ) - ) - (net (rename s_axi_araddr_reg_n_0__3_ "s_axi_araddr_reg_n_0_[3]") (joined - (portref I5 (instanceref s_axi_araddr_3__i_1)) - (portref Q (instanceref s_axi_araddr_reg_3_)) - (portref (member s_axi_araddr 0) (instanceref axi_uart_inst)) - ) - ) - (net s_axi_aresetn0 (joined - (portref CE (instanceref disp_reg_0_)) - (portref CE (instanceref disp_reg_1_)) - (portref CE (instanceref disp_reg_2_)) - (portref CE (instanceref disp_reg_3_)) - (portref CE (instanceref disp_reg_4_)) - (portref CE (instanceref disp_reg_5_)) - (portref CE (instanceref disp_reg_6_)) - (portref CE (instanceref disp_reg_7_)) - (portref O (instanceref axi_uart_inst_i_1)) - (portref s_axi_aresetn (instanceref axi_uart_inst)) - ) - ) - (net s_axi_arready (joined - (portref I0 (instanceref s_axi_arvalid_i_1)) - (portref I1 (instanceref RCS_0__i_1)) - (portref s_axi_arready (instanceref axi_uart_inst)) - ) - ) - (net s_axi_arvalid (joined - (portref I5 (instanceref s_axi_arvalid_i_1)) - (portref Q (instanceref s_axi_arvalid_reg)) - (portref s_axi_arvalid (instanceref axi_uart_inst)) - ) - ) - (net s_axi_arvalid_i_1_n_0 (joined - (portref D (instanceref s_axi_arvalid_reg)) - (portref O (instanceref s_axi_arvalid_i_1)) - ) - ) - (net s_axi_arvalid_i_2_n_0 (joined - (portref I1 (instanceref s_axi_arvalid_i_1)) - (portref O (instanceref s_axi_arvalid_i_2)) - ) - ) - (net s_axi_arvalid_i_3_n_0 (joined - (portref I3 (instanceref s_axi_arvalid_i_1)) - (portref O (instanceref s_axi_arvalid_i_3)) - ) - ) - (net (rename s_axi_awaddr_3__i_1_n_0 "s_axi_awaddr[3]_i_1_n_0") (joined - (portref D (instanceref s_axi_awaddr_reg_3_)) - (portref O (instanceref s_axi_awaddr_3__i_1)) - ) - ) - (net (rename s_axi_awaddr_reg_n_0__3_ "s_axi_awaddr_reg_n_0_[3]") (joined - (portref I5 (instanceref s_axi_awaddr_3__i_1)) - (portref Q (instanceref s_axi_awaddr_reg_3_)) - (portref (member s_axi_awaddr 0) (instanceref axi_uart_inst)) - ) - ) - (net s_axi_awready (joined - (portref I0 (instanceref WCS_1__i_1)) - (portref I0 (instanceref s_axi_awvalid_i_2)) - (portref I1 (instanceref WCS_2__i_1)) - (portref s_axi_awready (instanceref axi_uart_inst)) - ) - ) - (net s_axi_awvalid_i_1_n_0 (joined - (portref D (instanceref s_axi_awvalid_reg)) - (portref O (instanceref s_axi_awvalid_i_1)) - ) - ) - (net s_axi_awvalid_i_2_n_0 (joined - (portref I0 (instanceref s_axi_awvalid_i_1)) - (portref O (instanceref s_axi_awvalid_i_2)) - ) - ) - (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined - (portref D (instanceref uart_rdat_reg_0_)) - (portref I0 (instanceref statReg_0__i_1)) - (portref (member s_axi_rdata 31) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined - (portref D (instanceref uart_rdat_reg_1_)) - (portref (member s_axi_rdata 30) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined - (portref D (instanceref uart_rdat_reg_2_)) - (portref (member s_axi_rdata 29) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined - (portref D (instanceref uart_rdat_reg_3_)) - (portref (member s_axi_rdata 28) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined - (portref D (instanceref uart_rdat_reg_4_)) - (portref (member s_axi_rdata 27) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined - (portref D (instanceref uart_rdat_reg_5_)) - (portref (member s_axi_rdata 26) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined - (portref D (instanceref uart_rdat_reg_6_)) - (portref (member s_axi_rdata 25) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined - (portref D (instanceref uart_rdat_reg_7_)) - (portref (member s_axi_rdata 24) (instanceref axi_uart_inst)) - ) - ) - (net s_axi_rvalid (joined - (portref I0 (instanceref RCS_0__i_1)) - (portref I0 (instanceref RCS_1__i_1)) - (portref I0 (instanceref uart_rdat_7__i_1)) - (portref I1 (instanceref RCS_2__i_1)) - (portref I1 (instanceref rdStat_i_1)) - (portref I2 (instanceref statReg_0__i_2)) - (portref s_axi_rvalid (instanceref axi_uart_inst)) - ) - ) - (net s_axi_wdata (joined - (portref CE (instanceref s_axi_wdata_reg_0_)) - (portref CE (instanceref s_axi_wdata_reg_1_)) - (portref CE (instanceref s_axi_wdata_reg_2_)) - (portref CE (instanceref s_axi_wdata_reg_3_)) - (portref CE (instanceref s_axi_wdata_reg_4_)) - (portref CE (instanceref s_axi_wdata_reg_5_)) - (portref CE (instanceref s_axi_wdata_reg_6_)) - (portref CE (instanceref s_axi_wstrb_reg_3_)) - (portref O (instanceref s_axi_wdata_4__i_1)) - ) - ) - (net (rename s_axi_wdata_0__i_1_n_0 "s_axi_wdata[0]_i_1_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_0_)) - (portref O (instanceref s_axi_wdata_0__i_1)) - ) - ) - (net (rename s_axi_wdata_0__i_2_n_0 "s_axi_wdata[0]_i_2_n_0") (joined - (portref I2 (instanceref s_axi_wdata_0__i_1)) - (portref O (instanceref s_axi_wdata_0__i_2)) - ) - ) - (net (rename s_axi_wdata_0__i_3_n_0 "s_axi_wdata[0]_i_3_n_0") (joined - (portref I3 (instanceref s_axi_wdata_0__i_1)) - (portref O (instanceref s_axi_wdata_0__i_3)) - ) - ) - (net (rename s_axi_wdata_0__i_4_n_0 "s_axi_wdata[0]_i_4_n_0") (joined - (portref I4 (instanceref s_axi_wdata_0__i_3)) - (portref O (instanceref s_axi_wdata_0__i_4)) - ) - ) - (net (rename s_axi_wdata_0__i_5_n_0 "s_axi_wdata[0]_i_5_n_0") (joined - (portref I5 (instanceref s_axi_wdata_0__i_4)) - (portref O (instanceref s_axi_wdata_0__i_5)) - ) - ) - (net (rename s_axi_wdata_1__i_1_n_0 "s_axi_wdata[1]_i_1_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_1_)) - (portref O (instanceref s_axi_wdata_1__i_1)) - ) - ) - (net (rename s_axi_wdata_1__i_2_n_0 "s_axi_wdata[1]_i_2_n_0") (joined - (portref I2 (instanceref s_axi_wdata_1__i_1)) - (portref O (instanceref s_axi_wdata_1__i_2)) - ) - ) - (net (rename s_axi_wdata_1__i_3_n_0 "s_axi_wdata[1]_i_3_n_0") (joined - (portref I3 (instanceref s_axi_wdata_1__i_1)) - (portref O (instanceref s_axi_wdata_1__i_3)) - ) - ) - (net (rename s_axi_wdata_1__i_4_n_0 "s_axi_wdata[1]_i_4_n_0") (joined - (portref I0 (instanceref s_axi_wdata_4__i_4)) - (portref I0 (instanceref s_axi_wdata_4__i_6)) - (portref I4 (instanceref s_axi_wdata_0__i_1)) - (portref I4 (instanceref s_axi_wdata_1__i_1)) - (portref I4 (instanceref s_axi_wdata_5__i_1)) - (portref I5 (instanceref s_axi_wdata_2__i_1)) - (portref I5 (instanceref s_axi_wdata_3__i_1)) - (portref O (instanceref s_axi_wdata_1__i_4)) - ) - ) - (net (rename s_axi_wdata_1__i_5_n_0 "s_axi_wdata[1]_i_5_n_0") (joined - (portref I4 (instanceref s_axi_wdata_1__i_3)) - (portref O (instanceref s_axi_wdata_1__i_5)) - ) - ) - (net (rename s_axi_wdata_1__i_6_n_0 "s_axi_wdata[1]_i_6_n_0") (joined - (portref I4 (instanceref s_axi_wdata_1__i_5)) - (portref O (instanceref s_axi_wdata_1__i_6)) - ) - ) - (net (rename s_axi_wdata_2__i_1_n_0 "s_axi_wdata[2]_i_1_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_2_)) - (portref O (instanceref s_axi_wdata_2__i_1)) - ) - ) - (net (rename s_axi_wdata_2__i_2_n_0 "s_axi_wdata[2]_i_2_n_0") (joined - (portref I1 (instanceref s_axi_wdata_2__i_1)) - (portref O (instanceref s_axi_wdata_2__i_2)) - ) - ) - (net (rename s_axi_wdata_2__i_3_n_0 "s_axi_wdata[2]_i_3_n_0") (joined - (portref I2 (instanceref s_axi_wdata_2__i_1)) - (portref O (instanceref s_axi_wdata_2__i_3)) - ) - ) - (net (rename s_axi_wdata_2__i_4_n_0 "s_axi_wdata[2]_i_4_n_0") (joined - (portref I3 (instanceref s_axi_wdata_2__i_1)) - (portref O (instanceref s_axi_wdata_2__i_4)) - ) - ) - (net (rename s_axi_wdata_2__i_5_n_0 "s_axi_wdata[2]_i_5_n_0") (joined - (portref I5 (instanceref s_axi_wdata_2__i_4)) - (portref O (instanceref s_axi_wdata_2__i_5)) - ) - ) - (net (rename s_axi_wdata_3__i_1_n_0 "s_axi_wdata[3]_i_1_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_3_)) - (portref O (instanceref s_axi_wdata_3__i_1)) - ) - ) - (net (rename s_axi_wdata_3__i_2_n_0 "s_axi_wdata[3]_i_2_n_0") (joined - (portref I1 (instanceref s_axi_wdata_3__i_1)) - (portref O (instanceref s_axi_wdata_3__i_2)) - ) - ) - (net (rename s_axi_wdata_3__i_3_n_0 "s_axi_wdata[3]_i_3_n_0") (joined - (portref I2 (instanceref s_axi_wdata_3__i_1)) - (portref O (instanceref s_axi_wdata_3__i_3)) - ) - ) - (net (rename s_axi_wdata_3__i_4_n_0 "s_axi_wdata[3]_i_4_n_0") (joined - (portref I3 (instanceref s_axi_wdata_3__i_1)) - (portref O (instanceref s_axi_wdata_3__i_4)) - ) - ) - (net (rename s_axi_wdata_3__i_5_n_0 "s_axi_wdata[3]_i_5_n_0") (joined - (portref I5 (instanceref s_axi_wdata_3__i_4)) - (portref O (instanceref s_axi_wdata_3__i_5)) - ) - ) - (net (rename s_axi_wdata_4__i_2_n_0 "s_axi_wdata[4]_i_2_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_4_)) - (portref O (instanceref s_axi_wdata_4__i_2)) - ) - ) - (net (rename s_axi_wdata_4__i_4_n_0 "s_axi_wdata[4]_i_4_n_0") (joined - (portref I0 (instanceref s_axi_wdata_2__i_1)) - (portref I0 (instanceref s_axi_wdata_3__i_1)) - (portref I0 (instanceref s_axi_wdata_5__i_1)) - (portref I1 (instanceref s_axi_wdata_0__i_1)) - (portref I1 (instanceref s_axi_wdata_1__i_1)) - (portref I1 (instanceref s_axi_wdata_4__i_2)) - (portref I2 (instanceref s_axi_wdata_6__i_2)) - (portref O (instanceref s_axi_wdata_4__i_4)) - ) - ) - (net (rename s_axi_wdata_4__i_5_n_0 "s_axi_wdata[4]_i_5_n_0") (joined - (portref I2 (instanceref s_axi_wdata_4__i_2)) - (portref O (instanceref s_axi_wdata_4__i_5)) - ) - ) - (net (rename s_axi_wdata_4__i_6_n_0 "s_axi_wdata[4]_i_6_n_0") (joined - (portref I3 (instanceref s_axi_wdata_4__i_2)) - (portref O (instanceref s_axi_wdata_4__i_6)) - ) - ) - (net (rename s_axi_wdata_4__i_7_n_0 "s_axi_wdata[4]_i_7_n_0") (joined - (portref I1 (instanceref s_axi_wdata_0__i_3)) - (portref I1 (instanceref s_axi_wdata_1__i_3)) - (portref I3 (instanceref s_axi_wdata_4__i_6)) - (portref O (instanceref s_axi_wdata_4__i_7)) - ) - ) - (net (rename s_axi_wdata_4__i_8_n_0 "s_axi_wdata[4]_i_8_n_0") (joined - (portref I0 (instanceref s_axi_wdata_0__i_3)) - (portref I0 (instanceref s_axi_wdata_1__i_3)) - (portref I5 (instanceref s_axi_wdata_4__i_6)) - (portref O (instanceref s_axi_wdata_4__i_8)) - ) - ) - (net (rename s_axi_wdata_5__i_1_n_0 "s_axi_wdata[5]_i_1_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_5_)) - (portref O (instanceref s_axi_wdata_5__i_1)) - ) - ) - (net (rename s_axi_wdata_5__i_2_n_0 "s_axi_wdata[5]_i_2_n_0") (joined - (portref I1 (instanceref s_axi_wdata_5__i_1)) - (portref O (instanceref s_axi_wdata_5__i_2)) - ) - ) - (net (rename s_axi_wdata_5__i_3_n_0 "s_axi_wdata[5]_i_3_n_0") (joined - (portref I2 (instanceref s_axi_wdata_5__i_1)) - (portref O (instanceref s_axi_wdata_5__i_3)) - ) - ) - (net (rename s_axi_wdata_5__i_4_n_0 "s_axi_wdata[5]_i_4_n_0") (joined - (portref I1 (instanceref s_axi_wdata_4__i_6)) - (portref I3 (instanceref s_axi_wdata_5__i_1)) - (portref O (instanceref s_axi_wdata_5__i_4)) - ) - ) - (net (rename s_axi_wdata_5__i_5_n_0 "s_axi_wdata[5]_i_5_n_0") (joined - (portref I2 (instanceref s_axi_wdata_5__i_4)) - (portref O (instanceref s_axi_wdata_5__i_5)) - ) - ) - (net (rename s_axi_wdata_5__i_6_n_0 "s_axi_wdata[5]_i_6_n_0") (joined - (portref I3 (instanceref s_axi_wdata_5__i_4)) - (portref O (instanceref s_axi_wdata_5__i_6)) - ) - ) - (net (rename s_axi_wdata_6__i_1_n_0 "s_axi_wdata[6]_i_1_n_0") (joined - (portref O (instanceref s_axi_wdata_6__i_1)) - (portref R (instanceref s_axi_wdata_reg_2_)) - (portref R (instanceref s_axi_wdata_reg_3_)) - (portref R (instanceref s_axi_wdata_reg_5_)) - (portref R (instanceref s_axi_wdata_reg_6_)) - ) - ) - (net (rename s_axi_wdata_6__i_2_n_0 "s_axi_wdata[6]_i_2_n_0") (joined - (portref D (instanceref s_axi_wdata_reg_6_)) - (portref O (instanceref s_axi_wdata_6__i_2)) - ) - ) - (net (rename s_axi_wdata_6__i_3_n_0 "s_axi_wdata[6]_i_3_n_0") (joined - (portref I0 (instanceref s_axi_wdata_6__i_2)) - (portref O (instanceref s_axi_wdata_6__i_3)) - ) - ) - (net (rename s_axi_wdata_6__i_4_n_0 "s_axi_wdata[6]_i_4_n_0") (joined - (portref I1 (instanceref s_axi_wdata_6__i_2)) - (portref O (instanceref s_axi_wdata_6__i_4)) - ) - ) - (net (rename s_axi_wdata_6__i_5_n_0 "s_axi_wdata[6]_i_5_n_0") (joined - (portref I4 (instanceref s_axi_wdata_6__i_2)) - (portref O (instanceref s_axi_wdata_6__i_5)) - ) - ) - (net (rename s_axi_wdata_6__i_6_n_0 "s_axi_wdata[6]_i_6_n_0") (joined - (portref I0 (instanceref s_axi_wdata_6__i_5)) - (portref O (instanceref s_axi_wdata_6__i_6)) - ) - ) - (net (rename s_axi_wdata_6__i_7_n_0 "s_axi_wdata[6]_i_7_n_0") (joined - (portref I5 (instanceref s_axi_wdata_6__i_5)) - (portref O (instanceref s_axi_wdata_6__i_7)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__0_ "s_axi_wdata_reg_n_0_[0]") (joined - (portref Q (instanceref s_axi_wdata_reg_0_)) - (portref (member s_axi_wdata 31) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__1_ "s_axi_wdata_reg_n_0_[1]") (joined - (portref Q (instanceref s_axi_wdata_reg_1_)) - (portref (member s_axi_wdata 30) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__2_ "s_axi_wdata_reg_n_0_[2]") (joined - (portref Q (instanceref s_axi_wdata_reg_2_)) - (portref (member s_axi_wdata 29) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__3_ "s_axi_wdata_reg_n_0_[3]") (joined - (portref Q (instanceref s_axi_wdata_reg_3_)) - (portref (member s_axi_wdata 28) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__4_ "s_axi_wdata_reg_n_0_[4]") (joined - (portref Q (instanceref s_axi_wdata_reg_4_)) - (portref (member s_axi_wdata 27) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__5_ "s_axi_wdata_reg_n_0_[5]") (joined - (portref Q (instanceref s_axi_wdata_reg_5_)) - (portref (member s_axi_wdata 26) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wdata_reg_n_0__6_ "s_axi_wdata_reg_n_0_[6]") (joined - (portref Q (instanceref s_axi_wdata_reg_6_)) - (portref (member s_axi_wdata 25) (instanceref axi_uart_inst)) - ) - ) - (net s_axi_wready (joined - (portref I0 (instanceref WCS_2__i_1)) - (portref I1 (instanceref WCS_1__i_1)) - (portref I1 (instanceref s_axi_awvalid_i_2)) - (portref s_axi_wready (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wstrb_3_ "s_axi_wstrb[3]") (joined - (portref Q (instanceref s_axi_wstrb_reg_3_)) - (portref (member s_axi_wstrb 3) (instanceref axi_uart_inst)) - (portref (member s_axi_wstrb 2) (instanceref axi_uart_inst)) - (portref (member s_axi_wstrb 1) (instanceref axi_uart_inst)) - (portref (member s_axi_wstrb 0) (instanceref axi_uart_inst)) - ) - ) - (net (rename s_axi_wstrb_3__i_1_n_0 "s_axi_wstrb[3]_i_1_n_0") (joined - (portref D (instanceref s_axi_wstrb_reg_3_)) - (portref I2 (instanceref WCS_0__i_1)) - (portref I2 (instanceref WCS_1__i_1)) - (portref O (instanceref s_axi_wstrb_3__i_1)) - ) - ) - (net s_axi_wvalid (joined - (portref I4 (instanceref s_axi_awvalid_i_1)) - (portref Q (instanceref s_axi_awvalid_reg)) - (portref s_axi_awvalid (instanceref axi_uart_inst)) - (portref s_axi_wvalid (instanceref axi_uart_inst)) - ) - ) - (net (rename statReg_0__i_1_n_0 "statReg[0]_i_1_n_0") (joined - (portref D (instanceref statReg_reg_0_)) - (portref O (instanceref statReg_0__i_1)) - ) - ) - (net (rename statReg_0__i_2_n_0 "statReg[0]_i_2_n_0") (joined - (portref I1 (instanceref statReg_0__i_1)) - (portref O (instanceref statReg_0__i_2)) - ) - ) - (net (rename statReg_reg_n_0__0_ "statReg_reg_n_0_[0]") (joined - (portref I1 (instanceref RCS_1__i_1)) - (portref I1 (instanceref bn_ascii_62__i_1)) - (portref I1 (instanceref byte_len_7__i_1)) - (portref I1 (instanceref byte_num_31__i_1)) - (portref I1 (instanceref disp_0__i_1)) - (portref I1 (instanceref s_axi_arvalid_i_3)) - (portref I2 (instanceref byte_cnt_31__i_1)) - (portref I2 (instanceref disp_1__i_1)) - (portref I2 (instanceref disp_2__i_2)) - (portref I2 (instanceref disp_3__i_1)) - (portref I2 (instanceref disp_4__i_1)) - (portref I2 (instanceref recv_done_i_1)) - (portref I3 (instanceref disp_5__i_1)) - (portref I4 (instanceref disp_6__i_1)) - (portref I4 (instanceref disp_6__i_2)) - (portref I4 (instanceref disp_7__i_1)) - (portref I4 (instanceref rdStat_i_1)) - (portref I4 (instanceref statReg_0__i_1)) - (portref Q (instanceref statReg_reg_0_)) - ) - ) - (net uart_rdat (joined - (portref CE (instanceref uart_rdat_reg_0_)) - (portref CE (instanceref uart_rdat_reg_1_)) - (portref CE (instanceref uart_rdat_reg_2_)) - (portref CE (instanceref uart_rdat_reg_3_)) - (portref CE (instanceref uart_rdat_reg_4_)) - (portref CE (instanceref uart_rdat_reg_5_)) - (portref CE (instanceref uart_rdat_reg_6_)) - (portref CE (instanceref uart_rdat_reg_7_)) - (portref O (instanceref uart_rdat_7__i_1)) - ) - ) - (net (rename uart_rdat_reg_n_0__0_ "uart_rdat_reg_n_0_[0]") (joined - (portref D (instanceref byte_len_reg_0_)) - (portref D (instanceref byte_num_reg_0_)) - (portref D (instanceref dbuf_reg_0_)) - (portref D (instanceref upg_dat_o_reg_0_)) - (portref I0 (instanceref bn_ascii_0__i_1)) - (portref I0 (instanceref bn_ascii_1__i_1)) - (portref I3 (instanceref bn_ascii_2__i_1)) - (portref I5 (instanceref wr_byte_len_done_i_1)) - (portref Q (instanceref uart_rdat_reg_0_)) - ) - ) - (net (rename uart_rdat_reg_n_0__1_ "uart_rdat_reg_n_0_[1]") (joined - (portref D (instanceref byte_len_reg_1_)) - (portref D (instanceref byte_num_reg_1_)) - (portref D (instanceref dbuf_reg_1_)) - (portref D (instanceref upg_dat_o_reg_1_)) - (portref I0 (instanceref bn_ascii_2__i_1)) - (portref I0 (instanceref bn_ascii_5__i_1)) - (portref I1 (instanceref bn_ascii_0__i_1)) - (portref I2 (instanceref bn_ascii_3__i_1)) - (portref I2 (instanceref bn_ascii_6__i_1)) - (portref I3 (instanceref bn_ascii_1__i_1)) - (portref I3 (instanceref wr_byte_len_done_i_2)) - (portref Q (instanceref uart_rdat_reg_1_)) - ) - ) - (net (rename uart_rdat_reg_n_0__2_ "uart_rdat_reg_n_0_[2]") (joined - (portref D (instanceref byte_len_reg_2_)) - (portref D (instanceref byte_num_reg_2_)) - (portref D (instanceref dbuf_reg_2_)) - (portref D (instanceref upg_dat_o_reg_2_)) - (portref I1 (instanceref bn_ascii_2__i_1)) - (portref I1 (instanceref bn_ascii_3__i_1)) - (portref I1 (instanceref bn_ascii_5__i_1)) - (portref I1 (instanceref bn_ascii_6__i_1)) - (portref I2 (instanceref bn_ascii_0__i_1)) - (portref I2 (instanceref bn_ascii_1__i_1)) - (portref I2 (instanceref wr_byte_len_done_i_2)) - (portref Q (instanceref uart_rdat_reg_2_)) - ) - ) - (net (rename uart_rdat_reg_n_0__3_ "uart_rdat_reg_n_0_[3]") (joined - (portref D (instanceref byte_len_reg_3_)) - (portref D (instanceref byte_num_reg_3_)) - (portref D (instanceref dbuf_reg_3_)) - (portref D (instanceref upg_dat_o_reg_3_)) - (portref I0 (instanceref bn_ascii_3__i_1)) - (portref I0 (instanceref bn_ascii_6__i_1)) - (portref I1 (instanceref bn_ascii_1__i_1)) - (portref I2 (instanceref bn_ascii_2__i_1)) - (portref I2 (instanceref bn_ascii_5__i_1)) - (portref I3 (instanceref bn_ascii_0__i_1)) - (portref I3 (instanceref wr_byte_len_done_i_1)) - (portref Q (instanceref uart_rdat_reg_3_)) - ) - ) - (net (rename uart_rdat_reg_n_0__4_ "uart_rdat_reg_n_0_[4]") (joined - (portref D (instanceref byte_len_reg_4_)) - (portref D (instanceref byte_num_reg_4_)) - (portref D (instanceref dbuf_reg_4_)) - (portref D (instanceref upg_dat_o_reg_4_)) - (portref I0 (instanceref bn_ascii_8__i_1)) - (portref I0 (instanceref bn_ascii_9__i_1)) - (portref I2 (instanceref wr_byte_len_done_i_1)) - (portref I3 (instanceref bn_ascii_10__i_1)) - (portref Q (instanceref uart_rdat_reg_4_)) - ) - ) - (net (rename uart_rdat_reg_n_0__5_ "uart_rdat_reg_n_0_[5]") (joined - (portref D (instanceref byte_len_reg_5_)) - (portref D (instanceref byte_num_reg_5_)) - (portref D (instanceref dbuf_reg_5_)) - (portref D (instanceref upg_dat_o_reg_5_)) - (portref I0 (instanceref bn_ascii_10__i_1)) - (portref I0 (instanceref bn_ascii_13__i_1)) - (portref I1 (instanceref bn_ascii_8__i_1)) - (portref I1 (instanceref wr_byte_len_done_i_2)) - (portref I2 (instanceref bn_ascii_11__i_1)) - (portref I2 (instanceref bn_ascii_14__i_1)) - (portref I3 (instanceref bn_ascii_9__i_1)) - (portref Q (instanceref uart_rdat_reg_5_)) - ) - ) - (net (rename uart_rdat_reg_n_0__6_ "uart_rdat_reg_n_0_[6]") (joined - (portref D (instanceref byte_len_reg_6_)) - (portref D (instanceref byte_num_reg_6_)) - (portref D (instanceref dbuf_reg_6_)) - (portref D (instanceref upg_dat_o_reg_6_)) - (portref I0 (instanceref wr_byte_len_done_i_2)) - (portref I1 (instanceref bn_ascii_10__i_1)) - (portref I1 (instanceref bn_ascii_11__i_1)) - (portref I1 (instanceref bn_ascii_13__i_1)) - (portref I1 (instanceref bn_ascii_14__i_1)) - (portref I2 (instanceref bn_ascii_8__i_1)) - (portref I2 (instanceref bn_ascii_9__i_1)) - (portref Q (instanceref uart_rdat_reg_6_)) - ) - ) - (net (rename uart_rdat_reg_n_0__7_ "uart_rdat_reg_n_0_[7]") (joined - (portref D (instanceref byte_len_reg_7_)) - (portref D (instanceref byte_num_reg_7_)) - (portref D (instanceref dbuf_reg_7_)) - (portref D (instanceref upg_dat_o_reg_7_)) - (portref I0 (instanceref bn_ascii_11__i_1)) - (portref I0 (instanceref bn_ascii_14__i_1)) - (portref I1 (instanceref bn_ascii_9__i_1)) - (portref I2 (instanceref bn_ascii_10__i_1)) - (portref I2 (instanceref bn_ascii_13__i_1)) - (portref I3 (instanceref bn_ascii_8__i_1)) - (portref I4 (instanceref wr_byte_len_done_i_1)) - (portref Q (instanceref uart_rdat_reg_7_)) - ) - ) - (net uart_wen5_out (joined - (portref I0 (instanceref msg_indx_7__i_1)) - (portref I0 (instanceref uart_wen_i_1)) - (portref I1 (instanceref s_axi_awvalid_i_1)) - (portref I3 (instanceref s_axi_wdata_4__i_1)) - (portref O (instanceref s_axi_wdata_4__i_3)) - ) - ) - (net uart_wen_i_1_n_0 (joined - (portref D (instanceref uart_wen_reg)) - (portref O (instanceref uart_wen_i_1)) - ) - ) - (net uart_wen_reg_n_0 (joined - (portref I1 (instanceref s_axi_wdata_4__i_3)) - (portref I2 (instanceref s_axi_wstrb_3__i_1)) - (portref I5 (instanceref uart_wen_i_1)) - (portref Q (instanceref uart_wen_reg)) - ) - ) - (net (rename upg_adr_o_0_ "upg_adr_o[0]") (joined - (portref O (instanceref upg_adr_o_OBUF_0__inst)) - (portref (member upg_adr_o 14)) - ) - ) - (net (rename upg_adr_o_10_ "upg_adr_o[10]") (joined - (portref O (instanceref upg_adr_o_OBUF_10__inst)) - (portref (member upg_adr_o 4)) - ) - ) - (net (rename upg_adr_o_11_ "upg_adr_o[11]") (joined - (portref O (instanceref upg_adr_o_OBUF_11__inst)) - (portref (member upg_adr_o 3)) - ) - ) - (net (rename upg_adr_o_12_ "upg_adr_o[12]") (joined - (portref O (instanceref upg_adr_o_OBUF_12__inst)) - (portref (member upg_adr_o 2)) - ) - ) - (net (rename upg_adr_o_13_ "upg_adr_o[13]") (joined - (portref O (instanceref upg_adr_o_OBUF_13__inst)) - (portref (member upg_adr_o 1)) - ) - ) - (net (rename upg_adr_o_14_ "upg_adr_o[14]") (joined - (portref O (instanceref upg_adr_o_OBUF_14__inst)) - (portref (member upg_adr_o 0)) - ) - ) - (net (rename upg_adr_o_14__i_1_n_0 "upg_adr_o[14]_i_1_n_0") (joined - (portref CE (instanceref upg_adr_o_reg_0_)) - (portref CE (instanceref upg_adr_o_reg_10_)) - (portref CE (instanceref upg_adr_o_reg_11_)) - (portref CE (instanceref upg_adr_o_reg_12_)) - (portref CE (instanceref upg_adr_o_reg_13_)) - (portref CE (instanceref upg_adr_o_reg_14_)) - (portref CE (instanceref upg_adr_o_reg_1_)) - (portref CE (instanceref upg_adr_o_reg_2_)) - (portref CE (instanceref upg_adr_o_reg_3_)) - (portref CE (instanceref upg_adr_o_reg_4_)) - (portref CE (instanceref upg_adr_o_reg_5_)) - (portref CE (instanceref upg_adr_o_reg_6_)) - (portref CE (instanceref upg_adr_o_reg_7_)) - (portref CE (instanceref upg_adr_o_reg_8_)) - (portref CE (instanceref upg_adr_o_reg_9_)) - (portref CE (instanceref upg_dat_o_reg_0_)) - (portref CE (instanceref upg_dat_o_reg_10_)) - (portref CE (instanceref upg_dat_o_reg_11_)) - (portref CE (instanceref upg_dat_o_reg_12_)) - (portref CE (instanceref upg_dat_o_reg_13_)) - (portref CE (instanceref upg_dat_o_reg_14_)) - (portref CE (instanceref upg_dat_o_reg_15_)) - (portref CE (instanceref upg_dat_o_reg_16_)) - (portref CE (instanceref upg_dat_o_reg_17_)) - (portref CE (instanceref upg_dat_o_reg_18_)) - (portref CE (instanceref upg_dat_o_reg_19_)) - (portref CE (instanceref upg_dat_o_reg_1_)) - (portref CE (instanceref upg_dat_o_reg_20_)) - (portref CE (instanceref upg_dat_o_reg_21_)) - (portref CE (instanceref upg_dat_o_reg_22_)) - (portref CE (instanceref upg_dat_o_reg_23_)) - (portref CE (instanceref upg_dat_o_reg_24_)) - (portref CE (instanceref upg_dat_o_reg_25_)) - (portref CE (instanceref upg_dat_o_reg_26_)) - (portref CE (instanceref upg_dat_o_reg_27_)) - (portref CE (instanceref upg_dat_o_reg_28_)) - (portref CE (instanceref upg_dat_o_reg_29_)) - (portref CE (instanceref upg_dat_o_reg_2_)) - (portref CE (instanceref upg_dat_o_reg_30_)) - (portref CE (instanceref upg_dat_o_reg_31_)) - (portref CE (instanceref upg_dat_o_reg_3_)) - (portref CE (instanceref upg_dat_o_reg_4_)) - (portref CE (instanceref upg_dat_o_reg_5_)) - (portref CE (instanceref upg_dat_o_reg_6_)) - (portref CE (instanceref upg_dat_o_reg_7_)) - (portref CE (instanceref upg_dat_o_reg_8_)) - (portref CE (instanceref upg_dat_o_reg_9_)) - (portref O (instanceref upg_adr_o_14__i_1)) - ) - ) - (net (rename upg_adr_o_1_ "upg_adr_o[1]") (joined - (portref O (instanceref upg_adr_o_OBUF_1__inst)) - (portref (member upg_adr_o 13)) - ) - ) - (net (rename upg_adr_o_2_ "upg_adr_o[2]") (joined - (portref O (instanceref upg_adr_o_OBUF_2__inst)) - (portref (member upg_adr_o 12)) - ) - ) - (net (rename upg_adr_o_3_ "upg_adr_o[3]") (joined - (portref O (instanceref upg_adr_o_OBUF_3__inst)) - (portref (member upg_adr_o 11)) - ) - ) - (net (rename upg_adr_o_4_ "upg_adr_o[4]") (joined - (portref O (instanceref upg_adr_o_OBUF_4__inst)) - (portref (member upg_adr_o 10)) - ) - ) - (net (rename upg_adr_o_5_ "upg_adr_o[5]") (joined - (portref O (instanceref upg_adr_o_OBUF_5__inst)) - (portref (member upg_adr_o 9)) - ) - ) - (net (rename upg_adr_o_6_ "upg_adr_o[6]") (joined - (portref O (instanceref upg_adr_o_OBUF_6__inst)) - (portref (member upg_adr_o 8)) - ) - ) - (net (rename upg_adr_o_7_ "upg_adr_o[7]") (joined - (portref O (instanceref upg_adr_o_OBUF_7__inst)) - (portref (member upg_adr_o 7)) - ) - ) - (net (rename upg_adr_o_8_ "upg_adr_o[8]") (joined - (portref O (instanceref upg_adr_o_OBUF_8__inst)) - (portref (member upg_adr_o 6)) - ) - ) - (net (rename upg_adr_o_9_ "upg_adr_o[9]") (joined - (portref O (instanceref upg_adr_o_OBUF_9__inst)) - (portref (member upg_adr_o 5)) - ) - ) - (net (rename upg_adr_o_OBUF_0_ "upg_adr_o_OBUF[0]") (joined - (portref I (instanceref upg_adr_o_OBUF_0__inst)) - (portref Q (instanceref upg_adr_o_reg_0_)) - ) - ) - (net (rename upg_adr_o_OBUF_10_ "upg_adr_o_OBUF[10]") (joined - (portref I (instanceref upg_adr_o_OBUF_10__inst)) - (portref Q (instanceref upg_adr_o_reg_10_)) - ) - ) - (net (rename upg_adr_o_OBUF_11_ "upg_adr_o_OBUF[11]") (joined - (portref I (instanceref upg_adr_o_OBUF_11__inst)) - (portref Q (instanceref upg_adr_o_reg_11_)) - ) - ) - (net (rename upg_adr_o_OBUF_12_ "upg_adr_o_OBUF[12]") (joined - (portref I (instanceref upg_adr_o_OBUF_12__inst)) - (portref Q (instanceref upg_adr_o_reg_12_)) - ) - ) - (net (rename upg_adr_o_OBUF_13_ "upg_adr_o_OBUF[13]") (joined - (portref I (instanceref upg_adr_o_OBUF_13__inst)) - (portref Q (instanceref upg_adr_o_reg_13_)) - ) - ) - (net (rename upg_adr_o_OBUF_14_ "upg_adr_o_OBUF[14]") (joined - (portref I (instanceref upg_adr_o_OBUF_14__inst)) - (portref Q (instanceref upg_adr_o_reg_14_)) - ) - ) - (net (rename upg_adr_o_OBUF_1_ "upg_adr_o_OBUF[1]") (joined - (portref I (instanceref upg_adr_o_OBUF_1__inst)) - (portref Q (instanceref upg_adr_o_reg_1_)) - ) - ) - (net (rename upg_adr_o_OBUF_2_ "upg_adr_o_OBUF[2]") (joined - (portref I (instanceref upg_adr_o_OBUF_2__inst)) - (portref Q (instanceref upg_adr_o_reg_2_)) - ) - ) - (net (rename upg_adr_o_OBUF_3_ "upg_adr_o_OBUF[3]") (joined - (portref I (instanceref upg_adr_o_OBUF_3__inst)) - (portref Q (instanceref upg_adr_o_reg_3_)) - ) - ) - (net (rename upg_adr_o_OBUF_4_ "upg_adr_o_OBUF[4]") (joined - (portref I (instanceref upg_adr_o_OBUF_4__inst)) - (portref Q (instanceref upg_adr_o_reg_4_)) - ) - ) - (net (rename upg_adr_o_OBUF_5_ "upg_adr_o_OBUF[5]") (joined - (portref I (instanceref upg_adr_o_OBUF_5__inst)) - (portref Q (instanceref upg_adr_o_reg_5_)) - ) - ) - (net (rename upg_adr_o_OBUF_6_ "upg_adr_o_OBUF[6]") (joined - (portref I (instanceref upg_adr_o_OBUF_6__inst)) - (portref Q (instanceref upg_adr_o_reg_6_)) - ) - ) - (net (rename upg_adr_o_OBUF_7_ "upg_adr_o_OBUF[7]") (joined - (portref I (instanceref upg_adr_o_OBUF_7__inst)) - (portref Q (instanceref upg_adr_o_reg_7_)) - ) - ) - (net (rename upg_adr_o_OBUF_8_ "upg_adr_o_OBUF[8]") (joined - (portref I (instanceref upg_adr_o_OBUF_8__inst)) - (portref Q (instanceref upg_adr_o_reg_8_)) - ) - ) - (net (rename upg_adr_o_OBUF_9_ "upg_adr_o_OBUF[9]") (joined - (portref I (instanceref upg_adr_o_OBUF_9__inst)) - (portref Q (instanceref upg_adr_o_reg_9_)) - ) - ) - (net upg_clk_i (joined - (portref I (instanceref upg_clk_i_IBUF_inst)) - (portref upg_clk_i) - ) - ) - (net upg_clk_i_IBUF (joined - (portref I (instanceref upg_clk_i_IBUF_BUFG_inst)) - (portref O (instanceref upg_clk_i_IBUF_inst)) - ) - ) - (net upg_clk_i_IBUF_BUFG (joined - (portref C (instanceref RCS_reg_0_)) - (portref C (instanceref RCS_reg_1_)) - (portref C (instanceref RCS_reg_2_)) - (portref C (instanceref WCS_reg_0_)) - (portref C (instanceref WCS_reg_1_)) - (portref C (instanceref WCS_reg_2_)) - (portref C (instanceref initFlag_reg)) - (portref C (instanceref msg_indx_reg_0_)) - (portref C (instanceref msg_indx_reg_1_)) - (portref C (instanceref msg_indx_reg_2_)) - (portref C (instanceref msg_indx_reg_3_)) - (portref C (instanceref msg_indx_reg_4_)) - (portref C (instanceref msg_indx_reg_5_)) - (portref C (instanceref msg_indx_reg_6_)) - (portref C (instanceref msg_indx_reg_7_)) - (portref C (instanceref oldInitF_reg)) - (portref C (instanceref rdStat_reg)) - (portref C (instanceref rwait_cnt_reg_0_)) - (portref C (instanceref rwait_cnt_reg_10_)) - (portref C (instanceref rwait_cnt_reg_11_)) - (portref C (instanceref rwait_cnt_reg_12_)) - (portref C (instanceref rwait_cnt_reg_13_)) - (portref C (instanceref rwait_cnt_reg_14_)) - (portref C (instanceref rwait_cnt_reg_15_)) - (portref C (instanceref rwait_cnt_reg_1_)) - (portref C (instanceref rwait_cnt_reg_2_)) - (portref C (instanceref rwait_cnt_reg_3_)) - (portref C (instanceref rwait_cnt_reg_4_)) - (portref C (instanceref rwait_cnt_reg_5_)) - (portref C (instanceref rwait_cnt_reg_6_)) - (portref C (instanceref rwait_cnt_reg_7_)) - (portref C (instanceref rwait_cnt_reg_8_)) - (portref C (instanceref rwait_cnt_reg_9_)) - (portref C (instanceref s_axi_araddr_reg_3_)) - (portref C (instanceref s_axi_arvalid_reg)) - (portref C (instanceref s_axi_awaddr_reg_3_)) - (portref C (instanceref s_axi_awvalid_reg)) - (portref C (instanceref s_axi_wdata_reg_0_)) - (portref C (instanceref s_axi_wdata_reg_1_)) - (portref C (instanceref s_axi_wdata_reg_2_)) - (portref C (instanceref s_axi_wdata_reg_3_)) - (portref C (instanceref s_axi_wdata_reg_4_)) - (portref C (instanceref s_axi_wdata_reg_5_)) - (portref C (instanceref s_axi_wdata_reg_6_)) - (portref C (instanceref s_axi_wstrb_reg_3_)) - (portref C (instanceref statReg_reg_0_)) - (portref C (instanceref uart_rdat_reg_0_)) - (portref C (instanceref uart_rdat_reg_1_)) - (portref C (instanceref uart_rdat_reg_2_)) - (portref C (instanceref uart_rdat_reg_3_)) - (portref C (instanceref uart_rdat_reg_4_)) - (portref C (instanceref uart_rdat_reg_5_)) - (portref C (instanceref uart_rdat_reg_6_)) - (portref C (instanceref uart_rdat_reg_7_)) - (portref C (instanceref uart_wen_reg)) - (portref C (instanceref upg_done_o_reg)) - (portref C (instanceref wwait_cnt_reg_0_)) - (portref C (instanceref wwait_cnt_reg_10_)) - (portref C (instanceref wwait_cnt_reg_11_)) - (portref C (instanceref wwait_cnt_reg_12_)) - (portref C (instanceref wwait_cnt_reg_13_)) - (portref C (instanceref wwait_cnt_reg_14_)) - (portref C (instanceref wwait_cnt_reg_15_)) - (portref C (instanceref wwait_cnt_reg_1_)) - (portref C (instanceref wwait_cnt_reg_2_)) - (portref C (instanceref wwait_cnt_reg_3_)) - (portref C (instanceref wwait_cnt_reg_4_)) - (portref C (instanceref wwait_cnt_reg_5_)) - (portref C (instanceref wwait_cnt_reg_6_)) - (portref C (instanceref wwait_cnt_reg_7_)) - (portref C (instanceref wwait_cnt_reg_8_)) - (portref C (instanceref wwait_cnt_reg_9_)) - (portref O (instanceref upg_clk_i_IBUF_BUFG_inst)) - (portref s_axi_aclk (instanceref axi_uart_inst)) - ) - ) - (net upg_clk_o (joined - (portref O (instanceref upg_clk_o_OBUF_inst)) - (portref upg_clk_o) - ) - ) - (net upg_clk_o_OBUF (joined - (portref I (instanceref upg_clk_o_OBUF_inst)) - (portref O (instanceref upg_clk_o_OBUF_inst_i_1)) - ) - ) - (net upg_clk_o_OBUF_inst_i_2_n_0 (joined - (portref I0 (instanceref upg_wen_o_i_5)) - (portref I1 (instanceref upg_clk_o_OBUF_inst_i_1)) - (portref I2 (instanceref disp_1__i_3)) - (portref I2 (instanceref disp_7__i_3)) - (portref I3 (instanceref disp_1__i_2)) - (portref I3 (instanceref disp_6__i_3)) - (portref O (instanceref upg_clk_o_OBUF_inst_i_2)) - ) - ) - (net (rename upg_dat_o_0_ "upg_dat_o[0]") (joined - (portref O (instanceref upg_dat_o_OBUF_0__inst)) - (portref (member upg_dat_o 31)) - ) - ) - (net (rename upg_dat_o_10_ "upg_dat_o[10]") (joined - (portref O (instanceref upg_dat_o_OBUF_10__inst)) - (portref (member upg_dat_o 21)) - ) - ) - (net (rename upg_dat_o_11_ "upg_dat_o[11]") (joined - (portref O (instanceref upg_dat_o_OBUF_11__inst)) - (portref (member upg_dat_o 20)) - ) - ) - (net (rename upg_dat_o_12_ "upg_dat_o[12]") (joined - (portref O (instanceref upg_dat_o_OBUF_12__inst)) - (portref (member upg_dat_o 19)) - ) - ) - (net (rename upg_dat_o_13_ "upg_dat_o[13]") (joined - (portref O (instanceref upg_dat_o_OBUF_13__inst)) - (portref (member upg_dat_o 18)) - ) - ) - (net (rename upg_dat_o_14_ "upg_dat_o[14]") (joined - (portref O (instanceref upg_dat_o_OBUF_14__inst)) - (portref (member upg_dat_o 17)) - ) - ) - (net (rename upg_dat_o_15_ "upg_dat_o[15]") (joined - (portref O (instanceref upg_dat_o_OBUF_15__inst)) - (portref (member upg_dat_o 16)) - ) - ) - (net (rename upg_dat_o_16_ "upg_dat_o[16]") (joined - (portref O (instanceref upg_dat_o_OBUF_16__inst)) - (portref (member upg_dat_o 15)) - ) - ) - (net (rename upg_dat_o_17_ "upg_dat_o[17]") (joined - (portref O (instanceref upg_dat_o_OBUF_17__inst)) - (portref (member upg_dat_o 14)) - ) - ) - (net (rename upg_dat_o_18_ "upg_dat_o[18]") (joined - (portref O (instanceref upg_dat_o_OBUF_18__inst)) - (portref (member upg_dat_o 13)) - ) - ) - (net (rename upg_dat_o_19_ "upg_dat_o[19]") (joined - (portref O (instanceref upg_dat_o_OBUF_19__inst)) - (portref (member upg_dat_o 12)) - ) - ) - (net (rename upg_dat_o_1_ "upg_dat_o[1]") (joined - (portref O (instanceref upg_dat_o_OBUF_1__inst)) - (portref (member upg_dat_o 30)) - ) - ) - (net (rename upg_dat_o_20_ "upg_dat_o[20]") (joined - (portref O (instanceref upg_dat_o_OBUF_20__inst)) - (portref (member upg_dat_o 11)) - ) - ) - (net (rename upg_dat_o_21_ "upg_dat_o[21]") (joined - (portref O (instanceref upg_dat_o_OBUF_21__inst)) - (portref (member upg_dat_o 10)) - ) - ) - (net (rename upg_dat_o_22_ "upg_dat_o[22]") (joined - (portref O (instanceref upg_dat_o_OBUF_22__inst)) - (portref (member upg_dat_o 9)) - ) - ) - (net (rename upg_dat_o_23_ "upg_dat_o[23]") (joined - (portref O (instanceref upg_dat_o_OBUF_23__inst)) - (portref (member upg_dat_o 8)) - ) - ) - (net (rename upg_dat_o_24_ "upg_dat_o[24]") (joined - (portref O (instanceref upg_dat_o_OBUF_24__inst)) - (portref (member upg_dat_o 7)) - ) - ) - (net (rename upg_dat_o_25_ "upg_dat_o[25]") (joined - (portref O (instanceref upg_dat_o_OBUF_25__inst)) - (portref (member upg_dat_o 6)) - ) - ) - (net (rename upg_dat_o_26_ "upg_dat_o[26]") (joined - (portref O (instanceref upg_dat_o_OBUF_26__inst)) - (portref (member upg_dat_o 5)) - ) - ) - (net (rename upg_dat_o_27_ "upg_dat_o[27]") (joined - (portref O (instanceref upg_dat_o_OBUF_27__inst)) - (portref (member upg_dat_o 4)) - ) - ) - (net (rename upg_dat_o_28_ "upg_dat_o[28]") (joined - (portref O (instanceref upg_dat_o_OBUF_28__inst)) - (portref (member upg_dat_o 3)) - ) - ) - (net (rename upg_dat_o_29_ "upg_dat_o[29]") (joined - (portref O (instanceref upg_dat_o_OBUF_29__inst)) - (portref (member upg_dat_o 2)) - ) - ) - (net (rename upg_dat_o_2_ "upg_dat_o[2]") (joined - (portref O (instanceref upg_dat_o_OBUF_2__inst)) - (portref (member upg_dat_o 29)) - ) - ) - (net (rename upg_dat_o_30_ "upg_dat_o[30]") (joined - (portref O (instanceref upg_dat_o_OBUF_30__inst)) - (portref (member upg_dat_o 1)) - ) - ) - (net (rename upg_dat_o_31_ "upg_dat_o[31]") (joined - (portref O (instanceref upg_dat_o_OBUF_31__inst)) - (portref (member upg_dat_o 0)) - ) - ) - (net (rename upg_dat_o_3_ "upg_dat_o[3]") (joined - (portref O (instanceref upg_dat_o_OBUF_3__inst)) - (portref (member upg_dat_o 28)) - ) - ) - (net (rename upg_dat_o_4_ "upg_dat_o[4]") (joined - (portref O (instanceref upg_dat_o_OBUF_4__inst)) - (portref (member upg_dat_o 27)) - ) - ) - (net (rename upg_dat_o_5_ "upg_dat_o[5]") (joined - (portref O (instanceref upg_dat_o_OBUF_5__inst)) - (portref (member upg_dat_o 26)) - ) - ) - (net (rename upg_dat_o_6_ "upg_dat_o[6]") (joined - (portref O (instanceref upg_dat_o_OBUF_6__inst)) - (portref (member upg_dat_o 25)) - ) - ) - (net (rename upg_dat_o_7_ "upg_dat_o[7]") (joined - (portref O (instanceref upg_dat_o_OBUF_7__inst)) - (portref (member upg_dat_o 24)) - ) - ) - (net (rename upg_dat_o_8_ "upg_dat_o[8]") (joined - (portref O (instanceref upg_dat_o_OBUF_8__inst)) - (portref (member upg_dat_o 23)) - ) - ) - (net (rename upg_dat_o_9_ "upg_dat_o[9]") (joined - (portref O (instanceref upg_dat_o_OBUF_9__inst)) - (portref (member upg_dat_o 22)) - ) - ) - (net (rename upg_dat_o_OBUF_0_ "upg_dat_o_OBUF[0]") (joined - (portref I (instanceref upg_dat_o_OBUF_0__inst)) - (portref Q (instanceref upg_dat_o_reg_0_)) - ) - ) - (net (rename upg_dat_o_OBUF_10_ "upg_dat_o_OBUF[10]") (joined - (portref I (instanceref upg_dat_o_OBUF_10__inst)) - (portref Q (instanceref upg_dat_o_reg_10_)) - ) - ) - (net (rename upg_dat_o_OBUF_11_ "upg_dat_o_OBUF[11]") (joined - (portref I (instanceref upg_dat_o_OBUF_11__inst)) - (portref Q (instanceref upg_dat_o_reg_11_)) - ) - ) - (net (rename upg_dat_o_OBUF_12_ "upg_dat_o_OBUF[12]") (joined - (portref I (instanceref upg_dat_o_OBUF_12__inst)) - (portref Q (instanceref upg_dat_o_reg_12_)) - ) - ) - (net (rename upg_dat_o_OBUF_13_ "upg_dat_o_OBUF[13]") (joined - (portref I (instanceref upg_dat_o_OBUF_13__inst)) - (portref Q (instanceref upg_dat_o_reg_13_)) - ) - ) - (net (rename upg_dat_o_OBUF_14_ "upg_dat_o_OBUF[14]") (joined - (portref I (instanceref upg_dat_o_OBUF_14__inst)) - (portref Q (instanceref upg_dat_o_reg_14_)) - ) - ) - (net (rename upg_dat_o_OBUF_15_ "upg_dat_o_OBUF[15]") (joined - (portref I (instanceref upg_dat_o_OBUF_15__inst)) - (portref Q (instanceref upg_dat_o_reg_15_)) - ) - ) - (net (rename upg_dat_o_OBUF_16_ "upg_dat_o_OBUF[16]") (joined - (portref I (instanceref upg_dat_o_OBUF_16__inst)) - (portref Q (instanceref upg_dat_o_reg_16_)) - ) - ) - (net (rename upg_dat_o_OBUF_17_ "upg_dat_o_OBUF[17]") (joined - (portref I (instanceref upg_dat_o_OBUF_17__inst)) - (portref Q (instanceref upg_dat_o_reg_17_)) - ) - ) - (net (rename upg_dat_o_OBUF_18_ "upg_dat_o_OBUF[18]") (joined - (portref I (instanceref upg_dat_o_OBUF_18__inst)) - (portref Q (instanceref upg_dat_o_reg_18_)) - ) - ) - (net (rename upg_dat_o_OBUF_19_ "upg_dat_o_OBUF[19]") (joined - (portref I (instanceref upg_dat_o_OBUF_19__inst)) - (portref Q (instanceref upg_dat_o_reg_19_)) - ) - ) - (net (rename upg_dat_o_OBUF_1_ "upg_dat_o_OBUF[1]") (joined - (portref I (instanceref upg_dat_o_OBUF_1__inst)) - (portref Q (instanceref upg_dat_o_reg_1_)) - ) - ) - (net (rename upg_dat_o_OBUF_20_ "upg_dat_o_OBUF[20]") (joined - (portref I (instanceref upg_dat_o_OBUF_20__inst)) - (portref Q (instanceref upg_dat_o_reg_20_)) - ) - ) - (net (rename upg_dat_o_OBUF_21_ "upg_dat_o_OBUF[21]") (joined - (portref I (instanceref upg_dat_o_OBUF_21__inst)) - (portref Q (instanceref upg_dat_o_reg_21_)) - ) - ) - (net (rename upg_dat_o_OBUF_22_ "upg_dat_o_OBUF[22]") (joined - (portref I (instanceref upg_dat_o_OBUF_22__inst)) - (portref Q (instanceref upg_dat_o_reg_22_)) - ) - ) - (net (rename upg_dat_o_OBUF_23_ "upg_dat_o_OBUF[23]") (joined - (portref I (instanceref upg_dat_o_OBUF_23__inst)) - (portref Q (instanceref upg_dat_o_reg_23_)) - ) - ) - (net (rename upg_dat_o_OBUF_24_ "upg_dat_o_OBUF[24]") (joined - (portref I (instanceref upg_dat_o_OBUF_24__inst)) - (portref Q (instanceref upg_dat_o_reg_24_)) - ) - ) - (net (rename upg_dat_o_OBUF_25_ "upg_dat_o_OBUF[25]") (joined - (portref I (instanceref upg_dat_o_OBUF_25__inst)) - (portref Q (instanceref upg_dat_o_reg_25_)) - ) - ) - (net (rename upg_dat_o_OBUF_26_ "upg_dat_o_OBUF[26]") (joined - (portref I (instanceref upg_dat_o_OBUF_26__inst)) - (portref Q (instanceref upg_dat_o_reg_26_)) - ) - ) - (net (rename upg_dat_o_OBUF_27_ "upg_dat_o_OBUF[27]") (joined - (portref I (instanceref upg_dat_o_OBUF_27__inst)) - (portref Q (instanceref upg_dat_o_reg_27_)) - ) - ) - (net (rename upg_dat_o_OBUF_28_ "upg_dat_o_OBUF[28]") (joined - (portref I (instanceref upg_dat_o_OBUF_28__inst)) - (portref Q (instanceref upg_dat_o_reg_28_)) - ) - ) - (net (rename upg_dat_o_OBUF_29_ "upg_dat_o_OBUF[29]") (joined - (portref I (instanceref upg_dat_o_OBUF_29__inst)) - (portref Q (instanceref upg_dat_o_reg_29_)) - ) - ) - (net (rename upg_dat_o_OBUF_2_ "upg_dat_o_OBUF[2]") (joined - (portref I (instanceref upg_dat_o_OBUF_2__inst)) - (portref Q (instanceref upg_dat_o_reg_2_)) - ) - ) - (net (rename upg_dat_o_OBUF_30_ "upg_dat_o_OBUF[30]") (joined - (portref I (instanceref upg_dat_o_OBUF_30__inst)) - (portref Q (instanceref upg_dat_o_reg_30_)) - ) - ) - (net (rename upg_dat_o_OBUF_31_ "upg_dat_o_OBUF[31]") (joined - (portref I (instanceref upg_dat_o_OBUF_31__inst)) - (portref Q (instanceref upg_dat_o_reg_31_)) - ) - ) - (net (rename upg_dat_o_OBUF_3_ "upg_dat_o_OBUF[3]") (joined - (portref I (instanceref upg_dat_o_OBUF_3__inst)) - (portref Q (instanceref upg_dat_o_reg_3_)) - ) - ) - (net (rename upg_dat_o_OBUF_4_ "upg_dat_o_OBUF[4]") (joined - (portref I (instanceref upg_dat_o_OBUF_4__inst)) - (portref Q (instanceref upg_dat_o_reg_4_)) - ) - ) - (net (rename upg_dat_o_OBUF_5_ "upg_dat_o_OBUF[5]") (joined - (portref I (instanceref upg_dat_o_OBUF_5__inst)) - (portref Q (instanceref upg_dat_o_reg_5_)) - ) - ) - (net (rename upg_dat_o_OBUF_6_ "upg_dat_o_OBUF[6]") (joined - (portref I (instanceref upg_dat_o_OBUF_6__inst)) - (portref Q (instanceref upg_dat_o_reg_6_)) - ) - ) - (net (rename upg_dat_o_OBUF_7_ "upg_dat_o_OBUF[7]") (joined - (portref I (instanceref upg_dat_o_OBUF_7__inst)) - (portref Q (instanceref upg_dat_o_reg_7_)) - ) - ) - (net (rename upg_dat_o_OBUF_8_ "upg_dat_o_OBUF[8]") (joined - (portref I (instanceref upg_dat_o_OBUF_8__inst)) - (portref Q (instanceref upg_dat_o_reg_8_)) - ) - ) - (net (rename upg_dat_o_OBUF_9_ "upg_dat_o_OBUF[9]") (joined - (portref I (instanceref upg_dat_o_OBUF_9__inst)) - (portref Q (instanceref upg_dat_o_reg_9_)) - ) - ) - (net upg_done_o (joined - (portref O (instanceref upg_done_o_OBUF_inst)) - (portref upg_done_o) - ) - ) - (net upg_done_o_OBUF (joined - (portref I (instanceref upg_done_o_OBUF_inst)) - (portref Q (instanceref upg_done_o_reg)) - ) - ) - (net upg_done_o_i_1_n_0 (joined - (portref CE (instanceref upg_done_o_reg)) - (portref O (instanceref upg_done_o_i_1)) - ) - ) - (net upg_done_o_i_2_n_0 (joined - (portref D (instanceref upg_done_o_reg)) - (portref I0 (instanceref s_axi_wdata_4__i_3)) - (portref I0 (instanceref upg_done_o_i_1)) - (portref I1 (instanceref s_axi_wstrb_3__i_1)) - (portref O (instanceref upg_done_o_i_2)) - ) - ) - (net upg_done_o_i_3_n_0 (joined - (portref I5 (instanceref upg_done_o_i_2)) - (portref O (instanceref upg_done_o_i_3)) - ) - ) - (net upg_rst_i (joined - (portref I (instanceref upg_rst_i_IBUF_inst)) - (portref upg_rst_i) - ) - ) - (net upg_rst_i_IBUF (joined - (portref CLR (instanceref RCS_reg_0_)) - (portref CLR (instanceref RCS_reg_1_)) - (portref CLR (instanceref RCS_reg_2_)) - (portref CLR (instanceref WCS_reg_0_)) - (portref CLR (instanceref WCS_reg_1_)) - (portref CLR (instanceref WCS_reg_2_)) - (portref CLR (instanceref bn_ascii_reg_0_)) - (portref CLR (instanceref bn_ascii_reg_10_)) - (portref CLR (instanceref bn_ascii_reg_11_)) - (portref CLR (instanceref bn_ascii_reg_13_)) - (portref CLR (instanceref bn_ascii_reg_14_)) - (portref CLR (instanceref bn_ascii_reg_16_)) - (portref CLR (instanceref bn_ascii_reg_17_)) - (portref CLR (instanceref bn_ascii_reg_18_)) - (portref CLR (instanceref bn_ascii_reg_19_)) - (portref CLR (instanceref bn_ascii_reg_1_)) - (portref CLR (instanceref bn_ascii_reg_21_)) - (portref CLR (instanceref bn_ascii_reg_22_)) - (portref CLR (instanceref bn_ascii_reg_24_)) - (portref CLR (instanceref bn_ascii_reg_25_)) - (portref CLR (instanceref bn_ascii_reg_26_)) - (portref CLR (instanceref bn_ascii_reg_27_)) - (portref CLR (instanceref bn_ascii_reg_29_)) - (portref CLR (instanceref bn_ascii_reg_2_)) - (portref CLR (instanceref bn_ascii_reg_30_)) - (portref CLR (instanceref bn_ascii_reg_32_)) - (portref CLR (instanceref bn_ascii_reg_33_)) - (portref CLR (instanceref bn_ascii_reg_34_)) - (portref CLR (instanceref bn_ascii_reg_35_)) - (portref CLR (instanceref bn_ascii_reg_37_)) - (portref CLR (instanceref bn_ascii_reg_38_)) - (portref CLR (instanceref bn_ascii_reg_3_)) - (portref CLR (instanceref bn_ascii_reg_40_)) - (portref CLR (instanceref bn_ascii_reg_41_)) - (portref CLR (instanceref bn_ascii_reg_42_)) - (portref CLR (instanceref bn_ascii_reg_43_)) - (portref CLR (instanceref bn_ascii_reg_45_)) - (portref CLR (instanceref bn_ascii_reg_46_)) - (portref CLR (instanceref bn_ascii_reg_48_)) - (portref CLR (instanceref bn_ascii_reg_49_)) - (portref CLR (instanceref bn_ascii_reg_50_)) - (portref CLR (instanceref bn_ascii_reg_51_)) - (portref CLR (instanceref bn_ascii_reg_53_)) - (portref CLR (instanceref bn_ascii_reg_54_)) - (portref CLR (instanceref bn_ascii_reg_56_)) - (portref CLR (instanceref bn_ascii_reg_57_)) - (portref CLR (instanceref bn_ascii_reg_58_)) - (portref CLR (instanceref bn_ascii_reg_59_)) - (portref CLR (instanceref bn_ascii_reg_5_)) - (portref CLR (instanceref bn_ascii_reg_61_)) - (portref CLR (instanceref bn_ascii_reg_62_)) - (portref CLR (instanceref bn_ascii_reg_6_)) - (portref CLR (instanceref bn_ascii_reg_8_)) - (portref CLR (instanceref bn_ascii_reg_9_)) - (portref CLR (instanceref byte_cnt_reg_0_)) - (portref CLR (instanceref byte_cnt_reg_10_)) - (portref CLR (instanceref byte_cnt_reg_11_)) - (portref CLR (instanceref byte_cnt_reg_12_)) - (portref CLR (instanceref byte_cnt_reg_13_)) - (portref CLR (instanceref byte_cnt_reg_14_)) - (portref CLR (instanceref byte_cnt_reg_15_)) - (portref CLR (instanceref byte_cnt_reg_16_)) - (portref CLR (instanceref byte_cnt_reg_17_)) - (portref CLR (instanceref byte_cnt_reg_18_)) - (portref CLR (instanceref byte_cnt_reg_19_)) - (portref CLR (instanceref byte_cnt_reg_1_)) - (portref CLR (instanceref byte_cnt_reg_20_)) - (portref CLR (instanceref byte_cnt_reg_21_)) - (portref CLR (instanceref byte_cnt_reg_22_)) - (portref CLR (instanceref byte_cnt_reg_23_)) - (portref CLR (instanceref byte_cnt_reg_24_)) - (portref CLR (instanceref byte_cnt_reg_25_)) - (portref CLR (instanceref byte_cnt_reg_26_)) - (portref CLR (instanceref byte_cnt_reg_27_)) - (portref CLR (instanceref byte_cnt_reg_28_)) - (portref CLR (instanceref byte_cnt_reg_29_)) - (portref CLR (instanceref byte_cnt_reg_2_)) - (portref CLR (instanceref byte_cnt_reg_30_)) - (portref CLR (instanceref byte_cnt_reg_31_)) - (portref CLR (instanceref byte_cnt_reg_3_)) - (portref CLR (instanceref byte_cnt_reg_4_)) - (portref CLR (instanceref byte_cnt_reg_5_)) - (portref CLR (instanceref byte_cnt_reg_6_)) - (portref CLR (instanceref byte_cnt_reg_7_)) - (portref CLR (instanceref byte_cnt_reg_8_)) - (portref CLR (instanceref byte_cnt_reg_9_)) - (portref CLR (instanceref byte_len_reg_0_)) - (portref CLR (instanceref byte_len_reg_1_)) - (portref CLR (instanceref byte_len_reg_2_)) - (portref CLR (instanceref byte_len_reg_3_)) - (portref CLR (instanceref byte_len_reg_4_)) - (portref CLR (instanceref byte_len_reg_5_)) - (portref CLR (instanceref byte_len_reg_6_)) - (portref CLR (instanceref byte_len_reg_7_)) - (portref CLR (instanceref byte_num_reg_0_)) - (portref CLR (instanceref byte_num_reg_10_)) - (portref CLR (instanceref byte_num_reg_11_)) - (portref CLR (instanceref byte_num_reg_12_)) - (portref CLR (instanceref byte_num_reg_13_)) - (portref CLR (instanceref byte_num_reg_14_)) - (portref CLR (instanceref byte_num_reg_15_)) - (portref CLR (instanceref byte_num_reg_16_)) - (portref CLR (instanceref byte_num_reg_17_)) - (portref CLR (instanceref byte_num_reg_18_)) - (portref CLR (instanceref byte_num_reg_19_)) - (portref CLR (instanceref byte_num_reg_1_)) - (portref CLR (instanceref byte_num_reg_20_)) - (portref CLR (instanceref byte_num_reg_21_)) - (portref CLR (instanceref byte_num_reg_22_)) - (portref CLR (instanceref byte_num_reg_23_)) - (portref CLR (instanceref byte_num_reg_24_)) - (portref CLR (instanceref byte_num_reg_25_)) - (portref CLR (instanceref byte_num_reg_26_)) - (portref CLR (instanceref byte_num_reg_27_)) - (portref CLR (instanceref byte_num_reg_28_)) - (portref CLR (instanceref byte_num_reg_29_)) - (portref CLR (instanceref byte_num_reg_2_)) - (portref CLR (instanceref byte_num_reg_30_)) - (portref CLR (instanceref byte_num_reg_31_)) - (portref CLR (instanceref byte_num_reg_3_)) - (portref CLR (instanceref byte_num_reg_4_)) - (portref CLR (instanceref byte_num_reg_5_)) - (portref CLR (instanceref byte_num_reg_6_)) - (portref CLR (instanceref byte_num_reg_7_)) - (portref CLR (instanceref byte_num_reg_8_)) - (portref CLR (instanceref byte_num_reg_9_)) - (portref CLR (instanceref dbuf_reg_0_)) - (portref CLR (instanceref dbuf_reg_10_)) - (portref CLR (instanceref dbuf_reg_11_)) - (portref CLR (instanceref dbuf_reg_12_)) - (portref CLR (instanceref dbuf_reg_13_)) - (portref CLR (instanceref dbuf_reg_14_)) - (portref CLR (instanceref dbuf_reg_15_)) - (portref CLR (instanceref dbuf_reg_16_)) - (portref CLR (instanceref dbuf_reg_17_)) - (portref CLR (instanceref dbuf_reg_18_)) - (portref CLR (instanceref dbuf_reg_19_)) - (portref CLR (instanceref dbuf_reg_1_)) - (portref CLR (instanceref dbuf_reg_20_)) - (portref CLR (instanceref dbuf_reg_21_)) - (portref CLR (instanceref dbuf_reg_22_)) - (portref CLR (instanceref dbuf_reg_23_)) - (portref CLR (instanceref dbuf_reg_2_)) - (portref CLR (instanceref dbuf_reg_3_)) - (portref CLR (instanceref dbuf_reg_4_)) - (portref CLR (instanceref dbuf_reg_5_)) - (portref CLR (instanceref dbuf_reg_6_)) - (portref CLR (instanceref dbuf_reg_7_)) - (portref CLR (instanceref dbuf_reg_8_)) - (portref CLR (instanceref dbuf_reg_9_)) - (portref CLR (instanceref disp_reg_0_)) - (portref CLR (instanceref disp_reg_1_)) - (portref CLR (instanceref disp_reg_2_)) - (portref CLR (instanceref disp_reg_3_)) - (portref CLR (instanceref disp_reg_4_)) - (portref CLR (instanceref disp_reg_5_)) - (portref CLR (instanceref disp_reg_6_)) - (portref CLR (instanceref disp_reg_7_)) - (portref CLR (instanceref initFlag_reg)) - (portref CLR (instanceref len_cnt_reg_0_)) - (portref CLR (instanceref len_cnt_reg_1_)) - (portref CLR (instanceref len_cnt_reg_2_)) - (portref CLR (instanceref len_cnt_reg_3_)) - (portref CLR (instanceref msg_indx_reg_0_)) - (portref CLR (instanceref msg_indx_reg_1_)) - (portref CLR (instanceref msg_indx_reg_2_)) - (portref CLR (instanceref msg_indx_reg_3_)) - (portref CLR (instanceref msg_indx_reg_4_)) - (portref CLR (instanceref msg_indx_reg_5_)) - (portref CLR (instanceref msg_indx_reg_6_)) - (portref CLR (instanceref msg_indx_reg_7_)) - (portref CLR (instanceref oldInitF_reg)) - (portref CLR (instanceref rdStat_reg)) - (portref CLR (instanceref recv_done_reg)) - (portref CLR (instanceref rwait_cnt_reg_10_)) - (portref CLR (instanceref rwait_cnt_reg_11_)) - (portref CLR (instanceref rwait_cnt_reg_12_)) - (portref CLR (instanceref rwait_cnt_reg_13_)) - (portref CLR (instanceref rwait_cnt_reg_14_)) - (portref CLR (instanceref rwait_cnt_reg_15_)) - (portref CLR (instanceref rwait_cnt_reg_1_)) - (portref CLR (instanceref rwait_cnt_reg_2_)) - (portref CLR (instanceref rwait_cnt_reg_3_)) - (portref CLR (instanceref rwait_cnt_reg_4_)) - (portref CLR (instanceref rwait_cnt_reg_5_)) - (portref CLR (instanceref rwait_cnt_reg_6_)) - (portref CLR (instanceref rwait_cnt_reg_7_)) - (portref CLR (instanceref rwait_cnt_reg_8_)) - (portref CLR (instanceref rwait_cnt_reg_9_)) - (portref CLR (instanceref rx_done_reg)) - (portref CLR (instanceref statReg_reg_0_)) - (portref CLR (instanceref uart_wen_reg)) - (portref CLR (instanceref upg_adr_o_reg_0_)) - (portref CLR (instanceref upg_adr_o_reg_10_)) - (portref CLR (instanceref upg_adr_o_reg_11_)) - (portref CLR (instanceref upg_adr_o_reg_12_)) - (portref CLR (instanceref upg_adr_o_reg_13_)) - (portref CLR (instanceref upg_adr_o_reg_14_)) - (portref CLR (instanceref upg_adr_o_reg_1_)) - (portref CLR (instanceref upg_adr_o_reg_2_)) - (portref CLR (instanceref upg_adr_o_reg_3_)) - (portref CLR (instanceref upg_adr_o_reg_4_)) - (portref CLR (instanceref upg_adr_o_reg_5_)) - (portref CLR (instanceref upg_adr_o_reg_6_)) - (portref CLR (instanceref upg_adr_o_reg_7_)) - (portref CLR (instanceref upg_adr_o_reg_8_)) - (portref CLR (instanceref upg_adr_o_reg_9_)) - (portref CLR (instanceref upg_dat_o_reg_0_)) - (portref CLR (instanceref upg_dat_o_reg_10_)) - (portref CLR (instanceref upg_dat_o_reg_11_)) - (portref CLR (instanceref upg_dat_o_reg_12_)) - (portref CLR (instanceref upg_dat_o_reg_13_)) - (portref CLR (instanceref upg_dat_o_reg_14_)) - (portref CLR (instanceref upg_dat_o_reg_15_)) - (portref CLR (instanceref upg_dat_o_reg_16_)) - (portref CLR (instanceref upg_dat_o_reg_17_)) - (portref CLR (instanceref upg_dat_o_reg_18_)) - (portref CLR (instanceref upg_dat_o_reg_19_)) - (portref CLR (instanceref upg_dat_o_reg_1_)) - (portref CLR (instanceref upg_dat_o_reg_20_)) - (portref CLR (instanceref upg_dat_o_reg_21_)) - (portref CLR (instanceref upg_dat_o_reg_22_)) - (portref CLR (instanceref upg_dat_o_reg_23_)) - (portref CLR (instanceref upg_dat_o_reg_24_)) - (portref CLR (instanceref upg_dat_o_reg_25_)) - (portref CLR (instanceref upg_dat_o_reg_26_)) - (portref CLR (instanceref upg_dat_o_reg_27_)) - (portref CLR (instanceref upg_dat_o_reg_28_)) - (portref CLR (instanceref upg_dat_o_reg_29_)) - (portref CLR (instanceref upg_dat_o_reg_2_)) - (portref CLR (instanceref upg_dat_o_reg_30_)) - (portref CLR (instanceref upg_dat_o_reg_31_)) - (portref CLR (instanceref upg_dat_o_reg_3_)) - (portref CLR (instanceref upg_dat_o_reg_4_)) - (portref CLR (instanceref upg_dat_o_reg_5_)) - (portref CLR (instanceref upg_dat_o_reg_6_)) - (portref CLR (instanceref upg_dat_o_reg_7_)) - (portref CLR (instanceref upg_dat_o_reg_8_)) - (portref CLR (instanceref upg_dat_o_reg_9_)) - (portref CLR (instanceref upg_done_o_reg)) - (portref CLR (instanceref upg_wen_o_reg)) - (portref CLR (instanceref wr_byte_len_done_reg)) - (portref CLR (instanceref wr_byte_num_done_reg)) - (portref CLR (instanceref wwait_cnt_reg_10_)) - (portref CLR (instanceref wwait_cnt_reg_11_)) - (portref CLR (instanceref wwait_cnt_reg_12_)) - (portref CLR (instanceref wwait_cnt_reg_13_)) - (portref CLR (instanceref wwait_cnt_reg_14_)) - (portref CLR (instanceref wwait_cnt_reg_15_)) - (portref CLR (instanceref wwait_cnt_reg_1_)) - (portref CLR (instanceref wwait_cnt_reg_2_)) - (portref CLR (instanceref wwait_cnt_reg_3_)) - (portref CLR (instanceref wwait_cnt_reg_4_)) - (portref CLR (instanceref wwait_cnt_reg_5_)) - (portref CLR (instanceref wwait_cnt_reg_6_)) - (portref CLR (instanceref wwait_cnt_reg_7_)) - (portref CLR (instanceref wwait_cnt_reg_8_)) - (portref CLR (instanceref wwait_cnt_reg_9_)) - (portref I0 (instanceref axi_uart_inst_i_1)) - (portref I0 (instanceref s_axi_arvalid_i_2)) - (portref I1 (instanceref recv_done_i_1)) - (portref I1 (instanceref s_axi_wdata_4__i_1)) - (portref I1 (instanceref s_axi_wdata_6__i_1)) - (portref I1 (instanceref uart_wen_i_1)) - (portref I1 (instanceref upg_wen_o_i_1)) - (portref I2 (instanceref s_axi_araddr_3__i_1)) - (portref I2 (instanceref s_axi_awaddr_3__i_1)) - (portref I2 (instanceref s_axi_awvalid_i_2)) - (portref I2 (instanceref upg_adr_o_14__i_1)) - (portref I3 (instanceref byte_cnt_31__i_1)) - (portref I3 (instanceref uart_rdat_7__i_1)) - (portref I4 (instanceref upg_wen_o_i_3)) - (portref O (instanceref upg_rst_i_IBUF_inst)) - (portref PRE (instanceref rwait_cnt_reg_0_)) - (portref PRE (instanceref wwait_cnt_reg_0_)) - ) - ) - (net upg_rx_i (joined - (portref I (instanceref upg_rx_i_IBUF_inst)) - (portref upg_rx_i) - ) - ) - (net upg_rx_i_IBUF (joined - (portref O (instanceref upg_rx_i_IBUF_inst)) - (portref rx (instanceref axi_uart_inst)) - ) - ) - (net upg_tx_o (joined - (portref O (instanceref upg_tx_o_OBUF_inst)) - (portref upg_tx_o) - ) - ) - (net upg_tx_o_OBUF (joined - (portref I (instanceref upg_tx_o_OBUF_inst)) - (portref tx (instanceref axi_uart_inst)) - ) - ) - (net upg_wen_o (joined - (portref O (instanceref upg_wen_o_OBUF_inst)) - (portref upg_wen_o) - ) - ) - (net upg_wen_o2_out (joined - (portref CE (instanceref upg_wen_o_reg)) - (portref O (instanceref upg_wen_o_i_1)) - ) - ) - (net upg_wen_o_OBUF (joined - (portref I (instanceref upg_wen_o_OBUF_inst)) - (portref Q (instanceref upg_wen_o_reg)) - ) - ) - (net upg_wen_o_i_2_n_0 (joined - (portref D (instanceref upg_wen_o_reg)) - (portref O (instanceref upg_wen_o_i_2)) - ) - ) - (net upg_wen_o_i_4_n_0 (joined - (portref I0 (instanceref upg_wen_o_i_2)) - (portref I1 (instanceref upg_adr_o_14__i_1)) - (portref I2 (instanceref upg_wen_o_i_1)) - (portref I3 (instanceref disp_6__i_2)) - (portref O (instanceref upg_wen_o_i_4)) - ) - ) - (net upg_wen_o_i_5_n_0 (joined - (portref I0 (instanceref upg_wen_o_i_3)) - (portref O (instanceref upg_wen_o_i_5)) - ) - ) - (net upg_wen_o_i_6_n_0 (joined - (portref I4 (instanceref upg_wen_o_i_4)) - (portref O (instanceref upg_wen_o_i_6)) - ) - ) - (net wr_byte_len_done0 (joined - (portref D (instanceref wr_byte_len_done_reg)) - (portref I0 (instanceref byte_len_7__i_1)) - (portref O (instanceref wr_byte_len_done_i_1)) - ) - ) - (net wr_byte_len_done_i_2_n_0 (joined - (portref I1 (instanceref wr_byte_len_done_i_1)) - (portref O (instanceref wr_byte_len_done_i_2)) - ) - ) - (net wr_byte_len_done_reg_n_0 (joined - (portref I0 (instanceref byte_num_31__i_1)) - (portref I0 (instanceref wr_byte_len_done_i_1)) - (portref I2 (instanceref bn_ascii_62__i_1)) - (portref Q (instanceref wr_byte_len_done_reg)) - ) - ) - (net wr_byte_num_done (joined - (portref CE (instanceref bn_ascii_reg_0_)) - (portref CE (instanceref bn_ascii_reg_10_)) - (portref CE (instanceref bn_ascii_reg_11_)) - (portref CE (instanceref bn_ascii_reg_13_)) - (portref CE (instanceref bn_ascii_reg_14_)) - (portref CE (instanceref bn_ascii_reg_16_)) - (portref CE (instanceref bn_ascii_reg_17_)) - (portref CE (instanceref bn_ascii_reg_18_)) - (portref CE (instanceref bn_ascii_reg_19_)) - (portref CE (instanceref bn_ascii_reg_1_)) - (portref CE (instanceref bn_ascii_reg_21_)) - (portref CE (instanceref bn_ascii_reg_22_)) - (portref CE (instanceref bn_ascii_reg_24_)) - (portref CE (instanceref bn_ascii_reg_25_)) - (portref CE (instanceref bn_ascii_reg_26_)) - (portref CE (instanceref bn_ascii_reg_27_)) - (portref CE (instanceref bn_ascii_reg_29_)) - (portref CE (instanceref bn_ascii_reg_2_)) - (portref CE (instanceref bn_ascii_reg_30_)) - (portref CE (instanceref bn_ascii_reg_32_)) - (portref CE (instanceref bn_ascii_reg_33_)) - (portref CE (instanceref bn_ascii_reg_34_)) - (portref CE (instanceref bn_ascii_reg_35_)) - (portref CE (instanceref bn_ascii_reg_37_)) - (portref CE (instanceref bn_ascii_reg_38_)) - (portref CE (instanceref bn_ascii_reg_3_)) - (portref CE (instanceref bn_ascii_reg_40_)) - (portref CE (instanceref bn_ascii_reg_41_)) - (portref CE (instanceref bn_ascii_reg_42_)) - (portref CE (instanceref bn_ascii_reg_43_)) - (portref CE (instanceref bn_ascii_reg_45_)) - (portref CE (instanceref bn_ascii_reg_46_)) - (portref CE (instanceref bn_ascii_reg_48_)) - (portref CE (instanceref bn_ascii_reg_49_)) - (portref CE (instanceref bn_ascii_reg_50_)) - (portref CE (instanceref bn_ascii_reg_51_)) - (portref CE (instanceref bn_ascii_reg_53_)) - (portref CE (instanceref bn_ascii_reg_54_)) - (portref CE (instanceref bn_ascii_reg_56_)) - (portref CE (instanceref bn_ascii_reg_57_)) - (portref CE (instanceref bn_ascii_reg_58_)) - (portref CE (instanceref bn_ascii_reg_59_)) - (portref CE (instanceref bn_ascii_reg_5_)) - (portref CE (instanceref bn_ascii_reg_61_)) - (portref CE (instanceref bn_ascii_reg_62_)) - (portref CE (instanceref bn_ascii_reg_6_)) - (portref CE (instanceref bn_ascii_reg_8_)) - (portref CE (instanceref bn_ascii_reg_9_)) - (portref CE (instanceref wr_byte_num_done_reg)) - (portref O (instanceref bn_ascii_62__i_1)) - ) - ) - (net wr_byte_num_done0 (joined - (portref D (instanceref wr_byte_num_done_reg)) - (portref I3 (instanceref bn_ascii_62__i_1)) - (portref O (instanceref wr_byte_num_done_i_1)) - ) - ) - (net wr_byte_num_done_i_2_n_0 (joined - (portref I5 (instanceref wr_byte_num_done_i_1)) - (portref O (instanceref wr_byte_num_done_i_2)) - ) - ) - (net wr_byte_num_done_i_3_n_0 (joined - (portref I5 (instanceref wr_byte_num_done_i_2)) - (portref O (instanceref wr_byte_num_done_i_3)) - ) - ) - (net wr_byte_num_done_reg_n_0 (joined - (portref I0 (instanceref bn_ascii_62__i_1)) - (portref I0 (instanceref disp_3__i_1)) - (portref I0 (instanceref disp_4__i_1)) - (portref I0 (instanceref disp_6__i_2)) - (portref I1 (instanceref byte_cnt_31__i_1)) - (portref I1 (instanceref disp_5__i_2)) - (portref I2 (instanceref byte_num_31__i_1)) - (portref I2 (instanceref disp_0__i_1)) - (portref I3 (instanceref disp_1__i_1)) - (portref I3 (instanceref disp_2__i_2)) - (portref I3 (instanceref recv_done_i_1)) - (portref Q (instanceref wr_byte_num_done_reg)) - ) - ) - (net (rename wwait_cnt_0_ "wwait_cnt[0]") (joined - (portref D (instanceref wwait_cnt_reg_0_)) - (portref O (instanceref wwait_cnt_0__i_1)) - ) - ) - (net (rename wwait_cnt_10_ "wwait_cnt[10]") (joined - (portref D (instanceref wwait_cnt_reg_10_)) - (portref O (instanceref wwait_cnt_10__i_1)) - ) - ) - (net (rename wwait_cnt_11_ "wwait_cnt[11]") (joined - (portref D (instanceref wwait_cnt_reg_11_)) - (portref O (instanceref wwait_cnt_11__i_1)) - ) - ) - (net (rename wwait_cnt_12_ "wwait_cnt[12]") (joined - (portref D (instanceref wwait_cnt_reg_12_)) - (portref O (instanceref wwait_cnt_12__i_1)) - ) - ) - (net (rename wwait_cnt_13_ "wwait_cnt[13]") (joined - (portref D (instanceref wwait_cnt_reg_13_)) - (portref O (instanceref wwait_cnt_13__i_1)) - ) - ) - (net (rename wwait_cnt_14_ "wwait_cnt[14]") (joined - (portref D (instanceref wwait_cnt_reg_14_)) - (portref O (instanceref wwait_cnt_14__i_1)) - ) - ) - (net (rename wwait_cnt_15_ "wwait_cnt[15]") (joined - (portref D (instanceref wwait_cnt_reg_15_)) - (portref O (instanceref wwait_cnt_15__i_2)) - ) - ) - (net (rename wwait_cnt_15__i_1_n_0 "wwait_cnt[15]_i_1_n_0") (joined - (portref CE (instanceref wwait_cnt_reg_0_)) - (portref CE (instanceref wwait_cnt_reg_10_)) - (portref CE (instanceref wwait_cnt_reg_11_)) - (portref CE (instanceref wwait_cnt_reg_12_)) - (portref CE (instanceref wwait_cnt_reg_13_)) - (portref CE (instanceref wwait_cnt_reg_14_)) - (portref CE (instanceref wwait_cnt_reg_15_)) - (portref CE (instanceref wwait_cnt_reg_1_)) - (portref CE (instanceref wwait_cnt_reg_2_)) - (portref CE (instanceref wwait_cnt_reg_3_)) - (portref CE (instanceref wwait_cnt_reg_4_)) - (portref CE (instanceref wwait_cnt_reg_5_)) - (portref CE (instanceref wwait_cnt_reg_6_)) - (portref CE (instanceref wwait_cnt_reg_7_)) - (portref CE (instanceref wwait_cnt_reg_8_)) - (portref CE (instanceref wwait_cnt_reg_9_)) - (portref O (instanceref wwait_cnt_15__i_1)) - ) - ) - (net (rename wwait_cnt_15__i_4_n_0 "wwait_cnt[15]_i_4_n_0") (joined - (portref I1 (instanceref wwait_cnt_10__i_1)) - (portref I1 (instanceref wwait_cnt_11__i_1)) - (portref I1 (instanceref wwait_cnt_12__i_1)) - (portref I1 (instanceref wwait_cnt_13__i_1)) - (portref I1 (instanceref wwait_cnt_14__i_1)) - (portref I1 (instanceref wwait_cnt_15__i_2)) - (portref I1 (instanceref wwait_cnt_1__i_1)) - (portref I1 (instanceref wwait_cnt_2__i_1)) - (portref I1 (instanceref wwait_cnt_3__i_1)) - (portref I1 (instanceref wwait_cnt_4__i_1)) - (portref I1 (instanceref wwait_cnt_5__i_1)) - (portref I1 (instanceref wwait_cnt_6__i_1)) - (portref I1 (instanceref wwait_cnt_7__i_1)) - (portref I1 (instanceref wwait_cnt_8__i_1)) - (portref I1 (instanceref wwait_cnt_9__i_1)) - (portref O (instanceref wwait_cnt_15__i_4)) - ) - ) - (net (rename wwait_cnt_15__i_5_n_0 "wwait_cnt[15]_i_5_n_0") (joined - (portref I0 (instanceref wwait_cnt_15__i_4)) - (portref O (instanceref wwait_cnt_15__i_5)) - ) - ) - (net (rename wwait_cnt_15__i_6_n_0 "wwait_cnt[15]_i_6_n_0") (joined - (portref I5 (instanceref wwait_cnt_15__i_4)) - (portref O (instanceref wwait_cnt_15__i_6)) - ) - ) - (net (rename wwait_cnt_15__i_7_n_0 "wwait_cnt[15]_i_7_n_0") (joined - (portref I4 (instanceref wwait_cnt_15__i_6)) - (portref O (instanceref wwait_cnt_15__i_7)) - ) - ) - (net (rename wwait_cnt_1_ "wwait_cnt[1]") (joined - (portref D (instanceref wwait_cnt_reg_1_)) - (portref O (instanceref wwait_cnt_1__i_1)) - ) - ) - (net (rename wwait_cnt_2_ "wwait_cnt[2]") (joined - (portref D (instanceref wwait_cnt_reg_2_)) - (portref O (instanceref wwait_cnt_2__i_1)) - ) - ) - (net (rename wwait_cnt_3_ "wwait_cnt[3]") (joined - (portref D (instanceref wwait_cnt_reg_3_)) - (portref O (instanceref wwait_cnt_3__i_1)) - ) - ) - (net (rename wwait_cnt_4_ "wwait_cnt[4]") (joined - (portref D (instanceref wwait_cnt_reg_4_)) - (portref O (instanceref wwait_cnt_4__i_1)) - ) - ) - (net (rename wwait_cnt_5_ "wwait_cnt[5]") (joined - (portref D (instanceref wwait_cnt_reg_5_)) - (portref O (instanceref wwait_cnt_5__i_1)) - ) - ) - (net (rename wwait_cnt_6_ "wwait_cnt[6]") (joined - (portref D (instanceref wwait_cnt_reg_6_)) - (portref O (instanceref wwait_cnt_6__i_1)) - ) - ) - (net (rename wwait_cnt_7_ "wwait_cnt[7]") (joined - (portref D (instanceref wwait_cnt_reg_7_)) - (portref O (instanceref wwait_cnt_7__i_1)) - ) - ) - (net (rename wwait_cnt_8_ "wwait_cnt[8]") (joined - (portref D (instanceref wwait_cnt_reg_8_)) - (portref O (instanceref wwait_cnt_8__i_1)) - ) - ) - (net (rename wwait_cnt_9_ "wwait_cnt[9]") (joined - (portref D (instanceref wwait_cnt_reg_9_)) - (portref O (instanceref wwait_cnt_9__i_1)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_0 "wwait_cnt_reg[12]_i_2_n_0") (joined - (portref CI (instanceref wwait_cnt_reg_15__i_3)) - (portref (member CO 0) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_1 "wwait_cnt_reg[12]_i_2_n_1") (joined - (portref (member CO 1) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_2 "wwait_cnt_reg[12]_i_2_n_2") (joined - (portref (member CO 2) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_3 "wwait_cnt_reg[12]_i_2_n_3") (joined - (portref (member CO 3) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_4 "wwait_cnt_reg[12]_i_2_n_4") (joined - (portref I0 (instanceref wwait_cnt_12__i_1)) - (portref (member O 0) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_5 "wwait_cnt_reg[12]_i_2_n_5") (joined - (portref I0 (instanceref wwait_cnt_11__i_1)) - (portref (member O 1) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_6 "wwait_cnt_reg[12]_i_2_n_6") (joined - (portref I0 (instanceref wwait_cnt_10__i_1)) - (portref (member O 2) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_12__i_2_n_7 "wwait_cnt_reg[12]_i_2_n_7") (joined - (portref I0 (instanceref wwait_cnt_9__i_1)) - (portref (member O 3) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_15__i_3_n_2 "wwait_cnt_reg[15]_i_3_n_2") (joined - (portref (member CO 2) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_15__i_3_n_3 "wwait_cnt_reg[15]_i_3_n_3") (joined - (portref (member CO 3) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_15__i_3_n_5 "wwait_cnt_reg[15]_i_3_n_5") (joined - (portref I0 (instanceref wwait_cnt_15__i_2)) - (portref (member O 1) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_15__i_3_n_6 "wwait_cnt_reg[15]_i_3_n_6") (joined - (portref I0 (instanceref wwait_cnt_14__i_1)) - (portref (member O 2) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_15__i_3_n_7 "wwait_cnt_reg[15]_i_3_n_7") (joined - (portref I0 (instanceref wwait_cnt_13__i_1)) - (portref (member O 3) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_0 "wwait_cnt_reg[4]_i_2_n_0") (joined - (portref CI (instanceref wwait_cnt_reg_8__i_2)) - (portref (member CO 0) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_1 "wwait_cnt_reg[4]_i_2_n_1") (joined - (portref (member CO 1) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_2 "wwait_cnt_reg[4]_i_2_n_2") (joined - (portref (member CO 2) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_3 "wwait_cnt_reg[4]_i_2_n_3") (joined - (portref (member CO 3) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_4 "wwait_cnt_reg[4]_i_2_n_4") (joined - (portref I0 (instanceref wwait_cnt_4__i_1)) - (portref (member O 0) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_5 "wwait_cnt_reg[4]_i_2_n_5") (joined - (portref I0 (instanceref wwait_cnt_3__i_1)) - (portref (member O 1) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_6 "wwait_cnt_reg[4]_i_2_n_6") (joined - (portref I0 (instanceref wwait_cnt_2__i_1)) - (portref (member O 2) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_4__i_2_n_7 "wwait_cnt_reg[4]_i_2_n_7") (joined - (portref I0 (instanceref wwait_cnt_1__i_1)) - (portref (member O 3) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_0 "wwait_cnt_reg[8]_i_2_n_0") (joined - (portref CI (instanceref wwait_cnt_reg_12__i_2)) - (portref (member CO 0) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_1 "wwait_cnt_reg[8]_i_2_n_1") (joined - (portref (member CO 1) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_2 "wwait_cnt_reg[8]_i_2_n_2") (joined - (portref (member CO 2) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_3 "wwait_cnt_reg[8]_i_2_n_3") (joined - (portref (member CO 3) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_4 "wwait_cnt_reg[8]_i_2_n_4") (joined - (portref I0 (instanceref wwait_cnt_8__i_1)) - (portref (member O 0) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_5 "wwait_cnt_reg[8]_i_2_n_5") (joined - (portref I0 (instanceref wwait_cnt_7__i_1)) - (portref (member O 1) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_6 "wwait_cnt_reg[8]_i_2_n_6") (joined - (portref I0 (instanceref wwait_cnt_6__i_1)) - (portref (member O 2) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_8__i_2_n_7 "wwait_cnt_reg[8]_i_2_n_7") (joined - (portref I0 (instanceref wwait_cnt_5__i_1)) - (portref (member O 3) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__0_ "wwait_cnt_reg_n_0_[0]") (joined - (portref CYINIT (instanceref wwait_cnt_reg_4__i_2)) - (portref I0 (instanceref wwait_cnt_0__i_1)) - (portref I1 (instanceref wwait_cnt_15__i_5)) - (portref I2 (instanceref WCS_2__i_4)) - (portref Q (instanceref wwait_cnt_reg_0_)) - ) - ) - (net (rename wwait_cnt_reg_n_0__10_ "wwait_cnt_reg_n_0_[10]") (joined - (portref I2 (instanceref WCS_2__i_2)) - (portref I3 (instanceref wwait_cnt_15__i_7)) - (portref Q (instanceref wwait_cnt_reg_10_)) - (portref (member S 2) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__11_ "wwait_cnt_reg_n_0_[11]") (joined - (portref I2 (instanceref wwait_cnt_15__i_7)) - (portref I4 (instanceref WCS_2__i_2)) - (portref Q (instanceref wwait_cnt_reg_11_)) - (portref (member S 1) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__12_ "wwait_cnt_reg_n_0_[12]") (joined - (portref I0 (instanceref wwait_cnt_15__i_6)) - (portref I3 (instanceref WCS_2__i_2)) - (portref Q (instanceref wwait_cnt_reg_12_)) - (portref (member S 0) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__13_ "wwait_cnt_reg_n_0_[13]") (joined - (portref I1 (instanceref WCS_2__i_2)) - (portref I1 (instanceref wwait_cnt_15__i_6)) - (portref Q (instanceref wwait_cnt_reg_13_)) - (portref (member S 3) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_n_0__14_ "wwait_cnt_reg_n_0_[14]") (joined - (portref I1 (instanceref WCS_2__i_5)) - (portref I1 (instanceref wwait_cnt_15__i_7)) - (portref Q (instanceref wwait_cnt_reg_14_)) - (portref (member S 2) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_n_0__15_ "wwait_cnt_reg_n_0_[15]") (joined - (portref I0 (instanceref WCS_2__i_3)) - (portref I3 (instanceref wwait_cnt_15__i_6)) - (portref Q (instanceref wwait_cnt_reg_15_)) - (portref (member S 1) (instanceref wwait_cnt_reg_15__i_3)) - ) - ) - (net (rename wwait_cnt_reg_n_0__1_ "wwait_cnt_reg_n_0_[1]") (joined - (portref I1 (instanceref WCS_2__i_3)) - (portref I2 (instanceref wwait_cnt_15__i_6)) - (portref Q (instanceref wwait_cnt_reg_1_)) - (portref (member S 3) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__2_ "wwait_cnt_reg_n_0_[2]") (joined - (portref I3 (instanceref WCS_2__i_4)) - (portref I3 (instanceref wwait_cnt_15__i_5)) - (portref Q (instanceref wwait_cnt_reg_2_)) - (portref (member S 2) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__3_ "wwait_cnt_reg_n_0_[3]") (joined - (portref I2 (instanceref WCS_2__i_5)) - (portref I2 (instanceref wwait_cnt_15__i_5)) - (portref Q (instanceref wwait_cnt_reg_3_)) - (portref (member S 1) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__4_ "wwait_cnt_reg_n_0_[4]") (joined - (portref I2 (instanceref wwait_cnt_15__i_4)) - (portref I3 (instanceref WCS_2__i_3)) - (portref Q (instanceref wwait_cnt_reg_4_)) - (portref (member S 0) (instanceref wwait_cnt_reg_4__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__5_ "wwait_cnt_reg_n_0_[5]") (joined - (portref I1 (instanceref wwait_cnt_15__i_4)) - (portref I2 (instanceref WCS_2__i_3)) - (portref Q (instanceref wwait_cnt_reg_5_)) - (portref (member S 3) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__6_ "wwait_cnt_reg_n_0_[6]") (joined - (portref I0 (instanceref WCS_2__i_4)) - (portref I3 (instanceref wwait_cnt_15__i_4)) - (portref Q (instanceref wwait_cnt_reg_6_)) - (portref (member S 2) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__7_ "wwait_cnt_reg_n_0_[7]") (joined - (portref I0 (instanceref wwait_cnt_15__i_5)) - (portref I1 (instanceref WCS_2__i_4)) - (portref Q (instanceref wwait_cnt_reg_7_)) - (portref (member S 1) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__8_ "wwait_cnt_reg_n_0_[8]") (joined - (portref I0 (instanceref WCS_2__i_5)) - (portref I0 (instanceref wwait_cnt_15__i_7)) - (portref Q (instanceref wwait_cnt_reg_8_)) - (portref (member S 0) (instanceref wwait_cnt_reg_8__i_2)) - ) - ) - (net (rename wwait_cnt_reg_n_0__9_ "wwait_cnt_reg_n_0_[9]") (joined - (portref I3 (instanceref WCS_2__i_5)) - (portref I4 (instanceref wwait_cnt_15__i_4)) - (portref Q (instanceref wwait_cnt_reg_9_)) - (portref (member S 3) (instanceref wwait_cnt_reg_12__i_2)) - ) - ) - ) - - (property ADDR_WIDTH (integer 15)) - (property DATA_WIDTH (integer 32)) - (property BYTE_NUM (integer 4)) - (property WIDLE (integer 0)) - (property WDATA_VALID (integer 1)) - (property JUDGE_WRDY (integer 2)) - (property WDATA (integer 3)) - (property WDELAY (integer 4)) - (property RIDLE (integer 0)) - (property RDATA_VALID (integer 1)) - (property JUDGE_RRDY (integer 2)) - (property RDATA (integer 3)) - (property RDELAY (integer 4)) - (property WAIT_NUM (integer 765)) - (property MSG_LEN (integer 38)) - ) - ) - ) -(comment "Reference To The Cell Of Highest Level") - - (design uart_bmpg - (cellref uart_bmpg (libraryref work)) - (property XLNX_PROJ_DIR (string "H:/Workspace_Xilinx/Vivado/uart_bmpg")) - (property PART (string "xc7a100tfgg484-1")) - ) -) diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v deleted file mode 100644 index 81d902b..0000000 --- a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v +++ /dev/null @@ -1,37 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2018/04/27 07:17:21 -// Design Name: -// Module Name: uart_bmpg -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module uart_bmpg( - input wire upg_clk_i, // 10MHz - input wire upg_rst_i, // High active - // blkram signals - output wire upg_clk_o, - output reg upg_wen_o, - output reg [14:0] upg_adr_o, - output reg [31:0] upg_dat_o, - output reg upg_done_o, - // UART Pinouts - input wire upg_rx_i, - output wire upg_tx_o -); - -endmodule diff --git a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v b/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v deleted file mode 100644 index 78d3576..0000000 --- a/main/verilog/ip/SEU_CSE_507_user_uart_bmpg_1.3/upg.v +++ /dev/null @@ -1,51 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2018/07/12 08:40:58 -// Design Name: -// Module Name: upg -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module upg( - input upg_clk_i, // 10MHz - input upg_rst_i, // High active - // blkram signals - output upg_clk_o, - output upg_wen_o, - output [14:0] upg_adr_o, - output [31:0] upg_dat_o, - output upg_done_o, - // UART Pinouts - input upg_rx_i, - output upg_tx_o -); - - uart_bmpg upg_inst ( - .upg_clk_i (upg_clk_i), // 10MHz - .upg_rst_i (upg_rst_i), // High active - // blkram signals - .upg_clk_o (upg_clk_o), - .upg_wen_o (upg_wen_o), - .upg_adr_o (upg_adr_o), - .upg_dat_o (upg_dat_o), - .upg_done_o (upg_done_o), - // UART Pinouts - .upg_rx_i (upg_rx_i), - .upg_tx_o (upg_tx_o) - ); - -endmodule diff --git a/main/verilog/ip/cpuclk/.gitignore b/main/verilog/ip/cpuclk/.gitignore new file mode 100644 index 0000000..7a5e6cb --- /dev/null +++ b/main/verilog/ip/cpuclk/.gitignore @@ -0,0 +1,2 @@ +/* +!**.xci \ No newline at end of file diff --git a/main/verilog/ip/cpuclk/cpuclk.xci b/main/verilog/ip/cpuclk/cpuclk.xci new file mode 100644 index 0000000..cac6447 --- /dev/null +++ b/main/verilog/ip/cpuclk/cpuclk.xci @@ -0,0 +1,689 @@ + + + xilinx.com + xci + unknown + 1.0 + + + cpuclk + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0.000 + + + + 100000000 + 0.000 + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 23.000 + 0000 + 0000 + 10.000 + BUFG + 50.0 + false + 23.000 + 0.000 + 50.000 + 23 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 10.000 + 0.000 + 50.000 + 10 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 2.3 + 0.23 + 0.23 + 0.23 + 0.23 + 0.23 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 46.000 + 0.000 + FALSE + 10.000 + 10.000 + 40.000 + 0.500 + 0.000 + FALSE + 92 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 5 + None + 0.010 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1____23.000______0.000______50.0______342.117____303.235 + clk_out2____10.000______0.000______50.0______391.228____303.235 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + PLL + AUTO + 100.000 + 0.010 + 10.000 + Global_buffer + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + cpuclk + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 342.117 + false + 303.235 + 50.000 + 23 + 0.000 + 1 + true + BUFG + 391.228 + false + 303.235 + 50.000 + 10 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + cpuclk + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 46 + 0.000 + false + 10.000 + 10.000 + 40 + 0.500 + 0.000 + false + 92 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + PLL + mmcm_adv + 100.000 + 0.010 + 10.000 + Global_buffer + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + false + false + false + false + true + false + false + false + false + false + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/main/verilog/ip/iart_bmpg_0/.gitignore b/main/verilog/ip/iart_bmpg_0/.gitignore new file mode 100644 index 0000000..7a5e6cb --- /dev/null +++ b/main/verilog/ip/iart_bmpg_0/.gitignore @@ -0,0 +1,2 @@ +/* +!**.xci \ No newline at end of file diff --git a/main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci b/main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci new file mode 100644 index 0000000..6d7acbc --- /dev/null +++ b/main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci @@ -0,0 +1,41 @@ + + + xilinx.com + xci + unknown + 1.0 + + + uart_bmpg_0 + + + 128000 bps + uart_bmpg_0 + 8 bits + 10 MHz + No + Active High + 1 bit(s) + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 8 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + diff --git a/main/verilog/ip/prgrom/.gitignore b/main/verilog/ip/prgrom/.gitignore new file mode 100644 index 0000000..d3e4399 --- /dev/null +++ b/main/verilog/ip/prgrom/.gitignore @@ -0,0 +1,2 @@ +/* +!**.xci diff --git a/main/verilog/ip/blk_mem_gen_0.xci b/main/verilog/ip/prgrom/prgrom.xci similarity index 98% rename from main/verilog/ip/blk_mem_gen_0.xci rename to main/verilog/ip/prgrom/prgrom.xci index 0874ea9..4d6c97a 100644 --- a/main/verilog/ip/blk_mem_gen_0.xci +++ b/main/verilog/ip/prgrom/prgrom.xci @@ -6,7 +6,7 @@ 1.0 - blk_mem_gen_0 + prgrom 4096 @@ -124,8 +124,8 @@ 0 0 0 - blk_mem_gen_0.mem - blk_mem_gen_0.mif + prgrom.mem + prgrom.mif 0 1 0 @@ -164,9 +164,9 @@ false 9 NONE - ../../../../../main/test_coe/dmem32.coe + ../../../mips/coe/prgmip32.coe ALL - blk_mem_gen_0 + prgrom false false false diff --git a/main/verilog/ip/ram/.gitignore b/main/verilog/ip/ram/.gitignore new file mode 100644 index 0000000..d3e4399 --- /dev/null +++ b/main/verilog/ip/ram/.gitignore @@ -0,0 +1,2 @@ +/* +!**.xci diff --git a/main/verilog/ip/ram/RAM.xci b/main/verilog/ip/ram/RAM.xci new file mode 100644 index 0000000..3416ca9 --- /dev/null +++ b/main/verilog/ip/ram/RAM.xci @@ -0,0 +1,266 @@ + + + xilinx.com + xci + unknown + 1.0 + + + RAM + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + READ_WRITE + OTHER + NONE + 8192 + 32 + READ_WRITE + + 100000000 + 0.000 + 14 + 14 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 14 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 13.776802 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + RAM.mem + RAM.mif + 0 + 1 + 0 + 0 + 1 + 16384 + 16384 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 16384 + 16384 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../../../mips/coe/dmem32.coe + ALL + RAM + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 16384 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + artix7 + + xc7a100t + fgg484 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2017.4 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + -- Gitee From 9438238c8fbf3599956c750025f36f00677ad163 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 00:35:06 +0800 Subject: [PATCH 53/57] =?UTF-8?q?fix(verilog):=20=E4=BF=AE=E5=A4=8Dip?= =?UTF-8?q?=E6=A0=B8=E4=BD=8D=E7=BD=AE=EF=BC=8C=E5=88=86=E6=96=87=E4=BB=B6?= =?UTF-8?q?=E5=A4=B9=E5=AD=98=E5=82=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- main/verilog/ip/cpuclk/.gitignore | 2 -- main/verilog/ip/iart_bmpg_0/.gitignore | 2 -- main/verilog/ip/prgrom/.gitignore | 2 -- main/verilog/ip/ram/.gitignore | 2 -- main/verilog/{ip => ip_invoke}/cpuclk/cpuclk.xci | 0 main/verilog/{ip => ip_invoke}/iart_bmpg_0/uart_bmpg_0.xci | 0 main/verilog/{ip => ip_invoke}/prgrom/prgrom.xci | 0 main/verilog/{ip => ip_invoke}/ram/RAM.xci | 0 8 files changed, 8 deletions(-) delete mode 100644 main/verilog/ip/cpuclk/.gitignore delete mode 100644 main/verilog/ip/iart_bmpg_0/.gitignore delete mode 100644 main/verilog/ip/prgrom/.gitignore delete mode 100644 main/verilog/ip/ram/.gitignore rename main/verilog/{ip => ip_invoke}/cpuclk/cpuclk.xci (100%) rename main/verilog/{ip => ip_invoke}/iart_bmpg_0/uart_bmpg_0.xci (100%) rename main/verilog/{ip => ip_invoke}/prgrom/prgrom.xci (100%) rename main/verilog/{ip => ip_invoke}/ram/RAM.xci (100%) diff --git a/main/verilog/ip/cpuclk/.gitignore b/main/verilog/ip/cpuclk/.gitignore deleted file mode 100644 index 7a5e6cb..0000000 --- a/main/verilog/ip/cpuclk/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/* -!**.xci \ No newline at end of file diff --git a/main/verilog/ip/iart_bmpg_0/.gitignore b/main/verilog/ip/iart_bmpg_0/.gitignore deleted file mode 100644 index 7a5e6cb..0000000 --- a/main/verilog/ip/iart_bmpg_0/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/* -!**.xci \ No newline at end of file diff --git a/main/verilog/ip/prgrom/.gitignore b/main/verilog/ip/prgrom/.gitignore deleted file mode 100644 index d3e4399..0000000 --- a/main/verilog/ip/prgrom/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/* -!**.xci diff --git a/main/verilog/ip/ram/.gitignore b/main/verilog/ip/ram/.gitignore deleted file mode 100644 index d3e4399..0000000 --- a/main/verilog/ip/ram/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/* -!**.xci diff --git a/main/verilog/ip/cpuclk/cpuclk.xci b/main/verilog/ip_invoke/cpuclk/cpuclk.xci similarity index 100% rename from main/verilog/ip/cpuclk/cpuclk.xci rename to main/verilog/ip_invoke/cpuclk/cpuclk.xci diff --git a/main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci b/main/verilog/ip_invoke/iart_bmpg_0/uart_bmpg_0.xci similarity index 100% rename from main/verilog/ip/iart_bmpg_0/uart_bmpg_0.xci rename to main/verilog/ip_invoke/iart_bmpg_0/uart_bmpg_0.xci diff --git a/main/verilog/ip/prgrom/prgrom.xci b/main/verilog/ip_invoke/prgrom/prgrom.xci similarity index 100% rename from main/verilog/ip/prgrom/prgrom.xci rename to main/verilog/ip_invoke/prgrom/prgrom.xci diff --git a/main/verilog/ip/ram/RAM.xci b/main/verilog/ip_invoke/ram/RAM.xci similarity index 100% rename from main/verilog/ip/ram/RAM.xci rename to main/verilog/ip_invoke/ram/RAM.xci -- Gitee From 1eaaf9b759f74ea3e5a6aa6f65951c6bc7ffbaa9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 00:35:44 +0800 Subject: [PATCH 54/57] =?UTF-8?q?fix(verilog):=20=E4=BF=AE=E5=A4=8Dip?= =?UTF-8?q?=E6=A0=B8=E4=BD=8D=E7=BD=AE=EF=BC=8C=E5=88=86=E6=96=87=E4=BB=B6?= =?UTF-8?q?=E5=A4=B9=E5=AD=98=E5=82=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../component.xml | 345 + .../uart_bmpg.edif | 13965 ++++++++++++++++ .../uart_bmpg.v | 37 + .../SEU_CSE_507_user_uart_bmpg_1.3/upg.v | 51 + .../xgui/uart_bmpg_v1_3.tcl | 71 + 5 files changed, 14469 insertions(+) create mode 100644 main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/component.xml create mode 100644 main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif create mode 100644 main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v create mode 100644 main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/upg.v create mode 100644 main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl diff --git a/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/component.xml b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/component.xml new file mode 100644 index 0000000..8008995 --- /dev/null +++ b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/component.xml @@ -0,0 +1,345 @@ + + + SEU_CSE_507 + user + uart_bmpg + 1.3 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + upg + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 36acd76a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + upg + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6b59a370 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c3dd6d67 + + + + + xilinx_implementation + Implementation + :vivado.xilinx.com:implementation + + xilinx_implementation_view_fileset + + + + viewChecksum + 995a2cc2 + + + + + + + upg_clk_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_rst_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_clk_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_wen_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_adr_o + + out + + 14 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_dat_o + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_done_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_rx_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upg_tx_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + uart_bmpg.edif + edn + + + uart_bmpg.v + verilogSource + CHECKSUM_3f5e0c86 + + + upg.v + verilogSource + CHECKSUM_049fde7b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + uart_bmpg.v + verilogSource + + + upg.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/uart_bmpg_v1_3.tcl + tclSource + CHECKSUM_c3dd6d67 + XGUI_VERSION_2 + + + + xilinx_implementation_view_fileset + + uart_bmpg.edif + edn + + + + uart_bmpg_v1_3 + + + Component_Name + uart_bmpg_v1_3 + + + Input_Clock_Freqency + 10 MHz + + + + false + + + + + + Baud_Rate + 128000 bps + + + + false + + + + + + Data_Bits + 8 bits + + + + false + + + + + + Stop_Bits + Stop Bit(s) + 1 bit(s) + + + + false + + + + + + Parity + No + + + + false + + + + + + Reset + Active High + + + + false + + + + + + + + + artix7 + + + /UserIP + + uart_bmpg_v1_3 + package_project + 8 + 2018-07-14T12:11:51Z + + i:/uart_bmpg/uart_bmpg.srcs/sources_1/new + i:/uart_bmpg/uart_bmpg.srcs/sources_1/new + h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new + h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new + h:/Workspace_Xilinx/Vivado/uart_bmpg/uart_bmpg/uart_bmpg.srcs/sources_1/new + + + + 2017.4 + + + + + + diff --git a/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif new file mode 100644 index 0000000..e53e627 --- /dev/null +++ b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.edif @@ -0,0 +1,13965 @@ +(edif uart_bmpg + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2018 07 14 20 08 21) + (program "Vivado" (version "2017.4")) + (comment "Built on 'Fri Dec 15 20:55:39 MST 2017'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell FDCE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port CLR (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell FDRE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell SRL16E (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port A0 (direction INPUT)) + (port A1 (direction INPUT)) + (port A2 (direction INPUT)) + (port A3 (direction INPUT)) + (port CE (direction INPUT)) + (port CLK (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell FDSE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell CARRY4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CI (direction INPUT)) + (port CYINIT (direction INPUT)) + (port (array (rename CO "CO[3:0]") 4) (direction OUTPUT)) + (port (array (rename O "O[3:0]") 4) (direction OUTPUT)) + (port (array (rename DI "DI[3:0]") 4) (direction INPUT)) + (port (array (rename S "S[3:0]") 4) (direction INPUT)) + ) + ) + ) + (cell BUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell FDPE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell OBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell IBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library work_library0_1 + (edifLevel 0) + (technology (numberDefinition )) + (cell axi_uart_pselect_f (celltype GENERIC) + (view pselect_f (viewtype NETLIST) + (interface + (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) + (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) + (port ce_expnd_i_3 (direction OUTPUT)) + ) + (contents + (instance CS (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined + (portref I0 (instanceref CS)) + (portref bus2ip_addr_i_reg_2_) + ) + ) + (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined + (portref I1 (instanceref CS)) + (portref bus2ip_addr_i_reg_3_) + ) + ) + (net ce_expnd_i_3 (joined + (portref O (instanceref CS)) + (portref ce_expnd_i_3) + ) + ) + ) + + (property ORIG_REF_NAME (string "pselect_f")) + ) + ) + (cell axi_uart_pselect_f__parameterized1 (celltype GENERIC) + (view pselect_f__parameterized1 (viewtype NETLIST) + (interface + (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) + (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) + (port ce_expnd_i_1 (direction OUTPUT)) + ) + (contents + (instance CS (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined + (portref I1 (instanceref CS)) + (portref bus2ip_addr_i_reg_2_) + ) + ) + (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined + (portref I0 (instanceref CS)) + (portref bus2ip_addr_i_reg_3_) + ) + ) + (net ce_expnd_i_1 (joined + (portref O (instanceref CS)) + (portref ce_expnd_i_1) + ) + ) + ) + + (property ORIG_REF_NAME (string "pselect_f")) + ) + ) + (cell axi_uart_address_decoder (celltype GENERIC) + (view address_decoder (viewtype NETLIST) + (interface + (port FIFO_Full_reg (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) + (port (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (direction INPUT)) + (port (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (direction INPUT)) + (port bus2ip_rnw_i (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port enable_interrupts_reg (direction OUTPUT)) + (port enable_interrupts_reg_0 (direction OUTPUT)) + (port fifo_wr (direction OUTPUT)) + (port ip2bus_error (direction OUTPUT)) + (port reset_RX_FIFO (direction OUTPUT)) + (port reset_TX_FIFO (direction OUTPUT)) + (port rx_Buffer_Full (direction INPUT)) + (port rx_Data_Present_Pre_reg (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_bready (direction INPUT)) + (port (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (direction OUTPUT)) + (port s_axi_bvalid_i_reg (direction OUTPUT)) + (port s_axi_bvalid_i_reg_0 (direction INPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid_i_reg (direction OUTPUT)) + (port s_axi_rvalid_i_reg_0 (direction INPUT)) + (port s_axi_wvalid (direction INPUT)) + (port start2 (direction INPUT)) + (port (rename state_reg_0_ "state_reg[0]") (direction INPUT)) + (port (rename state_reg_1_ "state_reg[1]") (direction INPUT)) + (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port (array (rename D "D[1:0]") 2) (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (direction INPUT)) + (port (array (rename Q "Q[1:0]") 2) (direction INPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction INPUT)) + (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction INPUT)) + (port (array (rename s_axi_rdata_i_reg_7_ "s_axi_rdata_i_reg[7][7:0]") 8) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance Bus_RNW_reg_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hB8")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance Bus_RNW_reg_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1 "GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_ "GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1 "GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFEFFFF")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2 "GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename INFERRED_GEN_cnt_i_3__i_2 "INFERRED_GEN.cnt_i[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF7")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_3 "INFERRED_GEN.cnt_i[4]_i_3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h7")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_5 "INFERRED_GEN.cnt_i[4]_i_5") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFD")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16_i_1 "INFERRED_GEN.data_reg[15][7]_srl16_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h10")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I "MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I") (viewref pselect_f (cellref axi_uart_pselect_f (libraryref work_library0_1)))) + (instance (rename MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I "MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I") (viewref pselect_f__parameterized1 (cellref axi_uart_pselect_f__parameterized1 (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance clr_Status_i_1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance enable_interrupts_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFB08")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance reset_RX_FIFO_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance reset_TX_FIFO_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance rx_Data_Present_Pre_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0444")) + ) + (instance s_axi_arready_INST_0 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hF0F0F0E0")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename s_axi_bresp_i_1__i_1 "s_axi_bresp_i[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFB08")) + ) + (instance s_axi_bvalid_i_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h40FF4040")) + ) + (instance (rename s_axi_rdata_i_0__i_1 "s_axi_rdata_i[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h5050C000")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename s_axi_rdata_i_1__i_1 "s_axi_rdata_i[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename s_axi_rdata_i_2__i_1 "s_axi_rdata_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename s_axi_rdata_i_3__i_1 "s_axi_rdata_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_4__i_1 "s_axi_rdata_i[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_5__i_1 "s_axi_rdata_i[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_6__i_1 "s_axi_rdata_i[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hA0A0C000")) + ) + (instance (rename s_axi_rdata_i_7__i_2 "s_axi_rdata_i[7]_i_2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename s_axi_rresp_i_1__i_1 "s_axi_rresp_i[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hF0880088")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance s_axi_rvalid_i_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h40FF4040")) + ) + (instance s_axi_wready_INST_0 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0F0F0F0E")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename state_0__i_1 "state[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hCFEFCFEC")) + ) + (instance (rename state_1__i_1 "state[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hCFECCFECCFEFCFEC")) + ) + (instance tx_Buffer_Empty_Pre_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8808")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref Bus_RNW_reg_reg)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref Bus_RNW_reg_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg_i_1_n_0 (joined + (portref D (instanceref Bus_RNW_reg_reg)) + (portref O (instanceref Bus_RNW_reg_i_1)) + ) + ) + (net (rename D_0_ "D[0]") (joined + (portref O (instanceref state_0__i_1)) + (portref (member D 1)) + ) + ) + (net (rename D_1_ "D[1]") (joined + (portref O (instanceref state_1__i_1)) + (portref (member D 0)) + ) + ) + (net FIFO_Full_reg (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_3)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (joined + (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref I0 (instanceref s_axi_rresp_i_1__i_1)) + (portref I0 (instanceref s_axi_wready_INST_0)) + (portref I2 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref I2 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref I3 (instanceref s_axi_arready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_3)) + (portref I0 (instanceref s_axi_arready_INST_0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref I1 (instanceref s_axi_rdata_i_7__i_2)) + (portref I2 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I2 (instanceref s_axi_rresp_i_1__i_1)) + (portref I3 (instanceref rx_Data_Present_Pre_i_1)) + (portref I3 (instanceref s_axi_rdata_i_0__i_1)) + (portref I3 (instanceref s_axi_rdata_i_1__i_1)) + (portref I3 (instanceref s_axi_rdata_i_2__i_1)) + (portref I3 (instanceref s_axi_rdata_i_3__i_1)) + (portref I3 (instanceref s_axi_rdata_i_4__i_1)) + (portref I3 (instanceref s_axi_rdata_i_5__i_1)) + (portref I3 (instanceref s_axi_rdata_i_6__i_1)) + (portref I3 (instanceref s_axi_wready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg") (joined + (portref I0 (instanceref clr_Status_i_1)) + (portref I0 (instanceref s_axi_rdata_i_7__i_2)) + (portref I1 (instanceref s_axi_arready_INST_0)) + (portref I3 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I4 (instanceref s_axi_rdata_i_0__i_1)) + (portref I4 (instanceref s_axi_rdata_i_1__i_1)) + (portref I4 (instanceref s_axi_rdata_i_2__i_1)) + (portref I4 (instanceref s_axi_rdata_i_3__i_1)) + (portref I4 (instanceref s_axi_rdata_i_4__i_1)) + (portref I4 (instanceref s_axi_rdata_i_5__i_1)) + (portref I4 (instanceref s_axi_rdata_i_6__i_1)) + (portref I4 (instanceref s_axi_wready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg") (joined + (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref I1 (instanceref enable_interrupts_i_1)) + (portref I1 (instanceref reset_RX_FIFO_i_1)) + (portref I1 (instanceref reset_TX_FIFO_i_1)) + (portref I1 (instanceref s_axi_wready_INST_0)) + (portref I4 (instanceref s_axi_arready_INST_0)) + (portref Q (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref INFERRED_GEN_cnt_i_reg_2_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref INFERRED_GEN_cnt_i_reg_2__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref I0 (instanceref rx_Data_Present_Pre_i_1)) + (portref I0 (instanceref s_axi_rdata_i_0__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref I4 (instanceref s_axi_rresp_i_1__i_1)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (joined + (portref I0 (instanceref s_axi_rdata_i_2__i_1)) + (portref I1 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref INFERRED_GEN_cnt_i_reg_4__0_0_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref I0 (instanceref s_axi_bvalid_i_i_1)) + (portref I1 (instanceref s_axi_rvalid_i_i_1)) + (portref I2 (instanceref s_axi_bresp_i_1__i_1)) + (portref I2 (instanceref state_1__i_1)) + (portref I3 (instanceref state_0__i_1)) + (portref (member Q 1)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref I0 (instanceref s_axi_rvalid_i_i_1)) + (portref I1 (instanceref s_axi_bresp_i_1__i_1)) + (portref I1 (instanceref s_axi_bvalid_i_i_1)) + (portref I2 (instanceref state_0__i_1)) + (portref I3 (instanceref state_1__i_1)) + (portref (member Q 0)) + ) + ) + (net (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (joined + (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) + (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) + (portref bus2ip_addr_i_reg_2_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_2_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_2_) + ) + ) + (net (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (joined + (portref I0 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) + (portref I1 (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) + (portref bus2ip_addr_i_reg_3_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_3_ (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + (portref bus2ip_addr_i_reg_3_) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref O (instanceref clr_Status_i_1)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_rnw_i (joined + (portref I0 (instanceref Bus_RNW_reg_i_1)) + (portref bus2ip_rnw_i) + ) + ) + (net ce_expnd_i_0 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + (portref O (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_2)) + ) + ) + (net ce_expnd_i_1 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref ce_expnd_i_1 (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_2__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + ) + ) + (net ce_expnd_i_2 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref O (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_1__i_1)) + ) + ) + (net ce_expnd_i_3 (joined + (portref D (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref ce_expnd_i_3 (instanceref MEM_DECODE_GEN_0__PER_CE_GEN_0__MULTIPLE_CES_THIS_CS_GEN_CE_I)) + ) + ) + (net cs_ce_clr (joined + (portref O (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref R (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + ) + ) + (net enable_interrupts (joined + (portref I0 (instanceref s_axi_rdata_i_4__i_1)) + (portref I3 (instanceref enable_interrupts_i_1)) + (portref enable_interrupts) + ) + ) + (net enable_interrupts_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_2)) + (portref I0 (instanceref reset_RX_FIFO_i_1)) + (portref I0 (instanceref reset_TX_FIFO_i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_3)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref I1 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref I1 (instanceref clr_Status_i_1)) + (portref I2 (instanceref Bus_RNW_reg_i_1)) + (portref I2 (instanceref enable_interrupts_i_1)) + (portref I2 (instanceref rx_Data_Present_Pre_i_1)) + (portref I2 (instanceref s_axi_arready_INST_0)) + (portref I2 (instanceref s_axi_rdata_i_0__i_1)) + (portref I2 (instanceref s_axi_rdata_i_1__i_1)) + (portref I2 (instanceref s_axi_rdata_i_2__i_1)) + (portref I2 (instanceref s_axi_rdata_i_3__i_1)) + (portref I2 (instanceref s_axi_rdata_i_4__i_1)) + (portref I2 (instanceref s_axi_rdata_i_5__i_1)) + (portref I2 (instanceref s_axi_rdata_i_6__i_1)) + (portref I2 (instanceref s_axi_rdata_i_7__i_2)) + (portref I2 (instanceref s_axi_wready_INST_0)) + (portref I3 (instanceref s_axi_rresp_i_1__i_1)) + (portref I3 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref Q (instanceref Bus_RNW_reg_reg)) + (portref enable_interrupts_reg) + ) + ) + (net enable_interrupts_reg_0 (joined + (portref O (instanceref enable_interrupts_i_1)) + (portref enable_interrupts_reg_0) + ) + ) + (net fifo_wr (joined + (portref O (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref fifo_wr) + ) + ) + (net ip2bus_error (joined + (portref I0 (instanceref s_axi_bresp_i_1__i_1)) + (portref O (instanceref s_axi_rresp_i_1__i_1)) + (portref ip2bus_error) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref I1 (instanceref s_axi_rdata_i_0__i_1)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref I1 (instanceref s_axi_rdata_i_1__i_1)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref I1 (instanceref s_axi_rdata_i_2__i_1)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref I1 (instanceref s_axi_rdata_i_3__i_1)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref I1 (instanceref s_axi_rdata_i_4__i_1)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref I1 (instanceref s_axi_rdata_i_5__i_1)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref I1 (instanceref s_axi_rdata_i_6__i_1)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref I3 (instanceref s_axi_rdata_i_7__i_2)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref O (instanceref reset_RX_FIFO_i_1)) + (portref reset_RX_FIFO) + ) + ) + (net reset_TX_FIFO (joined + (portref O (instanceref reset_TX_FIFO_i_1)) + (portref reset_TX_FIFO) + ) + ) + (net rx_Buffer_Full (joined + (portref I0 (instanceref s_axi_rdata_i_1__i_1)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre_reg (joined + (portref O (instanceref rx_Data_Present_Pre_i_1)) + (portref rx_Data_Present_Pre_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref Bus_RNW_reg_reg)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref C (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I0 (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref I1 (instanceref rx_Data_Present_Pre_i_1)) + (portref I4 (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_3__i_1)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref I0 (instanceref state_1__i_1)) + (portref I2 (instanceref s_axi_rvalid_i_i_1)) + (portref O (instanceref s_axi_arready_INST_0)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref I4 (instanceref state_0__i_1)) + (portref I5 (instanceref state_1__i_1)) + (portref s_axi_arvalid) + ) + ) + (net s_axi_awready (joined + (portref I0 (instanceref state_0__i_1)) + (portref I2 (instanceref s_axi_bvalid_i_i_1)) + (portref O (instanceref s_axi_wready_INST_0)) + (portref s_axi_awready) + ) + ) + (net s_axi_bready (joined + (portref I3 (instanceref s_axi_bvalid_i_i_1)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref I3 (instanceref s_axi_bresp_i_1__i_1)) + (portref s_axi_bresp_0_) + ) + ) + (net (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (joined + (portref O (instanceref s_axi_bresp_i_1__i_1)) + (portref s_axi_bresp_i_reg_1_) + ) + ) + (net s_axi_bvalid_i_reg (joined + (portref O (instanceref s_axi_bvalid_i_i_1)) + (portref s_axi_bvalid_i_reg) + ) + ) + (net s_axi_bvalid_i_reg_0 (joined + (portref I4 (instanceref s_axi_bvalid_i_i_1)) + (portref s_axi_bvalid_i_reg_0) + ) + ) + (net (rename s_axi_rdata_i_reg_7__0_ "s_axi_rdata_i_reg[7][0]") (joined + (portref O (instanceref s_axi_rdata_i_0__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 7)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__1_ "s_axi_rdata_i_reg[7][1]") (joined + (portref O (instanceref s_axi_rdata_i_1__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 6)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__2_ "s_axi_rdata_i_reg[7][2]") (joined + (portref O (instanceref s_axi_rdata_i_2__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 5)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__3_ "s_axi_rdata_i_reg[7][3]") (joined + (portref O (instanceref s_axi_rdata_i_3__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 4)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__4_ "s_axi_rdata_i_reg[7][4]") (joined + (portref O (instanceref s_axi_rdata_i_4__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 3)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__5_ "s_axi_rdata_i_reg[7][5]") (joined + (portref O (instanceref s_axi_rdata_i_5__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 2)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__6_ "s_axi_rdata_i_reg[7][6]") (joined + (portref O (instanceref s_axi_rdata_i_6__i_1)) + (portref (member s_axi_rdata_i_reg_7_ 1)) + ) + ) + (net (rename s_axi_rdata_i_reg_7__7_ "s_axi_rdata_i_reg[7][7]") (joined + (portref O (instanceref s_axi_rdata_i_7__i_2)) + (portref (member s_axi_rdata_i_reg_7_ 0)) + ) + ) + (net s_axi_rready (joined + (portref I3 (instanceref s_axi_rvalid_i_i_1)) + (portref s_axi_rready) + ) + ) + (net s_axi_rvalid_i_reg (joined + (portref O (instanceref s_axi_rvalid_i_i_1)) + (portref s_axi_rvalid_i_reg) + ) + ) + (net s_axi_rvalid_i_reg_0 (joined + (portref I4 (instanceref s_axi_rvalid_i_i_1)) + (portref s_axi_rvalid_i_reg_0) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref I2 (instanceref reset_TX_FIFO_i_1)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref I2 (instanceref reset_RX_FIFO_i_1)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref I0 (instanceref enable_interrupts_i_1)) + (portref (member s_axi_wdata 0)) + ) + ) + (net s_axi_wvalid (joined + (portref I4 (instanceref state_1__i_1)) + (portref s_axi_wvalid) + ) + ) + (net start2 (joined + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_)) + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_)) + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_2__ce_out_i_reg_2_)) + (portref CE (instanceref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_)) + (portref I1 (instanceref Bus_RNW_reg_i_1)) + (portref start2) + ) + ) + (net (rename state_reg_0_ "state_reg[0]") (joined + (portref I1 (instanceref state_0__i_1)) + (portref state_reg_0_) + ) + ) + (net (rename state_reg_1_ "state_reg[1]") (joined + (portref I1 (instanceref state_1__i_1)) + (portref state_reg_1_) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref I0 (instanceref s_axi_rdata_i_5__i_1)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref I0 (instanceref s_axi_rdata_i_6__i_1)) + (portref (member status_reg 0)) + ) + ) + (net tx_Buffer_Empty_Pre_reg (joined + (portref O (instanceref tx_Buffer_Empty_Pre_i_1)) + (portref tx_Buffer_Empty_Pre_reg) + ) + ) + (net tx_Buffer_Full (joined + (portref I0 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1)) + (portref I0 (instanceref s_axi_rdata_i_3__i_1)) + (portref I1 (instanceref s_axi_rresp_i_1__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_5)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "address_decoder")) + ) + ) + (cell axi_uart_slave_attachment (celltype GENERIC) + (view slave_attachment (viewtype NETLIST) + (interface + (port FIFO_Full_reg (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) + (port bus2ip_reset (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port enable_interrupts_reg (direction OUTPUT)) + (port enable_interrupts_reg_0 (direction OUTPUT)) + (port fifo_wr (direction OUTPUT)) + (port reset_RX_FIFO (direction OUTPUT)) + (port reset_TX_FIFO (direction OUTPUT)) + (port rx_Buffer_Full (direction INPUT)) + (port rx_Data_Present_Pre_reg (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_awvalid (direction INPUT)) + (port s_axi_bready (direction INPUT)) + (port s_axi_bvalid (direction OUTPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid (direction OUTPUT)) + (port s_axi_wvalid (direction INPUT)) + (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction INPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction INPUT)) + (port (array (rename s_axi_araddr "s_axi_araddr[1:0]") 2) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[1:0]") 2) (direction INPUT)) + (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[7:0]") 8) (direction OUTPUT)) + (port (rename s_axi_rresp_0_ "s_axi_rresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance I_DECODER (viewref address_decoder (cellref axi_uart_address_decoder (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename bus2ip_addr_i_2__i_1 "bus2ip_addr_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hB8FFB800")) + ) + (instance (rename bus2ip_addr_i_3__i_1 "bus2ip_addr_i[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hB8FFB800")) + ) + (instance (rename bus2ip_addr_i_3__i_2 "bus2ip_addr_i[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hEF")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bus2ip_addr_i_reg_2_ "bus2ip_addr_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bus2ip_addr_i_reg_3_ "bus2ip_addr_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bus2ip_rnw_i_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFF7000000F0")) + ) + (instance bus2ip_rnw_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rst_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_bresp_i_reg_1_ "s_axi_bresp_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_bvalid_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_7__i_1 "s_axi_rdata_i[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename s_axi_rdata_i_reg_0_ "s_axi_rdata_i_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_1_ "s_axi_rdata_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_2_ "s_axi_rdata_i_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_3_ "s_axi_rdata_i_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_4_ "s_axi_rdata_i_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_5_ "s_axi_rdata_i_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_6_ "s_axi_rdata_i_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rdata_i_reg_7_ "s_axi_rdata_i_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_rresp_i_reg_1_ "s_axi_rresp_i_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_rvalid_i_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance start2_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h000000F8")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance start2_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename state_0__i_2 "state[0]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h002A2A2A")) + ) + (instance (rename state_1__i_2 "state[1]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h002A2A2A")) + ) + (instance (rename state_1__i_3 "state[1]_i_3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + ) + (instance (rename state_reg_0_ "state_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename state_reg_1_ "state_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref rst_reg)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref bus2ip_addr_i_reg_2_)) + (portref CE (instanceref bus2ip_addr_i_reg_3_)) + (portref CE (instanceref bus2ip_rnw_i_reg)) + (portref CE (instanceref rst_reg)) + (portref CE (instanceref s_axi_bresp_i_reg_1_)) + (portref CE (instanceref s_axi_bvalid_i_reg)) + (portref CE (instanceref s_axi_rvalid_i_reg)) + (portref CE (instanceref start2_reg)) + (portref CE (instanceref state_reg_0_)) + (portref CE (instanceref state_reg_1_)) + (portref P (instanceref VCC)) + ) + ) + (net FIFO_Full_reg (joined + (portref FIFO_Full_reg (instanceref I_DECODER)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 (instanceref I_DECODER)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__1 (instanceref I_DECODER)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined + (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref I_DECODER)) + (portref INFERRED_GEN_cnt_i_reg_2_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined + (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref I_DECODER)) + (portref INFERRED_GEN_cnt_i_reg_2__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_0_ (instanceref I_DECODER)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net I_DECODER_n_26 (joined + (portref D (instanceref s_axi_rvalid_i_reg)) + (portref s_axi_rvalid_i_reg (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_27 (joined + (portref D (instanceref s_axi_bvalid_i_reg)) + (portref s_axi_bvalid_i_reg (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_28 (joined + (portref D (instanceref s_axi_bresp_i_reg_1_)) + (portref s_axi_bresp_i_reg_1_ (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_5 (joined + (portref D (instanceref state_reg_1_)) + (portref (member D 0) (instanceref I_DECODER)) + ) + ) + (net I_DECODER_n_6 (joined + (portref D (instanceref state_reg_0_)) + (portref (member D 1) (instanceref I_DECODER)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_DECODER)) + (portref Q_0_) + ) + ) + (net (rename SIn_DBus_0_ "SIn_DBus[0]") (joined + (portref D (instanceref s_axi_rdata_i_reg_7_)) + (portref (member s_axi_rdata_i_reg_7_ 0) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_1_ "SIn_DBus[1]") (joined + (portref D (instanceref s_axi_rdata_i_reg_6_)) + (portref (member s_axi_rdata_i_reg_7_ 1) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_2_ "SIn_DBus[2]") (joined + (portref D (instanceref s_axi_rdata_i_reg_5_)) + (portref (member s_axi_rdata_i_reg_7_ 2) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_3_ "SIn_DBus[3]") (joined + (portref D (instanceref s_axi_rdata_i_reg_4_)) + (portref (member s_axi_rdata_i_reg_7_ 3) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_4_ "SIn_DBus[4]") (joined + (portref D (instanceref s_axi_rdata_i_reg_3_)) + (portref (member s_axi_rdata_i_reg_7_ 4) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_5_ "SIn_DBus[5]") (joined + (portref D (instanceref s_axi_rdata_i_reg_2_)) + (portref (member s_axi_rdata_i_reg_7_ 5) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_6_ "SIn_DBus[6]") (joined + (portref D (instanceref s_axi_rdata_i_reg_1_)) + (portref (member s_axi_rdata_i_reg_7_ 6) (instanceref I_DECODER)) + ) + ) + (net (rename SIn_DBus_7_ "SIn_DBus[7]") (joined + (portref D (instanceref s_axi_rdata_i_reg_0_)) + (portref (member s_axi_rdata_i_reg_7_ 7) (instanceref I_DECODER)) + ) + ) + (net (rename bus2ip_addr_i_2__i_1_n_0 "bus2ip_addr_i[2]_i_1_n_0") (joined + (portref D (instanceref bus2ip_addr_i_reg_2_)) + (portref O (instanceref bus2ip_addr_i_2__i_1)) + ) + ) + (net (rename bus2ip_addr_i_3__i_1_n_0 "bus2ip_addr_i[3]_i_1_n_0") (joined + (portref D (instanceref bus2ip_addr_i_reg_3_)) + (portref O (instanceref bus2ip_addr_i_3__i_1)) + ) + ) + (net (rename bus2ip_addr_i_3__i_2_n_0 "bus2ip_addr_i[3]_i_2_n_0") (joined + (portref I1 (instanceref bus2ip_addr_i_2__i_1)) + (portref I1 (instanceref bus2ip_addr_i_3__i_1)) + (portref O (instanceref bus2ip_addr_i_3__i_2)) + ) + ) + (net (rename bus2ip_addr_i_reg_n_0__2_ "bus2ip_addr_i_reg_n_0_[2]") (joined + (portref I4 (instanceref bus2ip_addr_i_2__i_1)) + (portref Q (instanceref bus2ip_addr_i_reg_2_)) + (portref bus2ip_addr_i_reg_2_ (instanceref I_DECODER)) + ) + ) + (net (rename bus2ip_addr_i_reg_n_0__3_ "bus2ip_addr_i_reg_n_0_[3]") (joined + (portref I4 (instanceref bus2ip_addr_i_3__i_1)) + (portref Q (instanceref bus2ip_addr_i_reg_3_)) + (portref bus2ip_addr_i_reg_3_ (instanceref I_DECODER)) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref bus2ip_rdce_0_ (instanceref I_DECODER)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_reset (joined + (portref D (instanceref rst_reg)) + (portref bus2ip_reset) + ) + ) + (net bus2ip_rnw_i (joined + (portref I5 (instanceref bus2ip_rnw_i_i_1)) + (portref Q (instanceref bus2ip_rnw_i_reg)) + (portref bus2ip_rnw_i (instanceref I_DECODER)) + ) + ) + (net bus2ip_rnw_i_i_1_n_0 (joined + (portref D (instanceref bus2ip_rnw_i_reg)) + (portref O (instanceref bus2ip_rnw_i_i_1)) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref I_DECODER)) + (portref enable_interrupts) + ) + ) + (net enable_interrupts_reg (joined + (portref enable_interrupts_reg (instanceref I_DECODER)) + (portref enable_interrupts_reg) + ) + ) + (net enable_interrupts_reg_0 (joined + (portref enable_interrupts_reg_0 (instanceref I_DECODER)) + (portref enable_interrupts_reg_0) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref I_DECODER)) + (portref fifo_wr) + ) + ) + (net ip2bus_error (joined + (portref D (instanceref s_axi_rresp_i_reg_1_)) + (portref ip2bus_error (instanceref I_DECODER)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref I_DECODER)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref I_DECODER)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref I_DECODER)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref I_DECODER)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref I_DECODER)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref I_DECODER)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref I_DECODER)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref I_DECODER)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref reset_RX_FIFO (instanceref I_DECODER)) + (portref reset_RX_FIFO) + ) + ) + (net reset_TX_FIFO (joined + (portref reset_TX_FIFO (instanceref I_DECODER)) + (portref reset_TX_FIFO) + ) + ) + (net rst (joined + (portref Q (instanceref rst_reg)) + (portref R (instanceref bus2ip_addr_i_reg_2_)) + (portref R (instanceref bus2ip_addr_i_reg_3_)) + (portref R (instanceref bus2ip_rnw_i_reg)) + (portref R (instanceref s_axi_bresp_i_reg_1_)) + (portref R (instanceref s_axi_bvalid_i_reg)) + (portref R (instanceref s_axi_rdata_i_reg_0_)) + (portref R (instanceref s_axi_rdata_i_reg_1_)) + (portref R (instanceref s_axi_rdata_i_reg_2_)) + (portref R (instanceref s_axi_rdata_i_reg_3_)) + (portref R (instanceref s_axi_rdata_i_reg_4_)) + (portref R (instanceref s_axi_rdata_i_reg_5_)) + (portref R (instanceref s_axi_rdata_i_reg_6_)) + (portref R (instanceref s_axi_rdata_i_reg_7_)) + (portref R (instanceref s_axi_rresp_i_reg_1_)) + (portref R (instanceref s_axi_rvalid_i_reg)) + (portref R (instanceref start2_reg)) + (portref R (instanceref state_reg_0_)) + (portref R (instanceref state_reg_1_)) + ) + ) + (net rx_Buffer_Full (joined + (portref rx_Buffer_Full (instanceref I_DECODER)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre_reg (joined + (portref rx_Data_Present_Pre_reg (instanceref I_DECODER)) + (portref rx_Data_Present_Pre_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref bus2ip_addr_i_reg_2_)) + (portref C (instanceref bus2ip_addr_i_reg_3_)) + (portref C (instanceref bus2ip_rnw_i_reg)) + (portref C (instanceref rst_reg)) + (portref C (instanceref s_axi_bresp_i_reg_1_)) + (portref C (instanceref s_axi_bvalid_i_reg)) + (portref C (instanceref s_axi_rdata_i_reg_0_)) + (portref C (instanceref s_axi_rdata_i_reg_1_)) + (portref C (instanceref s_axi_rdata_i_reg_2_)) + (portref C (instanceref s_axi_rdata_i_reg_3_)) + (portref C (instanceref s_axi_rdata_i_reg_4_)) + (portref C (instanceref s_axi_rdata_i_reg_5_)) + (portref C (instanceref s_axi_rdata_i_reg_6_)) + (portref C (instanceref s_axi_rdata_i_reg_7_)) + (portref C (instanceref s_axi_rresp_i_reg_1_)) + (portref C (instanceref s_axi_rvalid_i_reg)) + (portref C (instanceref start2_reg)) + (portref C (instanceref state_reg_0_)) + (portref C (instanceref state_reg_1_)) + (portref s_axi_aclk (instanceref I_DECODER)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined + (portref I2 (instanceref bus2ip_addr_i_2__i_1)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined + (portref I2 (instanceref bus2ip_addr_i_3__i_1)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_DECODER)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref I_DECODER)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref I2 (instanceref bus2ip_addr_i_3__i_2)) + (portref I2 (instanceref bus2ip_rnw_i_i_1)) + (portref I2 (instanceref start2_i_1)) + (portref s_axi_arvalid (instanceref I_DECODER)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined + (portref I0 (instanceref bus2ip_addr_i_2__i_1)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined + (portref I0 (instanceref bus2ip_addr_i_3__i_1)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref I_DECODER)) + (portref s_axi_awready) + ) + ) + (net s_axi_awvalid (joined + (portref I0 (instanceref bus2ip_rnw_i_i_1)) + (portref I0 (instanceref start2_i_1)) + (portref I0 (instanceref state_1__i_3)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref I3 (instanceref state_0__i_2)) + (portref I3 (instanceref state_1__i_2)) + (portref s_axi_bready (instanceref I_DECODER)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref Q (instanceref s_axi_bresp_i_reg_1_)) + (portref s_axi_bresp_0_ (instanceref I_DECODER)) + (portref s_axi_bresp_0_) + ) + ) + (net s_axi_bvalid (joined + (portref I4 (instanceref state_0__i_2)) + (portref I4 (instanceref state_1__i_2)) + (portref Q (instanceref s_axi_bvalid_i_reg)) + (portref s_axi_bvalid_i_reg_0 (instanceref I_DECODER)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_0_)) + (portref (member s_axi_rdata 7)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_1_)) + (portref (member s_axi_rdata 6)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_2_)) + (portref (member s_axi_rdata 5)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_3_)) + (portref (member s_axi_rdata 4)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_4_)) + (portref (member s_axi_rdata 3)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_5_)) + (portref (member s_axi_rdata 2)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_6_)) + (portref (member s_axi_rdata 1)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref Q (instanceref s_axi_rdata_i_reg_7_)) + (portref (member s_axi_rdata 0)) + ) + ) + (net s_axi_rdata_i (joined + (portref CE (instanceref s_axi_rdata_i_reg_0_)) + (portref CE (instanceref s_axi_rdata_i_reg_1_)) + (portref CE (instanceref s_axi_rdata_i_reg_2_)) + (portref CE (instanceref s_axi_rdata_i_reg_3_)) + (portref CE (instanceref s_axi_rdata_i_reg_4_)) + (portref CE (instanceref s_axi_rdata_i_reg_5_)) + (portref CE (instanceref s_axi_rdata_i_reg_6_)) + (portref CE (instanceref s_axi_rdata_i_reg_7_)) + (portref CE (instanceref s_axi_rresp_i_reg_1_)) + (portref O (instanceref s_axi_rdata_i_7__i_1)) + ) + ) + (net s_axi_rready (joined + (portref I2 (instanceref state_0__i_2)) + (portref I2 (instanceref state_1__i_2)) + (portref s_axi_rready (instanceref I_DECODER)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined + (portref Q (instanceref s_axi_rresp_i_reg_1_)) + (portref s_axi_rresp_0_) + ) + ) + (net s_axi_rvalid (joined + (portref I1 (instanceref state_0__i_2)) + (portref I1 (instanceref state_1__i_2)) + (portref Q (instanceref s_axi_rvalid_i_reg)) + (portref s_axi_rvalid_i_reg_0 (instanceref I_DECODER)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 2) (instanceref I_DECODER)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 1) (instanceref I_DECODER)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 0) (instanceref I_DECODER)) + (portref (member s_axi_wdata 0)) + ) + ) + (net s_axi_wvalid (joined + (portref I1 (instanceref bus2ip_rnw_i_i_1)) + (portref I1 (instanceref start2_i_1)) + (portref I1 (instanceref state_1__i_3)) + (portref s_axi_wvalid) + ) + ) + (net start2 (joined + (portref Q (instanceref start2_reg)) + (portref start2 (instanceref I_DECODER)) + ) + ) + (net start2_i_1_n_0 (joined + (portref D (instanceref start2_reg)) + (portref I3 (instanceref bus2ip_addr_i_2__i_1)) + (portref I3 (instanceref bus2ip_addr_i_3__i_1)) + (portref O (instanceref start2_i_1)) + ) + ) + (net (rename state_0_ "state[0]") (joined + (portref I0 (instanceref s_axi_rdata_i_7__i_1)) + (portref I0 (instanceref state_0__i_2)) + (portref I1 (instanceref bus2ip_addr_i_3__i_2)) + (portref I3 (instanceref bus2ip_rnw_i_i_1)) + (portref I3 (instanceref start2_i_1)) + (portref Q (instanceref state_reg_0_)) + (portref (member Q 1) (instanceref I_DECODER)) + ) + ) + (net (rename state_0__i_2_n_0 "state[0]_i_2_n_0") (joined + (portref O (instanceref state_0__i_2)) + (portref state_reg_0_ (instanceref I_DECODER)) + ) + ) + (net (rename state_1_ "state[1]") (joined + (portref I0 (instanceref bus2ip_addr_i_3__i_2)) + (portref I0 (instanceref state_1__i_2)) + (portref I1 (instanceref s_axi_rdata_i_7__i_1)) + (portref I4 (instanceref bus2ip_rnw_i_i_1)) + (portref I4 (instanceref start2_i_1)) + (portref Q (instanceref state_reg_1_)) + (portref (member Q 0) (instanceref I_DECODER)) + ) + ) + (net (rename state_1__i_2_n_0 "state[1]_i_2_n_0") (joined + (portref O (instanceref state_1__i_2)) + (portref state_reg_1_ (instanceref I_DECODER)) + ) + ) + (net (rename state_1__i_3_n_0 "state[1]_i_3_n_0") (joined + (portref O (instanceref state_1__i_3)) + (portref s_axi_wvalid (instanceref I_DECODER)) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref (member status_reg 1) (instanceref I_DECODER)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref (member status_reg 0) (instanceref I_DECODER)) + (portref (member status_reg 0)) + ) + ) + (net tx_Buffer_Empty_Pre_reg (joined + (portref tx_Buffer_Empty_Pre_reg (instanceref I_DECODER)) + (portref tx_Buffer_Empty_Pre_reg) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref I_DECODER)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "slave_attachment")) + ) + ) + (cell axi_uart_axi_lite_ipif (celltype GENERIC) + (view axi_lite_ipif (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction OUTPUT)) + (port FIFO_Full_reg (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction OUTPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (direction OUTPUT)) + (port bus2ip_reset (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port enable_interrupts_reg (direction OUTPUT)) + (port fifo_wr (direction OUTPUT)) + (port reset_RX_FIFO (direction OUTPUT)) + (port reset_TX_FIFO (direction OUTPUT)) + (port rx_Buffer_Full (direction INPUT)) + (port rx_Data_Present_Pre_reg (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_awvalid (direction INPUT)) + (port s_axi_bready (direction INPUT)) + (port s_axi_bvalid (direction OUTPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid (direction OUTPUT)) + (port s_axi_wvalid (direction INPUT)) + (port tx_Buffer_Empty_Pre_reg (direction OUTPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction INPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction INPUT)) + (port (array (rename s_axi_araddr "s_axi_araddr[1:0]") 2) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[1:0]") 2) (direction INPUT)) + (port (rename s_axi_bresp_0_ "s_axi_bresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[7:0]") 8) (direction OUTPUT)) + (port (rename s_axi_rresp_0_ "s_axi_rresp[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[2:0]") 3) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance I_SLAVE_ATTACHMENT (viewref slave_attachment (cellref axi_uart_slave_attachment (libraryref work_library0_1)))) + (net Bus_RNW_reg (joined + (portref enable_interrupts_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref Bus_RNW_reg) + ) + ) + (net FIFO_Full_reg (joined + (portref FIFO_Full_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0__0 (instanceref I_SLAVE_ATTACHMENT)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (joined + (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref I_SLAVE_ATTACHMENT)) + (portref INFERRED_GEN_cnt_i_reg_2_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0 "INFERRED_GEN.cnt_i_reg[2]_0") (joined + (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref I_SLAVE_ATTACHMENT)) + (portref INFERRED_GEN_cnt_i_reg_2__0) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref Q_0_) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref bus2ip_rdce_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_reset (joined + (portref bus2ip_reset (instanceref I_SLAVE_ATTACHMENT)) + (portref bus2ip_reset) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref I_SLAVE_ATTACHMENT)) + (portref enable_interrupts) + ) + ) + (net enable_interrupts_reg (joined + (portref enable_interrupts_reg_0 (instanceref I_SLAVE_ATTACHMENT)) + (portref enable_interrupts_reg) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref I_SLAVE_ATTACHMENT)) + (portref fifo_wr) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref reset_RX_FIFO (instanceref I_SLAVE_ATTACHMENT)) + (portref reset_RX_FIFO) + ) + ) + (net reset_TX_FIFO (joined + (portref reset_TX_FIFO (instanceref I_SLAVE_ATTACHMENT)) + (portref reset_TX_FIFO) + ) + ) + (net rx_Buffer_Full (joined + (portref rx_Buffer_Full (instanceref I_SLAVE_ATTACHMENT)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre_reg (joined + (portref rx_Data_Present_Pre_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref rx_Data_Present_Pre_reg) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined + (portref (member s_axi_araddr 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined + (portref (member s_axi_araddr 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref s_axi_arvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined + (portref (member s_axi_awaddr 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined + (portref (member s_axi_awaddr 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_awready) + ) + ) + (net s_axi_awvalid (joined + (portref s_axi_awvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref s_axi_bready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref s_axi_bresp_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_bresp_0_) + ) + ) + (net s_axi_bvalid (joined + (portref s_axi_bvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref (member s_axi_rdata 7) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 7)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref (member s_axi_rdata 6) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 6)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref (member s_axi_rdata 5) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 5)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref (member s_axi_rdata 4) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 4)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref (member s_axi_rdata 3) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 3)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref (member s_axi_rdata 2) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 2)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref (member s_axi_rdata 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 1)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref (member s_axi_rdata 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_rdata 0)) + ) + ) + (net s_axi_rready (joined + (portref s_axi_rready (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined + (portref s_axi_rresp_0_ (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_rresp_0_) + ) + ) + (net s_axi_rvalid (joined + (portref s_axi_rvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 2) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member s_axi_wdata 0)) + ) + ) + (net s_axi_wvalid (joined + (portref s_axi_wvalid (instanceref I_SLAVE_ATTACHMENT)) + (portref s_axi_wvalid) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref (member status_reg 1) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref (member status_reg 0) (instanceref I_SLAVE_ATTACHMENT)) + (portref (member status_reg 0)) + ) + ) + (net tx_Buffer_Empty_Pre_reg (joined + (portref tx_Buffer_Empty_Pre_reg (instanceref I_SLAVE_ATTACHMENT)) + (portref tx_Buffer_Empty_Pre_reg) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref I_SLAVE_ATTACHMENT)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "axi_lite_ipif")) + ) + ) + (cell axi_uart_baudrate (celltype GENERIC) + (view baudrate (viewtype NETLIST) + (interface + (port en_16x_Baud (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port (rename SR_0_ "SR[0]") (direction INPUT)) + ) + (contents + (instance EN_16x_Baud_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance EN_16x_Baud_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename count_0__i_1 "count[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h32")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename count_1__i_1 "count[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hC2")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename count_2__i_1 "count[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA9")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename count_reg_0_ "count_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename count_reg_1_ "count_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename count_reg_2_ "count_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref EN_16x_Baud_reg)) + (portref CE (instanceref count_reg_0_)) + (portref CE (instanceref count_reg_1_)) + (portref CE (instanceref count_reg_2_)) + (portref P (instanceref VCC)) + ) + ) + (net EN_16x_Baud_i_1_n_0 (joined + (portref D (instanceref EN_16x_Baud_reg)) + (portref O (instanceref EN_16x_Baud_i_1)) + ) + ) + (net (rename SR_0_ "SR[0]") (joined + (portref R (instanceref EN_16x_Baud_reg)) + (portref R (instanceref count_reg_0_)) + (portref R (instanceref count_reg_1_)) + (portref R (instanceref count_reg_2_)) + (portref SR_0_) + ) + ) + (net (rename count_0_ "count[0]") (joined + (portref I1 (instanceref EN_16x_Baud_i_1)) + (portref I1 (instanceref count_0__i_1)) + (portref I1 (instanceref count_1__i_1)) + (portref I1 (instanceref count_2__i_1)) + (portref Q (instanceref count_reg_0_)) + ) + ) + (net (rename count_0__i_1_n_0 "count[0]_i_1_n_0") (joined + (portref D (instanceref count_reg_0_)) + (portref O (instanceref count_0__i_1)) + ) + ) + (net (rename count_1_ "count[1]") (joined + (portref I0 (instanceref EN_16x_Baud_i_1)) + (portref I2 (instanceref count_0__i_1)) + (portref I2 (instanceref count_1__i_1)) + (portref I2 (instanceref count_2__i_1)) + (portref Q (instanceref count_reg_1_)) + ) + ) + (net (rename count_1__i_1_n_0 "count[1]_i_1_n_0") (joined + (portref D (instanceref count_reg_1_)) + (portref O (instanceref count_1__i_1)) + ) + ) + (net (rename count_2_ "count[2]") (joined + (portref I0 (instanceref count_0__i_1)) + (portref I0 (instanceref count_1__i_1)) + (portref I0 (instanceref count_2__i_1)) + (portref I2 (instanceref EN_16x_Baud_i_1)) + (portref Q (instanceref count_reg_2_)) + ) + ) + (net (rename count_2__i_1_n_0 "count[2]_i_1_n_0") (joined + (portref D (instanceref count_reg_2_)) + (portref O (instanceref count_2__i_1)) + ) + ) + (net en_16x_Baud (joined + (portref Q (instanceref EN_16x_Baud_reg)) + (portref en_16x_Baud) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref EN_16x_Baud_reg)) + (portref C (instanceref count_reg_0_)) + (portref C (instanceref count_reg_1_)) + (portref C (instanceref count_reg_2_)) + (portref s_axi_aclk) + ) + ) + ) + + (property ORIG_REF_NAME (string "baudrate")) + ) + ) + (cell axi_uart_dynshreg_i_f (celltype GENERIC) + (view dynshreg_i_f (viewtype NETLIST) + (interface + (port (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port en_16x_Baud (direction INPUT)) + (port fifo_Write0 (direction OUTPUT)) + (port frame_err_ocrd (direction INPUT)) + (port frame_err_ocrd_reg (direction OUTPUT)) + (port p_11_out (direction OUTPUT)) + (port p_14_out (direction OUTPUT)) + (port p_17_out (direction OUTPUT)) + (port p_20_out (direction OUTPUT)) + (port p_2_out (direction OUTPUT)) + (port p_5_out (direction OUTPUT)) + (port p_8_out (direction OUTPUT)) + (port running_reg (direction OUTPUT)) + (port running_reg_0 (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port scndry_out (direction INPUT)) + (port start_Edge_Detected (direction INPUT)) + (port status_reg_reg0 (direction OUTPUT)) + (port stop_Bit_Position_reg (direction OUTPUT)) + (port stop_Bit_Position_reg_0 (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename INFERRED_GEN_data_reg_14__0__srl15 "INFERRED_GEN.data_reg[14][0]_srl15") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 ")) + ) + (instance (rename INFERRED_GEN_data_reg_14__0__srl15_i_1 "INFERRED_GEN.data_reg[14][0]_srl15_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4440")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename INFERRED_GEN_data_reg_15__0_ "INFERRED_GEN.data_reg[15][0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_2__fifo_din_2__i_1 "SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_3__fifo_din_3__i_1 "SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_4__fifo_din_4__i_1 "SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_5__fifo_din_5__i_1 "SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_6__fifo_din_6__i_1 "SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_7__fifo_din_7__i_1 "SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_8__i_1 "SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0A000C00")) + ) + (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_8__i_2 "SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF7")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance fifo_Write_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8000")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance frame_err_ocrd_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00FF0080")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance running_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hBFFFA0A0")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename status_reg_1__i_1 "status_reg[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0000F200")) + ) + (instance (rename status_reg_1__i_2 "status_reg[1]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance stop_Bit_Position_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h2CCC")) + ) + (net (rename &_const0_ "") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref G (instanceref GND)) + (portref R (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net (rename &_const1_ "") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A2 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A3 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref P (instanceref VCC)) + ) + ) + (net (rename INFERRED_GEN_data_reg_14__0__srl15_n_0 "INFERRED_GEN.data_reg[14][0]_srl15_n_0") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref Q (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + ) + ) + (net (rename INFERRED_GEN_data_reg_15_ "INFERRED_GEN.data_reg[15]") (joined + (portref I0 (instanceref fifo_Write_i_1)) + (portref I0 (instanceref frame_err_ocrd_i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref I1 (instanceref running_i_1)) + (portref I2 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref I2 (instanceref status_reg_1__i_2)) + (portref I3 (instanceref stop_Bit_Position_i_1)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (joined + (portref I4 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I4 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref O (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_) + ) + ) + (net clr_Status (joined + (portref I4 (instanceref status_reg_1__i_1)) + (portref clr_Status) + ) + ) + (net en_16x_Baud (joined + (portref CE (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref I0 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref I1 (instanceref fifo_Write_i_1)) + (portref I1 (instanceref frame_err_ocrd_i_1)) + (portref I1 (instanceref status_reg_1__i_2)) + (portref I2 (instanceref running_i_1)) + (portref I2 (instanceref stop_Bit_Position_i_1)) + (portref en_16x_Baud) + ) + ) + (net fifo_Write0 (joined + (portref O (instanceref fifo_Write_i_1)) + (portref fifo_Write0) + ) + ) + (net frame_err_ocrd (joined + (portref I4 (instanceref frame_err_ocrd_i_1)) + (portref frame_err_ocrd) + ) + ) + (net frame_err_ocrd_reg (joined + (portref O (instanceref frame_err_ocrd_i_1)) + (portref frame_err_ocrd_reg) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref I1 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I1 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref I0 (instanceref stop_Bit_Position_i_1)) + (portref (member in 7)) + ) + ) + (net p_11_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref p_11_out) + ) + ) + (net p_14_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref p_14_out) + ) + ) + (net p_17_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref p_17_out) + ) + ) + (net p_20_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref p_20_out) + ) + ) + (net p_2_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref p_2_out) + ) + ) + (net p_5_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref p_5_out) + ) + ) + (net p_8_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref p_8_out) + ) + ) + (net recycle (joined + (portref D (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref O (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + ) + ) + (net running_reg (joined + (portref O (instanceref running_i_1)) + (portref running_reg) + ) + ) + (net running_reg_0 (joined + (portref I4 (instanceref running_i_1)) + (portref running_reg_0) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref CLK (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I3 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I3 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref I3 (instanceref status_reg_1__i_1)) + (portref s_axi_aresetn) + ) + ) + (net scndry_out (joined + (portref I1 (instanceref status_reg_1__i_1)) + (portref I3 (instanceref fifo_Write_i_1)) + (portref I3 (instanceref frame_err_ocrd_i_1)) + (portref scndry_out) + ) + ) + (net start_Edge_Detected (joined + (portref I0 (instanceref running_i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_2__fifo_din_2__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_3__fifo_din_3__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_4__fifo_din_4__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_5__fifo_din_5__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_6__fifo_din_6__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_7__fifo_din_7__i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_1)) + (portref I3 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref start_Edge_Detected) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref I2 (instanceref status_reg_1__i_1)) + (portref status_reg_0_) + ) + ) + (net (rename status_reg_1__i_2_n_0 "status_reg[1]_i_2_n_0") (joined + (portref I0 (instanceref status_reg_1__i_1)) + (portref O (instanceref status_reg_1__i_2)) + ) + ) + (net status_reg_reg0 (joined + (portref O (instanceref status_reg_1__i_1)) + (portref status_reg_reg0) + ) + ) + (net stop_Bit_Position_reg (joined + (portref O (instanceref stop_Bit_Position_i_1)) + (portref stop_Bit_Position_reg) + ) + ) + (net stop_Bit_Position_reg_0 (joined + (portref I0 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref I0 (instanceref status_reg_1__i_2)) + (portref I1 (instanceref stop_Bit_Position_i_1)) + (portref I2 (instanceref SERIAL_TO_PARALLEL_8__fifo_din_8__i_2)) + (portref I2 (instanceref fifo_Write_i_1)) + (portref I2 (instanceref frame_err_ocrd_i_1)) + (portref I3 (instanceref running_i_1)) + (portref stop_Bit_Position_reg_0) + ) + ) + (net valid_rx (joined + (portref I1 (instanceref INFERRED_GEN_data_reg_14__0__srl15_i_1)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_i_f")) + ) + ) + (cell axi_uart_cdc_sync (celltype GENERIC) + (view cdc_sync (viewtype NETLIST) + (interface + (port EN_16x_Baud_reg (direction INPUT)) + (port p_26_out (direction OUTPUT)) + (port rx (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port scndry_out (direction OUTPUT)) + (port start_Edge_Detected (direction INPUT)) + (port (rename in_0_ "in[0]") (direction INPUT)) + ) + (contents + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance (rename GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 "GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + (property XILINX_LEGACY_PRIM (string "FDR")) + (property INIT (string "1'b0")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename SERIAL_TO_PARALLEL_1__fifo_din_1__i_1 "SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFE00CE00")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref R (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + ) + ) + (net EN_16x_Baud_reg (joined + (portref I2 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref EN_16x_Baud_reg) + ) + ) + (net VCC_1 (joined + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref CE (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref P (instanceref VCC)) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref I4 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref in_0_) + ) + ) + (net p_26_out (joined + (portref O (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref p_26_out) + ) + ) + (net rx (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref rx) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref C (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I3 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref s_axi_aresetn) + ) + ) + (net s_level_out_d1_cdc_to (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to)) + ) + ) + (net s_level_out_d2 (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2)) + ) + ) + (net s_level_out_d3 (joined + (portref D (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3)) + ) + ) + (net scndry_out (joined + (portref I0 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref Q (instanceref GENERATE_LEVEL_P_S_CDC_SINGLE_BIT_CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4)) + (portref scndry_out) + ) + ) + (net start_Edge_Detected (joined + (portref I1 (instanceref SERIAL_TO_PARALLEL_1__fifo_din_1__i_1)) + (portref start_Edge_Detected) + ) + ) + ) + + (property ORIG_REF_NAME (string "cdc_sync")) + ) + ) + (cell axi_uart_cntr_incr_decr_addn_f_2 (celltype GENERIC) + (view cntr_incr_decr_addn_f_2 (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port FIFO_Full_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port enable_interrupts (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port fifo_full_p1 (direction OUTPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (direction INPUT)) + (port (array (rename Q "Q[4:0]") 5) (direction OUTPUT)) + (port (rename SS_0_ "SS[0]") (direction OUTPUT)) + ) + (contents + (instance FIFO_Full_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000009040000")) + ) + (instance FIFO_Full_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h7")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename INFERRED_GEN_cnt_i_0__i_1 "INFERRED_GEN.cnt_i[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hF70808F7")) + ) + (instance (rename INFERRED_GEN_cnt_i_1__i_1 "INFERRED_GEN.cnt_i[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAAAA6A5595AAAA")) + ) + (instance (rename INFERRED_GEN_cnt_i_2__i_1 "INFERRED_GEN.cnt_i[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFE017F80")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename INFERRED_GEN_cnt_i_3__i_1 "INFERRED_GEN.cnt_i[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF0F0F0E178F0F0F0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_1 "INFERRED_GEN.cnt_i[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_2 "INFERRED_GEN.cnt_i[4]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF0F0F4F4F00AF0F0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_4 "INFERRED_GEN.cnt_i[4]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_5__0 "INFERRED_GEN.cnt_i[4]_i_5__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h7F")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_6 "INFERRED_GEN.cnt_i[4]_i_6") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hDF")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_0_ "INFERRED_GEN.cnt_i_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_1_ "INFERRED_GEN.cnt_i_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_3_ "INFERRED_GEN.cnt_i_reg[3]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance Interrupt_i_2 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h1010F010")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (net (rename &_const1_ "") (joined + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref Bus_RNW_reg_reg) + ) + ) + (net FIFO_Full_i_2_n_0 (joined + (portref I5 (instanceref FIFO_Full_i_1)) + (portref O (instanceref FIFO_Full_i_2)) + ) + ) + (net FIFO_Full_reg (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_6)) + (portref FIFO_Full_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref I3 (instanceref FIFO_Full_i_1)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_4_n_0 "INFERRED_GEN.cnt_i[4]_i_4_n_0") (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_4)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_5__0_n_0 "INFERRED_GEN.cnt_i[4]_i_5__0_n_0") (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_6_n_0 "INFERRED_GEN.cnt_i[4]_i_6_n_0") (joined + (portref I0 (instanceref FIFO_Full_i_1)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_6)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_0_ "INFERRED_GEN.cnt_i_reg[4]_0[0]") (joined + (portref I3 (instanceref Interrupt_i_2)) + (portref INFERRED_GEN_cnt_i_reg_4__0_0_) + ) + ) + (net Interrupt0 (joined + (portref O (instanceref Interrupt_i_2)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref I1 (instanceref FIFO_Full_i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref (member Q 4)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref I0 (instanceref FIFO_Full_i_2)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_4)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref (member Q 3)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_4)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + (portref I1 (instanceref FIFO_Full_i_2)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_2__i_1)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref (member Q 2)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_4)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_5__0)) + (portref I4 (instanceref FIFO_Full_i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref (member Q 1)) + ) + ) + (net (rename Q_4_ "Q[4]") (joined + (portref I1 (instanceref Interrupt_i_2)) + (portref I2 (instanceref FIFO_Full_i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_0__i_1)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_2)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_1__i_1)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref (member Q 0)) + ) + ) + (net (rename SS_0_ "SS[0]") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_1)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref SS_0_) + ) + ) + (net (rename addr_i_p1_0_ "addr_i_p1[0]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref O (instanceref INFERRED_GEN_cnt_i_0__i_1)) + ) + ) + (net (rename addr_i_p1_1_ "addr_i_p1[1]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref O (instanceref INFERRED_GEN_cnt_i_1__i_1)) + ) + ) + (net (rename addr_i_p1_2_ "addr_i_p1[2]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref O (instanceref INFERRED_GEN_cnt_i_2__i_1)) + ) + ) + (net (rename addr_i_p1_3_ "addr_i_p1[3]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_1)) + ) + ) + (net (rename addr_i_p1_4_ "addr_i_p1[4]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_2)) + ) + ) + (net enable_interrupts (joined + (portref I2 (instanceref Interrupt_i_2)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_6)) + (portref fifo_Write) + ) + ) + (net fifo_full_p1 (joined + (portref O (instanceref FIFO_Full_i_1)) + (portref fifo_full_p1) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_1)) + (portref reset_RX_FIFO_reg) + ) + ) + (net rx_Data_Present_Pre (joined + (portref I0 (instanceref Interrupt_i_2)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_1)) + (portref s_axi_aresetn) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref I4 (instanceref Interrupt_i_2)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_6)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "cntr_incr_decr_addn_f")) + ) + ) + (cell axi_uart_dynshreg_f_3 (celltype GENERIC) + (view dynshreg_f_3 (viewtype NETLIST) + (interface + (port FIFO_Full_reg (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (array (rename Q "Q[3:0]") 4) (direction INPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + ) + (contents + (instance (rename INFERRED_GEN_data_reg_15__0__srl16 "INFERRED_GEN.data_reg[15][0]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__1__srl16 "INFERRED_GEN.data_reg[15][1]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__2__srl16 "INFERRED_GEN.data_reg[15][2]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__3__srl16 "INFERRED_GEN.data_reg[15][3]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__4__srl16 "INFERRED_GEN.data_reg[15][4]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__5__srl16 "INFERRED_GEN.data_reg[15][5]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__6__srl16 "INFERRED_GEN.data_reg[15][6]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16 "INFERRED_GEN.data_reg[15][7]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16_i_1__0 "INFERRED_GEN.data_reg[15][7]_srl16_i_1__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + ) + (net FIFO_Full_reg (joined + (portref I1 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + (portref FIFO_Full_reg) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 3)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 2)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref A2 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 1)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref A3 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 0)) + ) + ) + (net fifo_Write (joined + (portref I2 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + (portref fifo_Write) + ) + ) + (net fifo_wr (joined + (portref CE (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref O (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member in 7)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref Q (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref (member out 0)) + ) + ) + (net s_axi_aclk (joined + (portref CLK (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref s_axi_aclk) + ) + ) + (net valid_rx (joined + (portref I0 (instanceref INFERRED_GEN_data_reg_15__7__srl16_i_1__0)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_f")) + ) + ) + (cell axi_uart_srl_fifo_rbu_f_1 (celltype GENERIC) + (view srl_fifo_rbu_f_1 (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) + (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) + ) + (contents + (instance CNTR_INCR_DECR_ADDN_F_I (viewref cntr_incr_decr_addn_f_2 (cellref axi_uart_cntr_incr_decr_addn_f_2 (libraryref work_library0_1)))) + (instance DYNSHREG_F_I (viewref dynshreg_f_3 (cellref axi_uart_dynshreg_f_3 (libraryref work_library0_1)))) + (instance FIFO_Full_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename status_reg_2__i_1 "status_reg[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00EA0000")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref FIFO_Full_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Bus_RNW_reg_reg) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_3 (joined + (portref (member Q 1) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 0) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_4 (joined + (portref (member Q 2) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 1) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_5 (joined + (portref (member Q 3) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 2) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_6 (joined + (portref (member Q 4) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 3) (instanceref DYNSHREG_F_I)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net Interrupt0 (joined + (portref Interrupt0 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref (member Q 0) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Q_0_) + ) + ) + (net RX_FIFO_Reset (joined + (portref R (instanceref FIFO_Full_reg)) + (portref SS_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net clr_Status (joined + (portref I3 (instanceref status_reg_2__i_1)) + (portref clr_Status) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref I1 (instanceref status_reg_2__i_1)) + (portref fifo_Write (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref fifo_Write (instanceref DYNSHREG_F_I)) + (portref fifo_Write) + ) + ) + (net fifo_full_p1 (joined + (portref D (instanceref FIFO_Full_reg)) + (portref fifo_full_p1 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref (member in 0) (instanceref DYNSHREG_F_I)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref (member in 1) (instanceref DYNSHREG_F_I)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref (member in 2) (instanceref DYNSHREG_F_I)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref (member in 3) (instanceref DYNSHREG_F_I)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref (member in 4) (instanceref DYNSHREG_F_I)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref (member in 5) (instanceref DYNSHREG_F_I)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref (member in 6) (instanceref DYNSHREG_F_I)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref (member in 7) (instanceref DYNSHREG_F_I)) + (portref (member in 7)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref DYNSHREG_F_I)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref DYNSHREG_F_I)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref DYNSHREG_F_I)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref DYNSHREG_F_I)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref DYNSHREG_F_I)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref DYNSHREG_F_I)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref DYNSHREG_F_I)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref DYNSHREG_F_I)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref reset_RX_FIFO_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref reset_RX_FIFO_reg) + ) + ) + (net rx_Data_Present_Pre (joined + (portref rx_Data_Present_Pre (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref FIFO_Full_reg)) + (portref s_axi_aclk (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aclk (instanceref DYNSHREG_F_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I4 (instanceref status_reg_2__i_1)) + (portref s_axi_aresetn (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref I0 (instanceref status_reg_2__i_1)) + (portref status_reg_0_) + ) + ) + (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined + (portref FIFO_Full_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref FIFO_Full_reg (instanceref DYNSHREG_F_I)) + (portref I2 (instanceref status_reg_2__i_1)) + (portref Q (instanceref FIFO_Full_reg)) + (portref status_reg_reg_2_) + ) + ) + (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined + (portref O (instanceref status_reg_2__i_1)) + (portref status_reg_reg_2__0) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref tx_Buffer_Empty_Pre (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref valid_rx (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref valid_rx (instanceref DYNSHREG_F_I)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_rbu_f")) + ) + ) + (cell axi_uart_srl_fifo_f_0 (celltype GENERIC) + (view srl_fifo_f_0 (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port fifo_Write (direction INPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) + (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port valid_rx (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename in "in[0:7]") 8) (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (rename status_reg_0_ "status_reg[0]") (direction INPUT)) + ) + (contents + (instance I_SRL_FIFO_RBU_F (viewref srl_fifo_rbu_f_1 (cellref axi_uart_srl_fifo_rbu_f_1 (libraryref work_library0_1)))) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref Bus_RNW_reg_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net Interrupt0 (joined + (portref Interrupt0 (instanceref I_SRL_FIFO_RBU_F)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref Q_0_) + ) + ) + (net clr_Status (joined + (portref clr_Status (instanceref I_SRL_FIFO_RBU_F)) + (portref clr_Status) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref I_SRL_FIFO_RBU_F)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref fifo_Write (instanceref I_SRL_FIFO_RBU_F)) + (portref fifo_Write) + ) + ) + (net (rename in_0_ "in[0]") (joined + (portref (member in 0) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 0)) + ) + ) + (net (rename in_1_ "in[1]") (joined + (portref (member in 1) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 1)) + ) + ) + (net (rename in_2_ "in[2]") (joined + (portref (member in 2) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 2)) + ) + ) + (net (rename in_3_ "in[3]") (joined + (portref (member in 3) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 3)) + ) + ) + (net (rename in_4_ "in[4]") (joined + (portref (member in 4) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 4)) + ) + ) + (net (rename in_5_ "in[5]") (joined + (portref (member in 5) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 5)) + ) + ) + (net (rename in_6_ "in[6]") (joined + (portref (member in 6) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 6)) + ) + ) + (net (rename in_7_ "in[7]") (joined + (portref (member in 7) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member in 7)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref reset_RX_FIFO_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref reset_RX_FIFO_reg) + ) + ) + (net rx_Data_Present_Pre (joined + (portref rx_Data_Present_Pre (instanceref I_SRL_FIFO_RBU_F)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aresetn) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref status_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref status_reg_0_) + ) + ) + (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined + (portref status_reg_reg_2_ (instanceref I_SRL_FIFO_RBU_F)) + (portref status_reg_reg_2_) + ) + ) + (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined + (portref status_reg_reg_2__0 (instanceref I_SRL_FIFO_RBU_F)) + (portref status_reg_reg_2__0) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref tx_Buffer_Empty_Pre (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref valid_rx (instanceref I_SRL_FIFO_RBU_F)) + (portref valid_rx) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_f")) + ) + ) + (cell axi_uart_uartlite_rx (celltype GENERIC) + (view uartlite_rx (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port Interrupt0 (direction OUTPUT)) + (port clr_Status (direction INPUT)) + (port en_16x_Baud (direction INPUT)) + (port enable_interrupts (direction INPUT)) + (port reset_RX_FIFO_reg (direction INPUT)) + (port rx (direction INPUT)) + (port rx_Data_Present_Pre (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port status_reg_reg0 (direction OUTPUT)) + (port (rename status_reg_reg_2_ "status_reg_reg[2]") (direction OUTPUT)) + (port (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (direction OUTPUT)) + (port tx_Buffer_Empty_Pre (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (direction INPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (rename SR_0_ "SR[0]") (direction OUTPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction INPUT)) + ) + (contents + (instance DELAY_16_I (viewref dynshreg_i_f (cellref axi_uart_dynshreg_i_f (libraryref work_library0_1)))) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance INPUT_DOUBLE_REGS3 (viewref cdc_sync (cellref axi_uart_cdc_sync (libraryref work_library0_1)))) + (instance Interrupt_i_1 (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename SERIAL_TO_PARALLEL_1__fifo_din_reg_1_ "SERIAL_TO_PARALLEL[1].fifo_din_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ "SERIAL_TO_PARALLEL[2].fifo_din_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_3__fifo_din_reg_3_ "SERIAL_TO_PARALLEL[3].fifo_din_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_4__fifo_din_reg_4_ "SERIAL_TO_PARALLEL[4].fifo_din_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_5__fifo_din_reg_5_ "SERIAL_TO_PARALLEL[5].fifo_din_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_6__fifo_din_reg_6_ "SERIAL_TO_PARALLEL[6].fifo_din_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_7__fifo_din_reg_7_ "SERIAL_TO_PARALLEL[7].fifo_din_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SERIAL_TO_PARALLEL_8__fifo_din_reg_8_ "SERIAL_TO_PARALLEL[8].fifo_din_reg[8]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance SRL_FIFO_I (viewref srl_fifo_f_0 (cellref axi_uart_srl_fifo_f_0 (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance fifo_Write_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance frame_err_ocrd_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance running_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_1_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_2_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_3_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_4_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_5_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_6_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_7_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_8_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_9_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance start_Edge_Detected_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000010")) + ) + (instance start_Edge_Detected_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000010")) + ) + (instance start_Edge_Detected_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance stop_Bit_Position_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance valid_rx_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hBA")) + ) + (instance valid_rx_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref R (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref R (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref R (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref R (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref R (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref R (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref R (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref CE (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref CE (instanceref fifo_Write_reg)) + (portref CE (instanceref frame_err_ocrd_reg)) + (portref CE (instanceref running_reg)) + (portref CE (instanceref stop_Bit_Position_reg)) + (portref CE (instanceref valid_rx_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref SRL_FIFO_I)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref SRL_FIFO_I)) + (portref Bus_RNW_reg_reg) + ) + ) + (net DELAY_16_I_n_1 (joined + (portref EN_16x_Baud_reg (instanceref INPUT_DOUBLE_REGS3)) + (portref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_ (instanceref DELAY_16_I)) + ) + ) + (net DELAY_16_I_n_10 (joined + (portref D (instanceref stop_Bit_Position_reg)) + (portref stop_Bit_Position_reg (instanceref DELAY_16_I)) + ) + ) + (net DELAY_16_I_n_11 (joined + (portref D (instanceref frame_err_ocrd_reg)) + (portref frame_err_ocrd_reg (instanceref DELAY_16_I)) + ) + ) + (net DELAY_16_I_n_12 (joined + (portref D (instanceref running_reg)) + (portref running_reg (instanceref DELAY_16_I)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0_ "INFERRED_GEN.cnt_i_reg[4][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref SRL_FIFO_I)) + (portref INFERRED_GEN_cnt_i_reg_4__0_) + ) + ) + (net Interrupt0 (joined + (portref Interrupt0 (instanceref SRL_FIFO_I)) + (portref Interrupt0) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref SRL_FIFO_I)) + (portref Q_0_) + ) + ) + (net RX_D2 (joined + (portref D (instanceref rx_1_reg)) + (portref scndry_out (instanceref DELAY_16_I)) + (portref scndry_out (instanceref INPUT_DOUBLE_REGS3)) + ) + ) + (net (rename SR_0_ "SR[0]") (joined + (portref O (instanceref Interrupt_i_1)) + (portref R (instanceref fifo_Write_reg)) + (portref R (instanceref frame_err_ocrd_reg)) + (portref R (instanceref running_reg)) + (portref R (instanceref rx_1_reg)) + (portref R (instanceref rx_2_reg)) + (portref R (instanceref rx_3_reg)) + (portref R (instanceref rx_4_reg)) + (portref R (instanceref rx_5_reg)) + (portref R (instanceref rx_6_reg)) + (portref R (instanceref rx_7_reg)) + (portref R (instanceref rx_8_reg)) + (portref R (instanceref rx_9_reg)) + (portref R (instanceref start_Edge_Detected_reg)) + (portref R (instanceref stop_Bit_Position_reg)) + (portref R (instanceref valid_rx_reg)) + (portref SR_0_) + ) + ) + (net clr_Status (joined + (portref clr_Status (instanceref DELAY_16_I)) + (portref clr_Status (instanceref SRL_FIFO_I)) + (portref clr_Status) + ) + ) + (net en_16x_Baud (joined + (portref CE (instanceref rx_1_reg)) + (portref CE (instanceref rx_2_reg)) + (portref CE (instanceref rx_3_reg)) + (portref CE (instanceref rx_4_reg)) + (portref CE (instanceref rx_5_reg)) + (portref CE (instanceref rx_6_reg)) + (portref CE (instanceref rx_7_reg)) + (portref CE (instanceref rx_8_reg)) + (portref CE (instanceref rx_9_reg)) + (portref CE (instanceref start_Edge_Detected_reg)) + (portref en_16x_Baud (instanceref DELAY_16_I)) + (portref en_16x_Baud) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref SRL_FIFO_I)) + (portref enable_interrupts) + ) + ) + (net fifo_Write (joined + (portref I1 (instanceref valid_rx_i_1)) + (portref Q (instanceref fifo_Write_reg)) + (portref fifo_Write (instanceref SRL_FIFO_I)) + ) + ) + (net fifo_Write0 (joined + (portref D (instanceref fifo_Write_reg)) + (portref fifo_Write0 (instanceref DELAY_16_I)) + ) + ) + (net (rename fifo_din_1_ "fifo_din[1]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref (member in 0) (instanceref DELAY_16_I)) + (portref in_0_ (instanceref INPUT_DOUBLE_REGS3)) + (portref (member in 0) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_2_ "fifo_din[2]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref (member in 1) (instanceref DELAY_16_I)) + (portref (member in 1) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_3_ "fifo_din[3]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref (member in 2) (instanceref DELAY_16_I)) + (portref (member in 2) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_4_ "fifo_din[4]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref (member in 3) (instanceref DELAY_16_I)) + (portref (member in 3) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_5_ "fifo_din[5]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref (member in 4) (instanceref DELAY_16_I)) + (portref (member in 4) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_6_ "fifo_din[6]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref (member in 5) (instanceref DELAY_16_I)) + (portref (member in 5) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_7_ "fifo_din[7]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref (member in 6) (instanceref DELAY_16_I)) + (portref (member in 6) (instanceref SRL_FIFO_I)) + ) + ) + (net (rename fifo_din_8_ "fifo_din[8]") (joined + (portref Q (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref (member in 7) (instanceref DELAY_16_I)) + (portref (member in 7) (instanceref SRL_FIFO_I)) + ) + ) + (net frame_err_ocrd (joined + (portref I5 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref frame_err_ocrd_reg)) + (portref frame_err_ocrd (instanceref DELAY_16_I)) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref SRL_FIFO_I)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref SRL_FIFO_I)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref SRL_FIFO_I)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref SRL_FIFO_I)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref SRL_FIFO_I)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref SRL_FIFO_I)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref SRL_FIFO_I)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref SRL_FIFO_I)) + (portref (member out 0)) + ) + ) + (net p_11_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref p_11_out (instanceref DELAY_16_I)) + ) + ) + (net p_14_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref p_14_out (instanceref DELAY_16_I)) + ) + ) + (net p_17_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref p_17_out (instanceref DELAY_16_I)) + ) + ) + (net p_20_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref p_20_out (instanceref DELAY_16_I)) + ) + ) + (net p_26_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref p_26_out (instanceref INPUT_DOUBLE_REGS3)) + ) + ) + (net p_2_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref p_2_out (instanceref DELAY_16_I)) + ) + ) + (net p_5_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref p_5_out (instanceref DELAY_16_I)) + ) + ) + (net p_8_out (joined + (portref D (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref p_8_out (instanceref DELAY_16_I)) + ) + ) + (net reset_RX_FIFO_reg (joined + (portref reset_RX_FIFO_reg (instanceref SRL_FIFO_I)) + (portref reset_RX_FIFO_reg) + ) + ) + (net running_reg_n_0 (joined + (portref I3 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref running_reg)) + (portref running_reg_0 (instanceref DELAY_16_I)) + ) + ) + (net rx (joined + (portref rx (instanceref INPUT_DOUBLE_REGS3)) + (portref rx) + ) + ) + (net rx_1 (joined + (portref D (instanceref rx_2_reg)) + (portref I4 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_1_reg)) + ) + ) + (net rx_2 (joined + (portref D (instanceref rx_3_reg)) + (portref I1 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_2_reg)) + ) + ) + (net rx_3 (joined + (portref D (instanceref rx_4_reg)) + (portref I3 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_3_reg)) + ) + ) + (net rx_4 (joined + (portref D (instanceref rx_5_reg)) + (portref I5 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_4_reg)) + ) + ) + (net rx_5 (joined + (portref D (instanceref rx_6_reg)) + (portref I0 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_5_reg)) + ) + ) + (net rx_6 (joined + (portref D (instanceref rx_7_reg)) + (portref I4 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_6_reg)) + ) + ) + (net rx_7 (joined + (portref D (instanceref rx_8_reg)) + (portref I1 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_7_reg)) + ) + ) + (net rx_8 (joined + (portref D (instanceref rx_9_reg)) + (portref I0 (instanceref start_Edge_Detected_i_1)) + (portref Q (instanceref rx_8_reg)) + ) + ) + (net rx_9 (joined + (portref I2 (instanceref start_Edge_Detected_i_2)) + (portref Q (instanceref rx_9_reg)) + ) + ) + (net rx_Data_Present_Pre (joined + (portref rx_Data_Present_Pre (instanceref SRL_FIFO_I)) + (portref rx_Data_Present_Pre) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref SERIAL_TO_PARALLEL_1__fifo_din_reg_1_)) + (portref C (instanceref SERIAL_TO_PARALLEL_2__fifo_din_reg_2_)) + (portref C (instanceref SERIAL_TO_PARALLEL_3__fifo_din_reg_3_)) + (portref C (instanceref SERIAL_TO_PARALLEL_4__fifo_din_reg_4_)) + (portref C (instanceref SERIAL_TO_PARALLEL_5__fifo_din_reg_5_)) + (portref C (instanceref SERIAL_TO_PARALLEL_6__fifo_din_reg_6_)) + (portref C (instanceref SERIAL_TO_PARALLEL_7__fifo_din_reg_7_)) + (portref C (instanceref SERIAL_TO_PARALLEL_8__fifo_din_reg_8_)) + (portref C (instanceref fifo_Write_reg)) + (portref C (instanceref frame_err_ocrd_reg)) + (portref C (instanceref running_reg)) + (portref C (instanceref rx_1_reg)) + (portref C (instanceref rx_2_reg)) + (portref C (instanceref rx_3_reg)) + (portref C (instanceref rx_4_reg)) + (portref C (instanceref rx_5_reg)) + (portref C (instanceref rx_6_reg)) + (portref C (instanceref rx_7_reg)) + (portref C (instanceref rx_8_reg)) + (portref C (instanceref rx_9_reg)) + (portref C (instanceref start_Edge_Detected_reg)) + (portref C (instanceref stop_Bit_Position_reg)) + (portref C (instanceref valid_rx_reg)) + (portref s_axi_aclk (instanceref DELAY_16_I)) + (portref s_axi_aclk (instanceref INPUT_DOUBLE_REGS3)) + (portref s_axi_aclk (instanceref SRL_FIFO_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I0 (instanceref Interrupt_i_1)) + (portref s_axi_aresetn (instanceref DELAY_16_I)) + (portref s_axi_aresetn (instanceref INPUT_DOUBLE_REGS3)) + (portref s_axi_aresetn (instanceref SRL_FIFO_I)) + (portref s_axi_aresetn) + ) + ) + (net start_Edge_Detected (joined + (portref I0 (instanceref valid_rx_i_1)) + (portref Q (instanceref start_Edge_Detected_reg)) + (portref start_Edge_Detected (instanceref DELAY_16_I)) + (portref start_Edge_Detected (instanceref INPUT_DOUBLE_REGS3)) + ) + ) + (net start_Edge_Detected0 (joined + (portref D (instanceref start_Edge_Detected_reg)) + (portref O (instanceref start_Edge_Detected_i_1)) + ) + ) + (net start_Edge_Detected_i_2_n_0 (joined + (portref I2 (instanceref start_Edge_Detected_i_1)) + (portref O (instanceref start_Edge_Detected_i_2)) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref status_reg_0_ (instanceref SRL_FIFO_I)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref status_reg_0_ (instanceref DELAY_16_I)) + (portref (member status_reg 0)) + ) + ) + (net status_reg_reg0 (joined + (portref status_reg_reg0 (instanceref DELAY_16_I)) + (portref status_reg_reg0) + ) + ) + (net (rename status_reg_reg_2_ "status_reg_reg[2]") (joined + (portref status_reg_reg_2_ (instanceref SRL_FIFO_I)) + (portref status_reg_reg_2_) + ) + ) + (net (rename status_reg_reg_2__0 "status_reg_reg[2]_0") (joined + (portref status_reg_reg_2__0 (instanceref SRL_FIFO_I)) + (portref status_reg_reg_2__0) + ) + ) + (net stop_Bit_Position_reg_n_0 (joined + (portref Q (instanceref stop_Bit_Position_reg)) + (portref stop_Bit_Position_reg_0 (instanceref DELAY_16_I)) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref tx_Buffer_Empty_Pre (instanceref SRL_FIFO_I)) + (portref tx_Buffer_Empty_Pre) + ) + ) + (net valid_rx (joined + (portref I2 (instanceref valid_rx_i_1)) + (portref Q (instanceref valid_rx_reg)) + (portref valid_rx (instanceref DELAY_16_I)) + (portref valid_rx (instanceref SRL_FIFO_I)) + ) + ) + (net valid_rx_i_1_n_0 (joined + (portref D (instanceref valid_rx_reg)) + (portref O (instanceref valid_rx_i_1)) + ) + ) + ) + + (property ORIG_REF_NAME (string "uartlite_rx")) + ) + ) + (cell axi_uart_dynshreg_i_f__parameterized0 (celltype GENERIC) + (view dynshreg_i_f__parameterized0 (viewtype NETLIST) + (interface + (port en_16x_Baud (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port tx_Data_Enable_reg (direction OUTPUT)) + (port tx_Data_Enable_reg_0 (direction INPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename INFERRED_GEN_data_reg_14__0__srl15 "INFERRED_GEN.data_reg[14][0]_srl15") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__0_ "INFERRED_GEN.data_reg[15][0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance tx_Data_Enable_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + ) + (net (rename &_const0_ "") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref G (instanceref GND)) + (portref R (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net (rename &_const1_ "") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A2 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref A3 (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref P (instanceref VCC)) + ) + ) + (net (rename INFERRED_GEN_data_reg_14__0__srl15_n_0 "INFERRED_GEN.data_reg[14][0]_srl15_n_0") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref Q (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + ) + ) + (net (rename INFERRED_GEN_data_reg_n_0__15__0_ "INFERRED_GEN.data_reg_n_0_[15][0]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref I0 (instanceref tx_Data_Enable_i_1)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__0_)) + ) + ) + (net en_16x_Baud (joined + (portref CE (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref I2 (instanceref tx_Data_Enable_i_1)) + (portref en_16x_Baud) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_data_reg_15__0_)) + (portref CLK (instanceref INFERRED_GEN_data_reg_14__0__srl15)) + (portref s_axi_aclk) + ) + ) + (net tx_Data_Enable_reg (joined + (portref O (instanceref tx_Data_Enable_i_1)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Data_Enable_reg_0 (joined + (portref I1 (instanceref tx_Data_Enable_i_1)) + (portref tx_Data_Enable_reg_0) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_i_f")) + ) + ) + (cell axi_uart_cntr_incr_decr_addn_f (celltype GENERIC) + (view cntr_incr_decr_addn_f (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port fifo_Read (direction INPUT)) + (port fifo_full_p1 (direction OUTPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Full (direction INPUT)) + (port tx_DataBits (direction INPUT)) + (port tx_Data_Enable_reg (direction INPUT)) + (port tx_Start (direction INPUT)) + (port tx_Start0 (direction OUTPUT)) + (port (array (rename Q "Q[4:0]") 5) (direction OUTPUT)) + (port (rename SS_0_ "SS[0]") (direction OUTPUT)) + ) + (contents + (instance FIFO_Full_i_1__0 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000004090000")) + ) + (instance FIFO_Full_i_2__0 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h7")) + ) + (instance (rename INFERRED_GEN_cnt_i_0__i_1__0 "INFERRED_GEN.cnt_i[0]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hBBB4BBBB444B4444")) + ) + (instance (rename INFERRED_GEN_cnt_i_1__i_1__0 "INFERRED_GEN.cnt_i[1]_i_1__0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hAA9A65AA")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename INFERRED_GEN_cnt_i_2__i_1__0 "INFERRED_GEN.cnt_i[2]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF4FF0B00FFBF0040")) + ) + (instance (rename INFERRED_GEN_cnt_i_3__i_1__0 "INFERRED_GEN.cnt_i[3]_i_1__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAA6AAAAAA9AAAA")) + ) + (instance (rename INFERRED_GEN_cnt_i_3__i_2__0 "INFERRED_GEN.cnt_i[3]_i_2__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_1__0 "INFERRED_GEN.cnt_i[4]_i_1__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_2__0 "INFERRED_GEN.cnt_i[4]_i_2__0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF0F0FAFAF003F0F0")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_3__0 "INFERRED_GEN.cnt_i[4]_i_3__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0004")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename INFERRED_GEN_cnt_i_4__i_4__0 "INFERRED_GEN.cnt_i[4]_i_4__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h7F")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_0_ "INFERRED_GEN.cnt_i_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_1_ "INFERRED_GEN.cnt_i_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_2_ "INFERRED_GEN.cnt_i_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_3_ "INFERRED_GEN.cnt_i_reg[3]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance tx_Start_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0F02")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref CE (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref Bus_RNW_reg) + ) + ) + (net FIFO_Full_i_2__0_n_0 (joined + (portref I5 (instanceref FIFO_Full_i_1__0)) + (portref O (instanceref FIFO_Full_i_2__0)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref I4 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref I0 (instanceref FIFO_Full_i_1__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_3__i_2__0_n_0 "INFERRED_GEN.cnt_i[3]_i_2__0_n_0") (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_3__0_n_0 "INFERRED_GEN.cnt_i[4]_i_3__0_n_0") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + ) + ) + (net (rename INFERRED_GEN_cnt_i_4__i_4__0_n_0 "INFERRED_GEN.cnt_i[4]_i_4__0_n_0") (joined + (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref I1 (instanceref FIFO_Full_i_1__0)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref (member Q 4)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref I0 (instanceref FIFO_Full_i_2__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + (portref I3 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I5 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref (member Q 3)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + (portref I1 (instanceref FIFO_Full_i_2__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I4 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref (member Q 2)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_4__0)) + (portref I4 (instanceref FIFO_Full_i_1__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref (member Q 1)) + ) + ) + (net (rename Q_4_ "Q[4]") (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I0 (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I1 (instanceref tx_Start_i_1)) + (portref I2 (instanceref FIFO_Full_i_1__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref Q (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref (member Q 0)) + ) + ) + (net (rename SS_0_ "SS[0]") (joined + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref S (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref SS_0_) + ) + ) + (net (rename addr_i_p1_0_ "addr_i_p1[0]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref O (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + ) + ) + (net (rename addr_i_p1_1_ "addr_i_p1[1]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref O (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + ) + ) + (net (rename addr_i_p1_2_ "addr_i_p1[2]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref O (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + ) + ) + (net (rename addr_i_p1_3_ "addr_i_p1[3]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref O (instanceref INFERRED_GEN_cnt_i_3__i_1__0)) + ) + ) + (net (rename addr_i_p1_4_ "addr_i_p1[4]") (joined + (portref D (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref O (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + ) + ) + (net fifo_Read (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_2__i_1__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_3__i_2__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_2__0)) + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_3__0)) + (portref I2 (instanceref INFERRED_GEN_cnt_i_1__i_1__0)) + (portref I3 (instanceref FIFO_Full_i_1__0)) + (portref fifo_Read) + ) + ) + (net fifo_full_p1 (joined + (portref O (instanceref FIFO_Full_i_1__0)) + (portref fifo_full_p1) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref I0 (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref INFERRED_GEN_cnt_i_reg_0_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_1_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_2_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_3_)) + (portref C (instanceref INFERRED_GEN_cnt_i_reg_4_)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref I1 (instanceref INFERRED_GEN_cnt_i_4__i_1__0)) + (portref s_axi_aresetn) + ) + ) + (net tx_Buffer_Full (joined + (portref I2 (instanceref INFERRED_GEN_cnt_i_0__i_1__0)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref I2 (instanceref tx_Start_i_1)) + (portref tx_DataBits) + ) + ) + (net tx_Data_Enable_reg (joined + (portref I0 (instanceref tx_Start_i_1)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Start (joined + (portref I3 (instanceref tx_Start_i_1)) + (portref tx_Start) + ) + ) + (net tx_Start0 (joined + (portref O (instanceref tx_Start_i_1)) + (portref tx_Start0) + ) + ) + ) + + (property ORIG_REF_NAME (string "cntr_incr_decr_addn_f")) + ) + ) + (cell axi_uart_dynshreg_f (celltype GENERIC) + (view dynshreg_f (viewtype NETLIST) + (interface + (port fifo_wr (direction INPUT)) + (port mux_Out (direction OUTPUT)) + (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) + (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) + (port p_4_in (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port (array (rename Q "Q[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance (rename INFERRED_GEN_data_reg_15__0__srl16 "INFERRED_GEN.data_reg[15][0]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__1__srl16 "INFERRED_GEN.data_reg[15][1]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__2__srl16 "INFERRED_GEN.data_reg[15][2]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__3__srl16 "INFERRED_GEN.data_reg[15][3]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__4__srl16 "INFERRED_GEN.data_reg[15][4]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__5__srl16 "INFERRED_GEN.data_reg[15][5]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__6__srl16 "INFERRED_GEN.data_reg[15][6]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ")) + ) + (instance (rename INFERRED_GEN_data_reg_15__7__srl16 "INFERRED_GEN.data_reg[15][7]_srl16") (viewref netlist (cellref SRL16E (libraryref hdi_primitives))) + (property INIT (string "16'h0000")) + (property srl_bus_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ")) + (property srl_name (string "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ")) + ) + (instance serial_Data_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance serial_Data_i_2 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h44400040")) + ) + (instance serial_Data_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h88800080")) + ) + (instance serial_Data_i_4 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h44400040")) + ) + (instance serial_Data_i_5 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h000A000C")) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref A0 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A0 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 3)) + ) + ) + (net (rename Q_1_ "Q[1]") (joined + (portref A1 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A1 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 2)) + ) + ) + (net (rename Q_2_ "Q[2]") (joined + (portref A2 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A2 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 1)) + ) + ) + (net (rename Q_3_ "Q[3]") (joined + (portref A3 (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref A3 (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member Q 0)) + ) + ) + (net (rename fifo_DOut_0_ "fifo_DOut[0]") (joined + (portref I1 (instanceref serial_Data_i_5)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + ) + ) + (net (rename fifo_DOut_1_ "fifo_DOut[1]") (joined + (portref I2 (instanceref serial_Data_i_4)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + ) + ) + (net (rename fifo_DOut_2_ "fifo_DOut[2]") (joined + (portref I2 (instanceref serial_Data_i_2)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + ) + ) + (net (rename fifo_DOut_3_ "fifo_DOut[3]") (joined + (portref I4 (instanceref serial_Data_i_4)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + ) + ) + (net (rename fifo_DOut_4_ "fifo_DOut[4]") (joined + (portref I0 (instanceref serial_Data_i_5)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + ) + ) + (net (rename fifo_DOut_5_ "fifo_DOut[5]") (joined + (portref I2 (instanceref serial_Data_i_3)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + ) + ) + (net (rename fifo_DOut_6_ "fifo_DOut[6]") (joined + (portref I4 (instanceref serial_Data_i_2)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + ) + ) + (net (rename fifo_DOut_7_ "fifo_DOut[7]") (joined + (portref I4 (instanceref serial_Data_i_3)) + (portref Q (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + ) + ) + (net fifo_wr (joined + (portref CE (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CE (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref O (instanceref serial_Data_i_1)) + (portref mux_Out) + ) + ) + (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined + (portref I0 (instanceref serial_Data_i_3)) + (portref I0 (instanceref serial_Data_i_4)) + (portref I3 (instanceref serial_Data_i_2)) + (portref I4 (instanceref serial_Data_i_5)) + (portref mux_sel_reg_0_) + ) + ) + (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined + (portref I0 (instanceref serial_Data_i_2)) + (portref I1 (instanceref serial_Data_i_3)) + (portref I1 (instanceref serial_Data_i_4)) + (portref I3 (instanceref serial_Data_i_5)) + (portref mux_sel_reg_2_) + ) + ) + (net p_4_in (joined + (portref I1 (instanceref serial_Data_i_2)) + (portref I2 (instanceref serial_Data_i_5)) + (portref I3 (instanceref serial_Data_i_3)) + (portref I3 (instanceref serial_Data_i_4)) + (portref p_4_in) + ) + ) + (net s_axi_aclk (joined + (portref CLK (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref CLK (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__7__srl16)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__6__srl16)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__5__srl16)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__4__srl16)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__3__srl16)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__2__srl16)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__1__srl16)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref D (instanceref INFERRED_GEN_data_reg_15__0__srl16)) + (portref (member s_axi_wdata 0)) + ) + ) + (net serial_Data_i_2_n_0 (joined + (portref I0 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_2)) + ) + ) + (net serial_Data_i_3_n_0 (joined + (portref I1 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_3)) + ) + ) + (net serial_Data_i_4_n_0 (joined + (portref I2 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_4)) + ) + ) + (net serial_Data_i_5_n_0 (joined + (portref I3 (instanceref serial_Data_i_1)) + (portref O (instanceref serial_Data_i_5)) + ) + ) + ) + + (property ORIG_REF_NAME (string "dynshreg_f")) + ) + ) + (cell axi_uart_srl_fifo_rbu_f (celltype GENERIC) + (view srl_fifo_rbu_f (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port fifo_Read (direction INPUT)) + (port fifo_wr (direction INPUT)) + (port mux_Out (direction OUTPUT)) + (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) + (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) + (port p_4_in (direction INPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port tx_DataBits (direction INPUT)) + (port tx_Data_Enable_reg (direction INPUT)) + (port tx_Start (direction INPUT)) + (port tx_Start0 (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance CNTR_INCR_DECR_ADDN_F_I (viewref cntr_incr_decr_addn_f (cellref axi_uart_cntr_incr_decr_addn_f (libraryref work_library0_1)))) + (instance DYNSHREG_F_I (viewref dynshreg_f (cellref axi_uart_dynshreg_f (libraryref work_library0_1)))) + (instance FIFO_Full_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (net (rename &_const1_ "") (joined + (portref CE (instanceref FIFO_Full_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Bus_RNW_reg) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_2 (joined + (portref (member Q 1) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 0) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_3 (joined + (portref (member Q 2) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 1) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_4 (joined + (portref (member Q 3) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 2) (instanceref DYNSHREG_F_I)) + ) + ) + (net CNTR_INCR_DECR_ADDN_F_I_n_5 (joined + (portref (member Q 4) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref (member Q 3) (instanceref DYNSHREG_F_I)) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref (member Q 0) (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref Q_0_) + ) + ) + (net TX_FIFO_Reset (joined + (portref R (instanceref FIFO_Full_reg)) + (portref SS_0_ (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net fifo_Read (joined + (portref fifo_Read (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref fifo_Read) + ) + ) + (net fifo_full_p1 (joined + (portref D (instanceref FIFO_Full_reg)) + (portref fifo_full_p1 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref DYNSHREG_F_I)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref mux_Out (instanceref DYNSHREG_F_I)) + (portref mux_Out) + ) + ) + (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined + (portref mux_sel_reg_0_ (instanceref DYNSHREG_F_I)) + (portref mux_sel_reg_0_) + ) + ) + (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined + (portref mux_sel_reg_2_ (instanceref DYNSHREG_F_I)) + (portref mux_sel_reg_2_) + ) + ) + (net p_4_in (joined + (portref p_4_in (instanceref DYNSHREG_F_I)) + (portref p_4_in) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref reset_TX_FIFO_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref FIFO_Full_reg)) + (portref s_axi_aclk (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aclk (instanceref DYNSHREG_F_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref DYNSHREG_F_I)) + (portref (member s_axi_wdata 0)) + ) + ) + (net tx_Buffer_Full (joined + (portref Q (instanceref FIFO_Full_reg)) + (portref tx_Buffer_Full (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref tx_DataBits (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_DataBits) + ) + ) + (net tx_Data_Enable_reg (joined + (portref tx_Data_Enable_reg (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Start (joined + (portref tx_Start (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Start) + ) + ) + (net tx_Start0 (joined + (portref tx_Start0 (instanceref CNTR_INCR_DECR_ADDN_F_I)) + (portref tx_Start0) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_rbu_f")) + ) + ) + (cell axi_uart_srl_fifo_f (celltype GENERIC) + (view srl_fifo_f (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port fifo_Read (direction INPUT)) + (port fifo_wr (direction INPUT)) + (port mux_Out (direction OUTPUT)) + (port (rename mux_sel_reg_0_ "mux_sel_reg[0]") (direction INPUT)) + (port (rename mux_sel_reg_2_ "mux_sel_reg[2]") (direction INPUT)) + (port p_4_in (direction INPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port tx_DataBits (direction INPUT)) + (port tx_Data_Enable_reg (direction INPUT)) + (port tx_Start (direction INPUT)) + (port tx_Start0 (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance I_SRL_FIFO_RBU_F (viewref srl_fifo_rbu_f (cellref axi_uart_srl_fifo_rbu_f (libraryref work_library0_1)))) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref Bus_RNW_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref I_SRL_FIFO_RBU_F)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref Q_0_) + ) + ) + (net fifo_Read (joined + (portref fifo_Read (instanceref I_SRL_FIFO_RBU_F)) + (portref fifo_Read) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref I_SRL_FIFO_RBU_F)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref mux_Out (instanceref I_SRL_FIFO_RBU_F)) + (portref mux_Out) + ) + ) + (net (rename mux_sel_reg_0_ "mux_sel_reg[0]") (joined + (portref mux_sel_reg_0_ (instanceref I_SRL_FIFO_RBU_F)) + (portref mux_sel_reg_0_) + ) + ) + (net (rename mux_sel_reg_2_ "mux_sel_reg[2]") (joined + (portref mux_sel_reg_2_ (instanceref I_SRL_FIFO_RBU_F)) + (portref mux_sel_reg_2_) + ) + ) + (net p_4_in (joined + (portref p_4_in (instanceref I_SRL_FIFO_RBU_F)) + (portref p_4_in) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref reset_TX_FIFO_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref I_SRL_FIFO_RBU_F)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref I_SRL_FIFO_RBU_F)) + (portref (member s_axi_wdata 0)) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref tx_DataBits (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_DataBits) + ) + ) + (net tx_Data_Enable_reg (joined + (portref tx_Data_Enable_reg (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Data_Enable_reg) + ) + ) + (net tx_Start (joined + (portref tx_Start (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Start) + ) + ) + (net tx_Start0 (joined + (portref tx_Start0 (instanceref I_SRL_FIFO_RBU_F)) + (portref tx_Start0) + ) + ) + ) + + (property ORIG_REF_NAME (string "srl_fifo_f")) + ) + ) + (cell axi_uart_uartlite_tx (celltype GENERIC) + (view uartlite_tx (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port en_16x_Baud (direction INPUT)) + (port fifo_wr (direction INPUT)) + (port reset_TX_FIFO_reg (direction INPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx (direction OUTPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (rename SR_0_ "SR[0]") (direction INPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + ) + (contents + (instance MID_START_BIT_SRL16_I (viewref dynshreg_i_f__parameterized0 (cellref axi_uart_dynshreg_i_f__parameterized0 (libraryref work_library0_1)))) + (instance SRL_FIFO_I (viewref srl_fifo_f (cellref axi_uart_srl_fifo_f (libraryref work_library0_1)))) + (instance TX_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h31")) + ) + (instance TX_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance fifo_Read_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0100")) + ) + (instance fifo_Read_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename mux_sel_0__i_1 "mux_sel[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hE1F0F1F0")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename mux_sel_1__i_1 "mux_sel[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h99AAABAA")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename mux_sel_2__i_1 "mux_sel[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h7777888C")) + ) + (instance (rename mux_sel_reg_0_ "mux_sel_reg[0]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename mux_sel_reg_1_ "mux_sel_reg[1]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename mux_sel_reg_2_ "mux_sel_reg[2]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance serial_Data_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_DataBits_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0F08")) + ) + (instance tx_DataBits_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_Data_Enable_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_Start_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref TX_reg)) + (portref CE (instanceref fifo_Read_reg)) + (portref CE (instanceref mux_sel_reg_0_)) + (portref CE (instanceref mux_sel_reg_1_)) + (portref CE (instanceref mux_sel_reg_2_)) + (portref CE (instanceref serial_Data_reg)) + (portref CE (instanceref tx_DataBits_reg)) + (portref CE (instanceref tx_Data_Enable_reg)) + (portref CE (instanceref tx_Start_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref SRL_FIFO_I)) + (portref Bus_RNW_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref SRL_FIFO_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net MID_START_BIT_SRL16_I_n_0 (joined + (portref D (instanceref tx_Data_Enable_reg)) + (portref tx_Data_Enable_reg (instanceref MID_START_BIT_SRL16_I)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref SRL_FIFO_I)) + (portref Q_0_) + ) + ) + (net (rename SR_0_ "SR[0]") (joined + (portref R (instanceref fifo_Read_reg)) + (portref R (instanceref serial_Data_reg)) + (portref R (instanceref tx_DataBits_reg)) + (portref R (instanceref tx_Data_Enable_reg)) + (portref R (instanceref tx_Start_reg)) + (portref S (instanceref TX_reg)) + (portref S (instanceref mux_sel_reg_0_)) + (portref S (instanceref mux_sel_reg_1_)) + (portref S (instanceref mux_sel_reg_2_)) + (portref SR_0_) + ) + ) + (net TX0 (joined + (portref D (instanceref TX_reg)) + (portref O (instanceref TX_i_1)) + ) + ) + (net en_16x_Baud (joined + (portref en_16x_Baud (instanceref MID_START_BIT_SRL16_I)) + (portref en_16x_Baud) + ) + ) + (net fifo_Read (joined + (portref I2 (instanceref tx_DataBits_i_1)) + (portref Q (instanceref fifo_Read_reg)) + (portref fifo_Read (instanceref SRL_FIFO_I)) + ) + ) + (net fifo_Read0 (joined + (portref D (instanceref fifo_Read_reg)) + (portref O (instanceref fifo_Read_i_1)) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref SRL_FIFO_I)) + (portref fifo_wr) + ) + ) + (net mux_Out (joined + (portref D (instanceref serial_Data_reg)) + (portref mux_Out (instanceref SRL_FIFO_I)) + ) + ) + (net (rename mux_sel_0__i_1_n_0 "mux_sel[0]_i_1_n_0") (joined + (portref D (instanceref mux_sel_reg_0_)) + (portref O (instanceref mux_sel_0__i_1)) + ) + ) + (net (rename mux_sel_1__i_1_n_0 "mux_sel[1]_i_1_n_0") (joined + (portref D (instanceref mux_sel_reg_1_)) + (portref O (instanceref mux_sel_1__i_1)) + ) + ) + (net (rename mux_sel_2__i_1_n_0 "mux_sel[2]_i_1_n_0") (joined + (portref D (instanceref mux_sel_reg_2_)) + (portref O (instanceref mux_sel_2__i_1)) + ) + ) + (net (rename mux_sel_reg_n_0__0_ "mux_sel_reg_n_0_[0]") (joined + (portref I0 (instanceref fifo_Read_i_1)) + (portref I2 (instanceref mux_sel_0__i_1)) + (portref I2 (instanceref mux_sel_1__i_1)) + (portref I2 (instanceref mux_sel_2__i_1)) + (portref Q (instanceref mux_sel_reg_0_)) + (portref mux_sel_reg_0_ (instanceref SRL_FIFO_I)) + ) + ) + (net (rename mux_sel_reg_n_0__2_ "mux_sel_reg_n_0_[2]") (joined + (portref I1 (instanceref fifo_Read_i_1)) + (portref I1 (instanceref mux_sel_0__i_1)) + (portref I1 (instanceref mux_sel_1__i_1)) + (portref I4 (instanceref mux_sel_2__i_1)) + (portref Q (instanceref mux_sel_reg_2_)) + (portref mux_sel_reg_2_ (instanceref SRL_FIFO_I)) + ) + ) + (net p_4_in (joined + (portref I0 (instanceref mux_sel_0__i_1)) + (portref I0 (instanceref mux_sel_1__i_1)) + (portref I2 (instanceref fifo_Read_i_1)) + (portref I3 (instanceref mux_sel_2__i_1)) + (portref Q (instanceref mux_sel_reg_1_)) + (portref p_4_in (instanceref SRL_FIFO_I)) + ) + ) + (net reset_TX_FIFO_reg (joined + (portref reset_TX_FIFO_reg (instanceref SRL_FIFO_I)) + (portref reset_TX_FIFO_reg) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref TX_reg)) + (portref C (instanceref fifo_Read_reg)) + (portref C (instanceref mux_sel_reg_0_)) + (portref C (instanceref mux_sel_reg_1_)) + (portref C (instanceref mux_sel_reg_2_)) + (portref C (instanceref serial_Data_reg)) + (portref C (instanceref tx_DataBits_reg)) + (portref C (instanceref tx_Data_Enable_reg)) + (portref C (instanceref tx_Start_reg)) + (portref s_axi_aclk (instanceref MID_START_BIT_SRL16_I)) + (portref s_axi_aclk (instanceref SRL_FIFO_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref SRL_FIFO_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref SRL_FIFO_I)) + (portref (member s_axi_wdata 0)) + ) + ) + (net serial_Data (joined + (portref I2 (instanceref TX_i_1)) + (portref Q (instanceref serial_Data_reg)) + ) + ) + (net tx (joined + (portref Q (instanceref TX_reg)) + (portref tx) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref SRL_FIFO_I)) + (portref tx_Buffer_Full) + ) + ) + (net tx_DataBits (joined + (portref I0 (instanceref TX_i_1)) + (portref I0 (instanceref mux_sel_2__i_1)) + (portref I3 (instanceref tx_DataBits_i_1)) + (portref I4 (instanceref mux_sel_0__i_1)) + (portref I4 (instanceref mux_sel_1__i_1)) + (portref Q (instanceref tx_DataBits_reg)) + (portref tx_DataBits (instanceref SRL_FIFO_I)) + ) + ) + (net tx_DataBits0 (joined + (portref D (instanceref tx_DataBits_reg)) + (portref O (instanceref tx_DataBits_i_1)) + ) + ) + (net tx_Data_Enable_reg_n_0 (joined + (portref I1 (instanceref mux_sel_2__i_1)) + (portref I1 (instanceref tx_DataBits_i_1)) + (portref I3 (instanceref fifo_Read_i_1)) + (portref I3 (instanceref mux_sel_0__i_1)) + (portref I3 (instanceref mux_sel_1__i_1)) + (portref Q (instanceref tx_Data_Enable_reg)) + (portref tx_Data_Enable_reg (instanceref SRL_FIFO_I)) + (portref tx_Data_Enable_reg_0 (instanceref MID_START_BIT_SRL16_I)) + ) + ) + (net tx_Start (joined + (portref I0 (instanceref tx_DataBits_i_1)) + (portref I1 (instanceref TX_i_1)) + (portref Q (instanceref tx_Start_reg)) + (portref tx_Start (instanceref SRL_FIFO_I)) + ) + ) + (net tx_Start0 (joined + (portref D (instanceref tx_Start_reg)) + (portref tx_Start0 (instanceref SRL_FIFO_I)) + ) + ) + ) + + (property ORIG_REF_NAME (string "uartlite_tx")) + ) + ) + (cell axi_uart_uartlite_core (celltype GENERIC) + (view uartlite_core (viewtype NETLIST) + (interface + (port Bus_RNW_reg (direction INPUT)) + (port Bus_RNW_reg_reg (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (direction INPUT)) + (port (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (direction INPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_4__0 "INFERRED_GEN.cnt_i_reg[4]_0") (direction INPUT)) + (port bus2ip_reset (direction OUTPUT)) + (port enable_interrupts (direction OUTPUT)) + (port fifo_wr (direction INPUT)) + (port interrupt (direction OUTPUT)) + (port reset_RX_FIFO (direction INPUT)) + (port reset_TX_FIFO (direction INPUT)) + (port rx (direction INPUT)) + (port rx_Buffer_Full (direction OUTPUT)) + (port s_axi_aclk (direction INPUT)) + (port s_axi_aresetn (direction INPUT)) + (port tx (direction OUTPUT)) + (port tx_Buffer_Full (direction OUTPUT)) + (port (rename INFERRED_GEN_cnt_i_reg_2__0_ "INFERRED_GEN.cnt_i_reg[2][0]") (direction OUTPUT)) + (port (rename Q_0_ "Q[0]") (direction OUTPUT)) + (port (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (direction INPUT)) + (port (array (rename out "out[7:0]") 8) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[7:0]") 8) (direction INPUT)) + (port (array (rename status_reg "status_reg[1:0]") 2) (direction OUTPUT)) + ) + (contents + (instance BAUD_RATE_I (viewref baudrate (cellref axi_uart_baudrate (libraryref work_library0_1)))) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance Interrupt_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance UARTLITE_RX_I (viewref uartlite_rx (cellref axi_uart_uartlite_rx (libraryref work_library0_1)))) + (instance UARTLITE_TX_I (viewref uartlite_tx (cellref axi_uart_uartlite_tx (libraryref work_library0_1)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance clr_Status_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance enable_interrupts_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance reset_RX_FIFO_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance reset_TX_FIFO_reg (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance rx_Data_Present_Pre_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename status_reg_reg_1_ "status_reg_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename status_reg_reg_2_ "status_reg_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance tx_Buffer_Empty_Pre_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref R (instanceref rx_Data_Present_Pre_reg)) + (portref R (instanceref status_reg_reg_1_)) + (portref R (instanceref status_reg_reg_2_)) + (portref R (instanceref tx_Buffer_Empty_Pre_reg)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref Interrupt_reg)) + (portref CE (instanceref clr_Status_reg)) + (portref CE (instanceref enable_interrupts_reg)) + (portref CE (instanceref reset_RX_FIFO_reg)) + (portref CE (instanceref reset_TX_FIFO_reg)) + (portref CE (instanceref rx_Data_Present_Pre_reg)) + (portref CE (instanceref status_reg_reg_1_)) + (portref CE (instanceref status_reg_reg_2_)) + (portref CE (instanceref tx_Buffer_Empty_Pre_reg)) + (portref P (instanceref VCC)) + ) + ) + (net Bus_RNW_reg (joined + (portref Bus_RNW_reg (instanceref UARTLITE_RX_I)) + (portref Bus_RNW_reg (instanceref UARTLITE_TX_I)) + (portref Bus_RNW_reg) + ) + ) + (net Bus_RNW_reg_reg (joined + (portref Bus_RNW_reg_reg (instanceref UARTLITE_RX_I)) + (portref Bus_RNW_reg_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref UARTLITE_RX_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ "GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref UARTLITE_RX_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref UARTLITE_TX_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ "GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref UARTLITE_TX_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_) + ) + ) + (net (rename GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ "GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]") (joined + (portref D (instanceref enable_interrupts_reg)) + (portref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_2__0_ "INFERRED_GEN.cnt_i_reg[2][0]") (joined + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref UARTLITE_RX_I)) + (portref Q_0_ (instanceref UARTLITE_TX_I)) + (portref INFERRED_GEN_cnt_i_reg_2__0_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4_ "INFERRED_GEN.cnt_i_reg[4]") (joined + (portref D (instanceref tx_Buffer_Empty_Pre_reg)) + (portref INFERRED_GEN_cnt_i_reg_4_) + ) + ) + (net (rename INFERRED_GEN_cnt_i_reg_4__0 "INFERRED_GEN.cnt_i_reg[4]_0") (joined + (portref D (instanceref rx_Data_Present_Pre_reg)) + (portref INFERRED_GEN_cnt_i_reg_4__0) + ) + ) + (net Interrupt0 (joined + (portref D (instanceref Interrupt_reg)) + (portref Interrupt0 (instanceref UARTLITE_RX_I)) + ) + ) + (net (rename Q_0_ "Q[0]") (joined + (portref Q_0_ (instanceref UARTLITE_RX_I)) + (portref Q_0_) + ) + ) + (net UARTLITE_RX_I_n_4 (joined + (portref D (instanceref status_reg_reg_2_)) + (portref status_reg_reg_2__0 (instanceref UARTLITE_RX_I)) + ) + ) + (net (rename bus2ip_rdce_0_ "bus2ip_rdce[0]") (joined + (portref D (instanceref clr_Status_reg)) + (portref bus2ip_rdce_0_) + ) + ) + (net bus2ip_reset (joined + (portref R (instanceref Interrupt_reg)) + (portref R (instanceref clr_Status_reg)) + (portref R (instanceref enable_interrupts_reg)) + (portref S (instanceref reset_RX_FIFO_reg)) + (portref S (instanceref reset_TX_FIFO_reg)) + (portref SR_0_ (instanceref BAUD_RATE_I)) + (portref SR_0_ (instanceref UARTLITE_RX_I)) + (portref SR_0_ (instanceref UARTLITE_TX_I)) + (portref bus2ip_reset) + ) + ) + (net clr_Status (joined + (portref Q (instanceref clr_Status_reg)) + (portref clr_Status (instanceref UARTLITE_RX_I)) + ) + ) + (net en_16x_Baud (joined + (portref en_16x_Baud (instanceref BAUD_RATE_I)) + (portref en_16x_Baud (instanceref UARTLITE_RX_I)) + (portref en_16x_Baud (instanceref UARTLITE_TX_I)) + ) + ) + (net enable_interrupts (joined + (portref Q (instanceref enable_interrupts_reg)) + (portref enable_interrupts (instanceref UARTLITE_RX_I)) + (portref enable_interrupts) + ) + ) + (net fifo_wr (joined + (portref fifo_wr (instanceref UARTLITE_TX_I)) + (portref fifo_wr) + ) + ) + (net interrupt (joined + (portref Q (instanceref Interrupt_reg)) + (portref interrupt) + ) + ) + (net (rename out_0_ "out[0]") (joined + (portref (member out 7) (instanceref UARTLITE_RX_I)) + (portref (member out 7)) + ) + ) + (net (rename out_1_ "out[1]") (joined + (portref (member out 6) (instanceref UARTLITE_RX_I)) + (portref (member out 6)) + ) + ) + (net (rename out_2_ "out[2]") (joined + (portref (member out 5) (instanceref UARTLITE_RX_I)) + (portref (member out 5)) + ) + ) + (net (rename out_3_ "out[3]") (joined + (portref (member out 4) (instanceref UARTLITE_RX_I)) + (portref (member out 4)) + ) + ) + (net (rename out_4_ "out[4]") (joined + (portref (member out 3) (instanceref UARTLITE_RX_I)) + (portref (member out 3)) + ) + ) + (net (rename out_5_ "out[5]") (joined + (portref (member out 2) (instanceref UARTLITE_RX_I)) + (portref (member out 2)) + ) + ) + (net (rename out_6_ "out[6]") (joined + (portref (member out 1) (instanceref UARTLITE_RX_I)) + (portref (member out 1)) + ) + ) + (net (rename out_7_ "out[7]") (joined + (portref (member out 0) (instanceref UARTLITE_RX_I)) + (portref (member out 0)) + ) + ) + (net reset_RX_FIFO (joined + (portref D (instanceref reset_RX_FIFO_reg)) + (portref reset_RX_FIFO) + ) + ) + (net reset_RX_FIFO_reg_n_0 (joined + (portref Q (instanceref reset_RX_FIFO_reg)) + (portref reset_RX_FIFO_reg (instanceref UARTLITE_RX_I)) + ) + ) + (net reset_TX_FIFO (joined + (portref D (instanceref reset_TX_FIFO_reg)) + (portref reset_TX_FIFO) + ) + ) + (net reset_TX_FIFO_reg_n_0 (joined + (portref Q (instanceref reset_TX_FIFO_reg)) + (portref reset_TX_FIFO_reg (instanceref UARTLITE_TX_I)) + ) + ) + (net rx (joined + (portref rx (instanceref UARTLITE_RX_I)) + (portref rx) + ) + ) + (net rx_Buffer_Full (joined + (portref status_reg_reg_2_ (instanceref UARTLITE_RX_I)) + (portref rx_Buffer_Full) + ) + ) + (net rx_Data_Present_Pre (joined + (portref Q (instanceref rx_Data_Present_Pre_reg)) + (portref rx_Data_Present_Pre (instanceref UARTLITE_RX_I)) + ) + ) + (net s_axi_aclk (joined + (portref C (instanceref Interrupt_reg)) + (portref C (instanceref clr_Status_reg)) + (portref C (instanceref enable_interrupts_reg)) + (portref C (instanceref reset_RX_FIFO_reg)) + (portref C (instanceref reset_TX_FIFO_reg)) + (portref C (instanceref rx_Data_Present_Pre_reg)) + (portref C (instanceref status_reg_reg_1_)) + (portref C (instanceref status_reg_reg_2_)) + (portref C (instanceref tx_Buffer_Empty_Pre_reg)) + (portref s_axi_aclk (instanceref BAUD_RATE_I)) + (portref s_axi_aclk (instanceref UARTLITE_RX_I)) + (portref s_axi_aclk (instanceref UARTLITE_TX_I)) + (portref s_axi_aclk) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref UARTLITE_RX_I)) + (portref s_axi_aresetn (instanceref UARTLITE_TX_I)) + (portref s_axi_aresetn) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 7) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 6) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 3) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref UARTLITE_TX_I)) + (portref (member s_axi_wdata 0)) + ) + ) + (net (rename status_reg_0_ "status_reg[0]") (joined + (portref Q (instanceref status_reg_reg_2_)) + (portref (member status_reg 1) (instanceref UARTLITE_RX_I)) + (portref (member status_reg 1)) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref Q (instanceref status_reg_reg_1_)) + (portref (member status_reg 0) (instanceref UARTLITE_RX_I)) + (portref (member status_reg 0)) + ) + ) + (net status_reg_reg0 (joined + (portref D (instanceref status_reg_reg_1_)) + (portref status_reg_reg0 (instanceref UARTLITE_RX_I)) + ) + ) + (net tx (joined + (portref tx (instanceref UARTLITE_TX_I)) + (portref tx) + ) + ) + (net tx_Buffer_Empty_Pre (joined + (portref Q (instanceref tx_Buffer_Empty_Pre_reg)) + (portref tx_Buffer_Empty_Pre (instanceref UARTLITE_RX_I)) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref UARTLITE_TX_I)) + (portref tx_Buffer_Full) + ) + ) + ) + + (property ORIG_REF_NAME (string "uartlite_core")) + ) + ) + (cell axi_uart_axi_uartlite (celltype GENERIC) + (view axi_uartlite (viewtype NETLIST) + (interface + (port interrupt (direction OUTPUT)) + (port rx (direction INPUT)) + (port s_axi_aclk (direction INPUT) + (property max_fanout (string "10000")) + ) + (port s_axi_aresetn (direction INPUT) + (property max_fanout (string "10000")) + ) + (port s_axi_arready (direction OUTPUT)) + (port s_axi_arvalid (direction INPUT)) + (port s_axi_awready (direction OUTPUT)) + (port s_axi_awvalid (direction INPUT)) + (port s_axi_bready (direction INPUT)) + (port s_axi_bvalid (direction OUTPUT)) + (port s_axi_rready (direction INPUT)) + (port s_axi_rvalid (direction OUTPUT)) + (port s_axi_wready (direction OUTPUT)) + (port s_axi_wvalid (direction INPUT)) + (port tx (direction OUTPUT)) + (port (array (rename s_axi_araddr "s_axi_araddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_bresp "s_axi_bresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[31:0]") 32) (direction OUTPUT)) + (port (array (rename s_axi_rresp "s_axi_rresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[31:0]") 32) (direction INPUT)) + (port (array (rename s_axi_wstrb "s_axi_wstrb[3:0]") 4) (direction INPUT)) + ) + (contents + (instance AXI_LITE_IPIF_I (viewref axi_lite_ipif (cellref axi_uart_axi_lite_ipif (libraryref work_library0_1)))) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance UARTLITE_CORE_I (viewref uartlite_core (cellref axi_uart_uartlite_core (libraryref work_library0_1)))) + (net (rename &_const0_ "") (joined + (portref G (instanceref GND)) + (portref (member s_axi_bresp 1)) + (portref (member s_axi_rdata 21)) + (portref (member s_axi_rdata 20)) + (portref (member s_axi_rdata 19)) + (portref (member s_axi_rdata 18)) + (portref (member s_axi_rdata 17)) + (portref (member s_axi_rdata 16)) + (portref (member s_axi_rdata 15)) + (portref (member s_axi_rdata 14)) + (portref (member s_axi_rdata 13)) + (portref (member s_axi_rdata 12)) + (portref (member s_axi_rdata 11)) + (portref (member s_axi_rdata 10)) + (portref (member s_axi_rdata 9)) + (portref (member s_axi_rdata 8)) + (portref (member s_axi_rdata 7)) + (portref (member s_axi_rdata 6)) + (portref (member s_axi_rdata 5)) + (portref (member s_axi_rdata 4)) + (portref (member s_axi_rdata 3)) + (portref (member s_axi_rdata 2)) + (portref (member s_axi_rdata 1)) + (portref (member s_axi_rdata 0)) + (portref (member s_axi_rdata 23)) + (portref (member s_axi_rdata 22)) + (portref (member s_axi_rresp 1)) + ) + ) + (net AXI_LITE_IPIF_I_n_11 (joined + (portref Bus_RNW_reg_reg (instanceref UARTLITE_CORE_I)) + (portref INFERRED_GEN_cnt_i_reg_2_ (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_12 (joined + (portref INFERRED_GEN_cnt_i_reg_4__0 (instanceref UARTLITE_CORE_I)) + (portref rx_Data_Present_Pre_reg (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_13 (joined + (portref FIFO_Full_reg (instanceref AXI_LITE_IPIF_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg_0_ (instanceref UARTLITE_CORE_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_16 (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg_1_ (instanceref UARTLITE_CORE_I)) + (portref INFERRED_GEN_cnt_i_reg_2__0 (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_17 (joined + (portref INFERRED_GEN_cnt_i_reg_4_ (instanceref UARTLITE_CORE_I)) + (portref tx_Buffer_Empty_Pre_reg (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net AXI_LITE_IPIF_I_n_18 (joined + (portref GEN_BKEND_CE_REGISTERS_3__ce_out_i_reg_3_ (instanceref UARTLITE_CORE_I)) + (portref enable_interrupts_reg (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net (rename I_SLAVE_ATTACHMENT_I_DECODER_Bus_RNW_reg "I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg") (joined + (portref Bus_RNW_reg (instanceref AXI_LITE_IPIF_I)) + (portref Bus_RNW_reg (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename I_SLAVE_ATTACHMENT_I_DECODER_GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg "I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref AXI_LITE_IPIF_I)) + (portref GEN_BKEND_CE_REGISTERS_0__ce_out_i_reg (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename I_SLAVE_ATTACHMENT_I_DECODER_GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg "I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg") (joined + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref AXI_LITE_IPIF_I)) + (portref GEN_BKEND_CE_REGISTERS_1__ce_out_i_reg (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename UARTLITE_RX_I_rx_Data_Empty "UARTLITE_RX_I/rx_Data_Empty") (joined + (portref Q_0_ (instanceref AXI_LITE_IPIF_I)) + (portref Q_0_ (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename UARTLITE_TX_I_fifo_wr "UARTLITE_TX_I/fifo_wr") (joined + (portref fifo_wr (instanceref AXI_LITE_IPIF_I)) + (portref fifo_wr (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename bus2ip_rdce_1_ "bus2ip_rdce[1]") (joined + (portref bus2ip_rdce_0_ (instanceref AXI_LITE_IPIF_I)) + (portref bus2ip_rdce_0_ (instanceref UARTLITE_CORE_I)) + ) + ) + (net bus2ip_reset (joined + (portref bus2ip_reset (instanceref AXI_LITE_IPIF_I)) + (portref bus2ip_reset (instanceref UARTLITE_CORE_I)) + ) + ) + (net enable_interrupts (joined + (portref enable_interrupts (instanceref AXI_LITE_IPIF_I)) + (portref enable_interrupts (instanceref UARTLITE_CORE_I)) + ) + ) + (net interrupt (joined + (portref interrupt (instanceref UARTLITE_CORE_I)) + (portref interrupt) + ) + ) + (net reset_RX_FIFO (joined + (portref reset_RX_FIFO (instanceref AXI_LITE_IPIF_I)) + (portref reset_RX_FIFO (instanceref UARTLITE_CORE_I)) + ) + ) + (net reset_TX_FIFO (joined + (portref reset_TX_FIFO (instanceref AXI_LITE_IPIF_I)) + (portref reset_TX_FIFO (instanceref UARTLITE_CORE_I)) + ) + ) + (net rx (joined + (portref rx (instanceref UARTLITE_CORE_I)) + (portref rx) + ) + ) + (net rx_Buffer_Full (joined + (portref rx_Buffer_Full (instanceref AXI_LITE_IPIF_I)) + (portref rx_Buffer_Full (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_0_ "rx_Data[0]") (joined + (portref (member out 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 0) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_1_ "rx_Data[1]") (joined + (portref (member out 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 1) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_2_ "rx_Data[2]") (joined + (portref (member out 2) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 2) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_3_ "rx_Data[3]") (joined + (portref (member out 3) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 3) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_4_ "rx_Data[4]") (joined + (portref (member out 4) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 4) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_5_ "rx_Data[5]") (joined + (portref (member out 5) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 5) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_6_ "rx_Data[6]") (joined + (portref (member out 6) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 6) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename rx_Data_7_ "rx_Data[7]") (joined + (portref (member out 7) (instanceref AXI_LITE_IPIF_I)) + (portref (member out 7) (instanceref UARTLITE_CORE_I)) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_aclk (instanceref UARTLITE_CORE_I)) + (portref s_axi_aclk) + ) + + (property RTL_MAX_FANOUT (string "found")) + (property MAX_FANOUT (string "10000")) + ) + (net (rename s_axi_araddr_2_ "s_axi_araddr[2]") (joined + (portref (member s_axi_araddr 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_3_ "s_axi_araddr[3]") (joined + (portref (member s_axi_araddr 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_aresetn (instanceref UARTLITE_CORE_I)) + (portref s_axi_aresetn) + ) + + (property RTL_MAX_FANOUT (string "found")) + (property MAX_FANOUT (string "10000")) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref s_axi_arvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_2_ "s_axi_awaddr[2]") (joined + (portref (member s_axi_awaddr 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_3_ "s_axi_awaddr[3]") (joined + (portref (member s_axi_awaddr 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_awready) + (portref s_axi_wready) + ) + ) + (net s_axi_awvalid (joined + (portref s_axi_awvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref s_axi_bready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_1_ "s_axi_bresp[1]") (joined + (portref s_axi_bresp_0_ (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_bresp 0)) + ) + ) + (net s_axi_bvalid (joined + (portref s_axi_bvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref (member s_axi_rdata 7) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 31)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref (member s_axi_rdata 6) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 30)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref (member s_axi_rdata 5) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 29)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref (member s_axi_rdata 4) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 28)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref (member s_axi_rdata 3) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 27)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref (member s_axi_rdata 2) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 26)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref (member s_axi_rdata 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 25)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref (member s_axi_rdata 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rdata 24)) + ) + ) + (net s_axi_rready (joined + (portref s_axi_rready (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_1_ "s_axi_rresp[1]") (joined + (portref s_axi_rresp_0_ (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_rresp 0)) + ) + ) + (net s_axi_rvalid (joined + (portref s_axi_rvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 2) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_wdata 7) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 31)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_wdata 6) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 30)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 5) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 29)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 4) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 28)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member s_axi_wdata 3) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 27)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 2) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 26)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 1) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 25)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 0) (instanceref UARTLITE_CORE_I)) + (portref (member s_axi_wdata 24)) + ) + ) + (net s_axi_wvalid (joined + (portref s_axi_wvalid (instanceref AXI_LITE_IPIF_I)) + (portref s_axi_wvalid) + ) + ) + (net (rename status_reg_1_ "status_reg[1]") (joined + (portref (member status_reg 0) (instanceref AXI_LITE_IPIF_I)) + (portref (member status_reg 0) (instanceref UARTLITE_CORE_I)) + ) + ) + (net (rename status_reg_2_ "status_reg[2]") (joined + (portref (member status_reg 1) (instanceref AXI_LITE_IPIF_I)) + (portref (member status_reg 1) (instanceref UARTLITE_CORE_I)) + ) + ) + (net tx (joined + (portref tx (instanceref UARTLITE_CORE_I)) + (portref tx) + ) + ) + (net tx_Buffer_Empty (joined + (portref INFERRED_GEN_cnt_i_reg_2__0_ (instanceref UARTLITE_CORE_I)) + (portref INFERRED_GEN_cnt_i_reg_4__0_ (instanceref AXI_LITE_IPIF_I)) + ) + ) + (net tx_Buffer_Full (joined + (portref tx_Buffer_Full (instanceref AXI_LITE_IPIF_I)) + (portref tx_Buffer_Full (instanceref UARTLITE_CORE_I)) + ) + ) + ) + + (property C_FAMILY (string "artix7")) + (property C_S_AXI_ACLK_FREQ_HZ (integer 10000000)) + (property C_S_AXI_ADDR_WIDTH (integer 4)) + (property C_S_AXI_DATA_WIDTH (integer 32)) + (property C_BAUDRATE (integer 128000)) + (property C_DATA_BITS (integer 8)) + (property C_USE_PARITY (integer 0)) + (property C_ODD_PARITY (integer 0)) + (property downgradeipidentifiedwarnings (string "yes")) + (property ORIG_REF_NAME (string "axi_uartlite")) + ) + ) + (cell axi_uart (celltype GENERIC) + (view axi_uart (viewtype NETLIST) + (interface + (port interrupt (direction OUTPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME INTERRUPT, SENSITIVITY EDGE_RISING, PortWidth 1")) + (property x_interface_info (string "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT")) + ) + (port rx (direction INPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UARTLITE_BOARD_INTERFACE")) + (property x_interface_info (string "xilinx.com:interface:uart:1.0 UART RxD")) + ) + (port s_axi_aclk (direction INPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000")) + (property x_interface_info (string "xilinx.com:signal:clock:1.0 ACLK CLK")) + ) + (port s_axi_aresetn (direction INPUT) + (property x_interface_parameter (string "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW")) + (property x_interface_info (string "xilinx.com:signal:reset:1.0 ARESETN RST")) + ) + (port s_axi_arready (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI ARREADY")) + ) + (port s_axi_arvalid (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI ARVALID")) + ) + (port s_axi_awready (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI AWREADY")) + ) + (port s_axi_awvalid (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI AWVALID")) + ) + (port s_axi_bready (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI BREADY")) + ) + (port s_axi_bvalid (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI BVALID")) + ) + (port s_axi_rready (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI RREADY")) + ) + (port s_axi_rvalid (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI RVALID")) + ) + (port s_axi_wready (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI WREADY")) + ) + (port s_axi_wvalid (direction INPUT) + (property x_interface_info (string "xilinx.com:interface:aximm:1.0 S_AXI WVALID")) + ) + (port tx (direction OUTPUT) + (property x_interface_info (string "xilinx.com:interface:uart:1.0 UART TxD")) + ) + (port (array (rename s_axi_araddr "s_axi_araddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_awaddr "s_axi_awaddr[3:0]") 4) (direction INPUT)) + (port (array (rename s_axi_bresp "s_axi_bresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_rdata "s_axi_rdata[31:0]") 32) (direction OUTPUT)) + (port (array (rename s_axi_rresp "s_axi_rresp[1:0]") 2) (direction OUTPUT)) + (port (array (rename s_axi_wdata "s_axi_wdata[31:0]") 32) (direction INPUT)) + (port (array (rename s_axi_wstrb "s_axi_wstrb[3:0]") 4) (direction INPUT)) + ) + (contents + (instance U0 (viewref axi_uartlite (cellref axi_uart_axi_uartlite (libraryref work_library0_1))) + (property C_BAUDRATE (integer 128000)) + (property C_DATA_BITS (integer 8)) + (property C_FAMILY (string "artix7")) + (property C_ODD_PARITY (integer 0)) + (property C_S_AXI_ACLK_FREQ_HZ (integer 10000000)) + (property C_S_AXI_ADDR_WIDTH (integer 4)) + (property C_S_AXI_DATA_WIDTH (integer 32)) + (property C_USE_PARITY (integer 0)) + (property downgradeipidentifiedwarnings (string "yes")) + ) + (net interrupt (joined + (portref interrupt (instanceref U0)) + (portref interrupt) + ) + ) + (net rx (joined + (portref rx (instanceref U0)) + (portref rx) + ) + ) + (net s_axi_aclk (joined + (portref s_axi_aclk (instanceref U0)) + (portref s_axi_aclk) + ) + ) + (net (rename s_axi_araddr_0_ "s_axi_araddr[0]") (joined + (portref (member s_axi_araddr 3) (instanceref U0)) + (portref (member s_axi_araddr 3)) + ) + ) + (net (rename s_axi_araddr_1_ "s_axi_araddr[1]") (joined + (portref (member s_axi_araddr 2) (instanceref U0)) + (portref (member s_axi_araddr 2)) + ) + ) + (net (rename s_axi_araddr_2_ "s_axi_araddr[2]") (joined + (portref (member s_axi_araddr 1) (instanceref U0)) + (portref (member s_axi_araddr 1)) + ) + ) + (net (rename s_axi_araddr_3_ "s_axi_araddr[3]") (joined + (portref (member s_axi_araddr 0) (instanceref U0)) + (portref (member s_axi_araddr 0)) + ) + ) + (net s_axi_aresetn (joined + (portref s_axi_aresetn (instanceref U0)) + (portref s_axi_aresetn) + ) + ) + (net s_axi_arready (joined + (portref s_axi_arready (instanceref U0)) + (portref s_axi_arready) + ) + ) + (net s_axi_arvalid (joined + (portref s_axi_arvalid (instanceref U0)) + (portref s_axi_arvalid) + ) + ) + (net (rename s_axi_awaddr_0_ "s_axi_awaddr[0]") (joined + (portref (member s_axi_awaddr 3) (instanceref U0)) + (portref (member s_axi_awaddr 3)) + ) + ) + (net (rename s_axi_awaddr_1_ "s_axi_awaddr[1]") (joined + (portref (member s_axi_awaddr 2) (instanceref U0)) + (portref (member s_axi_awaddr 2)) + ) + ) + (net (rename s_axi_awaddr_2_ "s_axi_awaddr[2]") (joined + (portref (member s_axi_awaddr 1) (instanceref U0)) + (portref (member s_axi_awaddr 1)) + ) + ) + (net (rename s_axi_awaddr_3_ "s_axi_awaddr[3]") (joined + (portref (member s_axi_awaddr 0) (instanceref U0)) + (portref (member s_axi_awaddr 0)) + ) + ) + (net s_axi_awready (joined + (portref s_axi_awready (instanceref U0)) + (portref s_axi_awready) + ) + ) + (net s_axi_awvalid (joined + (portref s_axi_awvalid (instanceref U0)) + (portref s_axi_awvalid) + ) + ) + (net s_axi_bready (joined + (portref s_axi_bready (instanceref U0)) + (portref s_axi_bready) + ) + ) + (net (rename s_axi_bresp_0_ "s_axi_bresp[0]") (joined + (portref (member s_axi_bresp 1) (instanceref U0)) + (portref (member s_axi_bresp 1)) + ) + ) + (net (rename s_axi_bresp_1_ "s_axi_bresp[1]") (joined + (portref (member s_axi_bresp 0) (instanceref U0)) + (portref (member s_axi_bresp 0)) + ) + ) + (net s_axi_bvalid (joined + (portref s_axi_bvalid (instanceref U0)) + (portref s_axi_bvalid) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref (member s_axi_rdata 31) (instanceref U0)) + (portref (member s_axi_rdata 31)) + ) + ) + (net (rename s_axi_rdata_10_ "s_axi_rdata[10]") (joined + (portref (member s_axi_rdata 21) (instanceref U0)) + (portref (member s_axi_rdata 21)) + ) + ) + (net (rename s_axi_rdata_11_ "s_axi_rdata[11]") (joined + (portref (member s_axi_rdata 20) (instanceref U0)) + (portref (member s_axi_rdata 20)) + ) + ) + (net (rename s_axi_rdata_12_ "s_axi_rdata[12]") (joined + (portref (member s_axi_rdata 19) (instanceref U0)) + (portref (member s_axi_rdata 19)) + ) + ) + (net (rename s_axi_rdata_13_ "s_axi_rdata[13]") (joined + (portref (member s_axi_rdata 18) (instanceref U0)) + (portref (member s_axi_rdata 18)) + ) + ) + (net (rename s_axi_rdata_14_ "s_axi_rdata[14]") (joined + (portref (member s_axi_rdata 17) (instanceref U0)) + (portref (member s_axi_rdata 17)) + ) + ) + (net (rename s_axi_rdata_15_ "s_axi_rdata[15]") (joined + (portref (member s_axi_rdata 16) (instanceref U0)) + (portref (member s_axi_rdata 16)) + ) + ) + (net (rename s_axi_rdata_16_ "s_axi_rdata[16]") (joined + (portref (member s_axi_rdata 15) (instanceref U0)) + (portref (member s_axi_rdata 15)) + ) + ) + (net (rename s_axi_rdata_17_ "s_axi_rdata[17]") (joined + (portref (member s_axi_rdata 14) (instanceref U0)) + (portref (member s_axi_rdata 14)) + ) + ) + (net (rename s_axi_rdata_18_ "s_axi_rdata[18]") (joined + (portref (member s_axi_rdata 13) (instanceref U0)) + (portref (member s_axi_rdata 13)) + ) + ) + (net (rename s_axi_rdata_19_ "s_axi_rdata[19]") (joined + (portref (member s_axi_rdata 12) (instanceref U0)) + (portref (member s_axi_rdata 12)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref (member s_axi_rdata 30) (instanceref U0)) + (portref (member s_axi_rdata 30)) + ) + ) + (net (rename s_axi_rdata_20_ "s_axi_rdata[20]") (joined + (portref (member s_axi_rdata 11) (instanceref U0)) + (portref (member s_axi_rdata 11)) + ) + ) + (net (rename s_axi_rdata_21_ "s_axi_rdata[21]") (joined + (portref (member s_axi_rdata 10) (instanceref U0)) + (portref (member s_axi_rdata 10)) + ) + ) + (net (rename s_axi_rdata_22_ "s_axi_rdata[22]") (joined + (portref (member s_axi_rdata 9) (instanceref U0)) + (portref (member s_axi_rdata 9)) + ) + ) + (net (rename s_axi_rdata_23_ "s_axi_rdata[23]") (joined + (portref (member s_axi_rdata 8) (instanceref U0)) + (portref (member s_axi_rdata 8)) + ) + ) + (net (rename s_axi_rdata_24_ "s_axi_rdata[24]") (joined + (portref (member s_axi_rdata 7) (instanceref U0)) + (portref (member s_axi_rdata 7)) + ) + ) + (net (rename s_axi_rdata_25_ "s_axi_rdata[25]") (joined + (portref (member s_axi_rdata 6) (instanceref U0)) + (portref (member s_axi_rdata 6)) + ) + ) + (net (rename s_axi_rdata_26_ "s_axi_rdata[26]") (joined + (portref (member s_axi_rdata 5) (instanceref U0)) + (portref (member s_axi_rdata 5)) + ) + ) + (net (rename s_axi_rdata_27_ "s_axi_rdata[27]") (joined + (portref (member s_axi_rdata 4) (instanceref U0)) + (portref (member s_axi_rdata 4)) + ) + ) + (net (rename s_axi_rdata_28_ "s_axi_rdata[28]") (joined + (portref (member s_axi_rdata 3) (instanceref U0)) + (portref (member s_axi_rdata 3)) + ) + ) + (net (rename s_axi_rdata_29_ "s_axi_rdata[29]") (joined + (portref (member s_axi_rdata 2) (instanceref U0)) + (portref (member s_axi_rdata 2)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref (member s_axi_rdata 29) (instanceref U0)) + (portref (member s_axi_rdata 29)) + ) + ) + (net (rename s_axi_rdata_30_ "s_axi_rdata[30]") (joined + (portref (member s_axi_rdata 1) (instanceref U0)) + (portref (member s_axi_rdata 1)) + ) + ) + (net (rename s_axi_rdata_31_ "s_axi_rdata[31]") (joined + (portref (member s_axi_rdata 0) (instanceref U0)) + (portref (member s_axi_rdata 0)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref (member s_axi_rdata 28) (instanceref U0)) + (portref (member s_axi_rdata 28)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref (member s_axi_rdata 27) (instanceref U0)) + (portref (member s_axi_rdata 27)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref (member s_axi_rdata 26) (instanceref U0)) + (portref (member s_axi_rdata 26)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref (member s_axi_rdata 25) (instanceref U0)) + (portref (member s_axi_rdata 25)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref (member s_axi_rdata 24) (instanceref U0)) + (portref (member s_axi_rdata 24)) + ) + ) + (net (rename s_axi_rdata_8_ "s_axi_rdata[8]") (joined + (portref (member s_axi_rdata 23) (instanceref U0)) + (portref (member s_axi_rdata 23)) + ) + ) + (net (rename s_axi_rdata_9_ "s_axi_rdata[9]") (joined + (portref (member s_axi_rdata 22) (instanceref U0)) + (portref (member s_axi_rdata 22)) + ) + ) + (net s_axi_rready (joined + (portref s_axi_rready (instanceref U0)) + (portref s_axi_rready) + ) + ) + (net (rename s_axi_rresp_0_ "s_axi_rresp[0]") (joined + (portref (member s_axi_rresp 1) (instanceref U0)) + (portref (member s_axi_rresp 1)) + ) + ) + (net (rename s_axi_rresp_1_ "s_axi_rresp[1]") (joined + (portref (member s_axi_rresp 0) (instanceref U0)) + (portref (member s_axi_rresp 0)) + ) + ) + (net s_axi_rvalid (joined + (portref s_axi_rvalid (instanceref U0)) + (portref s_axi_rvalid) + ) + ) + (net (rename s_axi_wdata_0_ "s_axi_wdata[0]") (joined + (portref (member s_axi_wdata 31) (instanceref U0)) + (portref (member s_axi_wdata 31)) + ) + ) + (net (rename s_axi_wdata_10_ "s_axi_wdata[10]") (joined + (portref (member s_axi_wdata 21) (instanceref U0)) + (portref (member s_axi_wdata 21)) + ) + ) + (net (rename s_axi_wdata_11_ "s_axi_wdata[11]") (joined + (portref (member s_axi_wdata 20) (instanceref U0)) + (portref (member s_axi_wdata 20)) + ) + ) + (net (rename s_axi_wdata_12_ "s_axi_wdata[12]") (joined + (portref (member s_axi_wdata 19) (instanceref U0)) + (portref (member s_axi_wdata 19)) + ) + ) + (net (rename s_axi_wdata_13_ "s_axi_wdata[13]") (joined + (portref (member s_axi_wdata 18) (instanceref U0)) + (portref (member s_axi_wdata 18)) + ) + ) + (net (rename s_axi_wdata_14_ "s_axi_wdata[14]") (joined + (portref (member s_axi_wdata 17) (instanceref U0)) + (portref (member s_axi_wdata 17)) + ) + ) + (net (rename s_axi_wdata_15_ "s_axi_wdata[15]") (joined + (portref (member s_axi_wdata 16) (instanceref U0)) + (portref (member s_axi_wdata 16)) + ) + ) + (net (rename s_axi_wdata_16_ "s_axi_wdata[16]") (joined + (portref (member s_axi_wdata 15) (instanceref U0)) + (portref (member s_axi_wdata 15)) + ) + ) + (net (rename s_axi_wdata_17_ "s_axi_wdata[17]") (joined + (portref (member s_axi_wdata 14) (instanceref U0)) + (portref (member s_axi_wdata 14)) + ) + ) + (net (rename s_axi_wdata_18_ "s_axi_wdata[18]") (joined + (portref (member s_axi_wdata 13) (instanceref U0)) + (portref (member s_axi_wdata 13)) + ) + ) + (net (rename s_axi_wdata_19_ "s_axi_wdata[19]") (joined + (portref (member s_axi_wdata 12) (instanceref U0)) + (portref (member s_axi_wdata 12)) + ) + ) + (net (rename s_axi_wdata_1_ "s_axi_wdata[1]") (joined + (portref (member s_axi_wdata 30) (instanceref U0)) + (portref (member s_axi_wdata 30)) + ) + ) + (net (rename s_axi_wdata_20_ "s_axi_wdata[20]") (joined + (portref (member s_axi_wdata 11) (instanceref U0)) + (portref (member s_axi_wdata 11)) + ) + ) + (net (rename s_axi_wdata_21_ "s_axi_wdata[21]") (joined + (portref (member s_axi_wdata 10) (instanceref U0)) + (portref (member s_axi_wdata 10)) + ) + ) + (net (rename s_axi_wdata_22_ "s_axi_wdata[22]") (joined + (portref (member s_axi_wdata 9) (instanceref U0)) + (portref (member s_axi_wdata 9)) + ) + ) + (net (rename s_axi_wdata_23_ "s_axi_wdata[23]") (joined + (portref (member s_axi_wdata 8) (instanceref U0)) + (portref (member s_axi_wdata 8)) + ) + ) + (net (rename s_axi_wdata_24_ "s_axi_wdata[24]") (joined + (portref (member s_axi_wdata 7) (instanceref U0)) + (portref (member s_axi_wdata 7)) + ) + ) + (net (rename s_axi_wdata_25_ "s_axi_wdata[25]") (joined + (portref (member s_axi_wdata 6) (instanceref U0)) + (portref (member s_axi_wdata 6)) + ) + ) + (net (rename s_axi_wdata_26_ "s_axi_wdata[26]") (joined + (portref (member s_axi_wdata 5) (instanceref U0)) + (portref (member s_axi_wdata 5)) + ) + ) + (net (rename s_axi_wdata_27_ "s_axi_wdata[27]") (joined + (portref (member s_axi_wdata 4) (instanceref U0)) + (portref (member s_axi_wdata 4)) + ) + ) + (net (rename s_axi_wdata_28_ "s_axi_wdata[28]") (joined + (portref (member s_axi_wdata 3) (instanceref U0)) + (portref (member s_axi_wdata 3)) + ) + ) + (net (rename s_axi_wdata_29_ "s_axi_wdata[29]") (joined + (portref (member s_axi_wdata 2) (instanceref U0)) + (portref (member s_axi_wdata 2)) + ) + ) + (net (rename s_axi_wdata_2_ "s_axi_wdata[2]") (joined + (portref (member s_axi_wdata 29) (instanceref U0)) + (portref (member s_axi_wdata 29)) + ) + ) + (net (rename s_axi_wdata_30_ "s_axi_wdata[30]") (joined + (portref (member s_axi_wdata 1) (instanceref U0)) + (portref (member s_axi_wdata 1)) + ) + ) + (net (rename s_axi_wdata_31_ "s_axi_wdata[31]") (joined + (portref (member s_axi_wdata 0) (instanceref U0)) + (portref (member s_axi_wdata 0)) + ) + ) + (net (rename s_axi_wdata_3_ "s_axi_wdata[3]") (joined + (portref (member s_axi_wdata 28) (instanceref U0)) + (portref (member s_axi_wdata 28)) + ) + ) + (net (rename s_axi_wdata_4_ "s_axi_wdata[4]") (joined + (portref (member s_axi_wdata 27) (instanceref U0)) + (portref (member s_axi_wdata 27)) + ) + ) + (net (rename s_axi_wdata_5_ "s_axi_wdata[5]") (joined + (portref (member s_axi_wdata 26) (instanceref U0)) + (portref (member s_axi_wdata 26)) + ) + ) + (net (rename s_axi_wdata_6_ "s_axi_wdata[6]") (joined + (portref (member s_axi_wdata 25) (instanceref U0)) + (portref (member s_axi_wdata 25)) + ) + ) + (net (rename s_axi_wdata_7_ "s_axi_wdata[7]") (joined + (portref (member s_axi_wdata 24) (instanceref U0)) + (portref (member s_axi_wdata 24)) + ) + ) + (net (rename s_axi_wdata_8_ "s_axi_wdata[8]") (joined + (portref (member s_axi_wdata 23) (instanceref U0)) + (portref (member s_axi_wdata 23)) + ) + ) + (net (rename s_axi_wdata_9_ "s_axi_wdata[9]") (joined + (portref (member s_axi_wdata 22) (instanceref U0)) + (portref (member s_axi_wdata 22)) + ) + ) + (net s_axi_wready (joined + (portref s_axi_wready (instanceref U0)) + (portref s_axi_wready) + ) + ) + (net (rename s_axi_wstrb_0_ "s_axi_wstrb[0]") (joined + (portref (member s_axi_wstrb 3) (instanceref U0)) + (portref (member s_axi_wstrb 3)) + ) + ) + (net (rename s_axi_wstrb_1_ "s_axi_wstrb[1]") (joined + (portref (member s_axi_wstrb 2) (instanceref U0)) + (portref (member s_axi_wstrb 2)) + ) + ) + (net (rename s_axi_wstrb_2_ "s_axi_wstrb[2]") (joined + (portref (member s_axi_wstrb 1) (instanceref U0)) + (portref (member s_axi_wstrb 1)) + ) + ) + (net (rename s_axi_wstrb_3_ "s_axi_wstrb[3]") (joined + (portref (member s_axi_wstrb 0) (instanceref U0)) + (portref (member s_axi_wstrb 0)) + ) + ) + (net s_axi_wvalid (joined + (portref s_axi_wvalid (instanceref U0)) + (portref s_axi_wvalid) + ) + ) + (net tx (joined + (portref tx (instanceref U0)) + (portref tx) + ) + ) + ) + + (property downgradeipidentifiedwarnings (string "yes")) + (property x_core_info (string "axi_uartlite,Vivado 2017.4")) + (property CHECK_LICENSE_TYPE (string "axi_uart,axi_uartlite,{}")) + (property core_generation_info (string "axi_uart,axi_uartlite,{x_ipProduct=Vivado 2017.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=10000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=128000,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}")) + ) + ) + ) + (Library work + (edifLevel 0) + (technology (numberDefinition )) + (cell uart_bmpg (celltype GENERIC) + (view uart_bmpg (viewtype NETLIST) + (interface + (port upg_clk_i (direction INPUT)) + (port upg_clk_o (direction OUTPUT)) + (port upg_done_o (direction OUTPUT)) + (port upg_rst_i (direction INPUT)) + (port upg_rx_i (direction INPUT)) + (port upg_tx_o (direction OUTPUT)) + (port upg_wen_o (direction OUTPUT)) + (port (array (rename upg_adr_o "upg_adr_o[14:0]") 15) (direction OUTPUT)) + (port (array (rename upg_dat_o "upg_dat_o[31:0]") 32) (direction OUTPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename RCS_0__i_1 "RCS[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFF0050CF")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename RCS_1__i_1 "RCS[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF00FF0055FCFF00")) + ) + (instance (rename RCS_2__i_1 "RCS[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFF5C000")) + ) + (instance (rename RCS_reg_0_ "RCS_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RCS_reg_1_ "RCS_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RCS_reg_2_ "RCS_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename WCS_0__i_1 "WCS[0]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF0000FF0F080F")) + ) + (instance (rename WCS_0__i_2 "WCS[0]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename WCS_1__i_1 "WCS[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFF7700F0F0F0")) + ) + (instance (rename WCS_2__i_1 "WCS[2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF00FF88FF000F00")) + ) + (instance (rename WCS_2__i_2 "WCS[2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename WCS_2__i_3 "WCS[2]_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hEFFF")) + ) + (instance (rename WCS_2__i_4 "WCS[2]_i_4") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF7FFF")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename WCS_2__i_5 "WCS[2]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hEFFF")) + ) + (instance (rename WCS_reg_0_ "WCS_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename WCS_reg_1_ "WCS_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename WCS_reg_2_ "WCS_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance axi_uart_inst (viewref axi_uart (cellref axi_uart (libraryref work_library0_1))) + (property x_core_info (string "axi_uartlite,Vivado 2017.4")) + ) + (instance axi_uart_inst_i_1 (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename bn_ascii_0__i_1 "bn_ascii[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bn_ascii_10__i_1 "bn_ascii[10]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bn_ascii_11__i_1 "bn_ascii[11]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance (rename bn_ascii_13__i_1 "bn_ascii[13]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename bn_ascii_14__i_1 "bn_ascii[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + ) + (instance (rename bn_ascii_16__i_1 "bn_ascii[16]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename bn_ascii_17__i_1 "bn_ascii[17]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename bn_ascii_18__i_1 "bn_ascii[18]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bn_ascii_19__i_1 "bn_ascii[19]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bn_ascii_1__i_1 "bn_ascii[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bn_ascii_21__i_1 "bn_ascii[21]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bn_ascii_22__i_1 "bn_ascii[22]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bn_ascii_24__i_1 "bn_ascii[24]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bn_ascii_25__i_1 "bn_ascii[25]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bn_ascii_26__i_1 "bn_ascii[26]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bn_ascii_27__i_1 "bn_ascii[27]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bn_ascii_29__i_1 "bn_ascii[29]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bn_ascii_2__i_1 "bn_ascii[2]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bn_ascii_30__i_1 "bn_ascii[30]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bn_ascii_32__i_1 "bn_ascii[32]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bn_ascii_33__i_1 "bn_ascii[33]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bn_ascii_34__i_1 "bn_ascii[34]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bn_ascii_35__i_1 "bn_ascii[35]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bn_ascii_37__i_1 "bn_ascii[37]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bn_ascii_38__i_1 "bn_ascii[38]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bn_ascii_3__i_1 "bn_ascii[3]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bn_ascii_40__i_1 "bn_ascii[40]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bn_ascii_41__i_1 "bn_ascii[41]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bn_ascii_42__i_1 "bn_ascii[42]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bn_ascii_43__i_1 "bn_ascii[43]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bn_ascii_45__i_1 "bn_ascii[45]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bn_ascii_46__i_1 "bn_ascii[46]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bn_ascii_48__i_1 "bn_ascii[48]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bn_ascii_49__i_1 "bn_ascii[49]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bn_ascii_50__i_1 "bn_ascii[50]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bn_ascii_51__i_1 "bn_ascii[51]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bn_ascii_53__i_1 "bn_ascii[53]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bn_ascii_54__i_1 "bn_ascii[54]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bn_ascii_56__i_1 "bn_ascii[56]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bn_ascii_57__i_1 "bn_ascii[57]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bn_ascii_58__i_1 "bn_ascii[58]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCC8C")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bn_ascii_59__i_1 "bn_ascii[59]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bn_ascii_5__i_1 "bn_ascii[5]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bn_ascii_61__i_1 "bn_ascii[61]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h1F")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bn_ascii_62__i_1 "bn_ascii[62]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename bn_ascii_62__i_2 "bn_ascii[62]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bn_ascii_6__i_1 "bn_ascii[6]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hA8")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bn_ascii_8__i_1 "bn_ascii[8]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h56AA")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename bn_ascii_9__i_1 "bn_ascii[9]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBB40")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bn_ascii_reg_0_ "bn_ascii_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_10_ "bn_ascii_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_11_ "bn_ascii_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_13_ "bn_ascii_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_14_ "bn_ascii_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_16_ "bn_ascii_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_17_ "bn_ascii_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_18_ "bn_ascii_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_19_ "bn_ascii_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_1_ "bn_ascii_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_21_ "bn_ascii_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_22_ "bn_ascii_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_24_ "bn_ascii_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_25_ "bn_ascii_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_26_ "bn_ascii_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_27_ "bn_ascii_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_29_ "bn_ascii_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_2_ "bn_ascii_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_30_ "bn_ascii_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_32_ "bn_ascii_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_33_ "bn_ascii_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_34_ "bn_ascii_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_35_ "bn_ascii_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_37_ "bn_ascii_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_38_ "bn_ascii_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_3_ "bn_ascii_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_40_ "bn_ascii_reg[40]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_41_ "bn_ascii_reg[41]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_42_ "bn_ascii_reg[42]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_43_ "bn_ascii_reg[43]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_45_ "bn_ascii_reg[45]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_46_ "bn_ascii_reg[46]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_48_ "bn_ascii_reg[48]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_49_ "bn_ascii_reg[49]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_50_ "bn_ascii_reg[50]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_51_ "bn_ascii_reg[51]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_53_ "bn_ascii_reg[53]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_54_ "bn_ascii_reg[54]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_56_ "bn_ascii_reg[56]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_57_ "bn_ascii_reg[57]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_58_ "bn_ascii_reg[58]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_59_ "bn_ascii_reg[59]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_5_ "bn_ascii_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_61_ "bn_ascii_reg[61]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_62_ "bn_ascii_reg[62]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_6_ "bn_ascii_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_8_ "bn_ascii_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bn_ascii_reg_9_ "bn_ascii_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_0__i_1 "byte_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename byte_cnt_31__i_1 "byte_cnt[31]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0040")) + ) + (instance (rename byte_cnt_reg_0_ "byte_cnt_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_10_ "byte_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_11_ "byte_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_12_ "byte_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_12__i_1 "byte_cnt_reg[12]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_13_ "byte_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_14_ "byte_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_15_ "byte_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_16_ "byte_cnt_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_16__i_1 "byte_cnt_reg[16]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_17_ "byte_cnt_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_18_ "byte_cnt_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_19_ "byte_cnt_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_1_ "byte_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_20_ "byte_cnt_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_20__i_1 "byte_cnt_reg[20]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_21_ "byte_cnt_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_22_ "byte_cnt_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_23_ "byte_cnt_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_24_ "byte_cnt_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_24__i_1 "byte_cnt_reg[24]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_25_ "byte_cnt_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_26_ "byte_cnt_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_27_ "byte_cnt_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_28_ "byte_cnt_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_28__i_1 "byte_cnt_reg[28]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_29_ "byte_cnt_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_2_ "byte_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_30_ "byte_cnt_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_31_ "byte_cnt_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_31__i_2 "byte_cnt_reg[31]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_3_ "byte_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_4_ "byte_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_4__i_1 "byte_cnt_reg[4]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_5_ "byte_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_6_ "byte_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_7_ "byte_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_8_ "byte_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_cnt_reg_8__i_1 "byte_cnt_reg[8]_i_1") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename byte_cnt_reg_9_ "byte_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_7__i_1 "byte_len[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + ) + (instance (rename byte_len_reg_0_ "byte_len_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_1_ "byte_len_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_2_ "byte_len_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_3_ "byte_len_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_4_ "byte_len_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_5_ "byte_len_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_6_ "byte_len_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_len_reg_7_ "byte_len_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_31__i_1 "byte_num[31]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h08")) + ) + (instance (rename byte_num_reg_0_ "byte_num_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_10_ "byte_num_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_11_ "byte_num_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_12_ "byte_num_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_13_ "byte_num_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_14_ "byte_num_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_15_ "byte_num_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_16_ "byte_num_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_17_ "byte_num_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_18_ "byte_num_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_19_ "byte_num_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_1_ "byte_num_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_20_ "byte_num_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_21_ "byte_num_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_22_ "byte_num_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_23_ "byte_num_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_24_ "byte_num_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_25_ "byte_num_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_26_ "byte_num_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_27_ "byte_num_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_28_ "byte_num_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_29_ "byte_num_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_2_ "byte_num_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_30_ "byte_num_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_31_ "byte_num_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_3_ "byte_num_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_4_ "byte_num_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_5_ "byte_num_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_6_ "byte_num_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_7_ "byte_num_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_8_ "byte_num_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename byte_num_reg_9_ "byte_num_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_0_ "dbuf_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_10_ "dbuf_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_11_ "dbuf_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_12_ "dbuf_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_13_ "dbuf_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_14_ "dbuf_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_15_ "dbuf_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_16_ "dbuf_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_17_ "dbuf_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_18_ "dbuf_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_19_ "dbuf_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_1_ "dbuf_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_20_ "dbuf_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_21_ "dbuf_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_22_ "dbuf_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_23_ "dbuf_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_2_ "dbuf_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_3_ "dbuf_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_4_ "dbuf_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_5_ "dbuf_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_6_ "dbuf_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_7_ "dbuf_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_8_ "dbuf_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename dbuf_reg_9_ "dbuf_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_0__i_1 "disp[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h5595")) + ) + (instance (rename disp_1__i_1 "disp[1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h55556555")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename disp_1__i_2 "disp[1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFEFF0000EFFFFFFF")) + ) + (instance (rename disp_1__i_3 "disp[1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000FF00FFFFEFFF")) + ) + (instance (rename disp_2__i_1 "disp[2]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h82882222")) + ) + (instance (rename disp_2__i_2 "disp[2]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFEFFF")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename disp_3__i_1 "disp[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF0000007F807F80")) + ) + (instance (rename disp_3__i_2 "disp[3]_i_2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h00A2")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename disp_4__i_1 "disp[4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF0000007F807F80")) + ) + (instance (rename disp_5__i_1 "disp[5]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00000000BFFF4000")) + ) + (instance (rename disp_5__i_2 "disp[5]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hB")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename disp_5__i_3 "disp[5]_i_3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h20220000")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename disp_5__i_4 "disp[5]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename disp_6__i_1 "disp[6]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hB000B00000F0B000")) + ) + (instance (rename disp_6__i_2 "disp[6]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFDFFFF")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename disp_6__i_3 "disp[6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF7F7F7F7F7F7D7F7")) + ) + (instance (rename disp_7__i_1 "disp[7]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hD02FD0D0D0D0D0D0")) + ) + (instance (rename disp_7__i_2 "disp[7]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFDFFFFFFFFFFFFFF")) + ) + (instance (rename disp_7__i_3 "disp[7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFAAEFFFFFFFFFFF")) + ) + (instance (rename disp_7__i_4 "disp[7]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename disp_reg_0_ "disp_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_1_ "disp_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_2_ "disp_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_3_ "disp_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_4_ "disp_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_5_ "disp_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_6_ "disp_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename disp_reg_7_ "disp_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance initFlag_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hAAAE")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance initFlag_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_0__i_1 "len_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename len_cnt_1__i_1 "len_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename len_cnt_2__i_1 "len_cnt[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h6A")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename len_cnt_3__i_1 "len_cnt[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h6AAA")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename len_cnt_reg_0_ "len_cnt_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_reg_1_ "len_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_reg_2_ "len_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename len_cnt_reg_3_ "len_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_0__i_1 "msg_indx[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename msg_indx_1__i_1 "msg_indx[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename msg_indx_2__i_1 "msg_indx[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h6A")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename msg_indx_3__i_1 "msg_indx[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h6AAA")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename msg_indx_4__i_1 "msg_indx[4]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h6AAAAAAA")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename msg_indx_5__i_1 "msg_indx[5]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h6AAAAAAAAAAAAAAA")) + ) + (instance (rename msg_indx_6__i_1 "msg_indx[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename msg_indx_7__i_1 "msg_indx[7]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + ) + (instance (rename msg_indx_7__i_2 "msg_indx[7]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h6A")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename msg_indx_7__i_3 "msg_indx[7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h8000000000000000")) + ) + (instance (rename msg_indx_reg_0_ "msg_indx_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_1_ "msg_indx_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_2_ "msg_indx_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_3_ "msg_indx_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_4_ "msg_indx_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_5_ "msg_indx_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_6_ "msg_indx_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename msg_indx_reg_7_ "msg_indx_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance oldInitF_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF0200")) + ) + (instance oldInitF_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rdStat_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives)))) + (instance rdStat_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF708F708FF00FF0A")) + ) + (instance rdStat_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance recv_done_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF2000")) + ) + (instance recv_done_i_10 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_11 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_13 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_14 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_15 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_16 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_17 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_18 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_19 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_20 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_22 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_23 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_24 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_25 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_26 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_27 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_28 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_29 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_30 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_31 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_32 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_33 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h222B")) + ) + (instance recv_done_i_34 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_35 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_36 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_37 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h6006")) + ) + (instance recv_done_i_4 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_5 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_6 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_7 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h22B2")) + ) + (instance recv_done_i_8 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_i_9 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h9009")) + ) + (instance recv_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance recv_done_reg_i_12 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance recv_done_reg_i_2 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance recv_done_reg_i_21 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance recv_done_reg_i_3 (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_0__i_1 "rwait_cnt[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance (rename rwait_cnt_10__i_1 "rwait_cnt[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename rwait_cnt_11__i_1 "rwait_cnt[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename rwait_cnt_12__i_1 "rwait_cnt[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename rwait_cnt_13__i_1 "rwait_cnt[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename rwait_cnt_14__i_1 "rwait_cnt[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename rwait_cnt_15__i_1 "rwait_cnt[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h10")) + ) + (instance (rename rwait_cnt_15__i_2 "rwait_cnt[15]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename rwait_cnt_15__i_4 "rwait_cnt[15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000004000")) + ) + (instance (rename rwait_cnt_15__i_5 "rwait_cnt[15]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFD")) + ) + (instance (rename rwait_cnt_15__i_6 "rwait_cnt[15]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFBFF")) + ) + (instance (rename rwait_cnt_15__i_7 "rwait_cnt[15]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFEF")) + ) + (instance (rename rwait_cnt_1__i_1 "rwait_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename rwait_cnt_2__i_1 "rwait_cnt[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename rwait_cnt_3__i_1 "rwait_cnt[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename rwait_cnt_4__i_1 "rwait_cnt[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename rwait_cnt_5__i_1 "rwait_cnt[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename rwait_cnt_6__i_1 "rwait_cnt[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename rwait_cnt_7__i_1 "rwait_cnt[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename rwait_cnt_8__i_1 "rwait_cnt[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename rwait_cnt_9__i_1 "rwait_cnt[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename rwait_cnt_reg_0_ "rwait_cnt_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename rwait_cnt_reg_10_ "rwait_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_11_ "rwait_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_12_ "rwait_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_12__i_2 "rwait_cnt_reg[12]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_13_ "rwait_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_14_ "rwait_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_15_ "rwait_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_15__i_3 "rwait_cnt_reg[15]_i_3") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_1_ "rwait_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_2_ "rwait_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_3_ "rwait_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_4_ "rwait_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_4__i_2 "rwait_cnt_reg[4]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_5_ "rwait_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_6_ "rwait_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_7_ "rwait_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_8_ "rwait_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rwait_cnt_reg_8__i_2 "rwait_cnt_reg[8]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename rwait_cnt_reg_9_ "rwait_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance rx_done_i_1 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h38")) + ) + (instance rx_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_araddr_3__i_1 "s_axi_araddr[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFE00000002")) + ) + (instance (rename s_axi_araddr_reg_3_ "s_axi_araddr_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_arvalid_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF7373000C4040")) + ) + (instance s_axi_arvalid_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance s_axi_arvalid_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance s_axi_arvalid_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_awaddr_3__i_1 "s_axi_awaddr[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFD00000001")) + ) + (instance (rename s_axi_awaddr_reg_3_ "s_axi_awaddr_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance s_axi_awvalid_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFF558A00")) + ) + (instance s_axi_awvalid_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000F0008000F")) + ) + (instance s_axi_awvalid_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_0__i_1 "s_axi_wdata[0]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h20AA2020AAAAAAAA")) + ) + (instance (rename s_axi_wdata_0__i_2 "s_axi_wdata[0]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000004B560AB000")) + ) + (instance (rename s_axi_wdata_0__i_3 "s_axi_wdata[0]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hABEFABEFABEF0000")) + ) + (instance (rename s_axi_wdata_0__i_4 "s_axi_wdata[0]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000037F7FFFF37F7")) + ) + (instance (rename s_axi_wdata_0__i_5 "s_axi_wdata[0]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAFA0CFCFAFA0C0C0")) + ) + (instance (rename s_axi_wdata_1__i_1 "s_axi_wdata[1]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h20AA2020AAAAAAAA")) + ) + (instance (rename s_axi_wdata_1__i_2 "s_axi_wdata[1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000F008800441500")) + ) + (instance (rename s_axi_wdata_1__i_3 "s_axi_wdata[1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hABEFABEFABEF0000")) + ) + (instance (rename s_axi_wdata_1__i_4 "s_axi_wdata[1]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename s_axi_wdata_1__i_5 "s_axi_wdata[1]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF000057F757F7")) + ) + (instance (rename s_axi_wdata_1__i_6 "s_axi_wdata[1]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h05F5030305F5F3F3")) + ) + (instance (rename s_axi_wdata_2__i_1 "s_axi_wdata[2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h4F4F4FFF44444444")) + ) + (instance (rename s_axi_wdata_2__i_2 "s_axi_wdata[2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00000047C6526000")) + ) + (instance (rename s_axi_wdata_2__i_3 "s_axi_wdata[2]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFF4FFF7FFFFFFFF")) + ) + (instance (rename s_axi_wdata_2__i_4 "s_axi_wdata[2]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000037F7FFFF37F7")) + ) + (instance (rename s_axi_wdata_2__i_5 "s_axi_wdata[2]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAFA0CFCFAFA0C0C0")) + ) + (instance (rename s_axi_wdata_3__i_1 "s_axi_wdata[3]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h4F4F4FFF44444444")) + ) + (instance (rename s_axi_wdata_3__i_2 "s_axi_wdata[3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000046431202")) + ) + (instance (rename s_axi_wdata_3__i_3 "s_axi_wdata[3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFF35FFFFFFFF")) + ) + (instance (rename s_axi_wdata_3__i_4 "s_axi_wdata[3]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000037F7FFFF37F7")) + ) + (instance (rename s_axi_wdata_3__i_5 "s_axi_wdata[3]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAFA0CFCFAFA0C0C0")) + ) + (instance (rename s_axi_wdata_4__i_1 "s_axi_wdata[4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0100010101010101")) + ) + (instance (rename s_axi_wdata_4__i_2 "s_axi_wdata[4]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hAA20AAAA")) + ) + (instance (rename s_axi_wdata_4__i_3 "s_axi_wdata[4]_i_3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h54")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename s_axi_wdata_4__i_4 "s_axi_wdata[4]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h02A8")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename s_axi_wdata_4__i_5 "s_axi_wdata[4]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000009D584FF")) + ) + (instance (rename s_axi_wdata_4__i_6 "s_axi_wdata[4]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88888888AAA888A8")) + ) + (instance (rename s_axi_wdata_4__i_7 "s_axi_wdata[4]_i_7") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h45")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename s_axi_wdata_4__i_8 "s_axi_wdata[4]_i_8") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFD")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename s_axi_wdata_5__i_1 "s_axi_wdata[5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFF4F4444")) + ) + (instance (rename s_axi_wdata_5__i_2 "s_axi_wdata[5]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000FFF7FFFFF")) + ) + (instance (rename s_axi_wdata_5__i_3 "s_axi_wdata[5]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFF35FFFFFFFF")) + ) + (instance (rename s_axi_wdata_5__i_4 "s_axi_wdata[5]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0455")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename s_axi_wdata_5__i_5 "s_axi_wdata[5]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h05F5030305F5F3F3")) + ) + (instance (rename s_axi_wdata_5__i_6 "s_axi_wdata[5]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF47FF")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename s_axi_wdata_6__i_1 "s_axi_wdata[6]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00010101")) + ) + (instance (rename s_axi_wdata_6__i_2 "s_axi_wdata[6]_i_2") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h3A3A3A0A")) + ) + (instance (rename s_axi_wdata_6__i_3 "s_axi_wdata[6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00DF00F8009E0704")) + ) + (instance (rename s_axi_wdata_6__i_4 "s_axi_wdata[6]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000005300000000")) + ) + (instance (rename s_axi_wdata_6__i_5 "s_axi_wdata[6]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h00000000AAAAFEAE")) + ) + (instance (rename s_axi_wdata_6__i_6 "s_axi_wdata[6]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h8A80FFFF")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename s_axi_wdata_6__i_7 "s_axi_wdata[6]_i_7") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00103010")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename s_axi_wdata_reg_0_ "s_axi_wdata_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_1_ "s_axi_wdata_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_2_ "s_axi_wdata_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_3_ "s_axi_wdata_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_4_ "s_axi_wdata_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_5_ "s_axi_wdata_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wdata_reg_6_ "s_axi_wdata_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename s_axi_wstrb_3__i_1 "s_axi_wstrb[3]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h2220AAAA")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename s_axi_wstrb_reg_3_ "s_axi_wstrb_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename statReg_0__i_1 "statReg[0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFBF0080")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename statReg_0__i_2 "statReg[0]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename statReg_reg_0_ "statReg_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_7__i_1 "uart_rdat[7]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000080")) + ) + (instance (rename uart_rdat_reg_0_ "uart_rdat_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_1_ "uart_rdat_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_2_ "uart_rdat_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_3_ "uart_rdat_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_4_ "uart_rdat_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_5_ "uart_rdat_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_6_ "uart_rdat_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename uart_rdat_reg_7_ "uart_rdat_reg[7]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance uart_wen_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFEF00000020")) + ) + (instance uart_wen_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_14__i_1 "upg_adr_o[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + ) + (instance (rename upg_adr_o_OBUF_0__inst "upg_adr_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_10__inst "upg_adr_o_OBUF[10]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_11__inst "upg_adr_o_OBUF[11]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_12__inst "upg_adr_o_OBUF[12]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_13__inst "upg_adr_o_OBUF[13]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_14__inst "upg_adr_o_OBUF[14]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_1__inst "upg_adr_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_2__inst "upg_adr_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_3__inst "upg_adr_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_4__inst "upg_adr_o_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_5__inst "upg_adr_o_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_6__inst "upg_adr_o_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_7__inst "upg_adr_o_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_8__inst "upg_adr_o_OBUF[8]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_OBUF_9__inst "upg_adr_o_OBUF[9]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_adr_o_reg_0_ "upg_adr_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_10_ "upg_adr_o_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_11_ "upg_adr_o_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_12_ "upg_adr_o_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_13_ "upg_adr_o_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_14_ "upg_adr_o_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_1_ "upg_adr_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_2_ "upg_adr_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_3_ "upg_adr_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_4_ "upg_adr_o_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_5_ "upg_adr_o_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_6_ "upg_adr_o_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_7_ "upg_adr_o_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_8_ "upg_adr_o_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_adr_o_reg_9_ "upg_adr_o_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance upg_clk_i_IBUF_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives)))) + (instance upg_clk_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) + (instance upg_clk_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_clk_o_OBUF_inst_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFB")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance upg_clk_o_OBUF_inst_i_2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance (rename upg_dat_o_OBUF_0__inst "upg_dat_o_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_10__inst "upg_dat_o_OBUF[10]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_11__inst "upg_dat_o_OBUF[11]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_12__inst "upg_dat_o_OBUF[12]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_13__inst "upg_dat_o_OBUF[13]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_14__inst "upg_dat_o_OBUF[14]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_15__inst "upg_dat_o_OBUF[15]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_16__inst "upg_dat_o_OBUF[16]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_17__inst "upg_dat_o_OBUF[17]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_18__inst "upg_dat_o_OBUF[18]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_19__inst "upg_dat_o_OBUF[19]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_1__inst "upg_dat_o_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_20__inst "upg_dat_o_OBUF[20]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_21__inst "upg_dat_o_OBUF[21]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_22__inst "upg_dat_o_OBUF[22]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_23__inst "upg_dat_o_OBUF[23]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_24__inst "upg_dat_o_OBUF[24]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_25__inst "upg_dat_o_OBUF[25]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_26__inst "upg_dat_o_OBUF[26]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_27__inst "upg_dat_o_OBUF[27]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_28__inst "upg_dat_o_OBUF[28]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_29__inst "upg_dat_o_OBUF[29]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_2__inst "upg_dat_o_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_30__inst "upg_dat_o_OBUF[30]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_31__inst "upg_dat_o_OBUF[31]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_3__inst "upg_dat_o_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_4__inst "upg_dat_o_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_5__inst "upg_dat_o_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_6__inst "upg_dat_o_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_7__inst "upg_dat_o_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_8__inst "upg_dat_o_OBUF[8]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_OBUF_9__inst "upg_dat_o_OBUF[9]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance (rename upg_dat_o_reg_0_ "upg_dat_o_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_10_ "upg_dat_o_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_11_ "upg_dat_o_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_12_ "upg_dat_o_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_13_ "upg_dat_o_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_14_ "upg_dat_o_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_15_ "upg_dat_o_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_16_ "upg_dat_o_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_17_ "upg_dat_o_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_18_ "upg_dat_o_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_19_ "upg_dat_o_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_1_ "upg_dat_o_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_20_ "upg_dat_o_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_21_ "upg_dat_o_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_22_ "upg_dat_o_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_23_ "upg_dat_o_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_24_ "upg_dat_o_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_25_ "upg_dat_o_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_26_ "upg_dat_o_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_27_ "upg_dat_o_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_28_ "upg_dat_o_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_29_ "upg_dat_o_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_2_ "upg_dat_o_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_30_ "upg_dat_o_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_31_ "upg_dat_o_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_3_ "upg_dat_o_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_4_ "upg_dat_o_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_5_ "upg_dat_o_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_6_ "upg_dat_o_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_7_ "upg_dat_o_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_8_ "upg_dat_o_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename upg_dat_o_reg_9_ "upg_dat_o_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance upg_done_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_done_o_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + ) + (instance upg_done_o_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFEFEFEFEFEEEEEEE")) + ) + (instance upg_done_o_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance upg_done_o_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance upg_rst_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) + (instance upg_rx_i_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives)))) + (instance upg_tx_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_wen_o_OBUF_inst (viewref netlist (cellref OBUF (libraryref hdi_primitives)))) + (instance upg_wen_o_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hAAAB")) + ) + (instance upg_wen_o_i_2 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance upg_wen_o_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h0000AAA8")) + ) + (instance upg_wen_o_i_4 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFBBB0")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance upg_wen_o_i_5 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000002800000000")) + ) + (instance upg_wen_o_i_6 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFF00FFFFFE00FEFE")) + ) + (instance upg_wen_o_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance wr_byte_len_done_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h5555555555555554")) + ) + (instance wr_byte_len_done_i_2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance wr_byte_len_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance wr_byte_num_done_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000000006AAA9555")) + ) + (instance wr_byte_num_done_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFF96F6FF6")) + ) + (instance wr_byte_num_done_i_3 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFEFFFEFFFF")) + ) + (instance wr_byte_num_done_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_0__i_1 "wwait_cnt[0]_i_1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename wwait_cnt_10__i_1 "wwait_cnt[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename wwait_cnt_11__i_1 "wwait_cnt[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename wwait_cnt_12__i_1 "wwait_cnt[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename wwait_cnt_13__i_1 "wwait_cnt[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename wwait_cnt_14__i_1 "wwait_cnt[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename wwait_cnt_15__i_1 "wwait_cnt[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h10")) + ) + (instance (rename wwait_cnt_15__i_2 "wwait_cnt[15]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename wwait_cnt_15__i_4 "wwait_cnt[15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000040000000")) + ) + (instance (rename wwait_cnt_15__i_5 "wwait_cnt[15]_i_5") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h7FFF")) + ) + (instance (rename wwait_cnt_15__i_6 "wwait_cnt[15]_i_6") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename wwait_cnt_15__i_7 "wwait_cnt[15]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename wwait_cnt_1__i_1 "wwait_cnt[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename wwait_cnt_2__i_1 "wwait_cnt[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename wwait_cnt_3__i_1 "wwait_cnt[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename wwait_cnt_4__i_1 "wwait_cnt[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename wwait_cnt_5__i_1 "wwait_cnt[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename wwait_cnt_6__i_1 "wwait_cnt[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename wwait_cnt_7__i_1 "wwait_cnt[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename wwait_cnt_8__i_1 "wwait_cnt[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename wwait_cnt_9__i_1 "wwait_cnt[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename wwait_cnt_reg_0_ "wwait_cnt_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename wwait_cnt_reg_10_ "wwait_cnt_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_11_ "wwait_cnt_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_12_ "wwait_cnt_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_12__i_2 "wwait_cnt_reg[12]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_13_ "wwait_cnt_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_14_ "wwait_cnt_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_15_ "wwait_cnt_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_15__i_3 "wwait_cnt_reg[15]_i_3") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_1_ "wwait_cnt_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_2_ "wwait_cnt_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_3_ "wwait_cnt_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_4_ "wwait_cnt_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_4__i_2 "wwait_cnt_reg[4]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_5_ "wwait_cnt_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_6_ "wwait_cnt_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_7_ "wwait_cnt_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_8_ "wwait_cnt_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename wwait_cnt_reg_8__i_2 "wwait_cnt_reg[8]_i_2") (viewref netlist (cellref CARRY4 (libraryref hdi_primitives)))) + (instance (rename wwait_cnt_reg_9_ "wwait_cnt_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref CI (instanceref byte_cnt_reg_4__i_1)) + (portref CI (instanceref recv_done_reg_i_21)) + (portref CI (instanceref rwait_cnt_reg_4__i_2)) + (portref CI (instanceref wwait_cnt_reg_4__i_2)) + (portref CYINIT (instanceref byte_cnt_reg_12__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_16__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_20__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_24__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_28__i_1)) + (portref CYINIT (instanceref byte_cnt_reg_31__i_2)) + (portref CYINIT (instanceref byte_cnt_reg_8__i_1)) + (portref CYINIT (instanceref recv_done_reg_i_12)) + (portref CYINIT (instanceref recv_done_reg_i_2)) + (portref CYINIT (instanceref recv_done_reg_i_3)) + (portref CYINIT (instanceref rwait_cnt_reg_12__i_2)) + (portref CYINIT (instanceref rwait_cnt_reg_15__i_3)) + (portref CYINIT (instanceref rwait_cnt_reg_8__i_2)) + (portref CYINIT (instanceref wwait_cnt_reg_12__i_2)) + (portref CYINIT (instanceref wwait_cnt_reg_15__i_3)) + (portref CYINIT (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 3) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 3) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 3) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 3) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 3) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 3) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 3) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 3) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 3) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 3) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 3) (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 2) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 2) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 2) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 2) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 2) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 2) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 2) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 2) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 2) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 2) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 2) (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 1) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 1) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 1) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 1) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 1) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 1) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 1) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 1) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 1) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 1) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 1) (instanceref wwait_cnt_reg_8__i_2)) + (portref (member DI 0) (instanceref byte_cnt_reg_12__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_16__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_20__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_24__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_28__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_31__i_2)) + (portref (member DI 0) (instanceref byte_cnt_reg_4__i_1)) + (portref (member DI 0) (instanceref byte_cnt_reg_8__i_1)) + (portref (member DI 0) (instanceref rwait_cnt_reg_12__i_2)) + (portref (member DI 0) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member DI 0) (instanceref rwait_cnt_reg_4__i_2)) + (portref (member DI 0) (instanceref rwait_cnt_reg_8__i_2)) + (portref (member DI 0) (instanceref wwait_cnt_reg_12__i_2)) + (portref (member DI 0) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member DI 0) (instanceref wwait_cnt_reg_4__i_2)) + (portref (member DI 0) (instanceref wwait_cnt_reg_8__i_2)) + (portref G (instanceref GND)) + (portref R (instanceref s_axi_araddr_reg_3_)) + (portref R (instanceref s_axi_arvalid_reg)) + (portref R (instanceref s_axi_awaddr_reg_3_)) + (portref R (instanceref s_axi_awvalid_reg)) + (portref R (instanceref s_axi_wdata_reg_0_)) + (portref R (instanceref s_axi_wdata_reg_1_)) + (portref R (instanceref s_axi_wdata_reg_4_)) + (portref R (instanceref s_axi_wstrb_reg_3_)) + (portref R (instanceref uart_rdat_reg_0_)) + (portref R (instanceref uart_rdat_reg_1_)) + (portref R (instanceref uart_rdat_reg_2_)) + (portref R (instanceref uart_rdat_reg_3_)) + (portref R (instanceref uart_rdat_reg_4_)) + (portref R (instanceref uart_rdat_reg_5_)) + (portref R (instanceref uart_rdat_reg_6_)) + (portref R (instanceref uart_rdat_reg_7_)) + (portref (member S 0) (instanceref byte_cnt_reg_31__i_2)) + (portref (member S 0) (instanceref rwait_cnt_reg_15__i_3)) + (portref (member S 0) (instanceref wwait_cnt_reg_15__i_3)) + (portref (member s_axi_araddr 3) (instanceref axi_uart_inst)) + (portref (member s_axi_araddr 2) (instanceref axi_uart_inst)) + (portref (member s_axi_araddr 1) (instanceref axi_uart_inst)) + (portref (member s_axi_awaddr 3) (instanceref axi_uart_inst)) + (portref (member s_axi_awaddr 2) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 21) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 20) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 19) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 18) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 17) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 16) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 15) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 14) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 13) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 12) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 11) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 10) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 9) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 8) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 7) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 6) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 5) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 4) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 3) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 2) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 1) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 0) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 24) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 23) (instanceref axi_uart_inst)) + (portref (member s_axi_wdata 22) (instanceref axi_uart_inst)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref RCS_reg_0_)) + (portref CE (instanceref RCS_reg_1_)) + (portref CE (instanceref RCS_reg_2_)) + (portref CE (instanceref WCS_reg_0_)) + (portref CE (instanceref WCS_reg_1_)) + (portref CE (instanceref WCS_reg_2_)) + (portref CE (instanceref initFlag_reg)) + (portref CE (instanceref oldInitF_reg)) + (portref CE (instanceref rdStat_reg)) + (portref CE (instanceref recv_done_reg)) + (portref CE (instanceref rx_done_reg)) + (portref CE (instanceref s_axi_araddr_reg_3_)) + (portref CE (instanceref s_axi_arvalid_reg)) + (portref CE (instanceref s_axi_awaddr_reg_3_)) + (portref CE (instanceref s_axi_awvalid_reg)) + (portref CE (instanceref statReg_reg_0_)) + (portref CE (instanceref uart_wen_reg)) + (portref CYINIT (instanceref recv_done_reg_i_21)) + (portref P (instanceref VCC)) + (portref (member s_axi_awaddr 1) (instanceref axi_uart_inst)) + (portref s_axi_bready (instanceref axi_uart_inst)) + (portref s_axi_rready (instanceref axi_uart_inst)) + ) + ) + (net (rename RCS_0__i_1_n_0 "RCS[0]_i_1_n_0") (joined + (portref D (instanceref RCS_reg_0_)) + (portref O (instanceref RCS_0__i_1)) + ) + ) + (net (rename RCS_1__i_1_n_0 "RCS[1]_i_1_n_0") (joined + (portref D (instanceref RCS_reg_1_)) + (portref O (instanceref RCS_1__i_1)) + ) + ) + (net (rename RCS_2__i_1_n_0 "RCS[2]_i_1_n_0") (joined + (portref D (instanceref RCS_reg_2_)) + (portref O (instanceref RCS_2__i_1)) + ) + ) + (net (rename RCS_reg_n_0__0_ "RCS_reg_n_0_[0]") (joined + (portref I0 (instanceref rdStat_i_1)) + (portref I0 (instanceref statReg_0__i_2)) + (portref I1 (instanceref rwait_cnt_15__i_1)) + (portref I2 (instanceref uart_rdat_7__i_1)) + (portref I3 (instanceref RCS_0__i_1)) + (portref I3 (instanceref RCS_2__i_1)) + (portref I4 (instanceref RCS_1__i_1)) + (portref I4 (instanceref s_axi_araddr_3__i_1)) + (portref I4 (instanceref s_axi_arvalid_i_1)) + (portref Q (instanceref RCS_reg_0_)) + ) + ) + (net (rename RCS_reg_n_0__1_ "RCS_reg_n_0_[1]") (joined + (portref I0 (instanceref rwait_cnt_15__i_1)) + (portref I1 (instanceref statReg_0__i_2)) + (portref I1 (instanceref uart_rdat_7__i_1)) + (portref I2 (instanceref RCS_0__i_1)) + (portref I2 (instanceref RCS_2__i_1)) + (portref I2 (instanceref s_axi_arvalid_i_1)) + (portref I3 (instanceref RCS_1__i_1)) + (portref I3 (instanceref s_axi_araddr_3__i_1)) + (portref I5 (instanceref rdStat_i_1)) + (portref Q (instanceref RCS_reg_1_)) + ) + ) + (net (rename RCS_reg_n_0__2_ "RCS_reg_n_0_[2]") (joined + (portref I1 (instanceref s_axi_araddr_3__i_1)) + (portref I1 (instanceref s_axi_arvalid_i_2)) + (portref I2 (instanceref rdStat_i_1)) + (portref I2 (instanceref rwait_cnt_15__i_1)) + (portref I3 (instanceref statReg_0__i_1)) + (portref I4 (instanceref RCS_0__i_1)) + (portref I4 (instanceref RCS_2__i_1)) + (portref I4 (instanceref uart_rdat_7__i_1)) + (portref I5 (instanceref RCS_1__i_1)) + (portref Q (instanceref RCS_reg_2_)) + ) + ) + (net (rename WCS_0__i_1_n_0 "WCS[0]_i_1_n_0") (joined + (portref D (instanceref WCS_reg_0_)) + (portref O (instanceref WCS_0__i_1)) + ) + ) + (net (rename WCS_0__i_2_n_0 "WCS[0]_i_2_n_0") (joined + (portref I0 (instanceref WCS_0__i_1)) + (portref O (instanceref WCS_0__i_2)) + ) + ) + (net (rename WCS_1__i_1_n_0 "WCS[1]_i_1_n_0") (joined + (portref D (instanceref WCS_reg_1_)) + (portref O (instanceref WCS_1__i_1)) + ) + ) + (net (rename WCS_2__i_1_n_0 "WCS[2]_i_1_n_0") (joined + (portref D (instanceref WCS_reg_2_)) + (portref O (instanceref WCS_2__i_1)) + ) + ) + (net (rename WCS_2__i_2_n_0 "WCS[2]_i_2_n_0") (joined + (portref I1 (instanceref WCS_0__i_1)) + (portref I2 (instanceref WCS_2__i_1)) + (portref I3 (instanceref oldInitF_i_1)) + (portref O (instanceref WCS_2__i_2)) + ) + ) + (net (rename WCS_2__i_3_n_0 "WCS[2]_i_3_n_0") (joined + (portref I0 (instanceref WCS_2__i_2)) + (portref O (instanceref WCS_2__i_3)) + ) + ) + (net (rename WCS_2__i_4_n_0 "WCS[2]_i_4_n_0") (joined + (portref I5 (instanceref WCS_2__i_2)) + (portref O (instanceref WCS_2__i_4)) + ) + ) + (net (rename WCS_2__i_5_n_0 "WCS[2]_i_5_n_0") (joined + (portref I4 (instanceref WCS_2__i_4)) + (portref O (instanceref WCS_2__i_5)) + ) + ) + (net (rename WCS_reg_n_0__0_ "WCS_reg_n_0_[0]") (joined + (portref I0 (instanceref s_axi_wdata_0__i_1)) + (portref I0 (instanceref s_axi_wdata_1__i_1)) + (portref I0 (instanceref s_axi_wdata_4__i_2)) + (portref I0 (instanceref s_axi_wstrb_3__i_1)) + (portref I0 (instanceref wwait_cnt_15__i_1)) + (portref I1 (instanceref initFlag_i_1)) + (portref I1 (instanceref msg_indx_7__i_1)) + (portref I1 (instanceref upg_done_o_i_1)) + (portref I2 (instanceref oldInitF_i_1)) + (portref I2 (instanceref uart_wen_i_1)) + (portref I3 (instanceref s_axi_awaddr_3__i_1)) + (portref I3 (instanceref s_axi_awvalid_i_1)) + (portref I3 (instanceref s_axi_wdata_6__i_1)) + (portref I4 (instanceref WCS_0__i_1)) + (portref I4 (instanceref WCS_1__i_1)) + (portref I4 (instanceref WCS_2__i_1)) + (portref I5 (instanceref s_axi_awvalid_i_2)) + (portref I5 (instanceref s_axi_wdata_4__i_1)) + (portref Q (instanceref WCS_reg_0_)) + ) + ) + (net (rename WCS_reg_n_0__1_ "WCS_reg_n_0_[1]") (joined + (portref I0 (instanceref s_axi_wdata_4__i_1)) + (portref I1 (instanceref oldInitF_i_1)) + (portref I1 (instanceref wwait_cnt_15__i_1)) + (portref I2 (instanceref initFlag_i_1)) + (portref I2 (instanceref msg_indx_7__i_1)) + (portref I2 (instanceref s_axi_wdata_6__i_1)) + (portref I2 (instanceref upg_done_o_i_1)) + (portref I3 (instanceref uart_wen_i_1)) + (portref I4 (instanceref s_axi_awaddr_3__i_1)) + (portref I4 (instanceref s_axi_awvalid_i_2)) + (portref I5 (instanceref WCS_0__i_1)) + (portref I5 (instanceref WCS_1__i_1)) + (portref I5 (instanceref WCS_2__i_1)) + (portref Q (instanceref WCS_reg_1_)) + ) + ) + (net (rename WCS_reg_n_0__2_ "WCS_reg_n_0_[2]") (joined + (portref I0 (instanceref oldInitF_i_1)) + (portref I0 (instanceref s_axi_wdata_6__i_1)) + (portref I1 (instanceref s_axi_awaddr_3__i_1)) + (portref I2 (instanceref s_axi_wdata_4__i_1)) + (portref I2 (instanceref wwait_cnt_15__i_1)) + (portref I3 (instanceref WCS_0__i_1)) + (portref I3 (instanceref WCS_1__i_1)) + (portref I3 (instanceref WCS_2__i_1)) + (portref I3 (instanceref initFlag_i_1)) + (portref I3 (instanceref msg_indx_7__i_1)) + (portref I3 (instanceref s_axi_awvalid_i_2)) + (portref I3 (instanceref upg_done_o_i_1)) + (portref I4 (instanceref uart_wen_i_1)) + (portref Q (instanceref WCS_reg_2_)) + ) + ) + (net (rename bn_ascii_reg_n_0__0_ "bn_ascii_reg_n_0_[0]") (joined + (portref I2 (instanceref s_axi_wdata_0__i_3)) + (portref Q (instanceref bn_ascii_reg_0_)) + ) + ) + (net (rename bn_ascii_reg_n_0__1_ "bn_ascii_reg_n_0_[1]") (joined + (portref I2 (instanceref s_axi_wdata_1__i_3)) + (portref Q (instanceref bn_ascii_reg_1_)) + ) + ) + (net (rename bn_ascii_reg_n_0__2_ "bn_ascii_reg_n_0_[2]") (joined + (portref I0 (instanceref s_axi_wdata_2__i_3)) + (portref Q (instanceref bn_ascii_reg_2_)) + ) + ) + (net (rename bn_ascii_reg_n_0__3_ "bn_ascii_reg_n_0_[3]") (joined + (portref I1 (instanceref s_axi_wdata_3__i_3)) + (portref Q (instanceref bn_ascii_reg_3_)) + ) + ) + (net (rename bn_ascii_reg_n_0__48_ "bn_ascii_reg_n_0_[48]") (joined + (portref I3 (instanceref s_axi_wdata_0__i_4)) + (portref Q (instanceref bn_ascii_reg_48_)) + ) + ) + (net (rename bn_ascii_reg_n_0__49_ "bn_ascii_reg_n_0_[49]") (joined + (portref I3 (instanceref s_axi_wdata_1__i_5)) + (portref Q (instanceref bn_ascii_reg_49_)) + ) + ) + (net (rename bn_ascii_reg_n_0__50_ "bn_ascii_reg_n_0_[50]") (joined + (portref I3 (instanceref s_axi_wdata_2__i_4)) + (portref Q (instanceref bn_ascii_reg_50_)) + ) + ) + (net (rename bn_ascii_reg_n_0__51_ "bn_ascii_reg_n_0_[51]") (joined + (portref I3 (instanceref s_axi_wdata_3__i_4)) + (portref Q (instanceref bn_ascii_reg_51_)) + ) + ) + (net (rename bn_ascii_reg_n_0__53_ "bn_ascii_reg_n_0_[53]") (joined + (portref I0 (instanceref s_axi_wdata_5__i_6)) + (portref Q (instanceref bn_ascii_reg_53_)) + ) + ) + (net (rename bn_ascii_reg_n_0__54_ "bn_ascii_reg_n_0_[54]") (joined + (portref I4 (instanceref s_axi_wdata_6__i_7)) + (portref Q (instanceref bn_ascii_reg_54_)) + ) + ) + (net (rename bn_ascii_reg_n_0__56_ "bn_ascii_reg_n_0_[56]") (joined + (portref I0 (instanceref s_axi_wdata_0__i_4)) + (portref Q (instanceref bn_ascii_reg_56_)) + ) + ) + (net (rename bn_ascii_reg_n_0__57_ "bn_ascii_reg_n_0_[57]") (joined + (portref I1 (instanceref s_axi_wdata_1__i_5)) + (portref Q (instanceref bn_ascii_reg_57_)) + ) + ) + (net (rename bn_ascii_reg_n_0__58_ "bn_ascii_reg_n_0_[58]") (joined + (portref I0 (instanceref s_axi_wdata_2__i_4)) + (portref Q (instanceref bn_ascii_reg_58_)) + ) + ) + (net (rename bn_ascii_reg_n_0__59_ "bn_ascii_reg_n_0_[59]") (joined + (portref I0 (instanceref s_axi_wdata_3__i_4)) + (portref Q (instanceref bn_ascii_reg_59_)) + ) + ) + (net (rename bn_ascii_reg_n_0__5_ "bn_ascii_reg_n_0_[5]") (joined + (portref I1 (instanceref s_axi_wdata_5__i_3)) + (portref I2 (instanceref s_axi_wdata_4__i_6)) + (portref Q (instanceref bn_ascii_reg_5_)) + ) + ) + (net (rename bn_ascii_reg_n_0__61_ "bn_ascii_reg_n_0_[61]") (joined + (portref I2 (instanceref s_axi_wdata_5__i_6)) + (portref Q (instanceref bn_ascii_reg_61_)) + ) + ) + (net (rename bn_ascii_reg_n_0__62_ "bn_ascii_reg_n_0_[62]") (joined + (portref I0 (instanceref s_axi_wdata_6__i_7)) + (portref Q (instanceref bn_ascii_reg_62_)) + ) + ) + (net (rename bn_ascii_reg_n_0__6_ "bn_ascii_reg_n_0_[6]") (joined + (portref I0 (instanceref s_axi_wdata_6__i_4)) + (portref Q (instanceref bn_ascii_reg_6_)) + ) + ) + (net byte_cnt (joined + (portref CE (instanceref byte_cnt_reg_0_)) + (portref CE (instanceref byte_cnt_reg_10_)) + (portref CE (instanceref byte_cnt_reg_11_)) + (portref CE (instanceref byte_cnt_reg_12_)) + (portref CE (instanceref byte_cnt_reg_13_)) + (portref CE (instanceref byte_cnt_reg_14_)) + (portref CE (instanceref byte_cnt_reg_15_)) + (portref CE (instanceref byte_cnt_reg_16_)) + (portref CE (instanceref byte_cnt_reg_17_)) + (portref CE (instanceref byte_cnt_reg_18_)) + (portref CE (instanceref byte_cnt_reg_19_)) + (portref CE (instanceref byte_cnt_reg_1_)) + (portref CE (instanceref byte_cnt_reg_20_)) + (portref CE (instanceref byte_cnt_reg_21_)) + (portref CE (instanceref byte_cnt_reg_22_)) + (portref CE (instanceref byte_cnt_reg_23_)) + (portref CE (instanceref byte_cnt_reg_24_)) + (portref CE (instanceref byte_cnt_reg_25_)) + (portref CE (instanceref byte_cnt_reg_26_)) + (portref CE (instanceref byte_cnt_reg_27_)) + (portref CE (instanceref byte_cnt_reg_28_)) + (portref CE (instanceref byte_cnt_reg_29_)) + (portref CE (instanceref byte_cnt_reg_2_)) + (portref CE (instanceref byte_cnt_reg_30_)) + (portref CE (instanceref byte_cnt_reg_31_)) + (portref CE (instanceref byte_cnt_reg_3_)) + (portref CE (instanceref byte_cnt_reg_4_)) + (portref CE (instanceref byte_cnt_reg_5_)) + (portref CE (instanceref byte_cnt_reg_6_)) + (portref CE (instanceref byte_cnt_reg_7_)) + (portref CE (instanceref byte_cnt_reg_8_)) + (portref CE (instanceref byte_cnt_reg_9_)) + (portref CE (instanceref dbuf_reg_0_)) + (portref CE (instanceref dbuf_reg_10_)) + (portref CE (instanceref dbuf_reg_11_)) + (portref CE (instanceref dbuf_reg_12_)) + (portref CE (instanceref dbuf_reg_13_)) + (portref CE (instanceref dbuf_reg_14_)) + (portref CE (instanceref dbuf_reg_15_)) + (portref CE (instanceref dbuf_reg_16_)) + (portref CE (instanceref dbuf_reg_17_)) + (portref CE (instanceref dbuf_reg_18_)) + (portref CE (instanceref dbuf_reg_19_)) + (portref CE (instanceref dbuf_reg_1_)) + (portref CE (instanceref dbuf_reg_20_)) + (portref CE (instanceref dbuf_reg_21_)) + (portref CE (instanceref dbuf_reg_22_)) + (portref CE (instanceref dbuf_reg_23_)) + (portref CE (instanceref dbuf_reg_2_)) + (portref CE (instanceref dbuf_reg_3_)) + (portref CE (instanceref dbuf_reg_4_)) + (portref CE (instanceref dbuf_reg_5_)) + (portref CE (instanceref dbuf_reg_6_)) + (portref CE (instanceref dbuf_reg_7_)) + (portref CE (instanceref dbuf_reg_8_)) + (portref CE (instanceref dbuf_reg_9_)) + (portref O (instanceref byte_cnt_31__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_0 "byte_cnt_reg[12]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_16__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_1 "byte_cnt_reg[12]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_2 "byte_cnt_reg[12]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_12__i_1_n_3 "byte_cnt_reg[12]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_0 "byte_cnt_reg[16]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_20__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_1 "byte_cnt_reg[16]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_2 "byte_cnt_reg[16]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_16__i_1_n_3 "byte_cnt_reg[16]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_0 "byte_cnt_reg[20]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_24__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_1 "byte_cnt_reg[20]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_2 "byte_cnt_reg[20]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_20__i_1_n_3 "byte_cnt_reg[20]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_0 "byte_cnt_reg[24]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_28__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_1 "byte_cnt_reg[24]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_2 "byte_cnt_reg[24]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_24__i_1_n_3 "byte_cnt_reg[24]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_0 "byte_cnt_reg[28]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_31__i_2)) + (portref (member CO 0) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_1 "byte_cnt_reg[28]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_2 "byte_cnt_reg[28]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_28__i_1_n_3 "byte_cnt_reg[28]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_31__i_2_n_2 "byte_cnt_reg[31]_i_2_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_31__i_2_n_3 "byte_cnt_reg[31]_i_2_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_0 "byte_cnt_reg[4]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_8__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_1 "byte_cnt_reg[4]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_2 "byte_cnt_reg[4]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_4__i_1_n_3 "byte_cnt_reg[4]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_0 "byte_cnt_reg[8]_i_1_n_0") (joined + (portref CI (instanceref byte_cnt_reg_12__i_1)) + (portref (member CO 0) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_1 "byte_cnt_reg[8]_i_1_n_1") (joined + (portref (member CO 1) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_2 "byte_cnt_reg[8]_i_1_n_2") (joined + (portref (member CO 2) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_8__i_1_n_3 "byte_cnt_reg[8]_i_1_n_3") (joined + (portref (member CO 3) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__0_ "byte_cnt_reg_n_0_[0]") (joined + (portref CYINIT (instanceref byte_cnt_reg_4__i_1)) + (portref I0 (instanceref byte_cnt_0__i_1)) + (portref I1 (instanceref recv_done_i_37)) + (portref I2 (instanceref recv_done_i_33)) + (portref Q (instanceref byte_cnt_reg_0_)) + ) + ) + (net (rename byte_cnt_reg_n_0__17_ "byte_cnt_reg_n_0_[17]") (joined + (portref Q (instanceref byte_cnt_reg_17_)) + (portref (member S 3) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__18_ "byte_cnt_reg_n_0_[18]") (joined + (portref Q (instanceref byte_cnt_reg_18_)) + (portref (member S 2) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__19_ "byte_cnt_reg_n_0_[19]") (joined + (portref Q (instanceref byte_cnt_reg_19_)) + (portref (member S 1) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__1_ "byte_cnt_reg_n_0_[1]") (joined + (portref Q (instanceref byte_cnt_reg_1_)) + (portref (member S 3) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__20_ "byte_cnt_reg_n_0_[20]") (joined + (portref Q (instanceref byte_cnt_reg_20_)) + (portref (member S 0) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__21_ "byte_cnt_reg_n_0_[21]") (joined + (portref Q (instanceref byte_cnt_reg_21_)) + (portref (member S 3) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__22_ "byte_cnt_reg_n_0_[22]") (joined + (portref Q (instanceref byte_cnt_reg_22_)) + (portref (member S 2) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__23_ "byte_cnt_reg_n_0_[23]") (joined + (portref Q (instanceref byte_cnt_reg_23_)) + (portref (member S 1) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__24_ "byte_cnt_reg_n_0_[24]") (joined + (portref Q (instanceref byte_cnt_reg_24_)) + (portref (member S 0) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__25_ "byte_cnt_reg_n_0_[25]") (joined + (portref Q (instanceref byte_cnt_reg_25_)) + (portref (member S 3) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__26_ "byte_cnt_reg_n_0_[26]") (joined + (portref Q (instanceref byte_cnt_reg_26_)) + (portref (member S 2) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__27_ "byte_cnt_reg_n_0_[27]") (joined + (portref Q (instanceref byte_cnt_reg_27_)) + (portref (member S 1) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__28_ "byte_cnt_reg_n_0_[28]") (joined + (portref Q (instanceref byte_cnt_reg_28_)) + (portref (member S 0) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename byte_cnt_reg_n_0__29_ "byte_cnt_reg_n_0_[29]") (joined + (portref Q (instanceref byte_cnt_reg_29_)) + (portref (member S 3) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_n_0__30_ "byte_cnt_reg_n_0_[30]") (joined + (portref Q (instanceref byte_cnt_reg_30_)) + (portref (member S 2) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_cnt_reg_n_0__31_ "byte_cnt_reg_n_0_[31]") (joined + (portref Q (instanceref byte_cnt_reg_31_)) + (portref (member S 1) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename byte_len_7__i_1_n_0 "byte_len[7]_i_1_n_0") (joined + (portref CE (instanceref byte_len_reg_0_)) + (portref CE (instanceref byte_len_reg_1_)) + (portref CE (instanceref byte_len_reg_2_)) + (portref CE (instanceref byte_len_reg_3_)) + (portref CE (instanceref byte_len_reg_4_)) + (portref CE (instanceref byte_len_reg_5_)) + (portref CE (instanceref byte_len_reg_6_)) + (portref CE (instanceref byte_len_reg_7_)) + (portref CE (instanceref wr_byte_len_done_reg)) + (portref O (instanceref byte_len_7__i_1)) + ) + ) + (net (rename byte_len_reg_n_0__0_ "byte_len_reg_n_0_[0]") (joined + (portref I4 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_0_)) + ) + ) + (net (rename byte_len_reg_n_0__1_ "byte_len_reg_n_0_[1]") (joined + (portref I2 (instanceref wr_byte_num_done_i_2)) + (portref Q (instanceref byte_len_reg_1_)) + ) + ) + (net (rename byte_len_reg_n_0__2_ "byte_len_reg_n_0_[2]") (joined + (portref I1 (instanceref wr_byte_num_done_i_2)) + (portref Q (instanceref byte_len_reg_2_)) + ) + ) + (net (rename byte_len_reg_n_0__3_ "byte_len_reg_n_0_[3]") (joined + (portref I4 (instanceref wr_byte_num_done_i_1)) + (portref Q (instanceref byte_len_reg_3_)) + ) + ) + (net (rename byte_len_reg_n_0__4_ "byte_len_reg_n_0_[4]") (joined + (portref I1 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_4_)) + ) + ) + (net (rename byte_len_reg_n_0__5_ "byte_len_reg_n_0_[5]") (joined + (portref I0 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_5_)) + ) + ) + (net (rename byte_len_reg_n_0__6_ "byte_len_reg_n_0_[6]") (joined + (portref I3 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_6_)) + ) + ) + (net (rename byte_len_reg_n_0__7_ "byte_len_reg_n_0_[7]") (joined + (portref I2 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref byte_len_reg_7_)) + ) + ) + (net byte_num (joined + (portref CE (instanceref byte_num_reg_0_)) + (portref CE (instanceref byte_num_reg_10_)) + (portref CE (instanceref byte_num_reg_11_)) + (portref CE (instanceref byte_num_reg_12_)) + (portref CE (instanceref byte_num_reg_13_)) + (portref CE (instanceref byte_num_reg_14_)) + (portref CE (instanceref byte_num_reg_15_)) + (portref CE (instanceref byte_num_reg_16_)) + (portref CE (instanceref byte_num_reg_17_)) + (portref CE (instanceref byte_num_reg_18_)) + (portref CE (instanceref byte_num_reg_19_)) + (portref CE (instanceref byte_num_reg_1_)) + (portref CE (instanceref byte_num_reg_20_)) + (portref CE (instanceref byte_num_reg_21_)) + (portref CE (instanceref byte_num_reg_22_)) + (portref CE (instanceref byte_num_reg_23_)) + (portref CE (instanceref byte_num_reg_24_)) + (portref CE (instanceref byte_num_reg_25_)) + (portref CE (instanceref byte_num_reg_26_)) + (portref CE (instanceref byte_num_reg_27_)) + (portref CE (instanceref byte_num_reg_28_)) + (portref CE (instanceref byte_num_reg_29_)) + (portref CE (instanceref byte_num_reg_2_)) + (portref CE (instanceref byte_num_reg_30_)) + (portref CE (instanceref byte_num_reg_31_)) + (portref CE (instanceref byte_num_reg_3_)) + (portref CE (instanceref byte_num_reg_4_)) + (portref CE (instanceref byte_num_reg_5_)) + (portref CE (instanceref byte_num_reg_6_)) + (portref CE (instanceref byte_num_reg_7_)) + (portref CE (instanceref byte_num_reg_8_)) + (portref CE (instanceref byte_num_reg_9_)) + (portref CE (instanceref len_cnt_reg_0_)) + (portref CE (instanceref len_cnt_reg_1_)) + (portref CE (instanceref len_cnt_reg_2_)) + (portref CE (instanceref len_cnt_reg_3_)) + (portref O (instanceref byte_num_31__i_1)) + ) + ) + (net (rename byte_num_reg_n_0__24_ "byte_num_reg_n_0_[24]") (joined + (portref I2 (instanceref recv_done_i_11)) + (portref I3 (instanceref recv_done_i_7)) + (portref Q (instanceref byte_num_reg_24_)) + ) + ) + (net (rename byte_num_reg_n_0__25_ "byte_num_reg_n_0_[25]") (joined + (portref I0 (instanceref recv_done_i_11)) + (portref I1 (instanceref recv_done_i_7)) + (portref Q (instanceref byte_num_reg_25_)) + ) + ) + (net (rename byte_num_reg_n_0__26_ "byte_num_reg_n_0_[26]") (joined + (portref I2 (instanceref recv_done_i_10)) + (portref I3 (instanceref recv_done_i_6)) + (portref Q (instanceref byte_num_reg_26_)) + ) + ) + (net (rename byte_num_reg_n_0__27_ "byte_num_reg_n_0_[27]") (joined + (portref I0 (instanceref recv_done_i_10)) + (portref I1 (instanceref recv_done_i_6)) + (portref Q (instanceref byte_num_reg_27_)) + ) + ) + (net (rename byte_num_reg_n_0__28_ "byte_num_reg_n_0_[28]") (joined + (portref I2 (instanceref recv_done_i_9)) + (portref I3 (instanceref recv_done_i_5)) + (portref Q (instanceref byte_num_reg_28_)) + ) + ) + (net (rename byte_num_reg_n_0__29_ "byte_num_reg_n_0_[29]") (joined + (portref I0 (instanceref recv_done_i_9)) + (portref I1 (instanceref recv_done_i_5)) + (portref Q (instanceref byte_num_reg_29_)) + ) + ) + (net (rename byte_num_reg_n_0__30_ "byte_num_reg_n_0_[30]") (joined + (portref I2 (instanceref recv_done_i_8)) + (portref I3 (instanceref recv_done_i_4)) + (portref Q (instanceref byte_num_reg_30_)) + ) + ) + (net (rename byte_num_reg_n_0__31_ "byte_num_reg_n_0_[31]") (joined + (portref I0 (instanceref recv_done_i_8)) + (portref I1 (instanceref recv_done_i_4)) + (portref Q (instanceref byte_num_reg_31_)) + ) + ) + (net (rename data2_0_ "data2[0]") (joined + (portref I5 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_40_)) + ) + ) + (net (rename data2_1_ "data2[1]") (joined + (portref I1 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_41_)) + ) + ) + (net (rename data2_2_ "data2[2]") (joined + (portref I5 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_42_)) + ) + ) + (net (rename data2_3_ "data2[3]") (joined + (portref I5 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_43_)) + ) + ) + (net (rename data2_5_ "data2[5]") (joined + (portref I1 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_45_)) + ) + ) + (net (rename data2_6_ "data2[6]") (joined + (portref I1 (instanceref s_axi_wdata_6__i_5)) + (portref Q (instanceref bn_ascii_reg_46_)) + ) + ) + (net (rename data3_0_ "data3[0]") (joined + (portref I3 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_32_)) + ) + ) + (net (rename data3_1_ "data3[1]") (joined + (portref I0 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_33_)) + ) + ) + (net (rename data3_2_ "data3[2]") (joined + (portref I3 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_34_)) + ) + ) + (net (rename data3_3_ "data3[3]") (joined + (portref I3 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_35_)) + ) + ) + (net (rename data3_5_ "data3[5]") (joined + (portref I0 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_37_)) + ) + ) + (net (rename data3_6_ "data3[6]") (joined + (portref I3 (instanceref s_axi_wdata_6__i_5)) + (portref Q (instanceref bn_ascii_reg_38_)) + ) + ) + (net (rename data4_0_ "data4[0]") (joined + (portref I1 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_24_)) + ) + ) + (net (rename data4_1_ "data4[1]") (joined + (portref I5 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_25_)) + ) + ) + (net (rename data4_2_ "data4[2]") (joined + (portref I1 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_26_)) + ) + ) + (net (rename data4_3_ "data4[3]") (joined + (portref I1 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_27_)) + ) + ) + (net (rename data4_5_ "data4[5]") (joined + (portref I5 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_29_)) + ) + ) + (net (rename data4_6_ "data4[6]") (joined + (portref I3 (instanceref s_axi_wdata_6__i_6)) + (portref Q (instanceref bn_ascii_reg_30_)) + ) + ) + (net (rename data5_0_ "data5[0]") (joined + (portref I0 (instanceref s_axi_wdata_0__i_5)) + (portref Q (instanceref bn_ascii_reg_16_)) + ) + ) + (net (rename data5_1_ "data5[1]") (joined + (portref I3 (instanceref s_axi_wdata_1__i_6)) + (portref Q (instanceref bn_ascii_reg_17_)) + ) + ) + (net (rename data5_2_ "data5[2]") (joined + (portref I0 (instanceref s_axi_wdata_2__i_5)) + (portref Q (instanceref bn_ascii_reg_18_)) + ) + ) + (net (rename data5_3_ "data5[3]") (joined + (portref I0 (instanceref s_axi_wdata_3__i_5)) + (portref Q (instanceref bn_ascii_reg_19_)) + ) + ) + (net (rename data5_5_ "data5[5]") (joined + (portref I3 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref bn_ascii_reg_21_)) + ) + ) + (net (rename data5_6_ "data5[6]") (joined + (portref I1 (instanceref s_axi_wdata_6__i_6)) + (portref Q (instanceref bn_ascii_reg_22_)) + ) + ) + (net (rename data6_0_ "data6[0]") (joined + (portref I3 (instanceref s_axi_wdata_0__i_3)) + (portref Q (instanceref bn_ascii_reg_8_)) + ) + ) + (net (rename data6_1_ "data6[1]") (joined + (portref I3 (instanceref s_axi_wdata_1__i_3)) + (portref Q (instanceref bn_ascii_reg_9_)) + ) + ) + (net (rename data6_2_ "data6[2]") (joined + (portref I4 (instanceref s_axi_wdata_2__i_3)) + (portref Q (instanceref bn_ascii_reg_10_)) + ) + ) + (net (rename data6_3_ "data6[3]") (joined + (portref I0 (instanceref s_axi_wdata_3__i_3)) + (portref Q (instanceref bn_ascii_reg_11_)) + ) + ) + (net (rename data6_5_ "data6[5]") (joined + (portref I0 (instanceref s_axi_wdata_5__i_3)) + (portref I4 (instanceref s_axi_wdata_4__i_6)) + (portref Q (instanceref bn_ascii_reg_13_)) + ) + ) + (net (rename data6_6_ "data6[6]") (joined + (portref I1 (instanceref s_axi_wdata_6__i_4)) + (portref Q (instanceref bn_ascii_reg_14_)) + ) + ) + (net (rename dbuf_0_ "dbuf[0]") (joined + (portref D (instanceref dbuf_reg_8_)) + (portref D (instanceref upg_dat_o_reg_8_)) + (portref Q (instanceref dbuf_reg_0_)) + ) + ) + (net (rename dbuf_10_ "dbuf[10]") (joined + (portref D (instanceref dbuf_reg_18_)) + (portref D (instanceref upg_dat_o_reg_18_)) + (portref Q (instanceref dbuf_reg_10_)) + ) + ) + (net (rename dbuf_11_ "dbuf[11]") (joined + (portref D (instanceref dbuf_reg_19_)) + (portref D (instanceref upg_dat_o_reg_19_)) + (portref Q (instanceref dbuf_reg_11_)) + ) + ) + (net (rename dbuf_12_ "dbuf[12]") (joined + (portref D (instanceref dbuf_reg_20_)) + (portref D (instanceref upg_dat_o_reg_20_)) + (portref Q (instanceref dbuf_reg_12_)) + ) + ) + (net (rename dbuf_13_ "dbuf[13]") (joined + (portref D (instanceref dbuf_reg_21_)) + (portref D (instanceref upg_dat_o_reg_21_)) + (portref Q (instanceref dbuf_reg_13_)) + ) + ) + (net (rename dbuf_14_ "dbuf[14]") (joined + (portref D (instanceref dbuf_reg_22_)) + (portref D (instanceref upg_dat_o_reg_22_)) + (portref Q (instanceref dbuf_reg_14_)) + ) + ) + (net (rename dbuf_15_ "dbuf[15]") (joined + (portref D (instanceref dbuf_reg_23_)) + (portref D (instanceref upg_dat_o_reg_23_)) + (portref Q (instanceref dbuf_reg_15_)) + ) + ) + (net (rename dbuf_16_ "dbuf[16]") (joined + (portref D (instanceref upg_dat_o_reg_24_)) + (portref Q (instanceref dbuf_reg_16_)) + ) + ) + (net (rename dbuf_17_ "dbuf[17]") (joined + (portref D (instanceref upg_dat_o_reg_25_)) + (portref Q (instanceref dbuf_reg_17_)) + ) + ) + (net (rename dbuf_18_ "dbuf[18]") (joined + (portref D (instanceref upg_dat_o_reg_26_)) + (portref Q (instanceref dbuf_reg_18_)) + ) + ) + (net (rename dbuf_19_ "dbuf[19]") (joined + (portref D (instanceref upg_dat_o_reg_27_)) + (portref Q (instanceref dbuf_reg_19_)) + ) + ) + (net (rename dbuf_1_ "dbuf[1]") (joined + (portref D (instanceref dbuf_reg_9_)) + (portref D (instanceref upg_dat_o_reg_9_)) + (portref Q (instanceref dbuf_reg_1_)) + ) + ) + (net (rename dbuf_20_ "dbuf[20]") (joined + (portref D (instanceref upg_dat_o_reg_28_)) + (portref Q (instanceref dbuf_reg_20_)) + ) + ) + (net (rename dbuf_21_ "dbuf[21]") (joined + (portref D (instanceref upg_dat_o_reg_29_)) + (portref Q (instanceref dbuf_reg_21_)) + ) + ) + (net (rename dbuf_22_ "dbuf[22]") (joined + (portref D (instanceref upg_dat_o_reg_30_)) + (portref Q (instanceref dbuf_reg_22_)) + ) + ) + (net (rename dbuf_23_ "dbuf[23]") (joined + (portref D (instanceref upg_dat_o_reg_31_)) + (portref Q (instanceref dbuf_reg_23_)) + ) + ) + (net (rename dbuf_2_ "dbuf[2]") (joined + (portref D (instanceref dbuf_reg_10_)) + (portref D (instanceref upg_dat_o_reg_10_)) + (portref Q (instanceref dbuf_reg_2_)) + ) + ) + (net (rename dbuf_3_ "dbuf[3]") (joined + (portref D (instanceref dbuf_reg_11_)) + (portref D (instanceref upg_dat_o_reg_11_)) + (portref Q (instanceref dbuf_reg_3_)) + ) + ) + (net (rename dbuf_4_ "dbuf[4]") (joined + (portref D (instanceref dbuf_reg_12_)) + (portref D (instanceref upg_dat_o_reg_12_)) + (portref Q (instanceref dbuf_reg_4_)) + ) + ) + (net (rename dbuf_5_ "dbuf[5]") (joined + (portref D (instanceref dbuf_reg_13_)) + (portref D (instanceref upg_dat_o_reg_13_)) + (portref Q (instanceref dbuf_reg_5_)) + ) + ) + (net (rename dbuf_6_ "dbuf[6]") (joined + (portref D (instanceref dbuf_reg_14_)) + (portref D (instanceref upg_dat_o_reg_14_)) + (portref Q (instanceref dbuf_reg_6_)) + ) + ) + (net (rename dbuf_7_ "dbuf[7]") (joined + (portref D (instanceref dbuf_reg_15_)) + (portref D (instanceref upg_dat_o_reg_15_)) + (portref Q (instanceref dbuf_reg_7_)) + ) + ) + (net (rename dbuf_8_ "dbuf[8]") (joined + (portref D (instanceref dbuf_reg_16_)) + (portref D (instanceref upg_dat_o_reg_16_)) + (portref Q (instanceref dbuf_reg_8_)) + ) + ) + (net (rename dbuf_9_ "dbuf[9]") (joined + (portref D (instanceref dbuf_reg_17_)) + (portref D (instanceref upg_dat_o_reg_17_)) + (portref Q (instanceref dbuf_reg_9_)) + ) + ) + (net disp1 (joined + (portref I2 (instanceref disp_6__i_3)) + (portref I2 (instanceref disp_7__i_2)) + (portref I3 (instanceref disp_7__i_3)) + (portref I4 (instanceref disp_1__i_2)) + (portref I5 (instanceref disp_5__i_1)) + (portref I5 (instanceref upg_wen_o_i_5)) + (portref O (instanceref disp_5__i_4)) + ) + ) + (net (rename disp_0__i_1_n_0 "disp[0]_i_1_n_0") (joined + (portref D (instanceref disp_reg_0_)) + (portref O (instanceref disp_0__i_1)) + ) + ) + (net (rename disp_1__i_1_n_0 "disp[1]_i_1_n_0") (joined + (portref D (instanceref disp_reg_1_)) + (portref O (instanceref disp_1__i_1)) + ) + ) + (net (rename disp_1__i_2_n_0 "disp[1]_i_2_n_0") (joined + (portref I0 (instanceref disp_1__i_1)) + (portref I0 (instanceref disp_2__i_2)) + (portref O (instanceref disp_1__i_2)) + ) + ) + (net (rename disp_1__i_3_n_0 "disp[1]_i_3_n_0") (joined + (portref I0 (instanceref disp_0__i_1)) + (portref I1 (instanceref disp_1__i_1)) + (portref I1 (instanceref disp_2__i_2)) + (portref O (instanceref disp_1__i_3)) + ) + ) + (net (rename disp_2__i_1_n_0 "disp[2]_i_1_n_0") (joined + (portref D (instanceref disp_reg_2_)) + (portref O (instanceref disp_2__i_1)) + ) + ) + (net (rename disp_2__i_2_n_0 "disp[2]_i_2_n_0") (joined + (portref I0 (instanceref upg_adr_o_14__i_1)) + (portref I1 (instanceref disp_2__i_1)) + (portref I1 (instanceref upg_wen_o_i_2)) + (portref I3 (instanceref upg_wen_o_i_1)) + (portref O (instanceref disp_2__i_2)) + ) + ) + (net (rename disp_3__i_1_n_0 "disp[3]_i_1_n_0") (joined + (portref D (instanceref disp_reg_3_)) + (portref O (instanceref disp_3__i_1)) + ) + ) + (net (rename disp_3__i_2_n_0 "disp[3]_i_2_n_0") (joined + (portref I1 (instanceref disp_3__i_1)) + (portref O (instanceref disp_3__i_2)) + ) + ) + (net (rename disp_4__i_1_n_0 "disp[4]_i_1_n_0") (joined + (portref D (instanceref disp_reg_4_)) + (portref O (instanceref disp_4__i_1)) + ) + ) + (net (rename disp_5__i_1_n_0 "disp[5]_i_1_n_0") (joined + (portref D (instanceref disp_reg_5_)) + (portref O (instanceref disp_5__i_1)) + ) + ) + (net (rename disp_5__i_2_n_0 "disp[5]_i_2_n_0") (joined + (portref I0 (instanceref disp_5__i_1)) + (portref I0 (instanceref disp_7__i_3)) + (portref O (instanceref disp_5__i_2)) + ) + ) + (net (rename disp_5__i_3_n_0 "disp[5]_i_3_n_0") (joined + (portref I1 (instanceref disp_4__i_1)) + (portref I1 (instanceref disp_5__i_1)) + (portref O (instanceref disp_5__i_3)) + ) + ) + (net (rename disp_6__i_1_n_0 "disp[6]_i_1_n_0") (joined + (portref D (instanceref disp_reg_6_)) + (portref O (instanceref disp_6__i_1)) + ) + ) + (net (rename disp_6__i_2_n_0 "disp[6]_i_2_n_0") (joined + (portref I0 (instanceref disp_2__i_1)) + (portref I2 (instanceref disp_6__i_1)) + (portref O (instanceref disp_6__i_2)) + ) + ) + (net (rename disp_6__i_3_n_0 "disp[6]_i_3_n_0") (joined + (portref I1 (instanceref disp_5__i_3)) + (portref I2 (instanceref disp_6__i_2)) + (portref I3 (instanceref disp_3__i_2)) + (portref O (instanceref disp_6__i_3)) + ) + ) + (net (rename disp_7__i_1_n_0 "disp[7]_i_1_n_0") (joined + (portref D (instanceref disp_reg_7_)) + (portref O (instanceref disp_7__i_1)) + ) + ) + (net (rename disp_7__i_2_n_0 "disp[7]_i_2_n_0") (joined + (portref I3 (instanceref disp_7__i_1)) + (portref I5 (instanceref disp_6__i_1)) + (portref O (instanceref disp_7__i_2)) + ) + ) + (net (rename disp_7__i_3_n_0 "disp[7]_i_3_n_0") (joined + (portref I1 (instanceref disp_7__i_2)) + (portref O (instanceref disp_7__i_3)) + ) + ) + (net (rename disp_7__i_4_n_0 "disp[7]_i_4_n_0") (joined + (portref I1 (instanceref disp_7__i_3)) + (portref O (instanceref disp_7__i_4)) + ) + ) + (net (rename disp_reg_n_0__0_ "disp_reg_n_0_[0]") (joined + (portref I1 (instanceref disp_6__i_3)) + (portref I1 (instanceref upg_wen_o_i_3)) + (portref I1 (instanceref upg_wen_o_i_5)) + (portref I2 (instanceref disp_1__i_2)) + (portref I2 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I4 (instanceref disp_7__i_3)) + (portref I5 (instanceref disp_1__i_3)) + (portref Q (instanceref disp_reg_0_)) + ) + ) + (net (rename disp_reg_n_0__1_ "disp_reg_n_0_[1]") (joined + (portref I0 (instanceref disp_6__i_3)) + (portref I0 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I2 (instanceref upg_wen_o_i_5)) + (portref I5 (instanceref disp_1__i_2)) + (portref I5 (instanceref disp_7__i_3)) + (portref Q (instanceref disp_reg_1_)) + ) + ) + (net (rename disp_reg_n_0__2_ "disp_reg_n_0_[2]") (joined + (portref I0 (instanceref disp_3__i_2)) + (portref I1 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I2 (instanceref upg_wen_o_i_4)) + (portref I3 (instanceref disp_7__i_2)) + (portref I4 (instanceref disp_2__i_1)) + (portref I4 (instanceref disp_5__i_3)) + (portref Q (instanceref disp_reg_2_)) + ) + ) + (net (rename disp_reg_n_0__3_ "disp_reg_n_0_[3]") (joined + (portref I0 (instanceref disp_5__i_3)) + (portref I0 (instanceref disp_7__i_2)) + (portref I3 (instanceref disp_3__i_1)) + (portref I3 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I3 (instanceref upg_wen_o_i_4)) + (portref Q (instanceref disp_reg_3_)) + ) + ) + (net (rename disp_reg_n_0__4_ "disp_reg_n_0_[4]") (joined + (portref I1 (instanceref upg_wen_o_i_6)) + (portref I2 (instanceref disp_5__i_1)) + (portref I2 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I3 (instanceref disp_4__i_1)) + (portref I4 (instanceref disp_7__i_2)) + (portref Q (instanceref disp_reg_4_)) + ) + ) + (net (rename disp_reg_n_0__5_ "disp_reg_n_0_[5]") (joined + (portref I0 (instanceref upg_clk_o_OBUF_inst_i_2)) + (portref I4 (instanceref disp_5__i_1)) + (portref I5 (instanceref disp_7__i_2)) + (portref I5 (instanceref upg_wen_o_i_6)) + (portref Q (instanceref disp_reg_5_)) + ) + ) + (net (rename disp_reg_n_0__6_ "disp_reg_n_0_[6]") (joined + (portref I0 (instanceref disp_1__i_2)) + (portref I0 (instanceref disp_1__i_3)) + (portref I0 (instanceref disp_7__i_4)) + (portref I2 (instanceref upg_wen_o_i_6)) + (portref I3 (instanceref disp_6__i_1)) + (portref I3 (instanceref upg_wen_o_i_3)) + (portref I4 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I4 (instanceref upg_wen_o_i_5)) + (portref I5 (instanceref disp_6__i_3)) + (portref I5 (instanceref disp_7__i_1)) + (portref Q (instanceref disp_reg_6_)) + ) + ) + (net (rename disp_reg_n_0__7_ "disp_reg_n_0_[7]") (joined + (portref I0 (instanceref upg_wen_o_i_6)) + (portref I1 (instanceref disp_1__i_2)) + (portref I1 (instanceref disp_1__i_3)) + (portref I1 (instanceref disp_7__i_4)) + (portref I2 (instanceref disp_7__i_1)) + (portref I2 (instanceref upg_wen_o_i_3)) + (portref I3 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I3 (instanceref upg_wen_o_i_5)) + (portref I4 (instanceref disp_6__i_3)) + (portref Q (instanceref disp_reg_7_)) + ) + ) + (net (rename hex0_10_ "hex0[10]") (joined + (portref D (instanceref byte_num_reg_10_)) + (portref I1 (instanceref bn_ascii_18__i_1)) + (portref I1 (instanceref bn_ascii_19__i_1)) + (portref I1 (instanceref bn_ascii_21__i_1)) + (portref I1 (instanceref bn_ascii_22__i_1)) + (portref I2 (instanceref bn_ascii_16__i_1)) + (portref I2 (instanceref bn_ascii_17__i_1)) + (portref I2 (instanceref recv_done_i_36)) + (portref I3 (instanceref recv_done_i_32)) + (portref Q (instanceref byte_num_reg_2_)) + ) + ) + (net (rename hex0_11_ "hex0[11]") (joined + (portref D (instanceref byte_num_reg_11_)) + (portref I0 (instanceref bn_ascii_19__i_1)) + (portref I0 (instanceref bn_ascii_22__i_1)) + (portref I0 (instanceref recv_done_i_36)) + (portref I1 (instanceref bn_ascii_17__i_1)) + (portref I1 (instanceref recv_done_i_32)) + (portref I2 (instanceref bn_ascii_18__i_1)) + (portref I2 (instanceref bn_ascii_21__i_1)) + (portref I3 (instanceref bn_ascii_16__i_1)) + (portref Q (instanceref byte_num_reg_3_)) + ) + ) + (net (rename hex0_12_ "hex0[12]") (joined + (portref D (instanceref byte_num_reg_12_)) + (portref I0 (instanceref bn_ascii_24__i_1)) + (portref I0 (instanceref bn_ascii_25__i_1)) + (portref I2 (instanceref recv_done_i_35)) + (portref I3 (instanceref bn_ascii_26__i_1)) + (portref I3 (instanceref recv_done_i_31)) + (portref Q (instanceref byte_num_reg_4_)) + ) + ) + (net (rename hex0_13_ "hex0[13]") (joined + (portref D (instanceref byte_num_reg_13_)) + (portref I0 (instanceref bn_ascii_26__i_1)) + (portref I0 (instanceref bn_ascii_29__i_1)) + (portref I0 (instanceref recv_done_i_35)) + (portref I1 (instanceref bn_ascii_24__i_1)) + (portref I1 (instanceref recv_done_i_31)) + (portref I2 (instanceref bn_ascii_27__i_1)) + (portref I2 (instanceref bn_ascii_30__i_1)) + (portref I3 (instanceref bn_ascii_25__i_1)) + (portref Q (instanceref byte_num_reg_5_)) + ) + ) + (net (rename hex0_14_ "hex0[14]") (joined + (portref D (instanceref byte_num_reg_14_)) + (portref I1 (instanceref bn_ascii_26__i_1)) + (portref I1 (instanceref bn_ascii_27__i_1)) + (portref I1 (instanceref bn_ascii_29__i_1)) + (portref I1 (instanceref bn_ascii_30__i_1)) + (portref I2 (instanceref bn_ascii_24__i_1)) + (portref I2 (instanceref bn_ascii_25__i_1)) + (portref I2 (instanceref recv_done_i_34)) + (portref I3 (instanceref recv_done_i_30)) + (portref Q (instanceref byte_num_reg_6_)) + ) + ) + (net (rename hex0_15_ "hex0[15]") (joined + (portref D (instanceref byte_num_reg_15_)) + (portref I0 (instanceref bn_ascii_27__i_1)) + (portref I0 (instanceref bn_ascii_30__i_1)) + (portref I0 (instanceref recv_done_i_34)) + (portref I1 (instanceref bn_ascii_25__i_1)) + (portref I1 (instanceref recv_done_i_30)) + (portref I2 (instanceref bn_ascii_26__i_1)) + (portref I2 (instanceref bn_ascii_29__i_1)) + (portref I3 (instanceref bn_ascii_24__i_1)) + (portref Q (instanceref byte_num_reg_7_)) + ) + ) + (net (rename hex0_16_ "hex0[16]") (joined + (portref D (instanceref byte_num_reg_16_)) + (portref I0 (instanceref bn_ascii_32__i_1)) + (portref I0 (instanceref bn_ascii_33__i_1)) + (portref I2 (instanceref recv_done_i_29)) + (portref I3 (instanceref bn_ascii_34__i_1)) + (portref I3 (instanceref recv_done_i_25)) + (portref Q (instanceref byte_num_reg_8_)) + ) + ) + (net (rename hex0_17_ "hex0[17]") (joined + (portref D (instanceref byte_num_reg_17_)) + (portref I0 (instanceref bn_ascii_34__i_1)) + (portref I0 (instanceref bn_ascii_37__i_1)) + (portref I0 (instanceref recv_done_i_29)) + (portref I1 (instanceref bn_ascii_32__i_1)) + (portref I1 (instanceref recv_done_i_25)) + (portref I2 (instanceref bn_ascii_35__i_1)) + (portref I2 (instanceref bn_ascii_38__i_1)) + (portref I3 (instanceref bn_ascii_33__i_1)) + (portref Q (instanceref byte_num_reg_9_)) + ) + ) + (net (rename hex0_18_ "hex0[18]") (joined + (portref D (instanceref byte_num_reg_18_)) + (portref I1 (instanceref bn_ascii_34__i_1)) + (portref I1 (instanceref bn_ascii_35__i_1)) + (portref I1 (instanceref bn_ascii_37__i_1)) + (portref I1 (instanceref bn_ascii_38__i_1)) + (portref I2 (instanceref bn_ascii_32__i_1)) + (portref I2 (instanceref bn_ascii_33__i_1)) + (portref I2 (instanceref recv_done_i_28)) + (portref I3 (instanceref recv_done_i_24)) + (portref Q (instanceref byte_num_reg_10_)) + ) + ) + (net (rename hex0_19_ "hex0[19]") (joined + (portref D (instanceref byte_num_reg_19_)) + (portref I0 (instanceref bn_ascii_35__i_1)) + (portref I0 (instanceref bn_ascii_38__i_1)) + (portref I0 (instanceref recv_done_i_28)) + (portref I1 (instanceref bn_ascii_33__i_1)) + (portref I1 (instanceref recv_done_i_24)) + (portref I2 (instanceref bn_ascii_34__i_1)) + (portref I2 (instanceref bn_ascii_37__i_1)) + (portref I3 (instanceref bn_ascii_32__i_1)) + (portref Q (instanceref byte_num_reg_11_)) + ) + ) + (net (rename hex0_20_ "hex0[20]") (joined + (portref D (instanceref byte_num_reg_20_)) + (portref I0 (instanceref bn_ascii_40__i_1)) + (portref I0 (instanceref bn_ascii_41__i_1)) + (portref I2 (instanceref recv_done_i_27)) + (portref I3 (instanceref bn_ascii_42__i_1)) + (portref I3 (instanceref recv_done_i_23)) + (portref Q (instanceref byte_num_reg_12_)) + ) + ) + (net (rename hex0_21_ "hex0[21]") (joined + (portref D (instanceref byte_num_reg_21_)) + (portref I0 (instanceref bn_ascii_42__i_1)) + (portref I0 (instanceref bn_ascii_45__i_1)) + (portref I0 (instanceref recv_done_i_27)) + (portref I1 (instanceref bn_ascii_40__i_1)) + (portref I1 (instanceref recv_done_i_23)) + (portref I2 (instanceref bn_ascii_43__i_1)) + (portref I2 (instanceref bn_ascii_46__i_1)) + (portref I3 (instanceref bn_ascii_41__i_1)) + (portref Q (instanceref byte_num_reg_13_)) + ) + ) + (net (rename hex0_22_ "hex0[22]") (joined + (portref D (instanceref byte_num_reg_22_)) + (portref I1 (instanceref bn_ascii_42__i_1)) + (portref I1 (instanceref bn_ascii_43__i_1)) + (portref I1 (instanceref bn_ascii_45__i_1)) + (portref I1 (instanceref bn_ascii_46__i_1)) + (portref I2 (instanceref bn_ascii_40__i_1)) + (portref I2 (instanceref bn_ascii_41__i_1)) + (portref I2 (instanceref recv_done_i_26)) + (portref I3 (instanceref recv_done_i_22)) + (portref Q (instanceref byte_num_reg_14_)) + ) + ) + (net (rename hex0_23_ "hex0[23]") (joined + (portref D (instanceref byte_num_reg_23_)) + (portref I0 (instanceref bn_ascii_43__i_1)) + (portref I0 (instanceref bn_ascii_46__i_1)) + (portref I0 (instanceref recv_done_i_26)) + (portref I1 (instanceref bn_ascii_41__i_1)) + (portref I1 (instanceref recv_done_i_22)) + (portref I2 (instanceref bn_ascii_42__i_1)) + (portref I2 (instanceref bn_ascii_45__i_1)) + (portref I3 (instanceref bn_ascii_40__i_1)) + (portref Q (instanceref byte_num_reg_15_)) + ) + ) + (net (rename hex0_24_ "hex0[24]") (joined + (portref D (instanceref byte_num_reg_24_)) + (portref I0 (instanceref bn_ascii_48__i_1)) + (portref I0 (instanceref bn_ascii_49__i_1)) + (portref I2 (instanceref recv_done_i_20)) + (portref I3 (instanceref bn_ascii_50__i_1)) + (portref I3 (instanceref recv_done_i_16)) + (portref Q (instanceref byte_num_reg_16_)) + ) + ) + (net (rename hex0_25_ "hex0[25]") (joined + (portref D (instanceref byte_num_reg_25_)) + (portref I0 (instanceref bn_ascii_50__i_1)) + (portref I0 (instanceref bn_ascii_53__i_1)) + (portref I0 (instanceref recv_done_i_20)) + (portref I1 (instanceref bn_ascii_48__i_1)) + (portref I1 (instanceref recv_done_i_16)) + (portref I2 (instanceref bn_ascii_51__i_1)) + (portref I2 (instanceref bn_ascii_54__i_1)) + (portref I3 (instanceref bn_ascii_49__i_1)) + (portref Q (instanceref byte_num_reg_17_)) + ) + ) + (net (rename hex0_26_ "hex0[26]") (joined + (portref D (instanceref byte_num_reg_26_)) + (portref I1 (instanceref bn_ascii_50__i_1)) + (portref I1 (instanceref bn_ascii_51__i_1)) + (portref I1 (instanceref bn_ascii_53__i_1)) + (portref I1 (instanceref bn_ascii_54__i_1)) + (portref I2 (instanceref bn_ascii_48__i_1)) + (portref I2 (instanceref bn_ascii_49__i_1)) + (portref I2 (instanceref recv_done_i_19)) + (portref I3 (instanceref recv_done_i_15)) + (portref Q (instanceref byte_num_reg_18_)) + ) + ) + (net (rename hex0_27_ "hex0[27]") (joined + (portref D (instanceref byte_num_reg_27_)) + (portref I0 (instanceref bn_ascii_51__i_1)) + (portref I0 (instanceref bn_ascii_54__i_1)) + (portref I0 (instanceref recv_done_i_19)) + (portref I1 (instanceref bn_ascii_49__i_1)) + (portref I1 (instanceref recv_done_i_15)) + (portref I2 (instanceref bn_ascii_50__i_1)) + (portref I2 (instanceref bn_ascii_53__i_1)) + (portref I3 (instanceref bn_ascii_48__i_1)) + (portref Q (instanceref byte_num_reg_19_)) + ) + ) + (net (rename hex0_28_ "hex0[28]") (joined + (portref D (instanceref byte_num_reg_28_)) + (portref I0 (instanceref bn_ascii_56__i_1)) + (portref I0 (instanceref bn_ascii_57__i_1)) + (portref I2 (instanceref recv_done_i_18)) + (portref I3 (instanceref bn_ascii_58__i_1)) + (portref I3 (instanceref recv_done_i_14)) + (portref Q (instanceref byte_num_reg_20_)) + ) + ) + (net (rename hex0_29_ "hex0[29]") (joined + (portref D (instanceref byte_num_reg_29_)) + (portref I0 (instanceref bn_ascii_58__i_1)) + (portref I0 (instanceref bn_ascii_61__i_1)) + (portref I0 (instanceref recv_done_i_18)) + (portref I1 (instanceref bn_ascii_56__i_1)) + (portref I1 (instanceref recv_done_i_14)) + (portref I2 (instanceref bn_ascii_59__i_1)) + (portref I2 (instanceref bn_ascii_62__i_2)) + (portref I3 (instanceref bn_ascii_57__i_1)) + (portref Q (instanceref byte_num_reg_21_)) + ) + ) + (net (rename hex0_30_ "hex0[30]") (joined + (portref D (instanceref byte_num_reg_30_)) + (portref I1 (instanceref bn_ascii_58__i_1)) + (portref I1 (instanceref bn_ascii_59__i_1)) + (portref I1 (instanceref bn_ascii_61__i_1)) + (portref I1 (instanceref bn_ascii_62__i_2)) + (portref I2 (instanceref bn_ascii_56__i_1)) + (portref I2 (instanceref bn_ascii_57__i_1)) + (portref I2 (instanceref recv_done_i_17)) + (portref I3 (instanceref recv_done_i_13)) + (portref Q (instanceref byte_num_reg_22_)) + ) + ) + (net (rename hex0_31_ "hex0[31]") (joined + (portref D (instanceref byte_num_reg_31_)) + (portref I0 (instanceref bn_ascii_59__i_1)) + (portref I0 (instanceref bn_ascii_62__i_2)) + (portref I0 (instanceref recv_done_i_17)) + (portref I1 (instanceref bn_ascii_57__i_1)) + (portref I1 (instanceref recv_done_i_13)) + (portref I2 (instanceref bn_ascii_58__i_1)) + (portref I2 (instanceref bn_ascii_61__i_1)) + (portref I3 (instanceref bn_ascii_56__i_1)) + (portref Q (instanceref byte_num_reg_23_)) + ) + ) + (net (rename hex0_8_ "hex0[8]") (joined + (portref D (instanceref byte_num_reg_8_)) + (portref I0 (instanceref bn_ascii_16__i_1)) + (portref I0 (instanceref bn_ascii_17__i_1)) + (portref I0 (instanceref recv_done_i_37)) + (portref I3 (instanceref bn_ascii_18__i_1)) + (portref I3 (instanceref recv_done_i_33)) + (portref Q (instanceref byte_num_reg_0_)) + ) + ) + (net (rename hex0_9_ "hex0[9]") (joined + (portref D (instanceref byte_num_reg_9_)) + (portref I0 (instanceref bn_ascii_18__i_1)) + (portref I0 (instanceref bn_ascii_21__i_1)) + (portref I1 (instanceref bn_ascii_16__i_1)) + (portref I1 (instanceref recv_done_i_33)) + (portref I2 (instanceref bn_ascii_19__i_1)) + (portref I2 (instanceref bn_ascii_22__i_1)) + (portref I2 (instanceref recv_done_i_37)) + (portref I3 (instanceref bn_ascii_17__i_1)) + (portref Q (instanceref byte_num_reg_1_)) + ) + ) + (net (rename hex2ascii_return0_0_ "hex2ascii_return0[0]") (joined + (portref D (instanceref bn_ascii_reg_56_)) + (portref O (instanceref bn_ascii_56__i_1)) + ) + ) + (net (rename hex2ascii_return0_1_ "hex2ascii_return0[1]") (joined + (portref D (instanceref bn_ascii_reg_57_)) + (portref O (instanceref bn_ascii_57__i_1)) + ) + ) + (net (rename hex2ascii_return0_2_ "hex2ascii_return0[2]") (joined + (portref D (instanceref bn_ascii_reg_58_)) + (portref O (instanceref bn_ascii_58__i_1)) + ) + ) + (net (rename hex2ascii_return0_3_ "hex2ascii_return0[3]") (joined + (portref D (instanceref bn_ascii_reg_59_)) + (portref O (instanceref bn_ascii_59__i_1)) + ) + ) + (net (rename hex2ascii_return0_5_ "hex2ascii_return0[5]") (joined + (portref D (instanceref bn_ascii_reg_61_)) + (portref O (instanceref bn_ascii_61__i_1)) + ) + ) + (net (rename hex2ascii_return0_6_ "hex2ascii_return0[6]") (joined + (portref D (instanceref bn_ascii_reg_62_)) + (portref O (instanceref bn_ascii_62__i_2)) + ) + ) + (net (rename hex2ascii_return_0_ "hex2ascii_return[0]") (joined + (portref D (instanceref bn_ascii_reg_0_)) + (portref O (instanceref bn_ascii_0__i_1)) + ) + ) + (net (rename hex2ascii_return_10_ "hex2ascii_return[10]") (joined + (portref D (instanceref bn_ascii_reg_10_)) + (portref O (instanceref bn_ascii_10__i_1)) + ) + ) + (net (rename hex2ascii_return_11_ "hex2ascii_return[11]") (joined + (portref D (instanceref bn_ascii_reg_11_)) + (portref O (instanceref bn_ascii_11__i_1)) + ) + ) + (net (rename hex2ascii_return_13_ "hex2ascii_return[13]") (joined + (portref D (instanceref bn_ascii_reg_13_)) + (portref O (instanceref bn_ascii_13__i_1)) + ) + ) + (net (rename hex2ascii_return_14_ "hex2ascii_return[14]") (joined + (portref D (instanceref bn_ascii_reg_14_)) + (portref O (instanceref bn_ascii_14__i_1)) + ) + ) + (net (rename hex2ascii_return_16_ "hex2ascii_return[16]") (joined + (portref D (instanceref bn_ascii_reg_16_)) + (portref O (instanceref bn_ascii_16__i_1)) + ) + ) + (net (rename hex2ascii_return_17_ "hex2ascii_return[17]") (joined + (portref D (instanceref bn_ascii_reg_17_)) + (portref O (instanceref bn_ascii_17__i_1)) + ) + ) + (net (rename hex2ascii_return_18_ "hex2ascii_return[18]") (joined + (portref D (instanceref bn_ascii_reg_18_)) + (portref O (instanceref bn_ascii_18__i_1)) + ) + ) + (net (rename hex2ascii_return_19_ "hex2ascii_return[19]") (joined + (portref D (instanceref bn_ascii_reg_19_)) + (portref O (instanceref bn_ascii_19__i_1)) + ) + ) + (net (rename hex2ascii_return_1_ "hex2ascii_return[1]") (joined + (portref D (instanceref bn_ascii_reg_1_)) + (portref O (instanceref bn_ascii_1__i_1)) + ) + ) + (net (rename hex2ascii_return_21_ "hex2ascii_return[21]") (joined + (portref D (instanceref bn_ascii_reg_21_)) + (portref O (instanceref bn_ascii_21__i_1)) + ) + ) + (net (rename hex2ascii_return_22_ "hex2ascii_return[22]") (joined + (portref D (instanceref bn_ascii_reg_22_)) + (portref O (instanceref bn_ascii_22__i_1)) + ) + ) + (net (rename hex2ascii_return_24_ "hex2ascii_return[24]") (joined + (portref D (instanceref bn_ascii_reg_24_)) + (portref O (instanceref bn_ascii_24__i_1)) + ) + ) + (net (rename hex2ascii_return_25_ "hex2ascii_return[25]") (joined + (portref D (instanceref bn_ascii_reg_25_)) + (portref O (instanceref bn_ascii_25__i_1)) + ) + ) + (net (rename hex2ascii_return_26_ "hex2ascii_return[26]") (joined + (portref D (instanceref bn_ascii_reg_26_)) + (portref O (instanceref bn_ascii_26__i_1)) + ) + ) + (net (rename hex2ascii_return_27_ "hex2ascii_return[27]") (joined + (portref D (instanceref bn_ascii_reg_27_)) + (portref O (instanceref bn_ascii_27__i_1)) + ) + ) + (net (rename hex2ascii_return_29_ "hex2ascii_return[29]") (joined + (portref D (instanceref bn_ascii_reg_29_)) + (portref O (instanceref bn_ascii_29__i_1)) + ) + ) + (net (rename hex2ascii_return_2_ "hex2ascii_return[2]") (joined + (portref D (instanceref bn_ascii_reg_2_)) + (portref O (instanceref bn_ascii_2__i_1)) + ) + ) + (net (rename hex2ascii_return_30_ "hex2ascii_return[30]") (joined + (portref D (instanceref bn_ascii_reg_30_)) + (portref O (instanceref bn_ascii_30__i_1)) + ) + ) + (net (rename hex2ascii_return_32_ "hex2ascii_return[32]") (joined + (portref D (instanceref bn_ascii_reg_32_)) + (portref O (instanceref bn_ascii_32__i_1)) + ) + ) + (net (rename hex2ascii_return_33_ "hex2ascii_return[33]") (joined + (portref D (instanceref bn_ascii_reg_33_)) + (portref O (instanceref bn_ascii_33__i_1)) + ) + ) + (net (rename hex2ascii_return_34_ "hex2ascii_return[34]") (joined + (portref D (instanceref bn_ascii_reg_34_)) + (portref O (instanceref bn_ascii_34__i_1)) + ) + ) + (net (rename hex2ascii_return_35_ "hex2ascii_return[35]") (joined + (portref D (instanceref bn_ascii_reg_35_)) + (portref O (instanceref bn_ascii_35__i_1)) + ) + ) + (net (rename hex2ascii_return_37_ "hex2ascii_return[37]") (joined + (portref D (instanceref bn_ascii_reg_37_)) + (portref O (instanceref bn_ascii_37__i_1)) + ) + ) + (net (rename hex2ascii_return_38_ "hex2ascii_return[38]") (joined + (portref D (instanceref bn_ascii_reg_38_)) + (portref O (instanceref bn_ascii_38__i_1)) + ) + ) + (net (rename hex2ascii_return_3_ "hex2ascii_return[3]") (joined + (portref D (instanceref bn_ascii_reg_3_)) + (portref O (instanceref bn_ascii_3__i_1)) + ) + ) + (net (rename hex2ascii_return_40_ "hex2ascii_return[40]") (joined + (portref D (instanceref bn_ascii_reg_40_)) + (portref O (instanceref bn_ascii_40__i_1)) + ) + ) + (net (rename hex2ascii_return_41_ "hex2ascii_return[41]") (joined + (portref D (instanceref bn_ascii_reg_41_)) + (portref O (instanceref bn_ascii_41__i_1)) + ) + ) + (net (rename hex2ascii_return_42_ "hex2ascii_return[42]") (joined + (portref D (instanceref bn_ascii_reg_42_)) + (portref O (instanceref bn_ascii_42__i_1)) + ) + ) + (net (rename hex2ascii_return_43_ "hex2ascii_return[43]") (joined + (portref D (instanceref bn_ascii_reg_43_)) + (portref O (instanceref bn_ascii_43__i_1)) + ) + ) + (net (rename hex2ascii_return_45_ "hex2ascii_return[45]") (joined + (portref D (instanceref bn_ascii_reg_45_)) + (portref O (instanceref bn_ascii_45__i_1)) + ) + ) + (net (rename hex2ascii_return_46_ "hex2ascii_return[46]") (joined + (portref D (instanceref bn_ascii_reg_46_)) + (portref O (instanceref bn_ascii_46__i_1)) + ) + ) + (net (rename hex2ascii_return_48_ "hex2ascii_return[48]") (joined + (portref D (instanceref bn_ascii_reg_48_)) + (portref O (instanceref bn_ascii_48__i_1)) + ) + ) + (net (rename hex2ascii_return_49_ "hex2ascii_return[49]") (joined + (portref D (instanceref bn_ascii_reg_49_)) + (portref O (instanceref bn_ascii_49__i_1)) + ) + ) + (net (rename hex2ascii_return_50_ "hex2ascii_return[50]") (joined + (portref D (instanceref bn_ascii_reg_50_)) + (portref O (instanceref bn_ascii_50__i_1)) + ) + ) + (net (rename hex2ascii_return_51_ "hex2ascii_return[51]") (joined + (portref D (instanceref bn_ascii_reg_51_)) + (portref O (instanceref bn_ascii_51__i_1)) + ) + ) + (net (rename hex2ascii_return_53_ "hex2ascii_return[53]") (joined + (portref D (instanceref bn_ascii_reg_53_)) + (portref O (instanceref bn_ascii_53__i_1)) + ) + ) + (net (rename hex2ascii_return_54_ "hex2ascii_return[54]") (joined + (portref D (instanceref bn_ascii_reg_54_)) + (portref O (instanceref bn_ascii_54__i_1)) + ) + ) + (net (rename hex2ascii_return_5_ "hex2ascii_return[5]") (joined + (portref D (instanceref bn_ascii_reg_5_)) + (portref O (instanceref bn_ascii_5__i_1)) + ) + ) + (net (rename hex2ascii_return_6_ "hex2ascii_return[6]") (joined + (portref D (instanceref bn_ascii_reg_6_)) + (portref O (instanceref bn_ascii_6__i_1)) + ) + ) + (net (rename hex2ascii_return_8_ "hex2ascii_return[8]") (joined + (portref D (instanceref bn_ascii_reg_8_)) + (portref O (instanceref bn_ascii_8__i_1)) + ) + ) + (net (rename hex2ascii_return_9_ "hex2ascii_return[9]") (joined + (portref D (instanceref bn_ascii_reg_9_)) + (portref O (instanceref bn_ascii_9__i_1)) + ) + ) + (net initFlag (joined + (portref I0 (instanceref WCS_0__i_2)) + (portref I0 (instanceref initFlag_i_1)) + (portref I0 (instanceref s_axi_awaddr_3__i_1)) + (portref I2 (instanceref s_axi_awvalid_i_1)) + (portref I4 (instanceref s_axi_wdata_4__i_1)) + (portref I4 (instanceref s_axi_wdata_4__i_2)) + (portref I4 (instanceref s_axi_wdata_6__i_1)) + (portref I4 (instanceref s_axi_wstrb_3__i_1)) + (portref I5 (instanceref s_axi_wdata_0__i_1)) + (portref I5 (instanceref s_axi_wdata_1__i_1)) + (portref Q (instanceref initFlag_reg)) + ) + ) + (net initFlag_i_1_n_0 (joined + (portref D (instanceref initFlag_reg)) + (portref O (instanceref initFlag_i_1)) + ) + ) + (net (rename len_cnt_0__i_1_n_0 "len_cnt[0]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_0_)) + (portref O (instanceref len_cnt_0__i_1)) + ) + ) + (net (rename len_cnt_1__i_1_n_0 "len_cnt[1]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_1_)) + (portref O (instanceref len_cnt_1__i_1)) + ) + ) + (net (rename len_cnt_2__i_1_n_0 "len_cnt[2]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_2_)) + (portref O (instanceref len_cnt_2__i_1)) + ) + ) + (net (rename len_cnt_3__i_1_n_0 "len_cnt[3]_i_1_n_0") (joined + (portref D (instanceref len_cnt_reg_3_)) + (portref O (instanceref len_cnt_3__i_1)) + ) + ) + (net (rename len_cnt_reg__0_0_ "len_cnt_reg__0[0]") (joined + (portref I0 (instanceref len_cnt_0__i_1)) + (portref I0 (instanceref len_cnt_1__i_1)) + (portref I1 (instanceref len_cnt_3__i_1)) + (portref I1 (instanceref wr_byte_num_done_i_1)) + (portref I2 (instanceref len_cnt_2__i_1)) + (portref I4 (instanceref wr_byte_num_done_i_2)) + (portref I5 (instanceref wr_byte_num_done_i_3)) + (portref Q (instanceref len_cnt_reg_0_)) + ) + ) + (net (rename len_cnt_reg__0_1_ "len_cnt_reg__0[1]") (joined + (portref I1 (instanceref len_cnt_1__i_1)) + (portref I1 (instanceref len_cnt_2__i_1)) + (portref I2 (instanceref len_cnt_3__i_1)) + (portref I2 (instanceref wr_byte_num_done_i_1)) + (portref I3 (instanceref wr_byte_num_done_i_2)) + (portref Q (instanceref len_cnt_reg_1_)) + ) + ) + (net (rename len_cnt_reg__0_2_ "len_cnt_reg__0[2]") (joined + (portref I0 (instanceref len_cnt_2__i_1)) + (portref I0 (instanceref wr_byte_num_done_i_2)) + (portref I3 (instanceref len_cnt_3__i_1)) + (portref I3 (instanceref wr_byte_num_done_i_1)) + (portref Q (instanceref len_cnt_reg_2_)) + ) + ) + (net (rename len_cnt_reg__0_3_ "len_cnt_reg__0[3]") (joined + (portref I0 (instanceref len_cnt_3__i_1)) + (portref I0 (instanceref wr_byte_num_done_i_1)) + (portref Q (instanceref len_cnt_reg_3_)) + ) + ) + (net (rename msg_indx_7__i_1_n_0 "msg_indx[7]_i_1_n_0") (joined + (portref CE (instanceref msg_indx_reg_0_)) + (portref CE (instanceref msg_indx_reg_1_)) + (portref CE (instanceref msg_indx_reg_2_)) + (portref CE (instanceref msg_indx_reg_3_)) + (portref CE (instanceref msg_indx_reg_4_)) + (portref CE (instanceref msg_indx_reg_5_)) + (portref CE (instanceref msg_indx_reg_6_)) + (portref CE (instanceref msg_indx_reg_7_)) + (portref O (instanceref msg_indx_7__i_1)) + ) + ) + (net (rename msg_indx_7__i_3_n_0 "msg_indx[7]_i_3_n_0") (joined + (portref I1 (instanceref msg_indx_6__i_1)) + (portref I1 (instanceref msg_indx_7__i_2)) + (portref O (instanceref msg_indx_7__i_3)) + ) + ) + (net (rename msg_indx_reg__0_0_ "msg_indx_reg__0[0]") (joined + (portref I0 (instanceref msg_indx_0__i_1)) + (portref I0 (instanceref msg_indx_1__i_1)) + (portref I0 (instanceref s_axi_wdata_5__i_2)) + (portref I1 (instanceref s_axi_wdata_0__i_2)) + (portref I1 (instanceref s_axi_wdata_1__i_2)) + (portref I1 (instanceref s_axi_wdata_2__i_2)) + (portref I1 (instanceref s_axi_wdata_2__i_3)) + (portref I1 (instanceref s_axi_wdata_4__i_5)) + (portref I1 (instanceref s_axi_wdata_5__i_6)) + (portref I1 (instanceref s_axi_wdata_6__i_3)) + (portref I2 (instanceref msg_indx_2__i_1)) + (portref I2 (instanceref msg_indx_4__i_1)) + (portref I2 (instanceref msg_indx_7__i_3)) + (portref I2 (instanceref s_axi_wdata_0__i_4)) + (portref I2 (instanceref s_axi_wdata_1__i_5)) + (portref I2 (instanceref s_axi_wdata_2__i_4)) + (portref I2 (instanceref s_axi_wdata_3__i_3)) + (portref I2 (instanceref s_axi_wdata_3__i_4)) + (portref I2 (instanceref s_axi_wdata_4__i_7)) + (portref I2 (instanceref s_axi_wdata_5__i_3)) + (portref I2 (instanceref s_axi_wdata_6__i_4)) + (portref I2 (instanceref s_axi_wdata_6__i_5)) + (portref I2 (instanceref s_axi_wdata_6__i_6)) + (portref I3 (instanceref msg_indx_3__i_1)) + (portref I3 (instanceref msg_indx_5__i_1)) + (portref I3 (instanceref s_axi_wdata_6__i_7)) + (portref I4 (instanceref s_axi_wdata_0__i_5)) + (portref I4 (instanceref s_axi_wdata_1__i_6)) + (portref I4 (instanceref s_axi_wdata_2__i_5)) + (portref I4 (instanceref s_axi_wdata_3__i_2)) + (portref I4 (instanceref s_axi_wdata_3__i_5)) + (portref I4 (instanceref s_axi_wdata_5__i_5)) + (portref Q (instanceref msg_indx_reg_0_)) + ) + ) + (net (rename msg_indx_reg__0_1_ "msg_indx_reg__0[1]") (joined + (portref I0 (instanceref msg_indx_7__i_3)) + (portref I0 (instanceref s_axi_wdata_0__i_2)) + (portref I0 (instanceref s_axi_wdata_1__i_2)) + (portref I0 (instanceref s_axi_wdata_1__i_5)) + (portref I0 (instanceref s_axi_wdata_2__i_2)) + (portref I0 (instanceref s_axi_wdata_4__i_5)) + (portref I0 (instanceref s_axi_wdata_6__i_3)) + (portref I0 (instanceref s_axi_wdata_6__i_6)) + (portref I1 (instanceref msg_indx_1__i_1)) + (portref I1 (instanceref msg_indx_2__i_1)) + (portref I1 (instanceref msg_indx_3__i_1)) + (portref I1 (instanceref msg_indx_5__i_1)) + (portref I1 (instanceref s_axi_wdata_0__i_4)) + (portref I1 (instanceref s_axi_wdata_2__i_4)) + (portref I1 (instanceref s_axi_wdata_3__i_4)) + (portref I1 (instanceref s_axi_wdata_4__i_4)) + (portref I1 (instanceref s_axi_wdata_4__i_7)) + (portref I1 (instanceref s_axi_wdata_5__i_2)) + (portref I2 (instanceref s_axi_wdata_0__i_5)) + (portref I2 (instanceref s_axi_wdata_1__i_6)) + (portref I2 (instanceref s_axi_wdata_2__i_3)) + (portref I2 (instanceref s_axi_wdata_2__i_5)) + (portref I2 (instanceref s_axi_wdata_3__i_5)) + (portref I2 (instanceref s_axi_wdata_4__i_8)) + (portref I2 (instanceref s_axi_wdata_5__i_5)) + (portref I2 (instanceref s_axi_wdata_6__i_7)) + (portref I3 (instanceref s_axi_wdata_3__i_3)) + (portref I3 (instanceref s_axi_wdata_5__i_3)) + (portref I3 (instanceref s_axi_wdata_5__i_6)) + (portref I3 (instanceref s_axi_wdata_6__i_4)) + (portref I4 (instanceref msg_indx_4__i_1)) + (portref I4 (instanceref s_axi_wdata_6__i_5)) + (portref I4 (instanceref upg_done_o_i_2)) + (portref I5 (instanceref s_axi_wdata_3__i_2)) + (portref Q (instanceref msg_indx_reg_1_)) + ) + ) + (net (rename msg_indx_reg__0_2_ "msg_indx_reg__0[2]") (joined + (portref I0 (instanceref msg_indx_2__i_1)) + (portref I0 (instanceref s_axi_wdata_4__i_7)) + (portref I1 (instanceref msg_indx_7__i_3)) + (portref I1 (instanceref s_axi_wdata_4__i_8)) + (portref I1 (instanceref s_axi_wdata_5__i_4)) + (portref I1 (instanceref s_axi_wdata_6__i_7)) + (portref I2 (instanceref msg_indx_3__i_1)) + (portref I2 (instanceref msg_indx_5__i_1)) + (portref I2 (instanceref s_axi_wdata_0__i_2)) + (portref I2 (instanceref s_axi_wdata_1__i_2)) + (portref I2 (instanceref s_axi_wdata_2__i_2)) + (portref I2 (instanceref s_axi_wdata_4__i_4)) + (portref I2 (instanceref s_axi_wdata_4__i_5)) + (portref I2 (instanceref s_axi_wdata_5__i_2)) + (portref I2 (instanceref s_axi_wdata_6__i_3)) + (portref I3 (instanceref msg_indx_4__i_1)) + (portref I3 (instanceref s_axi_wdata_2__i_3)) + (portref I3 (instanceref s_axi_wdata_3__i_2)) + (portref I3 (instanceref upg_done_o_i_2)) + (portref I4 (instanceref s_axi_wdata_0__i_4)) + (portref I4 (instanceref s_axi_wdata_2__i_4)) + (portref I4 (instanceref s_axi_wdata_3__i_3)) + (portref I4 (instanceref s_axi_wdata_3__i_4)) + (portref I4 (instanceref s_axi_wdata_5__i_3)) + (portref I4 (instanceref s_axi_wdata_5__i_6)) + (portref I4 (instanceref s_axi_wdata_6__i_4)) + (portref I4 (instanceref s_axi_wdata_6__i_6)) + (portref I5 (instanceref s_axi_wdata_1__i_5)) + (portref Q (instanceref msg_indx_reg_2_)) + ) + ) + (net (rename msg_indx_reg__0_3_ "msg_indx_reg__0[3]") (joined + (portref I0 (instanceref msg_indx_3__i_1)) + (portref I0 (instanceref s_axi_wdata_4__i_8)) + (portref I0 (instanceref s_axi_wdata_5__i_4)) + (portref I0 (instanceref upg_done_o_i_3)) + (portref I1 (instanceref msg_indx_4__i_1)) + (portref I2 (instanceref s_axi_wdata_3__i_2)) + (portref I3 (instanceref msg_indx_7__i_3)) + (portref I3 (instanceref s_axi_wdata_0__i_2)) + (portref I3 (instanceref s_axi_wdata_2__i_2)) + (portref I3 (instanceref s_axi_wdata_4__i_4)) + (portref I3 (instanceref s_axi_wdata_5__i_2)) + (portref I3 (instanceref s_axi_wdata_6__i_2)) + (portref I4 (instanceref msg_indx_5__i_1)) + (portref I4 (instanceref s_axi_wdata_2__i_1)) + (portref I4 (instanceref s_axi_wdata_3__i_1)) + (portref I4 (instanceref s_axi_wdata_4__i_5)) + (portref I5 (instanceref s_axi_wdata_0__i_3)) + (portref I5 (instanceref s_axi_wdata_1__i_2)) + (portref I5 (instanceref s_axi_wdata_1__i_3)) + (portref I5 (instanceref s_axi_wdata_2__i_3)) + (portref I5 (instanceref s_axi_wdata_3__i_3)) + (portref I5 (instanceref s_axi_wdata_5__i_3)) + (portref I5 (instanceref s_axi_wdata_6__i_3)) + (portref I5 (instanceref s_axi_wdata_6__i_4)) + (portref Q (instanceref msg_indx_reg_3_)) + ) + ) + (net (rename msg_indx_reg__0_4_ "msg_indx_reg__0[4]") (joined + (portref I0 (instanceref msg_indx_4__i_1)) + (portref I1 (instanceref s_axi_wdata_3__i_2)) + (portref I1 (instanceref upg_done_o_i_3)) + (portref I3 (instanceref s_axi_wdata_1__i_4)) + (portref I3 (instanceref s_axi_wdata_4__i_5)) + (portref I4 (instanceref msg_indx_7__i_3)) + (portref I4 (instanceref s_axi_wdata_0__i_2)) + (portref I4 (instanceref s_axi_wdata_1__i_2)) + (portref I4 (instanceref s_axi_wdata_2__i_2)) + (portref I4 (instanceref s_axi_wdata_5__i_2)) + (portref I4 (instanceref s_axi_wdata_6__i_3)) + (portref I5 (instanceref msg_indx_5__i_1)) + (portref Q (instanceref msg_indx_reg_4_)) + ) + ) + (net (rename msg_indx_reg__0_5_ "msg_indx_reg__0[5]") (joined + (portref I0 (instanceref msg_indx_5__i_1)) + (portref I0 (instanceref s_axi_wdata_3__i_2)) + (portref I2 (instanceref s_axi_wdata_1__i_4)) + (portref I2 (instanceref upg_done_o_i_2)) + (portref I3 (instanceref s_axi_wdata_1__i_2)) + (portref I3 (instanceref s_axi_wdata_6__i_3)) + (portref I5 (instanceref msg_indx_7__i_3)) + (portref I5 (instanceref s_axi_wdata_0__i_2)) + (portref I5 (instanceref s_axi_wdata_2__i_2)) + (portref I5 (instanceref s_axi_wdata_4__i_5)) + (portref I5 (instanceref s_axi_wdata_5__i_2)) + (portref Q (instanceref msg_indx_reg_5_)) + ) + ) + (net (rename msg_indx_reg__1_6_ "msg_indx_reg__1[6]") (joined + (portref I0 (instanceref msg_indx_6__i_1)) + (portref I1 (instanceref s_axi_wdata_1__i_4)) + (portref I1 (instanceref upg_done_o_i_2)) + (portref I2 (instanceref msg_indx_7__i_2)) + (portref Q (instanceref msg_indx_reg_6_)) + ) + ) + (net (rename msg_indx_reg__1_7_ "msg_indx_reg__1[7]") (joined + (portref I0 (instanceref msg_indx_7__i_2)) + (portref I0 (instanceref s_axi_wdata_1__i_4)) + (portref I0 (instanceref upg_done_o_i_2)) + (portref Q (instanceref msg_indx_reg_7_)) + ) + ) + (net oldInitF_i_1_n_0 (joined + (portref D (instanceref oldInitF_reg)) + (portref O (instanceref oldInitF_i_1)) + ) + ) + (net oldInitF_reg_n_0 (joined + (portref I1 (instanceref WCS_0__i_2)) + (portref I4 (instanceref oldInitF_i_1)) + (portref Q (instanceref oldInitF_reg)) + ) + ) + (net (rename p_0_in_0_ "p_0_in[0]") (joined + (portref D (instanceref upg_adr_o_reg_0_)) + (portref Q (instanceref byte_cnt_reg_2_)) + (portref (member S 2) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename p_0_in_10_ "p_0_in[10]") (joined + (portref D (instanceref upg_adr_o_reg_10_)) + (portref Q (instanceref byte_cnt_reg_12_)) + (portref (member S 0) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in_11_ "p_0_in[11]") (joined + (portref D (instanceref upg_adr_o_reg_11_)) + (portref Q (instanceref byte_cnt_reg_13_)) + (portref (member S 3) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_12_ "p_0_in[12]") (joined + (portref D (instanceref upg_adr_o_reg_12_)) + (portref Q (instanceref byte_cnt_reg_14_)) + (portref (member S 2) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_13_ "p_0_in[13]") (joined + (portref D (instanceref upg_adr_o_reg_13_)) + (portref Q (instanceref byte_cnt_reg_15_)) + (portref (member S 1) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_14_ "p_0_in[14]") (joined + (portref D (instanceref upg_adr_o_reg_14_)) + (portref Q (instanceref byte_cnt_reg_16_)) + (portref (member S 0) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename p_0_in_1_ "p_0_in[1]") (joined + (portref D (instanceref upg_adr_o_reg_1_)) + (portref Q (instanceref byte_cnt_reg_3_)) + (portref (member S 1) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename p_0_in_2_ "p_0_in[2]") (joined + (portref D (instanceref upg_adr_o_reg_2_)) + (portref Q (instanceref byte_cnt_reg_4_)) + (portref (member S 0) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename p_0_in_3_ "p_0_in[3]") (joined + (portref D (instanceref upg_adr_o_reg_3_)) + (portref Q (instanceref byte_cnt_reg_5_)) + (portref (member S 3) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_4_ "p_0_in[4]") (joined + (portref D (instanceref upg_adr_o_reg_4_)) + (portref Q (instanceref byte_cnt_reg_6_)) + (portref (member S 2) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_5_ "p_0_in[5]") (joined + (portref D (instanceref upg_adr_o_reg_5_)) + (portref Q (instanceref byte_cnt_reg_7_)) + (portref (member S 1) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_6_ "p_0_in[6]") (joined + (portref D (instanceref upg_adr_o_reg_6_)) + (portref Q (instanceref byte_cnt_reg_8_)) + (portref (member S 0) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename p_0_in_7_ "p_0_in[7]") (joined + (portref D (instanceref upg_adr_o_reg_7_)) + (portref Q (instanceref byte_cnt_reg_9_)) + (portref (member S 3) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in_8_ "p_0_in[8]") (joined + (portref D (instanceref upg_adr_o_reg_8_)) + (portref Q (instanceref byte_cnt_reg_10_)) + (portref (member S 2) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in_9_ "p_0_in[9]") (joined + (portref D (instanceref upg_adr_o_reg_9_)) + (portref Q (instanceref byte_cnt_reg_11_)) + (portref (member S 1) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename p_0_in__0_0_ "p_0_in__0[0]") (joined + (portref D (instanceref msg_indx_reg_0_)) + (portref O (instanceref msg_indx_0__i_1)) + ) + ) + (net (rename p_0_in__0_1_ "p_0_in__0[1]") (joined + (portref D (instanceref msg_indx_reg_1_)) + (portref O (instanceref msg_indx_1__i_1)) + ) + ) + (net (rename p_0_in__0_2_ "p_0_in__0[2]") (joined + (portref D (instanceref msg_indx_reg_2_)) + (portref O (instanceref msg_indx_2__i_1)) + ) + ) + (net (rename p_0_in__0_3_ "p_0_in__0[3]") (joined + (portref D (instanceref msg_indx_reg_3_)) + (portref O (instanceref msg_indx_3__i_1)) + ) + ) + (net (rename p_0_in__0_4_ "p_0_in__0[4]") (joined + (portref D (instanceref msg_indx_reg_4_)) + (portref O (instanceref msg_indx_4__i_1)) + ) + ) + (net (rename p_0_in__0_5_ "p_0_in__0[5]") (joined + (portref D (instanceref msg_indx_reg_5_)) + (portref O (instanceref msg_indx_5__i_1)) + ) + ) + (net (rename p_0_in__0_6_ "p_0_in__0[6]") (joined + (portref D (instanceref msg_indx_reg_6_)) + (portref O (instanceref msg_indx_6__i_1)) + ) + ) + (net (rename p_0_in__0_7_ "p_0_in__0[7]") (joined + (portref D (instanceref msg_indx_reg_7_)) + (portref O (instanceref msg_indx_7__i_2)) + ) + ) + (net rdStat (joined + (portref I (instanceref rdStat_BUFG_inst)) + (portref I0 (instanceref s_axi_araddr_3__i_1)) + (portref I0 (instanceref s_axi_arvalid_i_3)) + (portref I2 (instanceref RCS_1__i_1)) + (portref I2 (instanceref statReg_0__i_1)) + (portref I3 (instanceref rdStat_i_1)) + (portref I5 (instanceref uart_rdat_7__i_1)) + (portref Q (instanceref rdStat_reg)) + ) + ) + (net rdStat_BUFG (joined + (portref C (instanceref bn_ascii_reg_0_)) + (portref C (instanceref bn_ascii_reg_10_)) + (portref C (instanceref bn_ascii_reg_11_)) + (portref C (instanceref bn_ascii_reg_13_)) + (portref C (instanceref bn_ascii_reg_14_)) + (portref C (instanceref bn_ascii_reg_16_)) + (portref C (instanceref bn_ascii_reg_17_)) + (portref C (instanceref bn_ascii_reg_18_)) + (portref C (instanceref bn_ascii_reg_19_)) + (portref C (instanceref bn_ascii_reg_1_)) + (portref C (instanceref bn_ascii_reg_21_)) + (portref C (instanceref bn_ascii_reg_22_)) + (portref C (instanceref bn_ascii_reg_24_)) + (portref C (instanceref bn_ascii_reg_25_)) + (portref C (instanceref bn_ascii_reg_26_)) + (portref C (instanceref bn_ascii_reg_27_)) + (portref C (instanceref bn_ascii_reg_29_)) + (portref C (instanceref bn_ascii_reg_2_)) + (portref C (instanceref bn_ascii_reg_30_)) + (portref C (instanceref bn_ascii_reg_32_)) + (portref C (instanceref bn_ascii_reg_33_)) + (portref C (instanceref bn_ascii_reg_34_)) + (portref C (instanceref bn_ascii_reg_35_)) + (portref C (instanceref bn_ascii_reg_37_)) + (portref C (instanceref bn_ascii_reg_38_)) + (portref C (instanceref bn_ascii_reg_3_)) + (portref C (instanceref bn_ascii_reg_40_)) + (portref C (instanceref bn_ascii_reg_41_)) + (portref C (instanceref bn_ascii_reg_42_)) + (portref C (instanceref bn_ascii_reg_43_)) + (portref C (instanceref bn_ascii_reg_45_)) + (portref C (instanceref bn_ascii_reg_46_)) + (portref C (instanceref bn_ascii_reg_48_)) + (portref C (instanceref bn_ascii_reg_49_)) + (portref C (instanceref bn_ascii_reg_50_)) + (portref C (instanceref bn_ascii_reg_51_)) + (portref C (instanceref bn_ascii_reg_53_)) + (portref C (instanceref bn_ascii_reg_54_)) + (portref C (instanceref bn_ascii_reg_56_)) + (portref C (instanceref bn_ascii_reg_57_)) + (portref C (instanceref bn_ascii_reg_58_)) + (portref C (instanceref bn_ascii_reg_59_)) + (portref C (instanceref bn_ascii_reg_5_)) + (portref C (instanceref bn_ascii_reg_61_)) + (portref C (instanceref bn_ascii_reg_62_)) + (portref C (instanceref bn_ascii_reg_6_)) + (portref C (instanceref bn_ascii_reg_8_)) + (portref C (instanceref bn_ascii_reg_9_)) + (portref C (instanceref byte_cnt_reg_0_)) + (portref C (instanceref byte_cnt_reg_10_)) + (portref C (instanceref byte_cnt_reg_11_)) + (portref C (instanceref byte_cnt_reg_12_)) + (portref C (instanceref byte_cnt_reg_13_)) + (portref C (instanceref byte_cnt_reg_14_)) + (portref C (instanceref byte_cnt_reg_15_)) + (portref C (instanceref byte_cnt_reg_16_)) + (portref C (instanceref byte_cnt_reg_17_)) + (portref C (instanceref byte_cnt_reg_18_)) + (portref C (instanceref byte_cnt_reg_19_)) + (portref C (instanceref byte_cnt_reg_1_)) + (portref C (instanceref byte_cnt_reg_20_)) + (portref C (instanceref byte_cnt_reg_21_)) + (portref C (instanceref byte_cnt_reg_22_)) + (portref C (instanceref byte_cnt_reg_23_)) + (portref C (instanceref byte_cnt_reg_24_)) + (portref C (instanceref byte_cnt_reg_25_)) + (portref C (instanceref byte_cnt_reg_26_)) + (portref C (instanceref byte_cnt_reg_27_)) + (portref C (instanceref byte_cnt_reg_28_)) + (portref C (instanceref byte_cnt_reg_29_)) + (portref C (instanceref byte_cnt_reg_2_)) + (portref C (instanceref byte_cnt_reg_30_)) + (portref C (instanceref byte_cnt_reg_31_)) + (portref C (instanceref byte_cnt_reg_3_)) + (portref C (instanceref byte_cnt_reg_4_)) + (portref C (instanceref byte_cnt_reg_5_)) + (portref C (instanceref byte_cnt_reg_6_)) + (portref C (instanceref byte_cnt_reg_7_)) + (portref C (instanceref byte_cnt_reg_8_)) + (portref C (instanceref byte_cnt_reg_9_)) + (portref C (instanceref byte_len_reg_0_)) + (portref C (instanceref byte_len_reg_1_)) + (portref C (instanceref byte_len_reg_2_)) + (portref C (instanceref byte_len_reg_3_)) + (portref C (instanceref byte_len_reg_4_)) + (portref C (instanceref byte_len_reg_5_)) + (portref C (instanceref byte_len_reg_6_)) + (portref C (instanceref byte_len_reg_7_)) + (portref C (instanceref byte_num_reg_0_)) + (portref C (instanceref byte_num_reg_10_)) + (portref C (instanceref byte_num_reg_11_)) + (portref C (instanceref byte_num_reg_12_)) + (portref C (instanceref byte_num_reg_13_)) + (portref C (instanceref byte_num_reg_14_)) + (portref C (instanceref byte_num_reg_15_)) + (portref C (instanceref byte_num_reg_16_)) + (portref C (instanceref byte_num_reg_17_)) + (portref C (instanceref byte_num_reg_18_)) + (portref C (instanceref byte_num_reg_19_)) + (portref C (instanceref byte_num_reg_1_)) + (portref C (instanceref byte_num_reg_20_)) + (portref C (instanceref byte_num_reg_21_)) + (portref C (instanceref byte_num_reg_22_)) + (portref C (instanceref byte_num_reg_23_)) + (portref C (instanceref byte_num_reg_24_)) + (portref C (instanceref byte_num_reg_25_)) + (portref C (instanceref byte_num_reg_26_)) + (portref C (instanceref byte_num_reg_27_)) + (portref C (instanceref byte_num_reg_28_)) + (portref C (instanceref byte_num_reg_29_)) + (portref C (instanceref byte_num_reg_2_)) + (portref C (instanceref byte_num_reg_30_)) + (portref C (instanceref byte_num_reg_31_)) + (portref C (instanceref byte_num_reg_3_)) + (portref C (instanceref byte_num_reg_4_)) + (portref C (instanceref byte_num_reg_5_)) + (portref C (instanceref byte_num_reg_6_)) + (portref C (instanceref byte_num_reg_7_)) + (portref C (instanceref byte_num_reg_8_)) + (portref C (instanceref byte_num_reg_9_)) + (portref C (instanceref dbuf_reg_0_)) + (portref C (instanceref dbuf_reg_10_)) + (portref C (instanceref dbuf_reg_11_)) + (portref C (instanceref dbuf_reg_12_)) + (portref C (instanceref dbuf_reg_13_)) + (portref C (instanceref dbuf_reg_14_)) + (portref C (instanceref dbuf_reg_15_)) + (portref C (instanceref dbuf_reg_16_)) + (portref C (instanceref dbuf_reg_17_)) + (portref C (instanceref dbuf_reg_18_)) + (portref C (instanceref dbuf_reg_19_)) + (portref C (instanceref dbuf_reg_1_)) + (portref C (instanceref dbuf_reg_20_)) + (portref C (instanceref dbuf_reg_21_)) + (portref C (instanceref dbuf_reg_22_)) + (portref C (instanceref dbuf_reg_23_)) + (portref C (instanceref dbuf_reg_2_)) + (portref C (instanceref dbuf_reg_3_)) + (portref C (instanceref dbuf_reg_4_)) + (portref C (instanceref dbuf_reg_5_)) + (portref C (instanceref dbuf_reg_6_)) + (portref C (instanceref dbuf_reg_7_)) + (portref C (instanceref dbuf_reg_8_)) + (portref C (instanceref dbuf_reg_9_)) + (portref C (instanceref disp_reg_0_)) + (portref C (instanceref disp_reg_1_)) + (portref C (instanceref disp_reg_2_)) + (portref C (instanceref disp_reg_3_)) + (portref C (instanceref disp_reg_4_)) + (portref C (instanceref disp_reg_5_)) + (portref C (instanceref disp_reg_6_)) + (portref C (instanceref disp_reg_7_)) + (portref C (instanceref len_cnt_reg_0_)) + (portref C (instanceref len_cnt_reg_1_)) + (portref C (instanceref len_cnt_reg_2_)) + (portref C (instanceref len_cnt_reg_3_)) + (portref C (instanceref recv_done_reg)) + (portref C (instanceref rx_done_reg)) + (portref C (instanceref upg_adr_o_reg_0_)) + (portref C (instanceref upg_adr_o_reg_10_)) + (portref C (instanceref upg_adr_o_reg_11_)) + (portref C (instanceref upg_adr_o_reg_12_)) + (portref C (instanceref upg_adr_o_reg_13_)) + (portref C (instanceref upg_adr_o_reg_14_)) + (portref C (instanceref upg_adr_o_reg_1_)) + (portref C (instanceref upg_adr_o_reg_2_)) + (portref C (instanceref upg_adr_o_reg_3_)) + (portref C (instanceref upg_adr_o_reg_4_)) + (portref C (instanceref upg_adr_o_reg_5_)) + (portref C (instanceref upg_adr_o_reg_6_)) + (portref C (instanceref upg_adr_o_reg_7_)) + (portref C (instanceref upg_adr_o_reg_8_)) + (portref C (instanceref upg_adr_o_reg_9_)) + (portref C (instanceref upg_dat_o_reg_0_)) + (portref C (instanceref upg_dat_o_reg_10_)) + (portref C (instanceref upg_dat_o_reg_11_)) + (portref C (instanceref upg_dat_o_reg_12_)) + (portref C (instanceref upg_dat_o_reg_13_)) + (portref C (instanceref upg_dat_o_reg_14_)) + (portref C (instanceref upg_dat_o_reg_15_)) + (portref C (instanceref upg_dat_o_reg_16_)) + (portref C (instanceref upg_dat_o_reg_17_)) + (portref C (instanceref upg_dat_o_reg_18_)) + (portref C (instanceref upg_dat_o_reg_19_)) + (portref C (instanceref upg_dat_o_reg_1_)) + (portref C (instanceref upg_dat_o_reg_20_)) + (portref C (instanceref upg_dat_o_reg_21_)) + (portref C (instanceref upg_dat_o_reg_22_)) + (portref C (instanceref upg_dat_o_reg_23_)) + (portref C (instanceref upg_dat_o_reg_24_)) + (portref C (instanceref upg_dat_o_reg_25_)) + (portref C (instanceref upg_dat_o_reg_26_)) + (portref C (instanceref upg_dat_o_reg_27_)) + (portref C (instanceref upg_dat_o_reg_28_)) + (portref C (instanceref upg_dat_o_reg_29_)) + (portref C (instanceref upg_dat_o_reg_2_)) + (portref C (instanceref upg_dat_o_reg_30_)) + (portref C (instanceref upg_dat_o_reg_31_)) + (portref C (instanceref upg_dat_o_reg_3_)) + (portref C (instanceref upg_dat_o_reg_4_)) + (portref C (instanceref upg_dat_o_reg_5_)) + (portref C (instanceref upg_dat_o_reg_6_)) + (portref C (instanceref upg_dat_o_reg_7_)) + (portref C (instanceref upg_dat_o_reg_8_)) + (portref C (instanceref upg_dat_o_reg_9_)) + (portref C (instanceref upg_wen_o_reg)) + (portref C (instanceref wr_byte_len_done_reg)) + (portref C (instanceref wr_byte_num_done_reg)) + (portref O (instanceref rdStat_BUFG_inst)) + ) + ) + (net rdStat_i_1_n_0 (joined + (portref D (instanceref rdStat_reg)) + (portref O (instanceref rdStat_i_1)) + ) + ) + (net recv_done0 (joined + (portref (member CO 0) (instanceref recv_done_reg_i_2)) + (portref I0 (instanceref recv_done_i_1)) + ) + ) + (net (rename recv_done1_0_ "recv_done1[0]") (joined + (portref D (instanceref byte_cnt_reg_0_)) + (portref O (instanceref byte_cnt_0__i_1)) + ) + ) + (net (rename recv_done1_10_ "recv_done1[10]") (joined + (portref D (instanceref byte_cnt_reg_10_)) + (portref I2 (instanceref recv_done_i_24)) + (portref I3 (instanceref recv_done_i_28)) + (portref (member O 2) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename recv_done1_11_ "recv_done1[11]") (joined + (portref D (instanceref byte_cnt_reg_11_)) + (portref I0 (instanceref recv_done_i_24)) + (portref I1 (instanceref recv_done_i_28)) + (portref (member O 1) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename recv_done1_12_ "recv_done1[12]") (joined + (portref D (instanceref byte_cnt_reg_12_)) + (portref I2 (instanceref recv_done_i_23)) + (portref I3 (instanceref recv_done_i_27)) + (portref (member O 0) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net (rename recv_done1_13_ "recv_done1[13]") (joined + (portref D (instanceref byte_cnt_reg_13_)) + (portref I0 (instanceref recv_done_i_23)) + (portref I1 (instanceref recv_done_i_27)) + (portref (member O 3) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_14_ "recv_done1[14]") (joined + (portref D (instanceref byte_cnt_reg_14_)) + (portref I2 (instanceref recv_done_i_22)) + (portref I3 (instanceref recv_done_i_26)) + (portref (member O 2) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_15_ "recv_done1[15]") (joined + (portref D (instanceref byte_cnt_reg_15_)) + (portref I0 (instanceref recv_done_i_22)) + (portref I1 (instanceref recv_done_i_26)) + (portref (member O 1) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_16_ "recv_done1[16]") (joined + (portref D (instanceref byte_cnt_reg_16_)) + (portref I2 (instanceref recv_done_i_16)) + (portref I3 (instanceref recv_done_i_20)) + (portref (member O 0) (instanceref byte_cnt_reg_16__i_1)) + ) + ) + (net (rename recv_done1_17_ "recv_done1[17]") (joined + (portref D (instanceref byte_cnt_reg_17_)) + (portref I0 (instanceref recv_done_i_16)) + (portref I1 (instanceref recv_done_i_20)) + (portref (member O 3) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_18_ "recv_done1[18]") (joined + (portref D (instanceref byte_cnt_reg_18_)) + (portref I2 (instanceref recv_done_i_15)) + (portref I3 (instanceref recv_done_i_19)) + (portref (member O 2) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_19_ "recv_done1[19]") (joined + (portref D (instanceref byte_cnt_reg_19_)) + (portref I0 (instanceref recv_done_i_15)) + (portref I1 (instanceref recv_done_i_19)) + (portref (member O 1) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_1_ "recv_done1[1]") (joined + (portref D (instanceref byte_cnt_reg_1_)) + (portref I0 (instanceref recv_done_i_33)) + (portref I3 (instanceref recv_done_i_37)) + (portref (member O 3) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_20_ "recv_done1[20]") (joined + (portref D (instanceref byte_cnt_reg_20_)) + (portref I2 (instanceref recv_done_i_14)) + (portref I3 (instanceref recv_done_i_18)) + (portref (member O 0) (instanceref byte_cnt_reg_20__i_1)) + ) + ) + (net (rename recv_done1_21_ "recv_done1[21]") (joined + (portref D (instanceref byte_cnt_reg_21_)) + (portref I0 (instanceref recv_done_i_14)) + (portref I1 (instanceref recv_done_i_18)) + (portref (member O 3) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_22_ "recv_done1[22]") (joined + (portref D (instanceref byte_cnt_reg_22_)) + (portref I2 (instanceref recv_done_i_13)) + (portref I3 (instanceref recv_done_i_17)) + (portref (member O 2) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_23_ "recv_done1[23]") (joined + (portref D (instanceref byte_cnt_reg_23_)) + (portref I0 (instanceref recv_done_i_13)) + (portref I1 (instanceref recv_done_i_17)) + (portref (member O 1) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_24_ "recv_done1[24]") (joined + (portref D (instanceref byte_cnt_reg_24_)) + (portref I2 (instanceref recv_done_i_7)) + (portref I3 (instanceref recv_done_i_11)) + (portref (member O 0) (instanceref byte_cnt_reg_24__i_1)) + ) + ) + (net (rename recv_done1_25_ "recv_done1[25]") (joined + (portref D (instanceref byte_cnt_reg_25_)) + (portref I0 (instanceref recv_done_i_7)) + (portref I1 (instanceref recv_done_i_11)) + (portref (member O 3) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_26_ "recv_done1[26]") (joined + (portref D (instanceref byte_cnt_reg_26_)) + (portref I2 (instanceref recv_done_i_6)) + (portref I3 (instanceref recv_done_i_10)) + (portref (member O 2) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_27_ "recv_done1[27]") (joined + (portref D (instanceref byte_cnt_reg_27_)) + (portref I0 (instanceref recv_done_i_6)) + (portref I1 (instanceref recv_done_i_10)) + (portref (member O 1) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_28_ "recv_done1[28]") (joined + (portref D (instanceref byte_cnt_reg_28_)) + (portref I2 (instanceref recv_done_i_5)) + (portref I3 (instanceref recv_done_i_9)) + (portref (member O 0) (instanceref byte_cnt_reg_28__i_1)) + ) + ) + (net (rename recv_done1_29_ "recv_done1[29]") (joined + (portref D (instanceref byte_cnt_reg_29_)) + (portref I0 (instanceref recv_done_i_5)) + (portref I1 (instanceref recv_done_i_9)) + (portref (member O 3) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename recv_done1_2_ "recv_done1[2]") (joined + (portref D (instanceref byte_cnt_reg_2_)) + (portref I2 (instanceref recv_done_i_32)) + (portref I3 (instanceref recv_done_i_36)) + (portref (member O 2) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_30_ "recv_done1[30]") (joined + (portref D (instanceref byte_cnt_reg_30_)) + (portref I2 (instanceref recv_done_i_4)) + (portref I3 (instanceref recv_done_i_8)) + (portref (member O 2) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename recv_done1_31_ "recv_done1[31]") (joined + (portref D (instanceref byte_cnt_reg_31_)) + (portref I0 (instanceref recv_done_i_4)) + (portref I1 (instanceref recv_done_i_8)) + (portref (member O 1) (instanceref byte_cnt_reg_31__i_2)) + ) + ) + (net (rename recv_done1_3_ "recv_done1[3]") (joined + (portref D (instanceref byte_cnt_reg_3_)) + (portref I0 (instanceref recv_done_i_32)) + (portref I1 (instanceref recv_done_i_36)) + (portref (member O 1) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_4_ "recv_done1[4]") (joined + (portref D (instanceref byte_cnt_reg_4_)) + (portref I2 (instanceref recv_done_i_31)) + (portref I3 (instanceref recv_done_i_35)) + (portref (member O 0) (instanceref byte_cnt_reg_4__i_1)) + ) + ) + (net (rename recv_done1_5_ "recv_done1[5]") (joined + (portref D (instanceref byte_cnt_reg_5_)) + (portref I0 (instanceref recv_done_i_31)) + (portref I1 (instanceref recv_done_i_35)) + (portref (member O 3) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_6_ "recv_done1[6]") (joined + (portref D (instanceref byte_cnt_reg_6_)) + (portref I2 (instanceref recv_done_i_30)) + (portref I3 (instanceref recv_done_i_34)) + (portref (member O 2) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_7_ "recv_done1[7]") (joined + (portref D (instanceref byte_cnt_reg_7_)) + (portref I0 (instanceref recv_done_i_30)) + (portref I1 (instanceref recv_done_i_34)) + (portref (member O 1) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_8_ "recv_done1[8]") (joined + (portref D (instanceref byte_cnt_reg_8_)) + (portref I2 (instanceref recv_done_i_25)) + (portref I3 (instanceref recv_done_i_29)) + (portref (member O 0) (instanceref byte_cnt_reg_8__i_1)) + ) + ) + (net (rename recv_done1_9_ "recv_done1[9]") (joined + (portref D (instanceref byte_cnt_reg_9_)) + (portref I0 (instanceref recv_done_i_25)) + (portref I1 (instanceref recv_done_i_29)) + (portref (member O 3) (instanceref byte_cnt_reg_12__i_1)) + ) + ) + (net recv_done_i_10_n_0 (joined + (portref O (instanceref recv_done_i_10)) + (portref (member S 2) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_i_11_n_0 (joined + (portref O (instanceref recv_done_i_11)) + (portref (member S 3) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_i_13_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_13)) + ) + ) + (net recv_done_i_14_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_14)) + ) + ) + (net recv_done_i_15_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_15)) + ) + ) + (net recv_done_i_16_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_3)) + (portref O (instanceref recv_done_i_16)) + ) + ) + (net recv_done_i_17_n_0 (joined + (portref O (instanceref recv_done_i_17)) + (portref (member S 0) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_18_n_0 (joined + (portref O (instanceref recv_done_i_18)) + (portref (member S 1) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_19_n_0 (joined + (portref O (instanceref recv_done_i_19)) + (portref (member S 2) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_1_n_0 (joined + (portref D (instanceref recv_done_reg)) + (portref O (instanceref recv_done_i_1)) + ) + ) + (net recv_done_i_20_n_0 (joined + (portref O (instanceref recv_done_i_20)) + (portref (member S 3) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_i_22_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_22)) + ) + ) + (net recv_done_i_23_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_23)) + ) + ) + (net recv_done_i_24_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_24)) + ) + ) + (net recv_done_i_25_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_12)) + (portref O (instanceref recv_done_i_25)) + ) + ) + (net recv_done_i_26_n_0 (joined + (portref O (instanceref recv_done_i_26)) + (portref (member S 0) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_27_n_0 (joined + (portref O (instanceref recv_done_i_27)) + (portref (member S 1) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_28_n_0 (joined + (portref O (instanceref recv_done_i_28)) + (portref (member S 2) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_29_n_0 (joined + (portref O (instanceref recv_done_i_29)) + (portref (member S 3) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_i_30_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_30)) + ) + ) + (net recv_done_i_31_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_31)) + ) + ) + (net recv_done_i_32_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_32)) + ) + ) + (net recv_done_i_33_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_21)) + (portref O (instanceref recv_done_i_33)) + ) + ) + (net recv_done_i_34_n_0 (joined + (portref O (instanceref recv_done_i_34)) + (portref (member S 0) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_35_n_0 (joined + (portref O (instanceref recv_done_i_35)) + (portref (member S 1) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_36_n_0 (joined + (portref O (instanceref recv_done_i_36)) + (portref (member S 2) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_37_n_0 (joined + (portref O (instanceref recv_done_i_37)) + (portref (member S 3) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_i_4_n_0 (joined + (portref (member DI 0) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_4)) + ) + ) + (net recv_done_i_5_n_0 (joined + (portref (member DI 1) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_5)) + ) + ) + (net recv_done_i_6_n_0 (joined + (portref (member DI 2) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_6)) + ) + ) + (net recv_done_i_7_n_0 (joined + (portref (member DI 3) (instanceref recv_done_reg_i_2)) + (portref O (instanceref recv_done_i_7)) + ) + ) + (net recv_done_i_8_n_0 (joined + (portref O (instanceref recv_done_i_8)) + (portref (member S 0) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_i_9_n_0 (joined + (portref O (instanceref recv_done_i_9)) + (portref (member S 1) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_12_n_0 (joined + (portref CI (instanceref recv_done_reg_i_3)) + (portref (member CO 0) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_12_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_12_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_12_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_12)) + ) + ) + (net recv_done_reg_i_21_n_0 (joined + (portref CI (instanceref recv_done_reg_i_12)) + (portref (member CO 0) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_21_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_21_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_21_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_21)) + ) + ) + (net recv_done_reg_i_2_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_2_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_2_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_2)) + ) + ) + (net recv_done_reg_i_3_n_0 (joined + (portref CI (instanceref recv_done_reg_i_2)) + (portref (member CO 0) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_i_3_n_1 (joined + (portref (member CO 1) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_i_3_n_2 (joined + (portref (member CO 2) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_i_3_n_3 (joined + (portref (member CO 3) (instanceref recv_done_reg_i_3)) + ) + ) + (net recv_done_reg_n_0 (joined + (portref I0 (instanceref byte_cnt_31__i_1)) + (portref I0 (instanceref disp_5__i_2)) + (portref I0 (instanceref disp_5__i_4)) + (portref I0 (instanceref disp_7__i_1)) + (portref I0 (instanceref rx_done_i_1)) + (portref I1 (instanceref disp_3__i_2)) + (portref I1 (instanceref disp_6__i_1)) + (portref I1 (instanceref disp_6__i_2)) + (portref I1 (instanceref upg_wen_o_i_4)) + (portref I3 (instanceref disp_0__i_1)) + (portref I3 (instanceref disp_1__i_3)) + (portref I3 (instanceref disp_2__i_1)) + (portref I3 (instanceref disp_5__i_3)) + (portref I4 (instanceref disp_1__i_1)) + (portref I4 (instanceref disp_2__i_2)) + (portref I4 (instanceref recv_done_i_1)) + (portref I4 (instanceref upg_wen_o_i_6)) + (portref I5 (instanceref disp_3__i_1)) + (portref I5 (instanceref disp_4__i_1)) + (portref Q (instanceref recv_done_reg)) + ) + ) + (net (rename rwait_cnt_0_ "rwait_cnt[0]") (joined + (portref D (instanceref rwait_cnt_reg_0_)) + (portref O (instanceref rwait_cnt_0__i_1)) + ) + ) + (net (rename rwait_cnt_10_ "rwait_cnt[10]") (joined + (portref D (instanceref rwait_cnt_reg_10_)) + (portref O (instanceref rwait_cnt_10__i_1)) + ) + ) + (net (rename rwait_cnt_11_ "rwait_cnt[11]") (joined + (portref D (instanceref rwait_cnt_reg_11_)) + (portref O (instanceref rwait_cnt_11__i_1)) + ) + ) + (net (rename rwait_cnt_12_ "rwait_cnt[12]") (joined + (portref D (instanceref rwait_cnt_reg_12_)) + (portref O (instanceref rwait_cnt_12__i_1)) + ) + ) + (net (rename rwait_cnt_13_ "rwait_cnt[13]") (joined + (portref D (instanceref rwait_cnt_reg_13_)) + (portref O (instanceref rwait_cnt_13__i_1)) + ) + ) + (net (rename rwait_cnt_14_ "rwait_cnt[14]") (joined + (portref D (instanceref rwait_cnt_reg_14_)) + (portref O (instanceref rwait_cnt_14__i_1)) + ) + ) + (net (rename rwait_cnt_15_ "rwait_cnt[15]") (joined + (portref D (instanceref rwait_cnt_reg_15_)) + (portref O (instanceref rwait_cnt_15__i_2)) + ) + ) + (net (rename rwait_cnt_15__i_1_n_0 "rwait_cnt[15]_i_1_n_0") (joined + (portref CE (instanceref rwait_cnt_reg_0_)) + (portref CE (instanceref rwait_cnt_reg_10_)) + (portref CE (instanceref rwait_cnt_reg_11_)) + (portref CE (instanceref rwait_cnt_reg_12_)) + (portref CE (instanceref rwait_cnt_reg_13_)) + (portref CE (instanceref rwait_cnt_reg_14_)) + (portref CE (instanceref rwait_cnt_reg_15_)) + (portref CE (instanceref rwait_cnt_reg_1_)) + (portref CE (instanceref rwait_cnt_reg_2_)) + (portref CE (instanceref rwait_cnt_reg_3_)) + (portref CE (instanceref rwait_cnt_reg_4_)) + (portref CE (instanceref rwait_cnt_reg_5_)) + (portref CE (instanceref rwait_cnt_reg_6_)) + (portref CE (instanceref rwait_cnt_reg_7_)) + (portref CE (instanceref rwait_cnt_reg_8_)) + (portref CE (instanceref rwait_cnt_reg_9_)) + (portref O (instanceref rwait_cnt_15__i_1)) + ) + ) + (net (rename rwait_cnt_15__i_4_n_0 "rwait_cnt[15]_i_4_n_0") (joined + (portref I0 (instanceref RCS_2__i_1)) + (portref I1 (instanceref rwait_cnt_0__i_1)) + (portref I1 (instanceref rwait_cnt_10__i_1)) + (portref I1 (instanceref rwait_cnt_11__i_1)) + (portref I1 (instanceref rwait_cnt_12__i_1)) + (portref I1 (instanceref rwait_cnt_13__i_1)) + (portref I1 (instanceref rwait_cnt_14__i_1)) + (portref I1 (instanceref rwait_cnt_15__i_2)) + (portref I1 (instanceref rwait_cnt_1__i_1)) + (portref I1 (instanceref rwait_cnt_2__i_1)) + (portref I1 (instanceref rwait_cnt_3__i_1)) + (portref I1 (instanceref rwait_cnt_4__i_1)) + (portref I1 (instanceref rwait_cnt_5__i_1)) + (portref I1 (instanceref rwait_cnt_6__i_1)) + (portref I1 (instanceref rwait_cnt_7__i_1)) + (portref I1 (instanceref rwait_cnt_8__i_1)) + (portref I1 (instanceref rwait_cnt_9__i_1)) + (portref O (instanceref rwait_cnt_15__i_4)) + ) + ) + (net (rename rwait_cnt_15__i_5_n_0 "rwait_cnt[15]_i_5_n_0") (joined + (portref I0 (instanceref rwait_cnt_15__i_4)) + (portref O (instanceref rwait_cnt_15__i_5)) + ) + ) + (net (rename rwait_cnt_15__i_6_n_0 "rwait_cnt[15]_i_6_n_0") (joined + (portref I5 (instanceref rwait_cnt_15__i_4)) + (portref O (instanceref rwait_cnt_15__i_6)) + ) + ) + (net (rename rwait_cnt_15__i_7_n_0 "rwait_cnt[15]_i_7_n_0") (joined + (portref I4 (instanceref rwait_cnt_15__i_6)) + (portref O (instanceref rwait_cnt_15__i_7)) + ) + ) + (net (rename rwait_cnt_1_ "rwait_cnt[1]") (joined + (portref D (instanceref rwait_cnt_reg_1_)) + (portref O (instanceref rwait_cnt_1__i_1)) + ) + ) + (net (rename rwait_cnt_2_ "rwait_cnt[2]") (joined + (portref D (instanceref rwait_cnt_reg_2_)) + (portref O (instanceref rwait_cnt_2__i_1)) + ) + ) + (net (rename rwait_cnt_3_ "rwait_cnt[3]") (joined + (portref D (instanceref rwait_cnt_reg_3_)) + (portref O (instanceref rwait_cnt_3__i_1)) + ) + ) + (net (rename rwait_cnt_4_ "rwait_cnt[4]") (joined + (portref D (instanceref rwait_cnt_reg_4_)) + (portref O (instanceref rwait_cnt_4__i_1)) + ) + ) + (net (rename rwait_cnt_5_ "rwait_cnt[5]") (joined + (portref D (instanceref rwait_cnt_reg_5_)) + (portref O (instanceref rwait_cnt_5__i_1)) + ) + ) + (net (rename rwait_cnt_6_ "rwait_cnt[6]") (joined + (portref D (instanceref rwait_cnt_reg_6_)) + (portref O (instanceref rwait_cnt_6__i_1)) + ) + ) + (net (rename rwait_cnt_7_ "rwait_cnt[7]") (joined + (portref D (instanceref rwait_cnt_reg_7_)) + (portref O (instanceref rwait_cnt_7__i_1)) + ) + ) + (net (rename rwait_cnt_8_ "rwait_cnt[8]") (joined + (portref D (instanceref rwait_cnt_reg_8_)) + (portref O (instanceref rwait_cnt_8__i_1)) + ) + ) + (net (rename rwait_cnt_9_ "rwait_cnt[9]") (joined + (portref D (instanceref rwait_cnt_reg_9_)) + (portref O (instanceref rwait_cnt_9__i_1)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_0 "rwait_cnt_reg[12]_i_2_n_0") (joined + (portref CI (instanceref rwait_cnt_reg_15__i_3)) + (portref (member CO 0) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_1 "rwait_cnt_reg[12]_i_2_n_1") (joined + (portref (member CO 1) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_2 "rwait_cnt_reg[12]_i_2_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_3 "rwait_cnt_reg[12]_i_2_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_4 "rwait_cnt_reg[12]_i_2_n_4") (joined + (portref I0 (instanceref rwait_cnt_12__i_1)) + (portref (member O 0) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_5 "rwait_cnt_reg[12]_i_2_n_5") (joined + (portref I0 (instanceref rwait_cnt_11__i_1)) + (portref (member O 1) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_6 "rwait_cnt_reg[12]_i_2_n_6") (joined + (portref I0 (instanceref rwait_cnt_10__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_12__i_2_n_7 "rwait_cnt_reg[12]_i_2_n_7") (joined + (portref I0 (instanceref rwait_cnt_9__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_2 "rwait_cnt_reg[15]_i_3_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_3 "rwait_cnt_reg[15]_i_3_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_5 "rwait_cnt_reg[15]_i_3_n_5") (joined + (portref I0 (instanceref rwait_cnt_15__i_2)) + (portref (member O 1) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_6 "rwait_cnt_reg[15]_i_3_n_6") (joined + (portref I0 (instanceref rwait_cnt_14__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_15__i_3_n_7 "rwait_cnt_reg[15]_i_3_n_7") (joined + (portref I0 (instanceref rwait_cnt_13__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_0 "rwait_cnt_reg[4]_i_2_n_0") (joined + (portref CI (instanceref rwait_cnt_reg_8__i_2)) + (portref (member CO 0) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_1 "rwait_cnt_reg[4]_i_2_n_1") (joined + (portref (member CO 1) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_2 "rwait_cnt_reg[4]_i_2_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_3 "rwait_cnt_reg[4]_i_2_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_4 "rwait_cnt_reg[4]_i_2_n_4") (joined + (portref I0 (instanceref rwait_cnt_4__i_1)) + (portref (member O 0) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_5 "rwait_cnt_reg[4]_i_2_n_5") (joined + (portref I0 (instanceref rwait_cnt_3__i_1)) + (portref (member O 1) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_6 "rwait_cnt_reg[4]_i_2_n_6") (joined + (portref I0 (instanceref rwait_cnt_2__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_4__i_2_n_7 "rwait_cnt_reg[4]_i_2_n_7") (joined + (portref I0 (instanceref rwait_cnt_1__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_0 "rwait_cnt_reg[8]_i_2_n_0") (joined + (portref CI (instanceref rwait_cnt_reg_12__i_2)) + (portref (member CO 0) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_1 "rwait_cnt_reg[8]_i_2_n_1") (joined + (portref (member CO 1) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_2 "rwait_cnt_reg[8]_i_2_n_2") (joined + (portref (member CO 2) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_3 "rwait_cnt_reg[8]_i_2_n_3") (joined + (portref (member CO 3) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_4 "rwait_cnt_reg[8]_i_2_n_4") (joined + (portref I0 (instanceref rwait_cnt_8__i_1)) + (portref (member O 0) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_5 "rwait_cnt_reg[8]_i_2_n_5") (joined + (portref I0 (instanceref rwait_cnt_7__i_1)) + (portref (member O 1) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_6 "rwait_cnt_reg[8]_i_2_n_6") (joined + (portref I0 (instanceref rwait_cnt_6__i_1)) + (portref (member O 2) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_8__i_2_n_7 "rwait_cnt_reg[8]_i_2_n_7") (joined + (portref I0 (instanceref rwait_cnt_5__i_1)) + (portref (member O 3) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__0_ "rwait_cnt_reg_n_0_[0]") (joined + (portref CYINIT (instanceref rwait_cnt_reg_4__i_2)) + (portref I0 (instanceref rwait_cnt_0__i_1)) + (portref I2 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_0_)) + ) + ) + (net (rename rwait_cnt_reg_n_0__10_ "rwait_cnt_reg_n_0_[10]") (joined + (portref I1 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_10_)) + (portref (member S 2) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__11_ "rwait_cnt_reg_n_0_[11]") (joined + (portref I4 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_11_)) + (portref (member S 1) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__12_ "rwait_cnt_reg_n_0_[12]") (joined + (portref I0 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_12_)) + (portref (member S 0) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__13_ "rwait_cnt_reg_n_0_[13]") (joined + (portref I1 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_13_)) + (portref (member S 3) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_n_0__14_ "rwait_cnt_reg_n_0_[14]") (joined + (portref I0 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_14_)) + (portref (member S 2) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_n_0__15_ "rwait_cnt_reg_n_0_[15]") (joined + (portref I3 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_15_)) + (portref (member S 1) (instanceref rwait_cnt_reg_15__i_3)) + ) + ) + (net (rename rwait_cnt_reg_n_0__1_ "rwait_cnt_reg_n_0_[1]") (joined + (portref I1 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_1_)) + (portref (member S 3) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__2_ "rwait_cnt_reg_n_0_[2]") (joined + (portref I1 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_2_)) + (portref (member S 2) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__3_ "rwait_cnt_reg_n_0_[3]") (joined + (portref I2 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_3_)) + (portref (member S 1) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__4_ "rwait_cnt_reg_n_0_[4]") (joined + (portref I0 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_4_)) + (portref (member S 0) (instanceref rwait_cnt_reg_4__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__5_ "rwait_cnt_reg_n_0_[5]") (joined + (portref I2 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_5_)) + (portref (member S 3) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__6_ "rwait_cnt_reg_n_0_[6]") (joined + (portref I3 (instanceref rwait_cnt_15__i_6)) + (portref Q (instanceref rwait_cnt_reg_6_)) + (portref (member S 2) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__7_ "rwait_cnt_reg_n_0_[7]") (joined + (portref I2 (instanceref rwait_cnt_15__i_5)) + (portref Q (instanceref rwait_cnt_reg_7_)) + (portref (member S 1) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__8_ "rwait_cnt_reg_n_0_[8]") (joined + (portref I3 (instanceref rwait_cnt_15__i_4)) + (portref Q (instanceref rwait_cnt_reg_8_)) + (portref (member S 0) (instanceref rwait_cnt_reg_8__i_2)) + ) + ) + (net (rename rwait_cnt_reg_n_0__9_ "rwait_cnt_reg_n_0_[9]") (joined + (portref I3 (instanceref rwait_cnt_15__i_7)) + (portref Q (instanceref rwait_cnt_reg_9_)) + (portref (member S 3) (instanceref rwait_cnt_reg_12__i_2)) + ) + ) + (net rx_done (joined + (portref I0 (instanceref upg_wen_o_i_1)) + (portref I1 (instanceref rx_done_i_1)) + (portref O (instanceref upg_wen_o_i_3)) + ) + ) + (net rx_done_i_1_n_0 (joined + (portref D (instanceref rx_done_reg)) + (portref O (instanceref rx_done_i_1)) + ) + ) + (net rx_done_reg_n_0 (joined + (portref I0 (instanceref disp_6__i_1)) + (portref I0 (instanceref upg_wen_o_i_4)) + (portref I1 (instanceref disp_5__i_4)) + (portref I1 (instanceref disp_7__i_1)) + (portref I2 (instanceref disp_2__i_1)) + (portref I2 (instanceref disp_3__i_2)) + (portref I2 (instanceref disp_5__i_3)) + (portref I2 (instanceref rx_done_i_1)) + (portref I2 (instanceref s_axi_wdata_4__i_3)) + (portref I3 (instanceref s_axi_wstrb_3__i_1)) + (portref I3 (instanceref upg_wen_o_i_6)) + (portref I4 (instanceref disp_1__i_3)) + (portref I4 (instanceref disp_3__i_1)) + (portref I4 (instanceref disp_4__i_1)) + (portref Q (instanceref rx_done_reg)) + ) + ) + (net (rename s_axi_araddr_3__i_1_n_0 "s_axi_araddr[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_araddr_reg_3_)) + (portref O (instanceref s_axi_araddr_3__i_1)) + ) + ) + (net (rename s_axi_araddr_reg_n_0__3_ "s_axi_araddr_reg_n_0_[3]") (joined + (portref I5 (instanceref s_axi_araddr_3__i_1)) + (portref Q (instanceref s_axi_araddr_reg_3_)) + (portref (member s_axi_araddr 0) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_aresetn0 (joined + (portref CE (instanceref disp_reg_0_)) + (portref CE (instanceref disp_reg_1_)) + (portref CE (instanceref disp_reg_2_)) + (portref CE (instanceref disp_reg_3_)) + (portref CE (instanceref disp_reg_4_)) + (portref CE (instanceref disp_reg_5_)) + (portref CE (instanceref disp_reg_6_)) + (portref CE (instanceref disp_reg_7_)) + (portref O (instanceref axi_uart_inst_i_1)) + (portref s_axi_aresetn (instanceref axi_uart_inst)) + ) + ) + (net s_axi_arready (joined + (portref I0 (instanceref s_axi_arvalid_i_1)) + (portref I1 (instanceref RCS_0__i_1)) + (portref s_axi_arready (instanceref axi_uart_inst)) + ) + ) + (net s_axi_arvalid (joined + (portref I5 (instanceref s_axi_arvalid_i_1)) + (portref Q (instanceref s_axi_arvalid_reg)) + (portref s_axi_arvalid (instanceref axi_uart_inst)) + ) + ) + (net s_axi_arvalid_i_1_n_0 (joined + (portref D (instanceref s_axi_arvalid_reg)) + (portref O (instanceref s_axi_arvalid_i_1)) + ) + ) + (net s_axi_arvalid_i_2_n_0 (joined + (portref I1 (instanceref s_axi_arvalid_i_1)) + (portref O (instanceref s_axi_arvalid_i_2)) + ) + ) + (net s_axi_arvalid_i_3_n_0 (joined + (portref I3 (instanceref s_axi_arvalid_i_1)) + (portref O (instanceref s_axi_arvalid_i_3)) + ) + ) + (net (rename s_axi_awaddr_3__i_1_n_0 "s_axi_awaddr[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_awaddr_reg_3_)) + (portref O (instanceref s_axi_awaddr_3__i_1)) + ) + ) + (net (rename s_axi_awaddr_reg_n_0__3_ "s_axi_awaddr_reg_n_0_[3]") (joined + (portref I5 (instanceref s_axi_awaddr_3__i_1)) + (portref Q (instanceref s_axi_awaddr_reg_3_)) + (portref (member s_axi_awaddr 0) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_awready (joined + (portref I0 (instanceref WCS_1__i_1)) + (portref I0 (instanceref s_axi_awvalid_i_2)) + (portref I1 (instanceref WCS_2__i_1)) + (portref s_axi_awready (instanceref axi_uart_inst)) + ) + ) + (net s_axi_awvalid_i_1_n_0 (joined + (portref D (instanceref s_axi_awvalid_reg)) + (portref O (instanceref s_axi_awvalid_i_1)) + ) + ) + (net s_axi_awvalid_i_2_n_0 (joined + (portref I0 (instanceref s_axi_awvalid_i_1)) + (portref O (instanceref s_axi_awvalid_i_2)) + ) + ) + (net (rename s_axi_rdata_0_ "s_axi_rdata[0]") (joined + (portref D (instanceref uart_rdat_reg_0_)) + (portref I0 (instanceref statReg_0__i_1)) + (portref (member s_axi_rdata 31) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_1_ "s_axi_rdata[1]") (joined + (portref D (instanceref uart_rdat_reg_1_)) + (portref (member s_axi_rdata 30) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_2_ "s_axi_rdata[2]") (joined + (portref D (instanceref uart_rdat_reg_2_)) + (portref (member s_axi_rdata 29) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_3_ "s_axi_rdata[3]") (joined + (portref D (instanceref uart_rdat_reg_3_)) + (portref (member s_axi_rdata 28) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_4_ "s_axi_rdata[4]") (joined + (portref D (instanceref uart_rdat_reg_4_)) + (portref (member s_axi_rdata 27) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_5_ "s_axi_rdata[5]") (joined + (portref D (instanceref uart_rdat_reg_5_)) + (portref (member s_axi_rdata 26) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_6_ "s_axi_rdata[6]") (joined + (portref D (instanceref uart_rdat_reg_6_)) + (portref (member s_axi_rdata 25) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_rdata_7_ "s_axi_rdata[7]") (joined + (portref D (instanceref uart_rdat_reg_7_)) + (portref (member s_axi_rdata 24) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_rvalid (joined + (portref I0 (instanceref RCS_0__i_1)) + (portref I0 (instanceref RCS_1__i_1)) + (portref I0 (instanceref uart_rdat_7__i_1)) + (portref I1 (instanceref RCS_2__i_1)) + (portref I1 (instanceref rdStat_i_1)) + (portref I2 (instanceref statReg_0__i_2)) + (portref s_axi_rvalid (instanceref axi_uart_inst)) + ) + ) + (net s_axi_wdata (joined + (portref CE (instanceref s_axi_wdata_reg_0_)) + (portref CE (instanceref s_axi_wdata_reg_1_)) + (portref CE (instanceref s_axi_wdata_reg_2_)) + (portref CE (instanceref s_axi_wdata_reg_3_)) + (portref CE (instanceref s_axi_wdata_reg_4_)) + (portref CE (instanceref s_axi_wdata_reg_5_)) + (portref CE (instanceref s_axi_wdata_reg_6_)) + (portref CE (instanceref s_axi_wstrb_reg_3_)) + (portref O (instanceref s_axi_wdata_4__i_1)) + ) + ) + (net (rename s_axi_wdata_0__i_1_n_0 "s_axi_wdata[0]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_0_)) + (portref O (instanceref s_axi_wdata_0__i_1)) + ) + ) + (net (rename s_axi_wdata_0__i_2_n_0 "s_axi_wdata[0]_i_2_n_0") (joined + (portref I2 (instanceref s_axi_wdata_0__i_1)) + (portref O (instanceref s_axi_wdata_0__i_2)) + ) + ) + (net (rename s_axi_wdata_0__i_3_n_0 "s_axi_wdata[0]_i_3_n_0") (joined + (portref I3 (instanceref s_axi_wdata_0__i_1)) + (portref O (instanceref s_axi_wdata_0__i_3)) + ) + ) + (net (rename s_axi_wdata_0__i_4_n_0 "s_axi_wdata[0]_i_4_n_0") (joined + (portref I4 (instanceref s_axi_wdata_0__i_3)) + (portref O (instanceref s_axi_wdata_0__i_4)) + ) + ) + (net (rename s_axi_wdata_0__i_5_n_0 "s_axi_wdata[0]_i_5_n_0") (joined + (portref I5 (instanceref s_axi_wdata_0__i_4)) + (portref O (instanceref s_axi_wdata_0__i_5)) + ) + ) + (net (rename s_axi_wdata_1__i_1_n_0 "s_axi_wdata[1]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_1_)) + (portref O (instanceref s_axi_wdata_1__i_1)) + ) + ) + (net (rename s_axi_wdata_1__i_2_n_0 "s_axi_wdata[1]_i_2_n_0") (joined + (portref I2 (instanceref s_axi_wdata_1__i_1)) + (portref O (instanceref s_axi_wdata_1__i_2)) + ) + ) + (net (rename s_axi_wdata_1__i_3_n_0 "s_axi_wdata[1]_i_3_n_0") (joined + (portref I3 (instanceref s_axi_wdata_1__i_1)) + (portref O (instanceref s_axi_wdata_1__i_3)) + ) + ) + (net (rename s_axi_wdata_1__i_4_n_0 "s_axi_wdata[1]_i_4_n_0") (joined + (portref I0 (instanceref s_axi_wdata_4__i_4)) + (portref I0 (instanceref s_axi_wdata_4__i_6)) + (portref I4 (instanceref s_axi_wdata_0__i_1)) + (portref I4 (instanceref s_axi_wdata_1__i_1)) + (portref I4 (instanceref s_axi_wdata_5__i_1)) + (portref I5 (instanceref s_axi_wdata_2__i_1)) + (portref I5 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_1__i_4)) + ) + ) + (net (rename s_axi_wdata_1__i_5_n_0 "s_axi_wdata[1]_i_5_n_0") (joined + (portref I4 (instanceref s_axi_wdata_1__i_3)) + (portref O (instanceref s_axi_wdata_1__i_5)) + ) + ) + (net (rename s_axi_wdata_1__i_6_n_0 "s_axi_wdata[1]_i_6_n_0") (joined + (portref I4 (instanceref s_axi_wdata_1__i_5)) + (portref O (instanceref s_axi_wdata_1__i_6)) + ) + ) + (net (rename s_axi_wdata_2__i_1_n_0 "s_axi_wdata[2]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_2_)) + (portref O (instanceref s_axi_wdata_2__i_1)) + ) + ) + (net (rename s_axi_wdata_2__i_2_n_0 "s_axi_wdata[2]_i_2_n_0") (joined + (portref I1 (instanceref s_axi_wdata_2__i_1)) + (portref O (instanceref s_axi_wdata_2__i_2)) + ) + ) + (net (rename s_axi_wdata_2__i_3_n_0 "s_axi_wdata[2]_i_3_n_0") (joined + (portref I2 (instanceref s_axi_wdata_2__i_1)) + (portref O (instanceref s_axi_wdata_2__i_3)) + ) + ) + (net (rename s_axi_wdata_2__i_4_n_0 "s_axi_wdata[2]_i_4_n_0") (joined + (portref I3 (instanceref s_axi_wdata_2__i_1)) + (portref O (instanceref s_axi_wdata_2__i_4)) + ) + ) + (net (rename s_axi_wdata_2__i_5_n_0 "s_axi_wdata[2]_i_5_n_0") (joined + (portref I5 (instanceref s_axi_wdata_2__i_4)) + (portref O (instanceref s_axi_wdata_2__i_5)) + ) + ) + (net (rename s_axi_wdata_3__i_1_n_0 "s_axi_wdata[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_3_)) + (portref O (instanceref s_axi_wdata_3__i_1)) + ) + ) + (net (rename s_axi_wdata_3__i_2_n_0 "s_axi_wdata[3]_i_2_n_0") (joined + (portref I1 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_3__i_2)) + ) + ) + (net (rename s_axi_wdata_3__i_3_n_0 "s_axi_wdata[3]_i_3_n_0") (joined + (portref I2 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_3__i_3)) + ) + ) + (net (rename s_axi_wdata_3__i_4_n_0 "s_axi_wdata[3]_i_4_n_0") (joined + (portref I3 (instanceref s_axi_wdata_3__i_1)) + (portref O (instanceref s_axi_wdata_3__i_4)) + ) + ) + (net (rename s_axi_wdata_3__i_5_n_0 "s_axi_wdata[3]_i_5_n_0") (joined + (portref I5 (instanceref s_axi_wdata_3__i_4)) + (portref O (instanceref s_axi_wdata_3__i_5)) + ) + ) + (net (rename s_axi_wdata_4__i_2_n_0 "s_axi_wdata[4]_i_2_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_4_)) + (portref O (instanceref s_axi_wdata_4__i_2)) + ) + ) + (net (rename s_axi_wdata_4__i_4_n_0 "s_axi_wdata[4]_i_4_n_0") (joined + (portref I0 (instanceref s_axi_wdata_2__i_1)) + (portref I0 (instanceref s_axi_wdata_3__i_1)) + (portref I0 (instanceref s_axi_wdata_5__i_1)) + (portref I1 (instanceref s_axi_wdata_0__i_1)) + (portref I1 (instanceref s_axi_wdata_1__i_1)) + (portref I1 (instanceref s_axi_wdata_4__i_2)) + (portref I2 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_4__i_4)) + ) + ) + (net (rename s_axi_wdata_4__i_5_n_0 "s_axi_wdata[4]_i_5_n_0") (joined + (portref I2 (instanceref s_axi_wdata_4__i_2)) + (portref O (instanceref s_axi_wdata_4__i_5)) + ) + ) + (net (rename s_axi_wdata_4__i_6_n_0 "s_axi_wdata[4]_i_6_n_0") (joined + (portref I3 (instanceref s_axi_wdata_4__i_2)) + (portref O (instanceref s_axi_wdata_4__i_6)) + ) + ) + (net (rename s_axi_wdata_4__i_7_n_0 "s_axi_wdata[4]_i_7_n_0") (joined + (portref I1 (instanceref s_axi_wdata_0__i_3)) + (portref I1 (instanceref s_axi_wdata_1__i_3)) + (portref I3 (instanceref s_axi_wdata_4__i_6)) + (portref O (instanceref s_axi_wdata_4__i_7)) + ) + ) + (net (rename s_axi_wdata_4__i_8_n_0 "s_axi_wdata[4]_i_8_n_0") (joined + (portref I0 (instanceref s_axi_wdata_0__i_3)) + (portref I0 (instanceref s_axi_wdata_1__i_3)) + (portref I5 (instanceref s_axi_wdata_4__i_6)) + (portref O (instanceref s_axi_wdata_4__i_8)) + ) + ) + (net (rename s_axi_wdata_5__i_1_n_0 "s_axi_wdata[5]_i_1_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_5_)) + (portref O (instanceref s_axi_wdata_5__i_1)) + ) + ) + (net (rename s_axi_wdata_5__i_2_n_0 "s_axi_wdata[5]_i_2_n_0") (joined + (portref I1 (instanceref s_axi_wdata_5__i_1)) + (portref O (instanceref s_axi_wdata_5__i_2)) + ) + ) + (net (rename s_axi_wdata_5__i_3_n_0 "s_axi_wdata[5]_i_3_n_0") (joined + (portref I2 (instanceref s_axi_wdata_5__i_1)) + (portref O (instanceref s_axi_wdata_5__i_3)) + ) + ) + (net (rename s_axi_wdata_5__i_4_n_0 "s_axi_wdata[5]_i_4_n_0") (joined + (portref I1 (instanceref s_axi_wdata_4__i_6)) + (portref I3 (instanceref s_axi_wdata_5__i_1)) + (portref O (instanceref s_axi_wdata_5__i_4)) + ) + ) + (net (rename s_axi_wdata_5__i_5_n_0 "s_axi_wdata[5]_i_5_n_0") (joined + (portref I2 (instanceref s_axi_wdata_5__i_4)) + (portref O (instanceref s_axi_wdata_5__i_5)) + ) + ) + (net (rename s_axi_wdata_5__i_6_n_0 "s_axi_wdata[5]_i_6_n_0") (joined + (portref I3 (instanceref s_axi_wdata_5__i_4)) + (portref O (instanceref s_axi_wdata_5__i_6)) + ) + ) + (net (rename s_axi_wdata_6__i_1_n_0 "s_axi_wdata[6]_i_1_n_0") (joined + (portref O (instanceref s_axi_wdata_6__i_1)) + (portref R (instanceref s_axi_wdata_reg_2_)) + (portref R (instanceref s_axi_wdata_reg_3_)) + (portref R (instanceref s_axi_wdata_reg_5_)) + (portref R (instanceref s_axi_wdata_reg_6_)) + ) + ) + (net (rename s_axi_wdata_6__i_2_n_0 "s_axi_wdata[6]_i_2_n_0") (joined + (portref D (instanceref s_axi_wdata_reg_6_)) + (portref O (instanceref s_axi_wdata_6__i_2)) + ) + ) + (net (rename s_axi_wdata_6__i_3_n_0 "s_axi_wdata[6]_i_3_n_0") (joined + (portref I0 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_6__i_3)) + ) + ) + (net (rename s_axi_wdata_6__i_4_n_0 "s_axi_wdata[6]_i_4_n_0") (joined + (portref I1 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_6__i_4)) + ) + ) + (net (rename s_axi_wdata_6__i_5_n_0 "s_axi_wdata[6]_i_5_n_0") (joined + (portref I4 (instanceref s_axi_wdata_6__i_2)) + (portref O (instanceref s_axi_wdata_6__i_5)) + ) + ) + (net (rename s_axi_wdata_6__i_6_n_0 "s_axi_wdata[6]_i_6_n_0") (joined + (portref I0 (instanceref s_axi_wdata_6__i_5)) + (portref O (instanceref s_axi_wdata_6__i_6)) + ) + ) + (net (rename s_axi_wdata_6__i_7_n_0 "s_axi_wdata[6]_i_7_n_0") (joined + (portref I5 (instanceref s_axi_wdata_6__i_5)) + (portref O (instanceref s_axi_wdata_6__i_7)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__0_ "s_axi_wdata_reg_n_0_[0]") (joined + (portref Q (instanceref s_axi_wdata_reg_0_)) + (portref (member s_axi_wdata 31) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__1_ "s_axi_wdata_reg_n_0_[1]") (joined + (portref Q (instanceref s_axi_wdata_reg_1_)) + (portref (member s_axi_wdata 30) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__2_ "s_axi_wdata_reg_n_0_[2]") (joined + (portref Q (instanceref s_axi_wdata_reg_2_)) + (portref (member s_axi_wdata 29) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__3_ "s_axi_wdata_reg_n_0_[3]") (joined + (portref Q (instanceref s_axi_wdata_reg_3_)) + (portref (member s_axi_wdata 28) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__4_ "s_axi_wdata_reg_n_0_[4]") (joined + (portref Q (instanceref s_axi_wdata_reg_4_)) + (portref (member s_axi_wdata 27) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__5_ "s_axi_wdata_reg_n_0_[5]") (joined + (portref Q (instanceref s_axi_wdata_reg_5_)) + (portref (member s_axi_wdata 26) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wdata_reg_n_0__6_ "s_axi_wdata_reg_n_0_[6]") (joined + (portref Q (instanceref s_axi_wdata_reg_6_)) + (portref (member s_axi_wdata 25) (instanceref axi_uart_inst)) + ) + ) + (net s_axi_wready (joined + (portref I0 (instanceref WCS_2__i_1)) + (portref I1 (instanceref WCS_1__i_1)) + (portref I1 (instanceref s_axi_awvalid_i_2)) + (portref s_axi_wready (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wstrb_3_ "s_axi_wstrb[3]") (joined + (portref Q (instanceref s_axi_wstrb_reg_3_)) + (portref (member s_axi_wstrb 3) (instanceref axi_uart_inst)) + (portref (member s_axi_wstrb 2) (instanceref axi_uart_inst)) + (portref (member s_axi_wstrb 1) (instanceref axi_uart_inst)) + (portref (member s_axi_wstrb 0) (instanceref axi_uart_inst)) + ) + ) + (net (rename s_axi_wstrb_3__i_1_n_0 "s_axi_wstrb[3]_i_1_n_0") (joined + (portref D (instanceref s_axi_wstrb_reg_3_)) + (portref I2 (instanceref WCS_0__i_1)) + (portref I2 (instanceref WCS_1__i_1)) + (portref O (instanceref s_axi_wstrb_3__i_1)) + ) + ) + (net s_axi_wvalid (joined + (portref I4 (instanceref s_axi_awvalid_i_1)) + (portref Q (instanceref s_axi_awvalid_reg)) + (portref s_axi_awvalid (instanceref axi_uart_inst)) + (portref s_axi_wvalid (instanceref axi_uart_inst)) + ) + ) + (net (rename statReg_0__i_1_n_0 "statReg[0]_i_1_n_0") (joined + (portref D (instanceref statReg_reg_0_)) + (portref O (instanceref statReg_0__i_1)) + ) + ) + (net (rename statReg_0__i_2_n_0 "statReg[0]_i_2_n_0") (joined + (portref I1 (instanceref statReg_0__i_1)) + (portref O (instanceref statReg_0__i_2)) + ) + ) + (net (rename statReg_reg_n_0__0_ "statReg_reg_n_0_[0]") (joined + (portref I1 (instanceref RCS_1__i_1)) + (portref I1 (instanceref bn_ascii_62__i_1)) + (portref I1 (instanceref byte_len_7__i_1)) + (portref I1 (instanceref byte_num_31__i_1)) + (portref I1 (instanceref disp_0__i_1)) + (portref I1 (instanceref s_axi_arvalid_i_3)) + (portref I2 (instanceref byte_cnt_31__i_1)) + (portref I2 (instanceref disp_1__i_1)) + (portref I2 (instanceref disp_2__i_2)) + (portref I2 (instanceref disp_3__i_1)) + (portref I2 (instanceref disp_4__i_1)) + (portref I2 (instanceref recv_done_i_1)) + (portref I3 (instanceref disp_5__i_1)) + (portref I4 (instanceref disp_6__i_1)) + (portref I4 (instanceref disp_6__i_2)) + (portref I4 (instanceref disp_7__i_1)) + (portref I4 (instanceref rdStat_i_1)) + (portref I4 (instanceref statReg_0__i_1)) + (portref Q (instanceref statReg_reg_0_)) + ) + ) + (net uart_rdat (joined + (portref CE (instanceref uart_rdat_reg_0_)) + (portref CE (instanceref uart_rdat_reg_1_)) + (portref CE (instanceref uart_rdat_reg_2_)) + (portref CE (instanceref uart_rdat_reg_3_)) + (portref CE (instanceref uart_rdat_reg_4_)) + (portref CE (instanceref uart_rdat_reg_5_)) + (portref CE (instanceref uart_rdat_reg_6_)) + (portref CE (instanceref uart_rdat_reg_7_)) + (portref O (instanceref uart_rdat_7__i_1)) + ) + ) + (net (rename uart_rdat_reg_n_0__0_ "uart_rdat_reg_n_0_[0]") (joined + (portref D (instanceref byte_len_reg_0_)) + (portref D (instanceref byte_num_reg_0_)) + (portref D (instanceref dbuf_reg_0_)) + (portref D (instanceref upg_dat_o_reg_0_)) + (portref I0 (instanceref bn_ascii_0__i_1)) + (portref I0 (instanceref bn_ascii_1__i_1)) + (portref I3 (instanceref bn_ascii_2__i_1)) + (portref I5 (instanceref wr_byte_len_done_i_1)) + (portref Q (instanceref uart_rdat_reg_0_)) + ) + ) + (net (rename uart_rdat_reg_n_0__1_ "uart_rdat_reg_n_0_[1]") (joined + (portref D (instanceref byte_len_reg_1_)) + (portref D (instanceref byte_num_reg_1_)) + (portref D (instanceref dbuf_reg_1_)) + (portref D (instanceref upg_dat_o_reg_1_)) + (portref I0 (instanceref bn_ascii_2__i_1)) + (portref I0 (instanceref bn_ascii_5__i_1)) + (portref I1 (instanceref bn_ascii_0__i_1)) + (portref I2 (instanceref bn_ascii_3__i_1)) + (portref I2 (instanceref bn_ascii_6__i_1)) + (portref I3 (instanceref bn_ascii_1__i_1)) + (portref I3 (instanceref wr_byte_len_done_i_2)) + (portref Q (instanceref uart_rdat_reg_1_)) + ) + ) + (net (rename uart_rdat_reg_n_0__2_ "uart_rdat_reg_n_0_[2]") (joined + (portref D (instanceref byte_len_reg_2_)) + (portref D (instanceref byte_num_reg_2_)) + (portref D (instanceref dbuf_reg_2_)) + (portref D (instanceref upg_dat_o_reg_2_)) + (portref I1 (instanceref bn_ascii_2__i_1)) + (portref I1 (instanceref bn_ascii_3__i_1)) + (portref I1 (instanceref bn_ascii_5__i_1)) + (portref I1 (instanceref bn_ascii_6__i_1)) + (portref I2 (instanceref bn_ascii_0__i_1)) + (portref I2 (instanceref bn_ascii_1__i_1)) + (portref I2 (instanceref wr_byte_len_done_i_2)) + (portref Q (instanceref uart_rdat_reg_2_)) + ) + ) + (net (rename uart_rdat_reg_n_0__3_ "uart_rdat_reg_n_0_[3]") (joined + (portref D (instanceref byte_len_reg_3_)) + (portref D (instanceref byte_num_reg_3_)) + (portref D (instanceref dbuf_reg_3_)) + (portref D (instanceref upg_dat_o_reg_3_)) + (portref I0 (instanceref bn_ascii_3__i_1)) + (portref I0 (instanceref bn_ascii_6__i_1)) + (portref I1 (instanceref bn_ascii_1__i_1)) + (portref I2 (instanceref bn_ascii_2__i_1)) + (portref I2 (instanceref bn_ascii_5__i_1)) + (portref I3 (instanceref bn_ascii_0__i_1)) + (portref I3 (instanceref wr_byte_len_done_i_1)) + (portref Q (instanceref uart_rdat_reg_3_)) + ) + ) + (net (rename uart_rdat_reg_n_0__4_ "uart_rdat_reg_n_0_[4]") (joined + (portref D (instanceref byte_len_reg_4_)) + (portref D (instanceref byte_num_reg_4_)) + (portref D (instanceref dbuf_reg_4_)) + (portref D (instanceref upg_dat_o_reg_4_)) + (portref I0 (instanceref bn_ascii_8__i_1)) + (portref I0 (instanceref bn_ascii_9__i_1)) + (portref I2 (instanceref wr_byte_len_done_i_1)) + (portref I3 (instanceref bn_ascii_10__i_1)) + (portref Q (instanceref uart_rdat_reg_4_)) + ) + ) + (net (rename uart_rdat_reg_n_0__5_ "uart_rdat_reg_n_0_[5]") (joined + (portref D (instanceref byte_len_reg_5_)) + (portref D (instanceref byte_num_reg_5_)) + (portref D (instanceref dbuf_reg_5_)) + (portref D (instanceref upg_dat_o_reg_5_)) + (portref I0 (instanceref bn_ascii_10__i_1)) + (portref I0 (instanceref bn_ascii_13__i_1)) + (portref I1 (instanceref bn_ascii_8__i_1)) + (portref I1 (instanceref wr_byte_len_done_i_2)) + (portref I2 (instanceref bn_ascii_11__i_1)) + (portref I2 (instanceref bn_ascii_14__i_1)) + (portref I3 (instanceref bn_ascii_9__i_1)) + (portref Q (instanceref uart_rdat_reg_5_)) + ) + ) + (net (rename uart_rdat_reg_n_0__6_ "uart_rdat_reg_n_0_[6]") (joined + (portref D (instanceref byte_len_reg_6_)) + (portref D (instanceref byte_num_reg_6_)) + (portref D (instanceref dbuf_reg_6_)) + (portref D (instanceref upg_dat_o_reg_6_)) + (portref I0 (instanceref wr_byte_len_done_i_2)) + (portref I1 (instanceref bn_ascii_10__i_1)) + (portref I1 (instanceref bn_ascii_11__i_1)) + (portref I1 (instanceref bn_ascii_13__i_1)) + (portref I1 (instanceref bn_ascii_14__i_1)) + (portref I2 (instanceref bn_ascii_8__i_1)) + (portref I2 (instanceref bn_ascii_9__i_1)) + (portref Q (instanceref uart_rdat_reg_6_)) + ) + ) + (net (rename uart_rdat_reg_n_0__7_ "uart_rdat_reg_n_0_[7]") (joined + (portref D (instanceref byte_len_reg_7_)) + (portref D (instanceref byte_num_reg_7_)) + (portref D (instanceref dbuf_reg_7_)) + (portref D (instanceref upg_dat_o_reg_7_)) + (portref I0 (instanceref bn_ascii_11__i_1)) + (portref I0 (instanceref bn_ascii_14__i_1)) + (portref I1 (instanceref bn_ascii_9__i_1)) + (portref I2 (instanceref bn_ascii_10__i_1)) + (portref I2 (instanceref bn_ascii_13__i_1)) + (portref I3 (instanceref bn_ascii_8__i_1)) + (portref I4 (instanceref wr_byte_len_done_i_1)) + (portref Q (instanceref uart_rdat_reg_7_)) + ) + ) + (net uart_wen5_out (joined + (portref I0 (instanceref msg_indx_7__i_1)) + (portref I0 (instanceref uart_wen_i_1)) + (portref I1 (instanceref s_axi_awvalid_i_1)) + (portref I3 (instanceref s_axi_wdata_4__i_1)) + (portref O (instanceref s_axi_wdata_4__i_3)) + ) + ) + (net uart_wen_i_1_n_0 (joined + (portref D (instanceref uart_wen_reg)) + (portref O (instanceref uart_wen_i_1)) + ) + ) + (net uart_wen_reg_n_0 (joined + (portref I1 (instanceref s_axi_wdata_4__i_3)) + (portref I2 (instanceref s_axi_wstrb_3__i_1)) + (portref I5 (instanceref uart_wen_i_1)) + (portref Q (instanceref uart_wen_reg)) + ) + ) + (net (rename upg_adr_o_0_ "upg_adr_o[0]") (joined + (portref O (instanceref upg_adr_o_OBUF_0__inst)) + (portref (member upg_adr_o 14)) + ) + ) + (net (rename upg_adr_o_10_ "upg_adr_o[10]") (joined + (portref O (instanceref upg_adr_o_OBUF_10__inst)) + (portref (member upg_adr_o 4)) + ) + ) + (net (rename upg_adr_o_11_ "upg_adr_o[11]") (joined + (portref O (instanceref upg_adr_o_OBUF_11__inst)) + (portref (member upg_adr_o 3)) + ) + ) + (net (rename upg_adr_o_12_ "upg_adr_o[12]") (joined + (portref O (instanceref upg_adr_o_OBUF_12__inst)) + (portref (member upg_adr_o 2)) + ) + ) + (net (rename upg_adr_o_13_ "upg_adr_o[13]") (joined + (portref O (instanceref upg_adr_o_OBUF_13__inst)) + (portref (member upg_adr_o 1)) + ) + ) + (net (rename upg_adr_o_14_ "upg_adr_o[14]") (joined + (portref O (instanceref upg_adr_o_OBUF_14__inst)) + (portref (member upg_adr_o 0)) + ) + ) + (net (rename upg_adr_o_14__i_1_n_0 "upg_adr_o[14]_i_1_n_0") (joined + (portref CE (instanceref upg_adr_o_reg_0_)) + (portref CE (instanceref upg_adr_o_reg_10_)) + (portref CE (instanceref upg_adr_o_reg_11_)) + (portref CE (instanceref upg_adr_o_reg_12_)) + (portref CE (instanceref upg_adr_o_reg_13_)) + (portref CE (instanceref upg_adr_o_reg_14_)) + (portref CE (instanceref upg_adr_o_reg_1_)) + (portref CE (instanceref upg_adr_o_reg_2_)) + (portref CE (instanceref upg_adr_o_reg_3_)) + (portref CE (instanceref upg_adr_o_reg_4_)) + (portref CE (instanceref upg_adr_o_reg_5_)) + (portref CE (instanceref upg_adr_o_reg_6_)) + (portref CE (instanceref upg_adr_o_reg_7_)) + (portref CE (instanceref upg_adr_o_reg_8_)) + (portref CE (instanceref upg_adr_o_reg_9_)) + (portref CE (instanceref upg_dat_o_reg_0_)) + (portref CE (instanceref upg_dat_o_reg_10_)) + (portref CE (instanceref upg_dat_o_reg_11_)) + (portref CE (instanceref upg_dat_o_reg_12_)) + (portref CE (instanceref upg_dat_o_reg_13_)) + (portref CE (instanceref upg_dat_o_reg_14_)) + (portref CE (instanceref upg_dat_o_reg_15_)) + (portref CE (instanceref upg_dat_o_reg_16_)) + (portref CE (instanceref upg_dat_o_reg_17_)) + (portref CE (instanceref upg_dat_o_reg_18_)) + (portref CE (instanceref upg_dat_o_reg_19_)) + (portref CE (instanceref upg_dat_o_reg_1_)) + (portref CE (instanceref upg_dat_o_reg_20_)) + (portref CE (instanceref upg_dat_o_reg_21_)) + (portref CE (instanceref upg_dat_o_reg_22_)) + (portref CE (instanceref upg_dat_o_reg_23_)) + (portref CE (instanceref upg_dat_o_reg_24_)) + (portref CE (instanceref upg_dat_o_reg_25_)) + (portref CE (instanceref upg_dat_o_reg_26_)) + (portref CE (instanceref upg_dat_o_reg_27_)) + (portref CE (instanceref upg_dat_o_reg_28_)) + (portref CE (instanceref upg_dat_o_reg_29_)) + (portref CE (instanceref upg_dat_o_reg_2_)) + (portref CE (instanceref upg_dat_o_reg_30_)) + (portref CE (instanceref upg_dat_o_reg_31_)) + (portref CE (instanceref upg_dat_o_reg_3_)) + (portref CE (instanceref upg_dat_o_reg_4_)) + (portref CE (instanceref upg_dat_o_reg_5_)) + (portref CE (instanceref upg_dat_o_reg_6_)) + (portref CE (instanceref upg_dat_o_reg_7_)) + (portref CE (instanceref upg_dat_o_reg_8_)) + (portref CE (instanceref upg_dat_o_reg_9_)) + (portref O (instanceref upg_adr_o_14__i_1)) + ) + ) + (net (rename upg_adr_o_1_ "upg_adr_o[1]") (joined + (portref O (instanceref upg_adr_o_OBUF_1__inst)) + (portref (member upg_adr_o 13)) + ) + ) + (net (rename upg_adr_o_2_ "upg_adr_o[2]") (joined + (portref O (instanceref upg_adr_o_OBUF_2__inst)) + (portref (member upg_adr_o 12)) + ) + ) + (net (rename upg_adr_o_3_ "upg_adr_o[3]") (joined + (portref O (instanceref upg_adr_o_OBUF_3__inst)) + (portref (member upg_adr_o 11)) + ) + ) + (net (rename upg_adr_o_4_ "upg_adr_o[4]") (joined + (portref O (instanceref upg_adr_o_OBUF_4__inst)) + (portref (member upg_adr_o 10)) + ) + ) + (net (rename upg_adr_o_5_ "upg_adr_o[5]") (joined + (portref O (instanceref upg_adr_o_OBUF_5__inst)) + (portref (member upg_adr_o 9)) + ) + ) + (net (rename upg_adr_o_6_ "upg_adr_o[6]") (joined + (portref O (instanceref upg_adr_o_OBUF_6__inst)) + (portref (member upg_adr_o 8)) + ) + ) + (net (rename upg_adr_o_7_ "upg_adr_o[7]") (joined + (portref O (instanceref upg_adr_o_OBUF_7__inst)) + (portref (member upg_adr_o 7)) + ) + ) + (net (rename upg_adr_o_8_ "upg_adr_o[8]") (joined + (portref O (instanceref upg_adr_o_OBUF_8__inst)) + (portref (member upg_adr_o 6)) + ) + ) + (net (rename upg_adr_o_9_ "upg_adr_o[9]") (joined + (portref O (instanceref upg_adr_o_OBUF_9__inst)) + (portref (member upg_adr_o 5)) + ) + ) + (net (rename upg_adr_o_OBUF_0_ "upg_adr_o_OBUF[0]") (joined + (portref I (instanceref upg_adr_o_OBUF_0__inst)) + (portref Q (instanceref upg_adr_o_reg_0_)) + ) + ) + (net (rename upg_adr_o_OBUF_10_ "upg_adr_o_OBUF[10]") (joined + (portref I (instanceref upg_adr_o_OBUF_10__inst)) + (portref Q (instanceref upg_adr_o_reg_10_)) + ) + ) + (net (rename upg_adr_o_OBUF_11_ "upg_adr_o_OBUF[11]") (joined + (portref I (instanceref upg_adr_o_OBUF_11__inst)) + (portref Q (instanceref upg_adr_o_reg_11_)) + ) + ) + (net (rename upg_adr_o_OBUF_12_ "upg_adr_o_OBUF[12]") (joined + (portref I (instanceref upg_adr_o_OBUF_12__inst)) + (portref Q (instanceref upg_adr_o_reg_12_)) + ) + ) + (net (rename upg_adr_o_OBUF_13_ "upg_adr_o_OBUF[13]") (joined + (portref I (instanceref upg_adr_o_OBUF_13__inst)) + (portref Q (instanceref upg_adr_o_reg_13_)) + ) + ) + (net (rename upg_adr_o_OBUF_14_ "upg_adr_o_OBUF[14]") (joined + (portref I (instanceref upg_adr_o_OBUF_14__inst)) + (portref Q (instanceref upg_adr_o_reg_14_)) + ) + ) + (net (rename upg_adr_o_OBUF_1_ "upg_adr_o_OBUF[1]") (joined + (portref I (instanceref upg_adr_o_OBUF_1__inst)) + (portref Q (instanceref upg_adr_o_reg_1_)) + ) + ) + (net (rename upg_adr_o_OBUF_2_ "upg_adr_o_OBUF[2]") (joined + (portref I (instanceref upg_adr_o_OBUF_2__inst)) + (portref Q (instanceref upg_adr_o_reg_2_)) + ) + ) + (net (rename upg_adr_o_OBUF_3_ "upg_adr_o_OBUF[3]") (joined + (portref I (instanceref upg_adr_o_OBUF_3__inst)) + (portref Q (instanceref upg_adr_o_reg_3_)) + ) + ) + (net (rename upg_adr_o_OBUF_4_ "upg_adr_o_OBUF[4]") (joined + (portref I (instanceref upg_adr_o_OBUF_4__inst)) + (portref Q (instanceref upg_adr_o_reg_4_)) + ) + ) + (net (rename upg_adr_o_OBUF_5_ "upg_adr_o_OBUF[5]") (joined + (portref I (instanceref upg_adr_o_OBUF_5__inst)) + (portref Q (instanceref upg_adr_o_reg_5_)) + ) + ) + (net (rename upg_adr_o_OBUF_6_ "upg_adr_o_OBUF[6]") (joined + (portref I (instanceref upg_adr_o_OBUF_6__inst)) + (portref Q (instanceref upg_adr_o_reg_6_)) + ) + ) + (net (rename upg_adr_o_OBUF_7_ "upg_adr_o_OBUF[7]") (joined + (portref I (instanceref upg_adr_o_OBUF_7__inst)) + (portref Q (instanceref upg_adr_o_reg_7_)) + ) + ) + (net (rename upg_adr_o_OBUF_8_ "upg_adr_o_OBUF[8]") (joined + (portref I (instanceref upg_adr_o_OBUF_8__inst)) + (portref Q (instanceref upg_adr_o_reg_8_)) + ) + ) + (net (rename upg_adr_o_OBUF_9_ "upg_adr_o_OBUF[9]") (joined + (portref I (instanceref upg_adr_o_OBUF_9__inst)) + (portref Q (instanceref upg_adr_o_reg_9_)) + ) + ) + (net upg_clk_i (joined + (portref I (instanceref upg_clk_i_IBUF_inst)) + (portref upg_clk_i) + ) + ) + (net upg_clk_i_IBUF (joined + (portref I (instanceref upg_clk_i_IBUF_BUFG_inst)) + (portref O (instanceref upg_clk_i_IBUF_inst)) + ) + ) + (net upg_clk_i_IBUF_BUFG (joined + (portref C (instanceref RCS_reg_0_)) + (portref C (instanceref RCS_reg_1_)) + (portref C (instanceref RCS_reg_2_)) + (portref C (instanceref WCS_reg_0_)) + (portref C (instanceref WCS_reg_1_)) + (portref C (instanceref WCS_reg_2_)) + (portref C (instanceref initFlag_reg)) + (portref C (instanceref msg_indx_reg_0_)) + (portref C (instanceref msg_indx_reg_1_)) + (portref C (instanceref msg_indx_reg_2_)) + (portref C (instanceref msg_indx_reg_3_)) + (portref C (instanceref msg_indx_reg_4_)) + (portref C (instanceref msg_indx_reg_5_)) + (portref C (instanceref msg_indx_reg_6_)) + (portref C (instanceref msg_indx_reg_7_)) + (portref C (instanceref oldInitF_reg)) + (portref C (instanceref rdStat_reg)) + (portref C (instanceref rwait_cnt_reg_0_)) + (portref C (instanceref rwait_cnt_reg_10_)) + (portref C (instanceref rwait_cnt_reg_11_)) + (portref C (instanceref rwait_cnt_reg_12_)) + (portref C (instanceref rwait_cnt_reg_13_)) + (portref C (instanceref rwait_cnt_reg_14_)) + (portref C (instanceref rwait_cnt_reg_15_)) + (portref C (instanceref rwait_cnt_reg_1_)) + (portref C (instanceref rwait_cnt_reg_2_)) + (portref C (instanceref rwait_cnt_reg_3_)) + (portref C (instanceref rwait_cnt_reg_4_)) + (portref C (instanceref rwait_cnt_reg_5_)) + (portref C (instanceref rwait_cnt_reg_6_)) + (portref C (instanceref rwait_cnt_reg_7_)) + (portref C (instanceref rwait_cnt_reg_8_)) + (portref C (instanceref rwait_cnt_reg_9_)) + (portref C (instanceref s_axi_araddr_reg_3_)) + (portref C (instanceref s_axi_arvalid_reg)) + (portref C (instanceref s_axi_awaddr_reg_3_)) + (portref C (instanceref s_axi_awvalid_reg)) + (portref C (instanceref s_axi_wdata_reg_0_)) + (portref C (instanceref s_axi_wdata_reg_1_)) + (portref C (instanceref s_axi_wdata_reg_2_)) + (portref C (instanceref s_axi_wdata_reg_3_)) + (portref C (instanceref s_axi_wdata_reg_4_)) + (portref C (instanceref s_axi_wdata_reg_5_)) + (portref C (instanceref s_axi_wdata_reg_6_)) + (portref C (instanceref s_axi_wstrb_reg_3_)) + (portref C (instanceref statReg_reg_0_)) + (portref C (instanceref uart_rdat_reg_0_)) + (portref C (instanceref uart_rdat_reg_1_)) + (portref C (instanceref uart_rdat_reg_2_)) + (portref C (instanceref uart_rdat_reg_3_)) + (portref C (instanceref uart_rdat_reg_4_)) + (portref C (instanceref uart_rdat_reg_5_)) + (portref C (instanceref uart_rdat_reg_6_)) + (portref C (instanceref uart_rdat_reg_7_)) + (portref C (instanceref uart_wen_reg)) + (portref C (instanceref upg_done_o_reg)) + (portref C (instanceref wwait_cnt_reg_0_)) + (portref C (instanceref wwait_cnt_reg_10_)) + (portref C (instanceref wwait_cnt_reg_11_)) + (portref C (instanceref wwait_cnt_reg_12_)) + (portref C (instanceref wwait_cnt_reg_13_)) + (portref C (instanceref wwait_cnt_reg_14_)) + (portref C (instanceref wwait_cnt_reg_15_)) + (portref C (instanceref wwait_cnt_reg_1_)) + (portref C (instanceref wwait_cnt_reg_2_)) + (portref C (instanceref wwait_cnt_reg_3_)) + (portref C (instanceref wwait_cnt_reg_4_)) + (portref C (instanceref wwait_cnt_reg_5_)) + (portref C (instanceref wwait_cnt_reg_6_)) + (portref C (instanceref wwait_cnt_reg_7_)) + (portref C (instanceref wwait_cnt_reg_8_)) + (portref C (instanceref wwait_cnt_reg_9_)) + (portref O (instanceref upg_clk_i_IBUF_BUFG_inst)) + (portref s_axi_aclk (instanceref axi_uart_inst)) + ) + ) + (net upg_clk_o (joined + (portref O (instanceref upg_clk_o_OBUF_inst)) + (portref upg_clk_o) + ) + ) + (net upg_clk_o_OBUF (joined + (portref I (instanceref upg_clk_o_OBUF_inst)) + (portref O (instanceref upg_clk_o_OBUF_inst_i_1)) + ) + ) + (net upg_clk_o_OBUF_inst_i_2_n_0 (joined + (portref I0 (instanceref upg_wen_o_i_5)) + (portref I1 (instanceref upg_clk_o_OBUF_inst_i_1)) + (portref I2 (instanceref disp_1__i_3)) + (portref I2 (instanceref disp_7__i_3)) + (portref I3 (instanceref disp_1__i_2)) + (portref I3 (instanceref disp_6__i_3)) + (portref O (instanceref upg_clk_o_OBUF_inst_i_2)) + ) + ) + (net (rename upg_dat_o_0_ "upg_dat_o[0]") (joined + (portref O (instanceref upg_dat_o_OBUF_0__inst)) + (portref (member upg_dat_o 31)) + ) + ) + (net (rename upg_dat_o_10_ "upg_dat_o[10]") (joined + (portref O (instanceref upg_dat_o_OBUF_10__inst)) + (portref (member upg_dat_o 21)) + ) + ) + (net (rename upg_dat_o_11_ "upg_dat_o[11]") (joined + (portref O (instanceref upg_dat_o_OBUF_11__inst)) + (portref (member upg_dat_o 20)) + ) + ) + (net (rename upg_dat_o_12_ "upg_dat_o[12]") (joined + (portref O (instanceref upg_dat_o_OBUF_12__inst)) + (portref (member upg_dat_o 19)) + ) + ) + (net (rename upg_dat_o_13_ "upg_dat_o[13]") (joined + (portref O (instanceref upg_dat_o_OBUF_13__inst)) + (portref (member upg_dat_o 18)) + ) + ) + (net (rename upg_dat_o_14_ "upg_dat_o[14]") (joined + (portref O (instanceref upg_dat_o_OBUF_14__inst)) + (portref (member upg_dat_o 17)) + ) + ) + (net (rename upg_dat_o_15_ "upg_dat_o[15]") (joined + (portref O (instanceref upg_dat_o_OBUF_15__inst)) + (portref (member upg_dat_o 16)) + ) + ) + (net (rename upg_dat_o_16_ "upg_dat_o[16]") (joined + (portref O (instanceref upg_dat_o_OBUF_16__inst)) + (portref (member upg_dat_o 15)) + ) + ) + (net (rename upg_dat_o_17_ "upg_dat_o[17]") (joined + (portref O (instanceref upg_dat_o_OBUF_17__inst)) + (portref (member upg_dat_o 14)) + ) + ) + (net (rename upg_dat_o_18_ "upg_dat_o[18]") (joined + (portref O (instanceref upg_dat_o_OBUF_18__inst)) + (portref (member upg_dat_o 13)) + ) + ) + (net (rename upg_dat_o_19_ "upg_dat_o[19]") (joined + (portref O (instanceref upg_dat_o_OBUF_19__inst)) + (portref (member upg_dat_o 12)) + ) + ) + (net (rename upg_dat_o_1_ "upg_dat_o[1]") (joined + (portref O (instanceref upg_dat_o_OBUF_1__inst)) + (portref (member upg_dat_o 30)) + ) + ) + (net (rename upg_dat_o_20_ "upg_dat_o[20]") (joined + (portref O (instanceref upg_dat_o_OBUF_20__inst)) + (portref (member upg_dat_o 11)) + ) + ) + (net (rename upg_dat_o_21_ "upg_dat_o[21]") (joined + (portref O (instanceref upg_dat_o_OBUF_21__inst)) + (portref (member upg_dat_o 10)) + ) + ) + (net (rename upg_dat_o_22_ "upg_dat_o[22]") (joined + (portref O (instanceref upg_dat_o_OBUF_22__inst)) + (portref (member upg_dat_o 9)) + ) + ) + (net (rename upg_dat_o_23_ "upg_dat_o[23]") (joined + (portref O (instanceref upg_dat_o_OBUF_23__inst)) + (portref (member upg_dat_o 8)) + ) + ) + (net (rename upg_dat_o_24_ "upg_dat_o[24]") (joined + (portref O (instanceref upg_dat_o_OBUF_24__inst)) + (portref (member upg_dat_o 7)) + ) + ) + (net (rename upg_dat_o_25_ "upg_dat_o[25]") (joined + (portref O (instanceref upg_dat_o_OBUF_25__inst)) + (portref (member upg_dat_o 6)) + ) + ) + (net (rename upg_dat_o_26_ "upg_dat_o[26]") (joined + (portref O (instanceref upg_dat_o_OBUF_26__inst)) + (portref (member upg_dat_o 5)) + ) + ) + (net (rename upg_dat_o_27_ "upg_dat_o[27]") (joined + (portref O (instanceref upg_dat_o_OBUF_27__inst)) + (portref (member upg_dat_o 4)) + ) + ) + (net (rename upg_dat_o_28_ "upg_dat_o[28]") (joined + (portref O (instanceref upg_dat_o_OBUF_28__inst)) + (portref (member upg_dat_o 3)) + ) + ) + (net (rename upg_dat_o_29_ "upg_dat_o[29]") (joined + (portref O (instanceref upg_dat_o_OBUF_29__inst)) + (portref (member upg_dat_o 2)) + ) + ) + (net (rename upg_dat_o_2_ "upg_dat_o[2]") (joined + (portref O (instanceref upg_dat_o_OBUF_2__inst)) + (portref (member upg_dat_o 29)) + ) + ) + (net (rename upg_dat_o_30_ "upg_dat_o[30]") (joined + (portref O (instanceref upg_dat_o_OBUF_30__inst)) + (portref (member upg_dat_o 1)) + ) + ) + (net (rename upg_dat_o_31_ "upg_dat_o[31]") (joined + (portref O (instanceref upg_dat_o_OBUF_31__inst)) + (portref (member upg_dat_o 0)) + ) + ) + (net (rename upg_dat_o_3_ "upg_dat_o[3]") (joined + (portref O (instanceref upg_dat_o_OBUF_3__inst)) + (portref (member upg_dat_o 28)) + ) + ) + (net (rename upg_dat_o_4_ "upg_dat_o[4]") (joined + (portref O (instanceref upg_dat_o_OBUF_4__inst)) + (portref (member upg_dat_o 27)) + ) + ) + (net (rename upg_dat_o_5_ "upg_dat_o[5]") (joined + (portref O (instanceref upg_dat_o_OBUF_5__inst)) + (portref (member upg_dat_o 26)) + ) + ) + (net (rename upg_dat_o_6_ "upg_dat_o[6]") (joined + (portref O (instanceref upg_dat_o_OBUF_6__inst)) + (portref (member upg_dat_o 25)) + ) + ) + (net (rename upg_dat_o_7_ "upg_dat_o[7]") (joined + (portref O (instanceref upg_dat_o_OBUF_7__inst)) + (portref (member upg_dat_o 24)) + ) + ) + (net (rename upg_dat_o_8_ "upg_dat_o[8]") (joined + (portref O (instanceref upg_dat_o_OBUF_8__inst)) + (portref (member upg_dat_o 23)) + ) + ) + (net (rename upg_dat_o_9_ "upg_dat_o[9]") (joined + (portref O (instanceref upg_dat_o_OBUF_9__inst)) + (portref (member upg_dat_o 22)) + ) + ) + (net (rename upg_dat_o_OBUF_0_ "upg_dat_o_OBUF[0]") (joined + (portref I (instanceref upg_dat_o_OBUF_0__inst)) + (portref Q (instanceref upg_dat_o_reg_0_)) + ) + ) + (net (rename upg_dat_o_OBUF_10_ "upg_dat_o_OBUF[10]") (joined + (portref I (instanceref upg_dat_o_OBUF_10__inst)) + (portref Q (instanceref upg_dat_o_reg_10_)) + ) + ) + (net (rename upg_dat_o_OBUF_11_ "upg_dat_o_OBUF[11]") (joined + (portref I (instanceref upg_dat_o_OBUF_11__inst)) + (portref Q (instanceref upg_dat_o_reg_11_)) + ) + ) + (net (rename upg_dat_o_OBUF_12_ "upg_dat_o_OBUF[12]") (joined + (portref I (instanceref upg_dat_o_OBUF_12__inst)) + (portref Q (instanceref upg_dat_o_reg_12_)) + ) + ) + (net (rename upg_dat_o_OBUF_13_ "upg_dat_o_OBUF[13]") (joined + (portref I (instanceref upg_dat_o_OBUF_13__inst)) + (portref Q (instanceref upg_dat_o_reg_13_)) + ) + ) + (net (rename upg_dat_o_OBUF_14_ "upg_dat_o_OBUF[14]") (joined + (portref I (instanceref upg_dat_o_OBUF_14__inst)) + (portref Q (instanceref upg_dat_o_reg_14_)) + ) + ) + (net (rename upg_dat_o_OBUF_15_ "upg_dat_o_OBUF[15]") (joined + (portref I (instanceref upg_dat_o_OBUF_15__inst)) + (portref Q (instanceref upg_dat_o_reg_15_)) + ) + ) + (net (rename upg_dat_o_OBUF_16_ "upg_dat_o_OBUF[16]") (joined + (portref I (instanceref upg_dat_o_OBUF_16__inst)) + (portref Q (instanceref upg_dat_o_reg_16_)) + ) + ) + (net (rename upg_dat_o_OBUF_17_ "upg_dat_o_OBUF[17]") (joined + (portref I (instanceref upg_dat_o_OBUF_17__inst)) + (portref Q (instanceref upg_dat_o_reg_17_)) + ) + ) + (net (rename upg_dat_o_OBUF_18_ "upg_dat_o_OBUF[18]") (joined + (portref I (instanceref upg_dat_o_OBUF_18__inst)) + (portref Q (instanceref upg_dat_o_reg_18_)) + ) + ) + (net (rename upg_dat_o_OBUF_19_ "upg_dat_o_OBUF[19]") (joined + (portref I (instanceref upg_dat_o_OBUF_19__inst)) + (portref Q (instanceref upg_dat_o_reg_19_)) + ) + ) + (net (rename upg_dat_o_OBUF_1_ "upg_dat_o_OBUF[1]") (joined + (portref I (instanceref upg_dat_o_OBUF_1__inst)) + (portref Q (instanceref upg_dat_o_reg_1_)) + ) + ) + (net (rename upg_dat_o_OBUF_20_ "upg_dat_o_OBUF[20]") (joined + (portref I (instanceref upg_dat_o_OBUF_20__inst)) + (portref Q (instanceref upg_dat_o_reg_20_)) + ) + ) + (net (rename upg_dat_o_OBUF_21_ "upg_dat_o_OBUF[21]") (joined + (portref I (instanceref upg_dat_o_OBUF_21__inst)) + (portref Q (instanceref upg_dat_o_reg_21_)) + ) + ) + (net (rename upg_dat_o_OBUF_22_ "upg_dat_o_OBUF[22]") (joined + (portref I (instanceref upg_dat_o_OBUF_22__inst)) + (portref Q (instanceref upg_dat_o_reg_22_)) + ) + ) + (net (rename upg_dat_o_OBUF_23_ "upg_dat_o_OBUF[23]") (joined + (portref I (instanceref upg_dat_o_OBUF_23__inst)) + (portref Q (instanceref upg_dat_o_reg_23_)) + ) + ) + (net (rename upg_dat_o_OBUF_24_ "upg_dat_o_OBUF[24]") (joined + (portref I (instanceref upg_dat_o_OBUF_24__inst)) + (portref Q (instanceref upg_dat_o_reg_24_)) + ) + ) + (net (rename upg_dat_o_OBUF_25_ "upg_dat_o_OBUF[25]") (joined + (portref I (instanceref upg_dat_o_OBUF_25__inst)) + (portref Q (instanceref upg_dat_o_reg_25_)) + ) + ) + (net (rename upg_dat_o_OBUF_26_ "upg_dat_o_OBUF[26]") (joined + (portref I (instanceref upg_dat_o_OBUF_26__inst)) + (portref Q (instanceref upg_dat_o_reg_26_)) + ) + ) + (net (rename upg_dat_o_OBUF_27_ "upg_dat_o_OBUF[27]") (joined + (portref I (instanceref upg_dat_o_OBUF_27__inst)) + (portref Q (instanceref upg_dat_o_reg_27_)) + ) + ) + (net (rename upg_dat_o_OBUF_28_ "upg_dat_o_OBUF[28]") (joined + (portref I (instanceref upg_dat_o_OBUF_28__inst)) + (portref Q (instanceref upg_dat_o_reg_28_)) + ) + ) + (net (rename upg_dat_o_OBUF_29_ "upg_dat_o_OBUF[29]") (joined + (portref I (instanceref upg_dat_o_OBUF_29__inst)) + (portref Q (instanceref upg_dat_o_reg_29_)) + ) + ) + (net (rename upg_dat_o_OBUF_2_ "upg_dat_o_OBUF[2]") (joined + (portref I (instanceref upg_dat_o_OBUF_2__inst)) + (portref Q (instanceref upg_dat_o_reg_2_)) + ) + ) + (net (rename upg_dat_o_OBUF_30_ "upg_dat_o_OBUF[30]") (joined + (portref I (instanceref upg_dat_o_OBUF_30__inst)) + (portref Q (instanceref upg_dat_o_reg_30_)) + ) + ) + (net (rename upg_dat_o_OBUF_31_ "upg_dat_o_OBUF[31]") (joined + (portref I (instanceref upg_dat_o_OBUF_31__inst)) + (portref Q (instanceref upg_dat_o_reg_31_)) + ) + ) + (net (rename upg_dat_o_OBUF_3_ "upg_dat_o_OBUF[3]") (joined + (portref I (instanceref upg_dat_o_OBUF_3__inst)) + (portref Q (instanceref upg_dat_o_reg_3_)) + ) + ) + (net (rename upg_dat_o_OBUF_4_ "upg_dat_o_OBUF[4]") (joined + (portref I (instanceref upg_dat_o_OBUF_4__inst)) + (portref Q (instanceref upg_dat_o_reg_4_)) + ) + ) + (net (rename upg_dat_o_OBUF_5_ "upg_dat_o_OBUF[5]") (joined + (portref I (instanceref upg_dat_o_OBUF_5__inst)) + (portref Q (instanceref upg_dat_o_reg_5_)) + ) + ) + (net (rename upg_dat_o_OBUF_6_ "upg_dat_o_OBUF[6]") (joined + (portref I (instanceref upg_dat_o_OBUF_6__inst)) + (portref Q (instanceref upg_dat_o_reg_6_)) + ) + ) + (net (rename upg_dat_o_OBUF_7_ "upg_dat_o_OBUF[7]") (joined + (portref I (instanceref upg_dat_o_OBUF_7__inst)) + (portref Q (instanceref upg_dat_o_reg_7_)) + ) + ) + (net (rename upg_dat_o_OBUF_8_ "upg_dat_o_OBUF[8]") (joined + (portref I (instanceref upg_dat_o_OBUF_8__inst)) + (portref Q (instanceref upg_dat_o_reg_8_)) + ) + ) + (net (rename upg_dat_o_OBUF_9_ "upg_dat_o_OBUF[9]") (joined + (portref I (instanceref upg_dat_o_OBUF_9__inst)) + (portref Q (instanceref upg_dat_o_reg_9_)) + ) + ) + (net upg_done_o (joined + (portref O (instanceref upg_done_o_OBUF_inst)) + (portref upg_done_o) + ) + ) + (net upg_done_o_OBUF (joined + (portref I (instanceref upg_done_o_OBUF_inst)) + (portref Q (instanceref upg_done_o_reg)) + ) + ) + (net upg_done_o_i_1_n_0 (joined + (portref CE (instanceref upg_done_o_reg)) + (portref O (instanceref upg_done_o_i_1)) + ) + ) + (net upg_done_o_i_2_n_0 (joined + (portref D (instanceref upg_done_o_reg)) + (portref I0 (instanceref s_axi_wdata_4__i_3)) + (portref I0 (instanceref upg_done_o_i_1)) + (portref I1 (instanceref s_axi_wstrb_3__i_1)) + (portref O (instanceref upg_done_o_i_2)) + ) + ) + (net upg_done_o_i_3_n_0 (joined + (portref I5 (instanceref upg_done_o_i_2)) + (portref O (instanceref upg_done_o_i_3)) + ) + ) + (net upg_rst_i (joined + (portref I (instanceref upg_rst_i_IBUF_inst)) + (portref upg_rst_i) + ) + ) + (net upg_rst_i_IBUF (joined + (portref CLR (instanceref RCS_reg_0_)) + (portref CLR (instanceref RCS_reg_1_)) + (portref CLR (instanceref RCS_reg_2_)) + (portref CLR (instanceref WCS_reg_0_)) + (portref CLR (instanceref WCS_reg_1_)) + (portref CLR (instanceref WCS_reg_2_)) + (portref CLR (instanceref bn_ascii_reg_0_)) + (portref CLR (instanceref bn_ascii_reg_10_)) + (portref CLR (instanceref bn_ascii_reg_11_)) + (portref CLR (instanceref bn_ascii_reg_13_)) + (portref CLR (instanceref bn_ascii_reg_14_)) + (portref CLR (instanceref bn_ascii_reg_16_)) + (portref CLR (instanceref bn_ascii_reg_17_)) + (portref CLR (instanceref bn_ascii_reg_18_)) + (portref CLR (instanceref bn_ascii_reg_19_)) + (portref CLR (instanceref bn_ascii_reg_1_)) + (portref CLR (instanceref bn_ascii_reg_21_)) + (portref CLR (instanceref bn_ascii_reg_22_)) + (portref CLR (instanceref bn_ascii_reg_24_)) + (portref CLR (instanceref bn_ascii_reg_25_)) + (portref CLR (instanceref bn_ascii_reg_26_)) + (portref CLR (instanceref bn_ascii_reg_27_)) + (portref CLR (instanceref bn_ascii_reg_29_)) + (portref CLR (instanceref bn_ascii_reg_2_)) + (portref CLR (instanceref bn_ascii_reg_30_)) + (portref CLR (instanceref bn_ascii_reg_32_)) + (portref CLR (instanceref bn_ascii_reg_33_)) + (portref CLR (instanceref bn_ascii_reg_34_)) + (portref CLR (instanceref bn_ascii_reg_35_)) + (portref CLR (instanceref bn_ascii_reg_37_)) + (portref CLR (instanceref bn_ascii_reg_38_)) + (portref CLR (instanceref bn_ascii_reg_3_)) + (portref CLR (instanceref bn_ascii_reg_40_)) + (portref CLR (instanceref bn_ascii_reg_41_)) + (portref CLR (instanceref bn_ascii_reg_42_)) + (portref CLR (instanceref bn_ascii_reg_43_)) + (portref CLR (instanceref bn_ascii_reg_45_)) + (portref CLR (instanceref bn_ascii_reg_46_)) + (portref CLR (instanceref bn_ascii_reg_48_)) + (portref CLR (instanceref bn_ascii_reg_49_)) + (portref CLR (instanceref bn_ascii_reg_50_)) + (portref CLR (instanceref bn_ascii_reg_51_)) + (portref CLR (instanceref bn_ascii_reg_53_)) + (portref CLR (instanceref bn_ascii_reg_54_)) + (portref CLR (instanceref bn_ascii_reg_56_)) + (portref CLR (instanceref bn_ascii_reg_57_)) + (portref CLR (instanceref bn_ascii_reg_58_)) + (portref CLR (instanceref bn_ascii_reg_59_)) + (portref CLR (instanceref bn_ascii_reg_5_)) + (portref CLR (instanceref bn_ascii_reg_61_)) + (portref CLR (instanceref bn_ascii_reg_62_)) + (portref CLR (instanceref bn_ascii_reg_6_)) + (portref CLR (instanceref bn_ascii_reg_8_)) + (portref CLR (instanceref bn_ascii_reg_9_)) + (portref CLR (instanceref byte_cnt_reg_0_)) + (portref CLR (instanceref byte_cnt_reg_10_)) + (portref CLR (instanceref byte_cnt_reg_11_)) + (portref CLR (instanceref byte_cnt_reg_12_)) + (portref CLR (instanceref byte_cnt_reg_13_)) + (portref CLR (instanceref byte_cnt_reg_14_)) + (portref CLR (instanceref byte_cnt_reg_15_)) + (portref CLR (instanceref byte_cnt_reg_16_)) + (portref CLR (instanceref byte_cnt_reg_17_)) + (portref CLR (instanceref byte_cnt_reg_18_)) + (portref CLR (instanceref byte_cnt_reg_19_)) + (portref CLR (instanceref byte_cnt_reg_1_)) + (portref CLR (instanceref byte_cnt_reg_20_)) + (portref CLR (instanceref byte_cnt_reg_21_)) + (portref CLR (instanceref byte_cnt_reg_22_)) + (portref CLR (instanceref byte_cnt_reg_23_)) + (portref CLR (instanceref byte_cnt_reg_24_)) + (portref CLR (instanceref byte_cnt_reg_25_)) + (portref CLR (instanceref byte_cnt_reg_26_)) + (portref CLR (instanceref byte_cnt_reg_27_)) + (portref CLR (instanceref byte_cnt_reg_28_)) + (portref CLR (instanceref byte_cnt_reg_29_)) + (portref CLR (instanceref byte_cnt_reg_2_)) + (portref CLR (instanceref byte_cnt_reg_30_)) + (portref CLR (instanceref byte_cnt_reg_31_)) + (portref CLR (instanceref byte_cnt_reg_3_)) + (portref CLR (instanceref byte_cnt_reg_4_)) + (portref CLR (instanceref byte_cnt_reg_5_)) + (portref CLR (instanceref byte_cnt_reg_6_)) + (portref CLR (instanceref byte_cnt_reg_7_)) + (portref CLR (instanceref byte_cnt_reg_8_)) + (portref CLR (instanceref byte_cnt_reg_9_)) + (portref CLR (instanceref byte_len_reg_0_)) + (portref CLR (instanceref byte_len_reg_1_)) + (portref CLR (instanceref byte_len_reg_2_)) + (portref CLR (instanceref byte_len_reg_3_)) + (portref CLR (instanceref byte_len_reg_4_)) + (portref CLR (instanceref byte_len_reg_5_)) + (portref CLR (instanceref byte_len_reg_6_)) + (portref CLR (instanceref byte_len_reg_7_)) + (portref CLR (instanceref byte_num_reg_0_)) + (portref CLR (instanceref byte_num_reg_10_)) + (portref CLR (instanceref byte_num_reg_11_)) + (portref CLR (instanceref byte_num_reg_12_)) + (portref CLR (instanceref byte_num_reg_13_)) + (portref CLR (instanceref byte_num_reg_14_)) + (portref CLR (instanceref byte_num_reg_15_)) + (portref CLR (instanceref byte_num_reg_16_)) + (portref CLR (instanceref byte_num_reg_17_)) + (portref CLR (instanceref byte_num_reg_18_)) + (portref CLR (instanceref byte_num_reg_19_)) + (portref CLR (instanceref byte_num_reg_1_)) + (portref CLR (instanceref byte_num_reg_20_)) + (portref CLR (instanceref byte_num_reg_21_)) + (portref CLR (instanceref byte_num_reg_22_)) + (portref CLR (instanceref byte_num_reg_23_)) + (portref CLR (instanceref byte_num_reg_24_)) + (portref CLR (instanceref byte_num_reg_25_)) + (portref CLR (instanceref byte_num_reg_26_)) + (portref CLR (instanceref byte_num_reg_27_)) + (portref CLR (instanceref byte_num_reg_28_)) + (portref CLR (instanceref byte_num_reg_29_)) + (portref CLR (instanceref byte_num_reg_2_)) + (portref CLR (instanceref byte_num_reg_30_)) + (portref CLR (instanceref byte_num_reg_31_)) + (portref CLR (instanceref byte_num_reg_3_)) + (portref CLR (instanceref byte_num_reg_4_)) + (portref CLR (instanceref byte_num_reg_5_)) + (portref CLR (instanceref byte_num_reg_6_)) + (portref CLR (instanceref byte_num_reg_7_)) + (portref CLR (instanceref byte_num_reg_8_)) + (portref CLR (instanceref byte_num_reg_9_)) + (portref CLR (instanceref dbuf_reg_0_)) + (portref CLR (instanceref dbuf_reg_10_)) + (portref CLR (instanceref dbuf_reg_11_)) + (portref CLR (instanceref dbuf_reg_12_)) + (portref CLR (instanceref dbuf_reg_13_)) + (portref CLR (instanceref dbuf_reg_14_)) + (portref CLR (instanceref dbuf_reg_15_)) + (portref CLR (instanceref dbuf_reg_16_)) + (portref CLR (instanceref dbuf_reg_17_)) + (portref CLR (instanceref dbuf_reg_18_)) + (portref CLR (instanceref dbuf_reg_19_)) + (portref CLR (instanceref dbuf_reg_1_)) + (portref CLR (instanceref dbuf_reg_20_)) + (portref CLR (instanceref dbuf_reg_21_)) + (portref CLR (instanceref dbuf_reg_22_)) + (portref CLR (instanceref dbuf_reg_23_)) + (portref CLR (instanceref dbuf_reg_2_)) + (portref CLR (instanceref dbuf_reg_3_)) + (portref CLR (instanceref dbuf_reg_4_)) + (portref CLR (instanceref dbuf_reg_5_)) + (portref CLR (instanceref dbuf_reg_6_)) + (portref CLR (instanceref dbuf_reg_7_)) + (portref CLR (instanceref dbuf_reg_8_)) + (portref CLR (instanceref dbuf_reg_9_)) + (portref CLR (instanceref disp_reg_0_)) + (portref CLR (instanceref disp_reg_1_)) + (portref CLR (instanceref disp_reg_2_)) + (portref CLR (instanceref disp_reg_3_)) + (portref CLR (instanceref disp_reg_4_)) + (portref CLR (instanceref disp_reg_5_)) + (portref CLR (instanceref disp_reg_6_)) + (portref CLR (instanceref disp_reg_7_)) + (portref CLR (instanceref initFlag_reg)) + (portref CLR (instanceref len_cnt_reg_0_)) + (portref CLR (instanceref len_cnt_reg_1_)) + (portref CLR (instanceref len_cnt_reg_2_)) + (portref CLR (instanceref len_cnt_reg_3_)) + (portref CLR (instanceref msg_indx_reg_0_)) + (portref CLR (instanceref msg_indx_reg_1_)) + (portref CLR (instanceref msg_indx_reg_2_)) + (portref CLR (instanceref msg_indx_reg_3_)) + (portref CLR (instanceref msg_indx_reg_4_)) + (portref CLR (instanceref msg_indx_reg_5_)) + (portref CLR (instanceref msg_indx_reg_6_)) + (portref CLR (instanceref msg_indx_reg_7_)) + (portref CLR (instanceref oldInitF_reg)) + (portref CLR (instanceref rdStat_reg)) + (portref CLR (instanceref recv_done_reg)) + (portref CLR (instanceref rwait_cnt_reg_10_)) + (portref CLR (instanceref rwait_cnt_reg_11_)) + (portref CLR (instanceref rwait_cnt_reg_12_)) + (portref CLR (instanceref rwait_cnt_reg_13_)) + (portref CLR (instanceref rwait_cnt_reg_14_)) + (portref CLR (instanceref rwait_cnt_reg_15_)) + (portref CLR (instanceref rwait_cnt_reg_1_)) + (portref CLR (instanceref rwait_cnt_reg_2_)) + (portref CLR (instanceref rwait_cnt_reg_3_)) + (portref CLR (instanceref rwait_cnt_reg_4_)) + (portref CLR (instanceref rwait_cnt_reg_5_)) + (portref CLR (instanceref rwait_cnt_reg_6_)) + (portref CLR (instanceref rwait_cnt_reg_7_)) + (portref CLR (instanceref rwait_cnt_reg_8_)) + (portref CLR (instanceref rwait_cnt_reg_9_)) + (portref CLR (instanceref rx_done_reg)) + (portref CLR (instanceref statReg_reg_0_)) + (portref CLR (instanceref uart_wen_reg)) + (portref CLR (instanceref upg_adr_o_reg_0_)) + (portref CLR (instanceref upg_adr_o_reg_10_)) + (portref CLR (instanceref upg_adr_o_reg_11_)) + (portref CLR (instanceref upg_adr_o_reg_12_)) + (portref CLR (instanceref upg_adr_o_reg_13_)) + (portref CLR (instanceref upg_adr_o_reg_14_)) + (portref CLR (instanceref upg_adr_o_reg_1_)) + (portref CLR (instanceref upg_adr_o_reg_2_)) + (portref CLR (instanceref upg_adr_o_reg_3_)) + (portref CLR (instanceref upg_adr_o_reg_4_)) + (portref CLR (instanceref upg_adr_o_reg_5_)) + (portref CLR (instanceref upg_adr_o_reg_6_)) + (portref CLR (instanceref upg_adr_o_reg_7_)) + (portref CLR (instanceref upg_adr_o_reg_8_)) + (portref CLR (instanceref upg_adr_o_reg_9_)) + (portref CLR (instanceref upg_dat_o_reg_0_)) + (portref CLR (instanceref upg_dat_o_reg_10_)) + (portref CLR (instanceref upg_dat_o_reg_11_)) + (portref CLR (instanceref upg_dat_o_reg_12_)) + (portref CLR (instanceref upg_dat_o_reg_13_)) + (portref CLR (instanceref upg_dat_o_reg_14_)) + (portref CLR (instanceref upg_dat_o_reg_15_)) + (portref CLR (instanceref upg_dat_o_reg_16_)) + (portref CLR (instanceref upg_dat_o_reg_17_)) + (portref CLR (instanceref upg_dat_o_reg_18_)) + (portref CLR (instanceref upg_dat_o_reg_19_)) + (portref CLR (instanceref upg_dat_o_reg_1_)) + (portref CLR (instanceref upg_dat_o_reg_20_)) + (portref CLR (instanceref upg_dat_o_reg_21_)) + (portref CLR (instanceref upg_dat_o_reg_22_)) + (portref CLR (instanceref upg_dat_o_reg_23_)) + (portref CLR (instanceref upg_dat_o_reg_24_)) + (portref CLR (instanceref upg_dat_o_reg_25_)) + (portref CLR (instanceref upg_dat_o_reg_26_)) + (portref CLR (instanceref upg_dat_o_reg_27_)) + (portref CLR (instanceref upg_dat_o_reg_28_)) + (portref CLR (instanceref upg_dat_o_reg_29_)) + (portref CLR (instanceref upg_dat_o_reg_2_)) + (portref CLR (instanceref upg_dat_o_reg_30_)) + (portref CLR (instanceref upg_dat_o_reg_31_)) + (portref CLR (instanceref upg_dat_o_reg_3_)) + (portref CLR (instanceref upg_dat_o_reg_4_)) + (portref CLR (instanceref upg_dat_o_reg_5_)) + (portref CLR (instanceref upg_dat_o_reg_6_)) + (portref CLR (instanceref upg_dat_o_reg_7_)) + (portref CLR (instanceref upg_dat_o_reg_8_)) + (portref CLR (instanceref upg_dat_o_reg_9_)) + (portref CLR (instanceref upg_done_o_reg)) + (portref CLR (instanceref upg_wen_o_reg)) + (portref CLR (instanceref wr_byte_len_done_reg)) + (portref CLR (instanceref wr_byte_num_done_reg)) + (portref CLR (instanceref wwait_cnt_reg_10_)) + (portref CLR (instanceref wwait_cnt_reg_11_)) + (portref CLR (instanceref wwait_cnt_reg_12_)) + (portref CLR (instanceref wwait_cnt_reg_13_)) + (portref CLR (instanceref wwait_cnt_reg_14_)) + (portref CLR (instanceref wwait_cnt_reg_15_)) + (portref CLR (instanceref wwait_cnt_reg_1_)) + (portref CLR (instanceref wwait_cnt_reg_2_)) + (portref CLR (instanceref wwait_cnt_reg_3_)) + (portref CLR (instanceref wwait_cnt_reg_4_)) + (portref CLR (instanceref wwait_cnt_reg_5_)) + (portref CLR (instanceref wwait_cnt_reg_6_)) + (portref CLR (instanceref wwait_cnt_reg_7_)) + (portref CLR (instanceref wwait_cnt_reg_8_)) + (portref CLR (instanceref wwait_cnt_reg_9_)) + (portref I0 (instanceref axi_uart_inst_i_1)) + (portref I0 (instanceref s_axi_arvalid_i_2)) + (portref I1 (instanceref recv_done_i_1)) + (portref I1 (instanceref s_axi_wdata_4__i_1)) + (portref I1 (instanceref s_axi_wdata_6__i_1)) + (portref I1 (instanceref uart_wen_i_1)) + (portref I1 (instanceref upg_wen_o_i_1)) + (portref I2 (instanceref s_axi_araddr_3__i_1)) + (portref I2 (instanceref s_axi_awaddr_3__i_1)) + (portref I2 (instanceref s_axi_awvalid_i_2)) + (portref I2 (instanceref upg_adr_o_14__i_1)) + (portref I3 (instanceref byte_cnt_31__i_1)) + (portref I3 (instanceref uart_rdat_7__i_1)) + (portref I4 (instanceref upg_wen_o_i_3)) + (portref O (instanceref upg_rst_i_IBUF_inst)) + (portref PRE (instanceref rwait_cnt_reg_0_)) + (portref PRE (instanceref wwait_cnt_reg_0_)) + ) + ) + (net upg_rx_i (joined + (portref I (instanceref upg_rx_i_IBUF_inst)) + (portref upg_rx_i) + ) + ) + (net upg_rx_i_IBUF (joined + (portref O (instanceref upg_rx_i_IBUF_inst)) + (portref rx (instanceref axi_uart_inst)) + ) + ) + (net upg_tx_o (joined + (portref O (instanceref upg_tx_o_OBUF_inst)) + (portref upg_tx_o) + ) + ) + (net upg_tx_o_OBUF (joined + (portref I (instanceref upg_tx_o_OBUF_inst)) + (portref tx (instanceref axi_uart_inst)) + ) + ) + (net upg_wen_o (joined + (portref O (instanceref upg_wen_o_OBUF_inst)) + (portref upg_wen_o) + ) + ) + (net upg_wen_o2_out (joined + (portref CE (instanceref upg_wen_o_reg)) + (portref O (instanceref upg_wen_o_i_1)) + ) + ) + (net upg_wen_o_OBUF (joined + (portref I (instanceref upg_wen_o_OBUF_inst)) + (portref Q (instanceref upg_wen_o_reg)) + ) + ) + (net upg_wen_o_i_2_n_0 (joined + (portref D (instanceref upg_wen_o_reg)) + (portref O (instanceref upg_wen_o_i_2)) + ) + ) + (net upg_wen_o_i_4_n_0 (joined + (portref I0 (instanceref upg_wen_o_i_2)) + (portref I1 (instanceref upg_adr_o_14__i_1)) + (portref I2 (instanceref upg_wen_o_i_1)) + (portref I3 (instanceref disp_6__i_2)) + (portref O (instanceref upg_wen_o_i_4)) + ) + ) + (net upg_wen_o_i_5_n_0 (joined + (portref I0 (instanceref upg_wen_o_i_3)) + (portref O (instanceref upg_wen_o_i_5)) + ) + ) + (net upg_wen_o_i_6_n_0 (joined + (portref I4 (instanceref upg_wen_o_i_4)) + (portref O (instanceref upg_wen_o_i_6)) + ) + ) + (net wr_byte_len_done0 (joined + (portref D (instanceref wr_byte_len_done_reg)) + (portref I0 (instanceref byte_len_7__i_1)) + (portref O (instanceref wr_byte_len_done_i_1)) + ) + ) + (net wr_byte_len_done_i_2_n_0 (joined + (portref I1 (instanceref wr_byte_len_done_i_1)) + (portref O (instanceref wr_byte_len_done_i_2)) + ) + ) + (net wr_byte_len_done_reg_n_0 (joined + (portref I0 (instanceref byte_num_31__i_1)) + (portref I0 (instanceref wr_byte_len_done_i_1)) + (portref I2 (instanceref bn_ascii_62__i_1)) + (portref Q (instanceref wr_byte_len_done_reg)) + ) + ) + (net wr_byte_num_done (joined + (portref CE (instanceref bn_ascii_reg_0_)) + (portref CE (instanceref bn_ascii_reg_10_)) + (portref CE (instanceref bn_ascii_reg_11_)) + (portref CE (instanceref bn_ascii_reg_13_)) + (portref CE (instanceref bn_ascii_reg_14_)) + (portref CE (instanceref bn_ascii_reg_16_)) + (portref CE (instanceref bn_ascii_reg_17_)) + (portref CE (instanceref bn_ascii_reg_18_)) + (portref CE (instanceref bn_ascii_reg_19_)) + (portref CE (instanceref bn_ascii_reg_1_)) + (portref CE (instanceref bn_ascii_reg_21_)) + (portref CE (instanceref bn_ascii_reg_22_)) + (portref CE (instanceref bn_ascii_reg_24_)) + (portref CE (instanceref bn_ascii_reg_25_)) + (portref CE (instanceref bn_ascii_reg_26_)) + (portref CE (instanceref bn_ascii_reg_27_)) + (portref CE (instanceref bn_ascii_reg_29_)) + (portref CE (instanceref bn_ascii_reg_2_)) + (portref CE (instanceref bn_ascii_reg_30_)) + (portref CE (instanceref bn_ascii_reg_32_)) + (portref CE (instanceref bn_ascii_reg_33_)) + (portref CE (instanceref bn_ascii_reg_34_)) + (portref CE (instanceref bn_ascii_reg_35_)) + (portref CE (instanceref bn_ascii_reg_37_)) + (portref CE (instanceref bn_ascii_reg_38_)) + (portref CE (instanceref bn_ascii_reg_3_)) + (portref CE (instanceref bn_ascii_reg_40_)) + (portref CE (instanceref bn_ascii_reg_41_)) + (portref CE (instanceref bn_ascii_reg_42_)) + (portref CE (instanceref bn_ascii_reg_43_)) + (portref CE (instanceref bn_ascii_reg_45_)) + (portref CE (instanceref bn_ascii_reg_46_)) + (portref CE (instanceref bn_ascii_reg_48_)) + (portref CE (instanceref bn_ascii_reg_49_)) + (portref CE (instanceref bn_ascii_reg_50_)) + (portref CE (instanceref bn_ascii_reg_51_)) + (portref CE (instanceref bn_ascii_reg_53_)) + (portref CE (instanceref bn_ascii_reg_54_)) + (portref CE (instanceref bn_ascii_reg_56_)) + (portref CE (instanceref bn_ascii_reg_57_)) + (portref CE (instanceref bn_ascii_reg_58_)) + (portref CE (instanceref bn_ascii_reg_59_)) + (portref CE (instanceref bn_ascii_reg_5_)) + (portref CE (instanceref bn_ascii_reg_61_)) + (portref CE (instanceref bn_ascii_reg_62_)) + (portref CE (instanceref bn_ascii_reg_6_)) + (portref CE (instanceref bn_ascii_reg_8_)) + (portref CE (instanceref bn_ascii_reg_9_)) + (portref CE (instanceref wr_byte_num_done_reg)) + (portref O (instanceref bn_ascii_62__i_1)) + ) + ) + (net wr_byte_num_done0 (joined + (portref D (instanceref wr_byte_num_done_reg)) + (portref I3 (instanceref bn_ascii_62__i_1)) + (portref O (instanceref wr_byte_num_done_i_1)) + ) + ) + (net wr_byte_num_done_i_2_n_0 (joined + (portref I5 (instanceref wr_byte_num_done_i_1)) + (portref O (instanceref wr_byte_num_done_i_2)) + ) + ) + (net wr_byte_num_done_i_3_n_0 (joined + (portref I5 (instanceref wr_byte_num_done_i_2)) + (portref O (instanceref wr_byte_num_done_i_3)) + ) + ) + (net wr_byte_num_done_reg_n_0 (joined + (portref I0 (instanceref bn_ascii_62__i_1)) + (portref I0 (instanceref disp_3__i_1)) + (portref I0 (instanceref disp_4__i_1)) + (portref I0 (instanceref disp_6__i_2)) + (portref I1 (instanceref byte_cnt_31__i_1)) + (portref I1 (instanceref disp_5__i_2)) + (portref I2 (instanceref byte_num_31__i_1)) + (portref I2 (instanceref disp_0__i_1)) + (portref I3 (instanceref disp_1__i_1)) + (portref I3 (instanceref disp_2__i_2)) + (portref I3 (instanceref recv_done_i_1)) + (portref Q (instanceref wr_byte_num_done_reg)) + ) + ) + (net (rename wwait_cnt_0_ "wwait_cnt[0]") (joined + (portref D (instanceref wwait_cnt_reg_0_)) + (portref O (instanceref wwait_cnt_0__i_1)) + ) + ) + (net (rename wwait_cnt_10_ "wwait_cnt[10]") (joined + (portref D (instanceref wwait_cnt_reg_10_)) + (portref O (instanceref wwait_cnt_10__i_1)) + ) + ) + (net (rename wwait_cnt_11_ "wwait_cnt[11]") (joined + (portref D (instanceref wwait_cnt_reg_11_)) + (portref O (instanceref wwait_cnt_11__i_1)) + ) + ) + (net (rename wwait_cnt_12_ "wwait_cnt[12]") (joined + (portref D (instanceref wwait_cnt_reg_12_)) + (portref O (instanceref wwait_cnt_12__i_1)) + ) + ) + (net (rename wwait_cnt_13_ "wwait_cnt[13]") (joined + (portref D (instanceref wwait_cnt_reg_13_)) + (portref O (instanceref wwait_cnt_13__i_1)) + ) + ) + (net (rename wwait_cnt_14_ "wwait_cnt[14]") (joined + (portref D (instanceref wwait_cnt_reg_14_)) + (portref O (instanceref wwait_cnt_14__i_1)) + ) + ) + (net (rename wwait_cnt_15_ "wwait_cnt[15]") (joined + (portref D (instanceref wwait_cnt_reg_15_)) + (portref O (instanceref wwait_cnt_15__i_2)) + ) + ) + (net (rename wwait_cnt_15__i_1_n_0 "wwait_cnt[15]_i_1_n_0") (joined + (portref CE (instanceref wwait_cnt_reg_0_)) + (portref CE (instanceref wwait_cnt_reg_10_)) + (portref CE (instanceref wwait_cnt_reg_11_)) + (portref CE (instanceref wwait_cnt_reg_12_)) + (portref CE (instanceref wwait_cnt_reg_13_)) + (portref CE (instanceref wwait_cnt_reg_14_)) + (portref CE (instanceref wwait_cnt_reg_15_)) + (portref CE (instanceref wwait_cnt_reg_1_)) + (portref CE (instanceref wwait_cnt_reg_2_)) + (portref CE (instanceref wwait_cnt_reg_3_)) + (portref CE (instanceref wwait_cnt_reg_4_)) + (portref CE (instanceref wwait_cnt_reg_5_)) + (portref CE (instanceref wwait_cnt_reg_6_)) + (portref CE (instanceref wwait_cnt_reg_7_)) + (portref CE (instanceref wwait_cnt_reg_8_)) + (portref CE (instanceref wwait_cnt_reg_9_)) + (portref O (instanceref wwait_cnt_15__i_1)) + ) + ) + (net (rename wwait_cnt_15__i_4_n_0 "wwait_cnt[15]_i_4_n_0") (joined + (portref I1 (instanceref wwait_cnt_10__i_1)) + (portref I1 (instanceref wwait_cnt_11__i_1)) + (portref I1 (instanceref wwait_cnt_12__i_1)) + (portref I1 (instanceref wwait_cnt_13__i_1)) + (portref I1 (instanceref wwait_cnt_14__i_1)) + (portref I1 (instanceref wwait_cnt_15__i_2)) + (portref I1 (instanceref wwait_cnt_1__i_1)) + (portref I1 (instanceref wwait_cnt_2__i_1)) + (portref I1 (instanceref wwait_cnt_3__i_1)) + (portref I1 (instanceref wwait_cnt_4__i_1)) + (portref I1 (instanceref wwait_cnt_5__i_1)) + (portref I1 (instanceref wwait_cnt_6__i_1)) + (portref I1 (instanceref wwait_cnt_7__i_1)) + (portref I1 (instanceref wwait_cnt_8__i_1)) + (portref I1 (instanceref wwait_cnt_9__i_1)) + (portref O (instanceref wwait_cnt_15__i_4)) + ) + ) + (net (rename wwait_cnt_15__i_5_n_0 "wwait_cnt[15]_i_5_n_0") (joined + (portref I0 (instanceref wwait_cnt_15__i_4)) + (portref O (instanceref wwait_cnt_15__i_5)) + ) + ) + (net (rename wwait_cnt_15__i_6_n_0 "wwait_cnt[15]_i_6_n_0") (joined + (portref I5 (instanceref wwait_cnt_15__i_4)) + (portref O (instanceref wwait_cnt_15__i_6)) + ) + ) + (net (rename wwait_cnt_15__i_7_n_0 "wwait_cnt[15]_i_7_n_0") (joined + (portref I4 (instanceref wwait_cnt_15__i_6)) + (portref O (instanceref wwait_cnt_15__i_7)) + ) + ) + (net (rename wwait_cnt_1_ "wwait_cnt[1]") (joined + (portref D (instanceref wwait_cnt_reg_1_)) + (portref O (instanceref wwait_cnt_1__i_1)) + ) + ) + (net (rename wwait_cnt_2_ "wwait_cnt[2]") (joined + (portref D (instanceref wwait_cnt_reg_2_)) + (portref O (instanceref wwait_cnt_2__i_1)) + ) + ) + (net (rename wwait_cnt_3_ "wwait_cnt[3]") (joined + (portref D (instanceref wwait_cnt_reg_3_)) + (portref O (instanceref wwait_cnt_3__i_1)) + ) + ) + (net (rename wwait_cnt_4_ "wwait_cnt[4]") (joined + (portref D (instanceref wwait_cnt_reg_4_)) + (portref O (instanceref wwait_cnt_4__i_1)) + ) + ) + (net (rename wwait_cnt_5_ "wwait_cnt[5]") (joined + (portref D (instanceref wwait_cnt_reg_5_)) + (portref O (instanceref wwait_cnt_5__i_1)) + ) + ) + (net (rename wwait_cnt_6_ "wwait_cnt[6]") (joined + (portref D (instanceref wwait_cnt_reg_6_)) + (portref O (instanceref wwait_cnt_6__i_1)) + ) + ) + (net (rename wwait_cnt_7_ "wwait_cnt[7]") (joined + (portref D (instanceref wwait_cnt_reg_7_)) + (portref O (instanceref wwait_cnt_7__i_1)) + ) + ) + (net (rename wwait_cnt_8_ "wwait_cnt[8]") (joined + (portref D (instanceref wwait_cnt_reg_8_)) + (portref O (instanceref wwait_cnt_8__i_1)) + ) + ) + (net (rename wwait_cnt_9_ "wwait_cnt[9]") (joined + (portref D (instanceref wwait_cnt_reg_9_)) + (portref O (instanceref wwait_cnt_9__i_1)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_0 "wwait_cnt_reg[12]_i_2_n_0") (joined + (portref CI (instanceref wwait_cnt_reg_15__i_3)) + (portref (member CO 0) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_1 "wwait_cnt_reg[12]_i_2_n_1") (joined + (portref (member CO 1) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_2 "wwait_cnt_reg[12]_i_2_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_3 "wwait_cnt_reg[12]_i_2_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_4 "wwait_cnt_reg[12]_i_2_n_4") (joined + (portref I0 (instanceref wwait_cnt_12__i_1)) + (portref (member O 0) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_5 "wwait_cnt_reg[12]_i_2_n_5") (joined + (portref I0 (instanceref wwait_cnt_11__i_1)) + (portref (member O 1) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_6 "wwait_cnt_reg[12]_i_2_n_6") (joined + (portref I0 (instanceref wwait_cnt_10__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_12__i_2_n_7 "wwait_cnt_reg[12]_i_2_n_7") (joined + (portref I0 (instanceref wwait_cnt_9__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_2 "wwait_cnt_reg[15]_i_3_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_3 "wwait_cnt_reg[15]_i_3_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_5 "wwait_cnt_reg[15]_i_3_n_5") (joined + (portref I0 (instanceref wwait_cnt_15__i_2)) + (portref (member O 1) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_6 "wwait_cnt_reg[15]_i_3_n_6") (joined + (portref I0 (instanceref wwait_cnt_14__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_15__i_3_n_7 "wwait_cnt_reg[15]_i_3_n_7") (joined + (portref I0 (instanceref wwait_cnt_13__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_0 "wwait_cnt_reg[4]_i_2_n_0") (joined + (portref CI (instanceref wwait_cnt_reg_8__i_2)) + (portref (member CO 0) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_1 "wwait_cnt_reg[4]_i_2_n_1") (joined + (portref (member CO 1) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_2 "wwait_cnt_reg[4]_i_2_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_3 "wwait_cnt_reg[4]_i_2_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_4 "wwait_cnt_reg[4]_i_2_n_4") (joined + (portref I0 (instanceref wwait_cnt_4__i_1)) + (portref (member O 0) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_5 "wwait_cnt_reg[4]_i_2_n_5") (joined + (portref I0 (instanceref wwait_cnt_3__i_1)) + (portref (member O 1) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_6 "wwait_cnt_reg[4]_i_2_n_6") (joined + (portref I0 (instanceref wwait_cnt_2__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_4__i_2_n_7 "wwait_cnt_reg[4]_i_2_n_7") (joined + (portref I0 (instanceref wwait_cnt_1__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_0 "wwait_cnt_reg[8]_i_2_n_0") (joined + (portref CI (instanceref wwait_cnt_reg_12__i_2)) + (portref (member CO 0) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_1 "wwait_cnt_reg[8]_i_2_n_1") (joined + (portref (member CO 1) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_2 "wwait_cnt_reg[8]_i_2_n_2") (joined + (portref (member CO 2) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_3 "wwait_cnt_reg[8]_i_2_n_3") (joined + (portref (member CO 3) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_4 "wwait_cnt_reg[8]_i_2_n_4") (joined + (portref I0 (instanceref wwait_cnt_8__i_1)) + (portref (member O 0) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_5 "wwait_cnt_reg[8]_i_2_n_5") (joined + (portref I0 (instanceref wwait_cnt_7__i_1)) + (portref (member O 1) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_6 "wwait_cnt_reg[8]_i_2_n_6") (joined + (portref I0 (instanceref wwait_cnt_6__i_1)) + (portref (member O 2) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_8__i_2_n_7 "wwait_cnt_reg[8]_i_2_n_7") (joined + (portref I0 (instanceref wwait_cnt_5__i_1)) + (portref (member O 3) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__0_ "wwait_cnt_reg_n_0_[0]") (joined + (portref CYINIT (instanceref wwait_cnt_reg_4__i_2)) + (portref I0 (instanceref wwait_cnt_0__i_1)) + (portref I1 (instanceref wwait_cnt_15__i_5)) + (portref I2 (instanceref WCS_2__i_4)) + (portref Q (instanceref wwait_cnt_reg_0_)) + ) + ) + (net (rename wwait_cnt_reg_n_0__10_ "wwait_cnt_reg_n_0_[10]") (joined + (portref I2 (instanceref WCS_2__i_2)) + (portref I3 (instanceref wwait_cnt_15__i_7)) + (portref Q (instanceref wwait_cnt_reg_10_)) + (portref (member S 2) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__11_ "wwait_cnt_reg_n_0_[11]") (joined + (portref I2 (instanceref wwait_cnt_15__i_7)) + (portref I4 (instanceref WCS_2__i_2)) + (portref Q (instanceref wwait_cnt_reg_11_)) + (portref (member S 1) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__12_ "wwait_cnt_reg_n_0_[12]") (joined + (portref I0 (instanceref wwait_cnt_15__i_6)) + (portref I3 (instanceref WCS_2__i_2)) + (portref Q (instanceref wwait_cnt_reg_12_)) + (portref (member S 0) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__13_ "wwait_cnt_reg_n_0_[13]") (joined + (portref I1 (instanceref WCS_2__i_2)) + (portref I1 (instanceref wwait_cnt_15__i_6)) + (portref Q (instanceref wwait_cnt_reg_13_)) + (portref (member S 3) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_n_0__14_ "wwait_cnt_reg_n_0_[14]") (joined + (portref I1 (instanceref WCS_2__i_5)) + (portref I1 (instanceref wwait_cnt_15__i_7)) + (portref Q (instanceref wwait_cnt_reg_14_)) + (portref (member S 2) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_n_0__15_ "wwait_cnt_reg_n_0_[15]") (joined + (portref I0 (instanceref WCS_2__i_3)) + (portref I3 (instanceref wwait_cnt_15__i_6)) + (portref Q (instanceref wwait_cnt_reg_15_)) + (portref (member S 1) (instanceref wwait_cnt_reg_15__i_3)) + ) + ) + (net (rename wwait_cnt_reg_n_0__1_ "wwait_cnt_reg_n_0_[1]") (joined + (portref I1 (instanceref WCS_2__i_3)) + (portref I2 (instanceref wwait_cnt_15__i_6)) + (portref Q (instanceref wwait_cnt_reg_1_)) + (portref (member S 3) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__2_ "wwait_cnt_reg_n_0_[2]") (joined + (portref I3 (instanceref WCS_2__i_4)) + (portref I3 (instanceref wwait_cnt_15__i_5)) + (portref Q (instanceref wwait_cnt_reg_2_)) + (portref (member S 2) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__3_ "wwait_cnt_reg_n_0_[3]") (joined + (portref I2 (instanceref WCS_2__i_5)) + (portref I2 (instanceref wwait_cnt_15__i_5)) + (portref Q (instanceref wwait_cnt_reg_3_)) + (portref (member S 1) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__4_ "wwait_cnt_reg_n_0_[4]") (joined + (portref I2 (instanceref wwait_cnt_15__i_4)) + (portref I3 (instanceref WCS_2__i_3)) + (portref Q (instanceref wwait_cnt_reg_4_)) + (portref (member S 0) (instanceref wwait_cnt_reg_4__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__5_ "wwait_cnt_reg_n_0_[5]") (joined + (portref I1 (instanceref wwait_cnt_15__i_4)) + (portref I2 (instanceref WCS_2__i_3)) + (portref Q (instanceref wwait_cnt_reg_5_)) + (portref (member S 3) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__6_ "wwait_cnt_reg_n_0_[6]") (joined + (portref I0 (instanceref WCS_2__i_4)) + (portref I3 (instanceref wwait_cnt_15__i_4)) + (portref Q (instanceref wwait_cnt_reg_6_)) + (portref (member S 2) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__7_ "wwait_cnt_reg_n_0_[7]") (joined + (portref I0 (instanceref wwait_cnt_15__i_5)) + (portref I1 (instanceref WCS_2__i_4)) + (portref Q (instanceref wwait_cnt_reg_7_)) + (portref (member S 1) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__8_ "wwait_cnt_reg_n_0_[8]") (joined + (portref I0 (instanceref WCS_2__i_5)) + (portref I0 (instanceref wwait_cnt_15__i_7)) + (portref Q (instanceref wwait_cnt_reg_8_)) + (portref (member S 0) (instanceref wwait_cnt_reg_8__i_2)) + ) + ) + (net (rename wwait_cnt_reg_n_0__9_ "wwait_cnt_reg_n_0_[9]") (joined + (portref I3 (instanceref WCS_2__i_5)) + (portref I4 (instanceref wwait_cnt_15__i_4)) + (portref Q (instanceref wwait_cnt_reg_9_)) + (portref (member S 3) (instanceref wwait_cnt_reg_12__i_2)) + ) + ) + ) + + (property ADDR_WIDTH (integer 15)) + (property DATA_WIDTH (integer 32)) + (property BYTE_NUM (integer 4)) + (property WIDLE (integer 0)) + (property WDATA_VALID (integer 1)) + (property JUDGE_WRDY (integer 2)) + (property WDATA (integer 3)) + (property WDELAY (integer 4)) + (property RIDLE (integer 0)) + (property RDATA_VALID (integer 1)) + (property JUDGE_RRDY (integer 2)) + (property RDATA (integer 3)) + (property RDELAY (integer 4)) + (property WAIT_NUM (integer 765)) + (property MSG_LEN (integer 38)) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design uart_bmpg + (cellref uart_bmpg (libraryref work)) + (property XLNX_PROJ_DIR (string "H:/Workspace_Xilinx/Vivado/uart_bmpg")) + (property PART (string "xc7a100tfgg484-1")) + ) +) diff --git a/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v new file mode 100644 index 0000000..81d902b --- /dev/null +++ b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/uart_bmpg.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2018/04/27 07:17:21 +// Design Name: +// Module Name: uart_bmpg +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module uart_bmpg( + input wire upg_clk_i, // 10MHz + input wire upg_rst_i, // High active + // blkram signals + output wire upg_clk_o, + output reg upg_wen_o, + output reg [14:0] upg_adr_o, + output reg [31:0] upg_dat_o, + output reg upg_done_o, + // UART Pinouts + input wire upg_rx_i, + output wire upg_tx_o +); + +endmodule diff --git a/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/upg.v b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/upg.v new file mode 100644 index 0000000..78d3576 --- /dev/null +++ b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/upg.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2018/07/12 08:40:58 +// Design Name: +// Module Name: upg +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module upg( + input upg_clk_i, // 10MHz + input upg_rst_i, // High active + // blkram signals + output upg_clk_o, + output upg_wen_o, + output [14:0] upg_adr_o, + output [31:0] upg_dat_o, + output upg_done_o, + // UART Pinouts + input upg_rx_i, + output upg_tx_o +); + + uart_bmpg upg_inst ( + .upg_clk_i (upg_clk_i), // 10MHz + .upg_rst_i (upg_rst_i), // High active + // blkram signals + .upg_clk_o (upg_clk_o), + .upg_wen_o (upg_wen_o), + .upg_adr_o (upg_adr_o), + .upg_dat_o (upg_dat_o), + .upg_done_o (upg_done_o), + // UART Pinouts + .upg_rx_i (upg_rx_i), + .upg_tx_o (upg_tx_o) + ); + +endmodule diff --git a/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl new file mode 100644 index 0000000..d789dd1 --- /dev/null +++ b/main/verilog/ip_import/SEU_CSE_507_user_uart_bmpg_1.3/xgui/uart_bmpg_v1_3.tcl @@ -0,0 +1,71 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set page [ipgui::add_page $IPINST -name "page"] + set_property tooltip {page} ${page} + ipgui::add_param $IPINST -name "Reset" -parent ${page} + ipgui::add_param $IPINST -name "Input_Clock_Freqency" -parent ${page} + ipgui::add_param $IPINST -name "Baud_Rate" -parent ${page} + ipgui::add_param $IPINST -name "Data_Bits" -parent ${page} + ipgui::add_param $IPINST -name "Parity" -parent ${page} + ipgui::add_param $IPINST -name "Stop_Bits" -parent ${page} + + +} + +proc update_PARAM_VALUE.Baud_Rate { PARAM_VALUE.Baud_Rate } { + # Procedure called to update Baud_Rate when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Baud_Rate { PARAM_VALUE.Baud_Rate } { + # Procedure called to validate Baud_Rate + return true +} + +proc update_PARAM_VALUE.Data_Bits { PARAM_VALUE.Data_Bits } { + # Procedure called to update Data_Bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Data_Bits { PARAM_VALUE.Data_Bits } { + # Procedure called to validate Data_Bits + return true +} + +proc update_PARAM_VALUE.Input_Clock_Freqency { PARAM_VALUE.Input_Clock_Freqency } { + # Procedure called to update Input_Clock_Freqency when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Input_Clock_Freqency { PARAM_VALUE.Input_Clock_Freqency } { + # Procedure called to validate Input_Clock_Freqency + return true +} + +proc update_PARAM_VALUE.Parity { PARAM_VALUE.Parity } { + # Procedure called to update Parity when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Parity { PARAM_VALUE.Parity } { + # Procedure called to validate Parity + return true +} + +proc update_PARAM_VALUE.Reset { PARAM_VALUE.Reset } { + # Procedure called to update Reset when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Reset { PARAM_VALUE.Reset } { + # Procedure called to validate Reset + return true +} + +proc update_PARAM_VALUE.Stop_Bits { PARAM_VALUE.Stop_Bits } { + # Procedure called to update Stop_Bits when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.Stop_Bits { PARAM_VALUE.Stop_Bits } { + # Procedure called to validate Stop_Bits + return true +} + + -- Gitee From 8163567d5e85f69f4aa43c85735a212d29c2920e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 01:05:10 +0800 Subject: [PATCH 55/57] =?UTF-8?q?doc(verilog):=20=E6=A0=87=E6=98=8E?= =?UTF-8?q?=E7=BC=96=E8=AF=91=E6=96=B9=E5=BC=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- README.md | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/README.md b/README.md index 09298b4..88010df 100644 --- a/README.md +++ b/README.md @@ -7,6 +7,80 @@ ## 缂栬瘧璇存槑 +鏈」鐩娇鐢╒ivado浣滀负EDA宸ュ叿锛屼笅杞戒唬鐮佸悗鍙互蹇熷垱寤哄彲缂栬瘧鐨刅ivado椤圭洰, 姝ラ濡備笅: + +1. 鍏嬮殕椤圭洰鍒版湰鍦 + + ```bash + git clone https://gitee.com/yecanming/SUSTech-CS202_214-Computer_Organization-Project.git + ``` + +2. 鏂板缓Vivado 椤圭洰 + + image-20220530004739327 + + 閫夋嫨RTL Project + + image-20220530004806679 + + 杩涘叆娣诲姞浠ｇ爜鐜妭 + + image-20220530004844350 + +3. 瀵煎叆verilog婧愪唬鐮侊紙鍙悎鎴愭枃浠讹級 + + 鐐瑰嚮Add Directories锛屽湪寮瑰嚭鏉ョ殑鏂囦欢绛愪腑閫夋嫨ip_invoke锛坸ci鏂囦欢锛岀敤浜庣敓鎴怚P鏍哥殑璋冪敤锛夊拰mips_cpu锛堜富瑕佺殑婧愪唬鐮侊級涓や釜鏂囦欢澶瑰鍏ャ + + image-20220530004950623 + +4. 娣诲姞绠¤剼绾︽潫鏂囦欢 + + image-20220530005242969 + + 鎵惧埌xdc鏂囦欢澶广 + + image-20220530005217981 + + 閫愪釜瀵煎叆鍏朵腑鎵鏈墄dc鏂囦欢锛堝寘鎷瓙鏂囦欢澶逛腑鐨勬枃浠讹級銆 + + 瀵煎叆鏃跺彲浠ユ寜浣廲trl澶氶夛紝鎻愰珮鏁堢巼銆 + +5. 寮鍙戞澘鍨嬪彿閫夋嫨 + + 鏈」鐩娇鐢╔ilinx鐨凪inisys寮鍙戞澘娴嬭瘯锛岃寮鍙戞澘鐨勮缃涓嬶細 + + image-20220530005445591 + +6. 瀵煎叆鑷畾涔塈P鏍 + + 杩欎簺IP鏍哥殑婧愪唬鐮佸湪鏈」鐩綋涓紝骞朵笉鏄痸ivado鑷甫鐨勶紝鍥犳闇瑕佸鍏ivado鐨処P Catalog銆 + + 鎴戜滑鐨勯」鐩富瑕佺敤鍒颁簡涓滃崡澶у璁＄畻鏈虹郴鎻愪緵鐨勪覆鍙OE鎺ユ敹IP鏍革紝寰堟湁甯姪锛屽湪姝よ嚧璋€ + + 棣栧厛鐐瑰嚮IP Catalog + + image-20220530005928253 + + 閫夋嫨Add Repository + + image-20220530010005020 + + 鎵惧埌ip_import鏂囦欢澶癸紝鐩存帴瀵煎叆 + + image-20220530010125596 + +7. 瀵煎叆Verilog娴嬭瘯锛堜豢鐪燂級鏂囦欢(鍙) + + 閫夋嫨Add or create simulation sources + + image-20220530010303825 + + 鎵惧埌test/verilog 鏂囦欢澶癸紝鐩存帴瀵煎叆鏂囦欢澶 + + image-20220530010351991 + + + ## 濡備綍鍙備笌寮鍙 1. 鍏嬮殕椤圭洰鍒版湰鍦 -- Gitee From d0884617ca2cee0124439ca7462ae95ed6babb99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 01:08:19 +0800 Subject: [PATCH 56/57] =?UTF-8?q?feat(verilog):=20sim=E4=BB=BF=E7=9C=9F?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E6=A8=A1=E5=9D=97=E4=BF=AE=E5=A4=8D=E5=91=BD?= =?UTF-8?q?=E5=90=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- test/verilog/{ => mips_cpu}/TestNewSituation1.v | 2 +- test/verilog/{ => mips_cpu}/TestSituation1.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename test/verilog/{ => mips_cpu}/TestNewSituation1.v (91%) rename test/verilog/{ => mips_cpu}/TestSituation1.v (94%) diff --git a/test/verilog/TestNewSituation1.v b/test/verilog/mips_cpu/TestNewSituation1.v similarity index 91% rename from test/verilog/TestNewSituation1.v rename to test/verilog/mips_cpu/TestNewSituation1.v index 211c73a..3a27a20 100644 --- a/test/verilog/TestNewSituation1.v +++ b/test/verilog/mips_cpu/TestNewSituation1.v @@ -9,7 +9,7 @@ always begin #1 Minisys_Clock = ~Minisys_Clock;//这个是外部的clock end -TOP_all use_main(Minisys_Switches,Minisys_Lights,Minisys_Clock,Minisys_Button); +TopAll use_main(Minisys_Switches,Minisys_Lights,Minisys_Clock,Minisys_Button); initial begin Minisys_Clock = 1'b0; diff --git a/test/verilog/TestSituation1.v b/test/verilog/mips_cpu/TestSituation1.v similarity index 94% rename from test/verilog/TestSituation1.v rename to test/verilog/mips_cpu/TestSituation1.v index 854fcea..51d38e4 100644 --- a/test/verilog/TestSituation1.v +++ b/test/verilog/mips_cpu/TestSituation1.v @@ -5,7 +5,7 @@ reg[23:0]Minisys_Switches; wire [23:0]Minisys_Lights; reg Minisys_Clock; reg[4:0] Minisys_Button; - TOP_all use_main(Minisys_Switches,Minisys_Lights,Minisys_Clock,Minisys_Button); + TopAll use_main(Minisys_Switches,Minisys_Lights,Minisys_Clock,Minisys_Button); initial begin Minisys_Clock = 1'b0; Minisys_Button = 5'b00000; -- Gitee From a47ce805b6b958b5fc833c0ea3370b9deb971be3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=8F=B6=E7=92=A8=E9=93=AD?= <12011404@mail.sustech.edu.cn> Date: Mon, 30 May 2022 01:09:25 +0800 Subject: [PATCH 57/57] =?UTF-8?q?doc(readme):=20=E7=BC=96=E8=AF=91?= =?UTF-8?q?=E6=96=B9=E5=BC=8F=E5=AF=B9=E5=BA=94=E7=9A=84=E5=9B=BE=E7=89=87?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- README.assets/image-20220530004739327.png | Bin 0 -> 75600 bytes README.assets/image-20220530004757891.png | Bin 0 -> 38309 bytes README.assets/image-20220530004806679.png | Bin 0 -> 38309 bytes README.assets/image-20220530004844350.png | Bin 0 -> 86963 bytes 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README.assets/image-20220530004844350.png create mode 100644 README.assets/image-20220530004929066.png create mode 100644 README.assets/image-20220530004950623.png create mode 100644 README.assets/image-20220530005217981.png create mode 100644 README.assets/image-20220530005242969.png create mode 100644 README.assets/image-20220530005445591.png create mode 100644 README.assets/image-20220530005928253.png create mode 100644 README.assets/image-20220530010005020.png create mode 100644 README.assets/image-20220530010050331.png create mode 100644 README.assets/image-20220530010125596.png create mode 100644 README.assets/image-20220530010303825.png create mode 100644 README.assets/image-20220530010351991.png diff --git a/README.assets/image-20220530004739327.png b/README.assets/image-20220530004739327.png new file mode 100644 index 0000000000000000000000000000000000000000..d06e43f448168b1ceb76052d46ff416df52c2609 GIT binary patch literal 75600 zcmc$^V|QiE_6M4D+)>B2ZL?$BR>!t&J3D44>7--ZNyoO09oxA%_vz=H{|C5Z+!wpX zSZnQ?HEVkQsv;ER#NoeUe+2;nftQpJQ33%0oBRCHLqmSPd0dx%0RbTdkrer^;+}Q7 z?%|HM=yQ2>v8JoOIzJx^{srb6Pq-{QW_6E&4DK%HlH@6E%sQvTGrR3dvBhSmv}FBc4%O z<%b=_l-j(6)-SRdyPU<0u#Ec8KcR_iX~|VpYcyyJ-}4GE87bLOgJLB5Mb#hLz=JTt z8xIYeCi~2zLE+Q|hW?$=58ustA4g3YiIv0zs(MCzb~vDuiY<&k>W#Xs<;YNN!M~ViV03jQE0m%KO~>|pi&;)~o@b`{m-jWwN^`l! zK%_bhO^N`>16m)WPNJF`#-#vmxGn6#}DE1a723=W|rlNYHI~=*sqg0NF(Tx~j zu9@UNE45q%u!ORN;ZmraE=$iZ#WBYs|Iw}kFDZ{V<}ii)OMEAl)x{ElM*Vk@fgkAM zq`J=aLub$JzF18d%L&qneZRQ&D%OPh>CS1oz}6MJ0lQ!3<0BV9X87@S2qpx3nia9^ z1eA3Uy@^M&c`(9Do5<_lRNvRL>4kH(3GKS4=#;;3Sk;T8ZfM=l^FDqRb3o-9T)Zpc zIBG~IQ@JNcNc{upEZ_;u5i%MZF|}lSqI{BKxy=I+4eUPug7uCs^A|{#G`^8?j*Jq< zKlZe?Mh`gxCSF#h#t2^sS4xrqLa&ZRM%HyOw){ba{A4fHG|vnZ#T9dO6yogM8M*0) zt)R$8ASTS37tQYm>UL_CUM28Q6Iv~WA)P$$G=q}qP0m-x1^%AmsLb`Du>Tpysa3$nVMgl1>t z{L#`3azmAQEATSIf1Fnx#}1Ed%w>Jk}38QD0=GthJ@S9cOSMO3(S4! zyMQ41*=1E(#-)HteQZK2Eq{gP2!qQn+Y&q(=z{a!!9p&8@n0IWD2$njjF<&t36}ET zG_QK*ER%rt5E_16=Bh5Kjbu|U-a5yMG>xeXw?Uh4zCq4w{gTEK z#@06;>WWrt@i(8St>UF*L;O^ z&z>FxLW^nyLp$kibA{2(oX6Poe@%8jct~>Nb+Z z(d>OI_7wK+I}VOSSZn@OX`fJM{uL$`AuEKQ8$^dbi_0ohzv6|vo!n~a zCJ{po_OBAFAuA7jTIRdNcOy51D=5W`jAo{;c3`teP|JYuMNl*0BHR%o+)TlR)qvS* z%{p;>g;}1vHY1!6ult>I9K{EExC4A=K+~jcl9N5Unu0C_S|zS0qzgsTE^SdQH4b&w z9xZN|f(PJLca8ne*4>{8tKdWWzX7kQARnEuP3!v|Kra)*fDur=ngrl~^DQ`o$rD#V zWr;Mxx~={S2^Wc0$kb?-yu!Q0d1LRHOE4HxexbB1W4Mh>QQ2#AdiKIt`{|-Dwh{oD z*x8WsnGhO^OsbBdtgPLlf>P)vmaySnwln6D0eL^O&uIgc=cLu7yCPJPH7N zW>WQXv0;OW5$ixlNC++8V!btQy2VNzp3&dAeLD-t}_cCSHHj_0f$W==rQAlGle2+G}x zFQ)2KnvwRI(>T{6E5kg|Nm)t^SO*OmMe-@tS!Z91*-jn|{u)AXbN_|khgT~7c$ama z_q#Vl7-H9CVH`hqv9lQ3a)t~$Gjl47&x#niSp^Y)r`=Xb9woXAIV?FYKvr(-z{Hs^ z@Y5X4ad+EF?XdXDeR!P2UN`9fO))|4dkNxV^_z3QxYTcP?@GU%{Qk{0mh*(g%yQ9f zE05)>A4K$Zv{Wz7C90fTEPr%3(QtE>?5~yVh%uG6VE6yDf;bQN9_4dt}5cFRmKr=xiEBycXp%|DA`Y)4lgK)^`MII{xs{eA|PbVf$f%$6? zhmvrmF&cB#^7nyGv=ncoQRl|;%b$4vf8}G#BqmHt9)zNcxDDSf&ZrZ+o+uxECTE?x zyvXB4fc1aq4d#g$vvPvq=^`R4W?n)*phV7n`;jhPeqrZQ+p?<*=ou{d$eJ&~ z7N7v*a35z}H`bfiUqDIjDb^Sw`5)~={a3Jn?=?ounyl*KITe7%H<0~%w z)R1kV9I4=g(E0Lzrrd(heTAeKu+tQtUo+pPR~eVpu<12TmrwRUAU9@?H0prl>b!~; z7OViZwT#Uvto#`?A^mPkGLj(Yc`oCK-0eMYYkn)ME-pDt>gIqB6TN7BV;HDw(+oUu z;5uZQwjgqyLfh|fX5&!MRFPweXS6{|q9{s4hUY_kf3e`#7Lqj%mRNH?)corSo|KXU|yW=GX_YXfn*19WNMkta-*-^1$beS=V}{`G@1 zGy2-(P}h@9r$bZFoH^KF`8BT>rY=L_*5Sv*eFya*Tjt|n!DOw1B4(TyS%M%+3|X7U z!vhbM-V04KN3 zJ5{;c6c7Fh84{AR{@ikvr+Zn=G5w?Ves~E*Ye4j{&T*+Dp?9J}5q9|# zp@Sl@T03onS-E?NBTr7JJB#OhyF6E0D6zm`N|zPAqyK&Jp}Ovw5kefOk&fU0v0-(( zuGt;XD7kl7GVRhB+`7Pte6TT4C|_wNmMG*lje~mXo7p6%iRO{K5;kskl;{T4Q!w= zgHOUmhkbmZ79>htT{EA18O5ZelcvXq=fZ?!@AWytdoz&nM<=P0`o`qR%R)7O2}R!;~$^5qd|O1MxJ*mNAo$%Cmqt zqmPhtjiksWv^$mXIDb@7qdiH`a0`#kF)M0=4%iub^0MvEETlHphbzlaM@CUD=hbG5 zCk^G+yxEV}RW4rGsxI8a*6lEqb(SS~#0W#2;14;MTNAwaT^ZsST)&*n;rhgZRf#et zjC*?K{I;d`j9AoPACKjjP;e{=L>DAWxP?WVYt1}r{g_?jpg?FFkY2y)I9+Xt**xR! z-*%z{@1ySj$+GRtvH=Me$Co0yzx=@EQkHeC<_~g5u~E$bPeo0FR$Aw)kN zr?{|;-g(^#VrXWno<1-GO4SKTQM*PH{WAy;8jYOzxZRDLc~4SLiFv6az38#rV&zxn zx6eoSY!R|iVVBP@wF!FpS1|7G|LVcS^pM3&4va0| zk($T4Xk1V1{?$T89_#!(3Q59vr~g~Pxl@+A6^7qf?vQeMLqL@RRI7!}^t3h0pYh!9 zm6i87c4#gyhz^t<={Xbs0_chKA>C1IN*>jLCl39B9TUi7COOCRkv`Yo z(XGm1oSh7rEO88ks#qQ^CfdJu*QQFF|5jCiwY{e;EQ8Wv+~hh#{Anfa+;kfpLRuTfPM|5|&`()pcwv$A8RJIsh+kY* zm9HdoRwC;bdh_x9!)X5$Bu99%X7_2c`pJZAJ|*I}*X0K@L!Zp8)8=-VD9rEI6^6&> zbreY5rjgU0`ybo6OuT74ftM zKIC5y<~_Xw(6KXLOHU|A$TptCsI2f0qV#>U#7%i5>e(M4=W0a6$M>(GuG13}rt0jv<%?=! zoh*aTU)jbq>k`pe61&X>)2kCy5z&J8Zg3qoK#+ub92%hZ$?F?&iHXJ+ODyrdvu3B3GYEnKq{nK)DZvWKp7wv-LQ8kG*kzMYa+O=v!(hwQUl!ku39DCwqyOjK*ok+{w%ooRY>zQ5m8=MKRX^h`2^WNg%w9DKY$r?N!lZQT~agYZ9n% z0659r#&AGo7>xLd#l<^Us0OU->KVtp)BK{dA~T6UT@D~whTM!tvi43_e!~Ad6AFq= zkICtJnblF56z0@#ML?nT(pblZ1j|Z|=qjVO;Dflrd_cs5k}7d)Y#F4Y&-WD{Ft=*M zc@hy7JY7{qwwOwZV67^Q!tX0!@Cp42K7If?dI3}7Z&Yz#KYWy>G}ya zzlxE}Ca)S8Jy*Fl9*@yo)tj%(#!T1S+dM9fEjZtwAU169_VP?oATzPbCBHAmV4^_? z8xbp_umH@NjQWG8OY?MSt$mXBnMcTO|JI5GXkyWW$qqUx+T!A(i>(pnXPe5$TQL^G&i8EIIraow2>xd{Y*9;;ussJT zS=?9rP?OJ+!<+rBEf(rZl%z6xfle+cxsHw%*EOEOOo_?Az;o~zS-+`7l!)k z>`rw~fZQ$+^P(jq>?fK<8`J1%_ER|K{9Xh9$Aq*fVf?&*`j?&JB1%Y^K@+&hn4CX` zuVS+*^C86^-2i4=3mq$tdz5WR`(i$% zp_!I3d8nIi^I7xI+o!SYy}V}0f!yTrxn++r2_^ouMcg1VLuMysx_&Wv6Co+)**Ru8 zv~$CuSj@5#k==5S%)k!2>ya9b^S6z4+6mc%9X>QR)V$6|8w65@0d|HUi#~dp1sdw0 z=;hJJy+SDWx;+=ERj@~fcUgE8ORn)J1B^4v`0%!zx{}Sp3TFlioE3A5q(>S$^+GK2 z=ysi*G4+hRe;Ur6L6h#hej^2=PoSa|AG;};I0IJo0>5cjACbddFgubDh|k}0WtJRP z?*4K4aY+C%iSiv(M&pc0grOsCRef`KMP+|x+BOKD%!SUa@*V64d{ymT_Qw`a8;QtK z%Y_lEc1`g(h1IxWn098wJNsuIhvR#U{w#|?CLju>@chbDWvL^^AB zfAH?36k_de8r0Gg4NK#ZMgbgupxS2}gAAu<>g>lUh9fmXIWl08DE_zEX_lml1TAC& z4MGkoYa67)Q@s#uD^Pb@cej1SfYUZg)Og$*^?s;&&!D(*I@bKN3ci=j(m0n|Ty zL7c$6$814-$BW~;CzanfOBfAvLsD|Q@wk-MH@$hdFl+3SOHS<1iW3-2%k|B$+f0(q z8h3UOFXnxu)PGu5*F26U0{xSfG`XYtaL1!pf?z`u>xdE_p+BhJLB} zrPA7nk^Hha!Lwr%|FYaHV*8oD$ZX|cZw6SuguRcj$LV#Yo`>%l}ulj$pMH+1!6%L0K*=iitTPz7l{Gv-v6`- zXb?1@?c?zE3v)`F2S1~75;U~Ek*U%(P0a4b^#KOzI5sIMSr+HSzfXM7l}3q4${x6O zt8vtg>CEKk?{FC`ur)PN{z%3Ye*mlhHc^r+zf2fLOoc3UCX*fL;Lg9s=2#W|>Tj2ieoX2A~BrRyYqYL z`v`vs9X7;Wwh{N`V3&z)3XECbPjfv%vsAAY_2^b|z=P@fnM`;TuJE(~f;2%QE*?^7_umN%+Ws^TOP zB345N;i8KCE5_~rXHz1xz4eW``DKE?ZPK0V$*As@kgAG^v(S6Zz)UEAAZy-Cj$RTBeeE9jjGB$BzB^V z=z)WhX^GZ}F_XClv+fcC5d|&{Sq;Z4w+eqX*+v%e+d{^aqQH*4g7klpK8{ZTLW{pP z>-@mwxpK0!eAvEeh(4+l3kot{WiFtNx&q(mN1-J|rT;v^FvhM}xKp?&ud7$|yB8z* zFY>mw7uX|rg0p!zwfzxRzRSB^ZI&#qz=%oPFR~sp&kLqs`Yp~6aa&@&G{{o+0SRF- z4|pQ(lVJBh6v=d9T2oYYTsw>IjpVFSi5N-X8BlCRgPBZ8TP%qQU!x&A`?;HKSUjQv z_6P7kBzZt0Vl60Up?`tQozVFO-_*!54o>}+sDo4#bFIC|xL=fNGJ~wqp`_8FoMXk# zulY&fefuJFqw*w+chDIN5yc)%m^%uLdJZ|282@91ywC!Po12D;rz_|>GP}MpyYuAJ zH(|=TFzT4V>KvH)`wYKqBljkFvhsCLkxWr%oRbu^FrGwEO3kTGt~L<=Pb#d=Ds0h1 zs}c^w=p)p6`E6~sI?Ak=MxPLb0h>I|5~4GZ=Va_9CrKArX3;3ljRQ3U5z`I~YVT@!|BHw0N0|E=fUSA+X0P zwd?ACi0B%4uOY)c#>RonvD(QA;x}klIP9@l0h&;uuo?rk@RE3@sYOY-~!eLu3dP9YFOC6`IH zx;fXFj}19GLs8o6_gOdkH42c8ACKf9n^RkV@mwK5Fnl2Tt*DEnXGl6`Wj~h2o%g-( zj>fe$W+hc!6mD>Zm}jQbP*eNiHINOox8Cs%E~8Xy%W70=>4nK+y4k=`=&g@f>{{=f zsufhp_L6W^%ksp4pGZ-zz0)+F)8`ejKqjq!*UEa*G6{{Z3fM_&v|q^#k0jW9a(LgU z)LzH@f7{EFU=qz~pabHOoOaoL!I+Hj4?py-8q~nJxtiQ~yj;)r#tW2_TUxnD>iNO{ zy$f(SNXf-;O`u#@-#MlJ9|dqr!QNkw ze6-7oPVl13w5IL1P}|c5CdU;(f0u`%Lqn_P?A@cGrC!&UKdS+Ieb+=>2t!Z6wIX>g z+jjvty9k`G7~?*_)#+68i-4-yRkRXN0j9+Dlr9~2Q5 ziclUdiD%IETV)MT($b*J;ujpUntatmuVPa;)nv%tLOT&kOOXi9(9pn{4|khqPIyCs zd6izJJe`?fP*#`yd}BM#5Uck32Pt}1chIdLykYv@AsmyeTj^}M>8YH_Mg+rd<0eK* zH!-RgQ1`-M*J(v?o9J_SVJA(wKm5*B&_(5qGj6cwhJepr62gl-lwLqLT(*txt;P^h zvvzyzl>HUrszL4@baM+AhkL(1ihtgbBHayQ-my`#(-uMoXc-s@9J{-Vcq0Vky6nvarPL8y`-4b?g9N#Pez)uy)qlpC8 zZPtTX8M4pmd2Wm{EPFA2CZX=7qDU=6y`wq{Q!c5(E;BAs$-6V%?qp# z-YLoEtOcZSQ=Q@g<%Z#WzHw(0esbkYG*uFb% z@r(%MNFyS$1_jRwh+-86uqoZ?ZX_)>Up4!%@i5H94&8 zl4Y$uTH^P_rY2jPWCUS{SuoCB>f6f84Oy2?+4l1T7L9&&0}^{GHkq)Ko`I<1fi8Ml z`A-W;&+wgeXP#P92?b<r) z>E(8UKnQEPqo>)C65pOf_5;TJR~O&+J$Wiean5TuU+mS+KPd9!6y;|i0zO+7dN${I zIW4prbrE*f@3gRJ5Ynr@ddrGqR&DYLnDizOEne^FNtA)HnhzEyVn`tJ@j zhyIL=ZoA6Xo~Kscww0lk9MvBbU0XtCEc@WgD_*@^h<;%LlTGo?+i0D)r(vs|x0fBf z?Ngw^Q+LMgkK<-boe$t-CR-A3n47*&<-a9jcKcwEJ6_(p4m~`~h(s;Fh!QaD(g?ip zBTkf+c#opz__;zsh=4v^&M|n74(Q8^KjC=aEOVb`zm(cK8fD!XrfUVX25D2$a*6)% zoqQT}Jv~gp!{A)!k6?IvlbXRI_tPz*^nD`~cuz=^?|4RTLzu)pN<$G97STE3}E+x~S?=bDiudCxsTu-3!S zc}v>{DnPURICtoNYE_=T>J=ohD9!cwJw3zg`noEY@Ja`1$geX+C@y9eQE)Mp;bzPH zL|=*zZ{O?jpe`P-EyZbmA2nGpnIy%l^Nm^lx5N)IVt*X@)px{Ip=WC)ltK-uj}qnQ z8EJi!(bO~EwnA{o1+X>umDuZ9Cc7)~ zfQ>SQrRYC8;lK5s(OP;1+3{-*)m}`9@;uRdN z`}m0+T=8)TCP*4C##;GuLn3HM}a zRzbpdhA33Nc|j$9S>ZUB?M)%$E+5_bzKfAjKKBwYlFwPFCZGGn3Cjn-V^ZVyE{ zp3f;^nwicP%el9=xEHa>*pXq>V6TtdBg;?YW>uF1T0_V_n73%i(#j?XK_<2lDPILy)a&PetL{Yn)!FW;~(2UKJ z*-Chl_P7M%a9zpJ)OEEdz~dZz^V`N9a{H`E$@KSFJg`VzlkFRS0nB`x{KpX|2o+(s z%DDo{$HiyN-h=#}ZdeZ{hPV1kKzffnsq9{Fb<5hEG#_q-$6^r+KC#O?K2g-60hXsp z^n}^Np~%V*n5L8&ja&YUJ>Ch558@=a3o1GF`pfIw4Wqtj9)PLE)?8%}t~-y=Mw9Ot zMiMG*wm7HflI#_%UG-L*)vzepluKxki|dyg_DlWAjkwR~hM~Va=(l*lNaE*{YjgMs zz6**C#G0jw=)YYJ(cO6 zOB`9>e1`)%8XbARKt!%183}x_ex#U*Gw}V%-S9vZ<+xm49WQ-%)d^{Xu6SZCC(s#8 zT#JxVPewdfqoDY?B_XjdBMY1GBsrxQH)%o`pCFl4mC53B{UDM-F!_YcF3^TEd#F}T z%_g%1?3q6$%Cj`b7_Glx-*?=^5&TwVCGbL{8Z8NYTtF<2cR#0lzZ}s%RYBVk*e11& zzX34kz0wbF!oeokgH(+|7^10$4Hmv|Dmnu~V>Wkk)k%?fpUA`32ih+OO*-8!Oq@Gn zdJmiIXMT{p00j=VB|&dz_+HQ5aWY6!e&)VorfB#5ewq;ejcfDfwIrF}9t_1esx{ZVABhjL`f;fH9LlHu>;uIsQtlhZ#a2|5thpt{`gof=@RHVX!6&t3F`Y35f7?v{Bewa&M*wJ- z8SNw33bvXzupzs=k=_1a%QTYaH`X<#P_4H#*%@m2ev2&g=V5ALErbIw(aWQ5(7E-~ z(JG#8^XZFQZRTtbWm)E0yj9?!RBINCq?8PKr(Nb84JCGCM}?VK?lbJSdxTOblsD&W zhAk*<=UP60bZo`!Xwhv6kr=x!XK(l{>Sn>+UFOx`Z~ z29jxV{`6YF(TEW(IU^Yse1vT#4|Dks^pA(l#Ar;-cab(|xP~wMu*FxJ)Z%&aP6@JE12nG`>pPib{94ITqOb=K9k=0w zVXU~bjjdViINUkC7ka?-HzlT7D#m~v2y)nrKq~{k9~Zn6=NuEtDv0IKg}}qmb0;HN z&PBNP1@eMy-Z6qseVG%C&VfytaAG1IvGHYc1l}8-SUcZ%h=rq#p%$Zv$jqU^uFhO1 zfl|}^-vhtjdT|ewM{*YEy#xN_F-T)|#$~exzEi&i8B@^3hhDNbxmXmv*q@%=!g-(d8-ZD}YH1>|0@ zM<0?Fd}qz+7X=u$lUknA-uRM#&O3HiCSLel&~?6GxW)7JU*vDURO5nBzbssZxZZ{a zy`CUa@1HSRMemaZH)ni8E<&R7R>|t^LOy*&uf7ro7R13nHj1JNzPhZK8Q# z$t~^7b`uH;Tfj2#Vmn7B7>?((hw;*t+t?TJwb=^_MG$(^a2OVQSY@O z33*r0@aXxE{aRW_ADAWAj=siC^jXXi3KX8JBvTf*JKC&=3PU+uK*zNEWanhU4ED-# zc5Qe}bFy_Yt?oc*irlRn6dQy9xk2`{< zvWHoa8K29zTInQS!J2Bk*QwPgSf@Ql24MAR@`we})|!#n&kehpqO_Q}%vcnqPnXxXqQ4A;E~WD&;o*aeYW&uzu|hSI2Yw zn5#8$&Le!shh^fNb8y7ZasC^PcDX(Pe)v1!qT6XEkfa!bT9)+ew%Y#Ax>jlTnU{ex z@VSI1VixVFK9S#v>j|h*IrS_B@2OG4~p{#eTg9E>;n5S- zv}?cRF3vAz(o>?q;c5q-%*RMl>6N)QDC+0*_EHcSyk)r?t>hmchMaD?CC}oR*2sYI zI*?9e$ZtHiHB&5y={02pe*z1@Omjzf3u-GuuWb`#6k|_2VoWAYyuCe!L5(R%aUYb5 zdk`CpmGnB=pyzWrOKcnf#{BoEWx^ZvgZP}Id{7<-Nl99r+03*ITWVjASTM4E)NO^KJ`PHrX<9EY)`KcOy8fIXLQ=6;!h8A-`*zX{C*m#bve1Gr<)aEb-S zCkdPMv2AtKmrT(~zh6Tw_5=VESsnA;4e%m=)*YaZ4^Z>Dy@VY*Ve=kEut4cpv4qnh zCe%6d!E)Fdh-Ki3n;?s}k0xxU?tBe-;XO0$v6eI*JZmW;qsA;5H+`SMlA)!-bDUPx z?UEsA;}41+y;t{HmKYf!ub2>hh?s3&U?9-|l9Mk4vrvcjm6W*~so`Rb@GxaM0r+^5 zD1Y8Y4t?LLJ*=@G;AY=Iit!~%I^pn>&=tnV&~YfzIp>LEe`ulCsq}M2PBX{ddr;W* zx9WC4=LJ6s9~N?vCyr~K*woN%nL}3y{2Wv&unP0h3lqbK0inZy=mL>K`&|Jm z=2%b{jPqi0-XT8L`}M3M6ooqxkM#a2eC967pRes*>$ftM&zS zvBl9+rxyvlYww*Jje~^TG#R5n2xlHeF`Qp9wyml$;fWLVDaR%*O;cJ|*ca@=luF+% zvNILBas?tx%uJccIN;%^Icw7a>=CbfQL92*5`-J4eTNS-`&Y=*R;8RjdNO@-u8ql) z0rc&*A%Gp^6K%C=+!+V0(C2+*&<~4=G%{noHSGy0%-RFSQTO2IN;Pa=Mi>^xwCG!R zWE4m)IU(-*C2sO$yn-?-=5r^*=wGe}GBeO_Daty`K~MS<21=pu$?mk8EPoKsNS3zq z*9B%80>fT5=p)H#D8f8oOLiG8jx^ouwa+uN8tP|P5a4*@Bo?8sp{RVKWbBG6riI@u z1X42|mVm0&*lW$y+Ics;C46oPCzS<_JW-_p$-N@bNOX@KbF5e5m>wd zx#E^*y>3qH48mh5DxSV12x9s*N1UT${5(9U@s*R$Rsje-*FXKveWs9NuvqR07{SG% zXrtk*-DPW+1B>rz=Tc4woP%q5Jw%zgZdjYjj1#hRhr6BFtnutV%t3WHyS6CMFG7OB z*Sii(*^C*;p##teeVAxwLG92gC??_FgxTpb!S5KS=Z83FvBb|{{3gyHoO7%RI6}$sIloW?ORN%=_dn36$$CWB$z7I^gqYwP?V+3+V8F6j(qht;pjZkgy3! zYP%Rccp{;jQ_nf*4MrG=G)}*B{}O8s8y`EHFfkM55fMSg4(D*T?wnVkDC-j@-8&$!mm%QMJo&6&iK?qG&b#SYTN0` zAXU;_ zb^6kLz!HH>)kEv)vwR*cDC%6(XsyV79xv-(SjYIs#zq#qp2-N$>_%s@S&g}BC2ER+90zcsC()7>NRiYKrH zmE8%#FHc{mCVS9RgV&h$mDSN5=vQlXI540wW-v-dgV}STjCqYmn(?)gU8lz&m)aa8 zi&KftnNutkOf-UI#ej7E7Jq{ z5-tYv;Y7A7PhC=XlR%=WCYE2wiKX$O1Zk4ch?;`4G?k600kN#vLYN)FT}`ktm`3G`dZ-+ zAtf0MC7clK2#XPBvr4lawqWhPI+TG?g1`oOyiOT!e6!CC-XKQ6KYbQV|B~ zwb`ni>pskHi^8tKp_N~RGCq2^Ga#mLcr!lKRy_O6^cLnn&cL8l+E4xs1x;G*&5PBQ z;OCwSE7kJsyoIHY6RXqHMe`%LL~VeqZ+snGsY@Qfe=}wX-oQ{3 zQVeoKR{Cgp!LD`?|1lHP+56 zF4SH@ip+;=?HRkc;Fr{sk3ef>I+@0gETOITbrzd2#nynd4yW(b_%&Jp9UVp~ov(=5 zOHoyTy#lk19Vb)Gzku_5O@1D8(t)4^9D zn0_`M>nO^%N6Q6oC)TGij?O7h)__qg9OT%Ga0T=mOazR^B`<$=^X{E%(% z%6*bePsFIo()`mS*hmtrO8J|T49EoHYhBs)D<010t>yJ(LiXb(Y|Y?aLv%W+t1ya1 z2f`QbgOs#yu9|RSk(9F;u^xo-MkXs3%f>tWRSe^BwB<49u{zKPiAnIcIhROjus%}z z<)-HYZZ`qBc$tD?!c9C^?r2#yg326VqHnh#qDk~OTxEWmpli!5$xQZRvb=)coKmAi zjB-p=3NZS;vL9|t>fYYLV}A%2fCBq0nW|y?6-Or~oZ9&#oA4L}U|Yn|fSkiDbD( ze|tHgm@9n`t-#Ze&1rs@mH#=p98$a$r4*sJ5)_iJZILox3%6C^#@YJ zXxC8d1{@By9ieL<*%$+ZQK=_G#k%&=24@;ZrS8O`E<#{QW|k-pyM@^YUMkwpuEk*mKPu4#hrmRtrjo;}9GJr_l`ye55;1kC=!r?b zS#~p4!=);L2b>wVkF2gPlCZCOX1hsMSA7H-hetiztPhHUSmPr;EB7bCq#>vY*#rjL zKjmwm(v|K})fF0l`=jNvKTGN5y-2#}yMuBpBr6qC-sY+<&vxUt76$c0`d_-+3?Emu zcx9zP%XzhPK*ah@J4SB$_ZuKqwB=vcqx8u;oxgF*0r$B1pS3edi+j0RbVI%=&oqB9 zvA4f>z>)$?oqg-4g{bS|oDT@e9cXFBBT#Mz%?vZZipJK9SfCWrGkHE2E7W%)aIf0jGH15_MEV*|vhM60<9nBWW9+6@ zw>3kDdwx;qH6`Ak-Rp4a@cv|0uDLij`p2TG0PhxJOw&2MXN-Np`Y6cxtE;t95=-3n zj!_x;={%HzLr87J97End!#HXvFKQb2R5GFKByOtCGd4WbL#@@tw|-A7i={!>1P>E5 zNUA@Ry=aa|Oj<`L%o3!Ar4{K1KJd7TmijUO-UaYyk%68aN#*15@LdO$pfDIp;+@Tu zO>0U%x#T3sm3flGJTIqAK~*({PQBQf&&CcgpntlmXn%cmdcBNThg)&}-R^mid>*#P z?@9m?O{#WS_j(f5wa0;I!$8pZ@+@c#!VXW)VL<;E zoqX%aT5<=(&@xJTeDcYb2w5J&6v%QnzR9;8(9Vy$k|o2QU))@%tY64}x(kcef9!vA zxqAv0s!YNuW9ir&tboGnZ{i&W<3YjA*^A0`(&MOKP9DSVA@GP9$^{Z9ux@qR-jf;n z9pj!jVQB{*ieR@m9U2VilHT9f7-%xdwfXk8X+hX4@KwdSyCpB`X~`D1!?hJgw|eqS zS3&7 zooFA&I{A_31Mu;2`lY2Hp(z?Hp$DiYP$>+Ft#S1}A#aY0HXM^|P#>Cs33d8aQMLaQ z%1;{j2imeZx_wROy+pfP>hE%u=WYJMC(Oi}z`hs~1m|TXs?s zMKGYiq&BW6{~ilp1_!Y4jpP`wU;JH&w;@BN7^yGPP?JQ49>Cw*PaI=0z!Xg{#>^8D z*WPV^O_g{oi)nfot>Fk9mzRQkgf(M&NOY@pEYMxzTM`l-qxQ~N{J7<{%?*++8`ZeY z;cCBcdvP}~Mvv3%xGmu`u>{tXuk<5^M8@s_#@j`;HCNxL0gxwB6Txqzu zF&_4)v`Wlq^1WSyJ3jY$K%xHwBaaL2^Zui;+mM9?l(A9(P?7?)ji+~pC#~iUk>UDu zVsROLEI!h8R{QC@bDMEsRB6Hg!`@d#RhlzvL*v>sPUG(GPUAH0?(Xi|G;SLjcXxMp zcWd0;-TmyDZ@!s1cjxwB>(3QykzIL{R4Pe5RZpVF(@yqhAN%mwUN<$p@@Eie+e(o&f$Vlr1^H-T)=$d(zBUS1PjuJdMqE|b8`=Zk&0J^%!HGgxA&wc1a^Nngb z(sd6iSvf^^@w}TReG|_KRo-z}(BNpU&FMn*2|y%=!V91GeTb5}N9@M@LQ%6RKtP|j z|CnrF#bf9?L#sD_c-59Ls#weA^jt7u-5nuVN4+=YMaMK%jFfZgy9T2ixi-wC_gYf@ zW8d4|EOv#-Fzsma9^@M;`KY{-q>BsO-r85zcsi>>ah^^3iY{qr*)anZYf!dUK+cR6 z4QX(n9AYBf_yFV9t1)ILt-YWmu_xSyM8@FH$XgDurh=&;cetTp$!u$#(Tj81F5huz z`^`ATwZc`IW%(WNJXgN4_6_^ZL#{u@dnR1g`CROvC8L4YnZj-r?kjtCZL_I~GRhcU z&U4bnx5@lkcSDwz%xzM*q|`&B5B$#YcFVUSQU1u6=PJ&@0kjozGe^j%k8Yd4+Kl1UOQk2C%9)v#)eo6#F8;h__1o!Bc??M4!amy8Op&;GrfCz zh$4*#7_bNoU1AwqhcIc)Ea*~FeioSI7W)+BcB-}BOmKIqX?Te4;L1)i5#r{S=l)!O zr_jd5bxOOmU3BXBs zLPVmYBWdUf_ws`KID+oDlD?pDuuyGkaC=*1_U^UcksF31!g&-7XBwa-i@l~Dyx6t} zg1hGJbf`Q=8FbykMMPS!gd4l3F$~Yll0=pO&G7NeMMTFvfzk*;wA;KxaRgT8<4m6p z{4h0$-F^3>(nzE-H>mn8ma7RqtEc>3Wfi%@PvR(++%BmQeW7^b+mw}gc@_Q!nNgi> zNipTE=H{!T6&a|#_ZBu!hpp-=$OLxVu?Ek(j?rktKPGf?G}&sKYcr$zcx)aw_sTT1 z1RIijFtG~i*M#nj9Vuwxqdqn*A{m&Ny6$PsEh^Gvjny&nvyPWx_I?I9Qo4HIQyt&b zUQ*GWwuEi0Oazrf9hzAil4uFaEGeioeNxia70bXgeRNugoIY(y#aj>7pS?sE+L;h? zA_;50O*m1nZ~FDg`*kO&$_swVu`0$|mOV??nRu=l5BBVXOLroVt2epS1r_f;pUWQYAnMD$HA z^|e0}bm;S`>Gwul>GL&k3(kh@cbDX3ni_Fb(mFB-5%K2LT}F|^yrN<=S8(+|p{&|E z_QKv9QpJ>TJ%W5)&tx~Qr+GNUMpMFsVy5TC(Xt}x@Q@uGHlA1f z*sH6Yg1VG@l;`oon00B=iK`y>zH3z*+qEb!h}M$3Te?hH`s9^{A=J1AXMdo3Sy5$P zmJ6CQDFmuN~x(7aq5kmmx!;FB0Zl$` zsdu*1c96X?V3oMjRxsqIqS={syu5Vs#C3OnESI4Mr;*!q`?F!xIN+Sr&?TDfKIZ!c zk@0CagJ-o2XUDOXF+=$`CKK|YrATuGJ#`5hCN(2WZDp~&aoCFZK|If~mgnQr>M}U} zH6}*wF{L!4NjyZ>wxL9wlAVwB>X1Fh0pC1Me$lG3`qu;N4{6V%?+LGK+N-FXFGk>^ z4u08NYgW%U;XJSOn#G=*o~ue21-EJBimgaavm5tJ8$N??ZXa9tP22Nmti&Ih^K!O(Oi}~2ONAG% z<DA^W75s&?!%JPtuSo+DBpUSD2@=+b5$@36?9M?OCd+rD>A zE-cwizJXlO+aozhzq)R}hICvD`COmWw_ySUz&`GJIkajHk3u7a`K^6lJv;1lxsUoA zuR3IvWM9R$r5XQ}{z$%hvw|Mf>v}m?!_aTq0PhD({nbZ+8vCs>Gnm>9Fpb{yd!s+Y?3teKn0tw9C>C+4m`8pdBGl4^5-JqW& zFU1^W-p~2MIdd>_sAXBk5|lhp2PuvnJRL{Sq7ouaEv(o}G183tMgb@_P_XJY_zqkW zQkpQLv7qsEoQ=I>>F%t*_vhq1Wga}TYYZJli<+^MpGTYRBCXAiAmu2QNd(&ZoJO#5uH42y}7iu-t^V3F#DjRA8=gG+8nPW8yxi_s? zU0K+@5x*EUrt5H=STUp#a!Wd@Gfry%NxOgsp^>7Y{-Hm>Fowru0(T^Zf>j%yj3W$~ z>>&~vI0c>)axm$fSn*SJBBZH>R2}8wYEv&L|ISZnJEJs|tRw^WR-&LWmNA8~T%WE@ zz=H=pA)dsrPA^GYtpPl&BHJ?1v|ja}^ayJiW#>~DIqPxwNSpztSi|9gby%QI_?Ng< zpP((?X*khBDRaK$dz1W?7AY9gNGT#;z0#&M*%DY1mU`7(%1B9W$P&x8%vkONRI0Up z9yr*RlyGT!k%h47IfjyLF?p-B@cI(ceid(pj7nR+~}(>nOR_J zQ+G4uVwzxJddzuB@`RWSvfl?EeQIrQvT5<{nGmDHi6^rU@)0@es)(q#AEZe^wZpCyk| zzpbo1VA#sNXmTH(V7#42Q_RV~{l(DH_mpGq^6A~dM0ve02g3K~>=yy~0qpm(EGqTI zJDO7uw4f!)We#B~N56>aA0o)3BMi%yyy^D&VL6L(_J*_6RVT`a8iXa=oEIB3y#M9o zxnld3*c#o!iJw)non8o2Ae)y{oIMSqS=wFo3^X8^5*Pg}o>fT|?(<)PYcYF4uW=68 z9z_@~#F_My%fBW~U?DvYU3Vhwc!iRt2|AIQ1sH?^?aZR4Y(JO`4fvZZ=nB1nf=Wj=U}k$XN%@YB=tZjzr1GoS6dGTWtpIXr&g;|z3+Qzcv1ic!ar@=(M4CR$=n@OJ)u%rcu%#KF1ha^1 za-%4lO6Syr)y4Z>4Y{@#=&_Q(E>|NN_?3heyO`K>h~)TYR>K%S#veY>bO%Q`rxY#DS!puqK(AZm202O<=#m#0G=(D_H9z_2d zFTVwp?50cHv5Y$#s*wtjStk>n$_oFICb{~YY2(T=Lf~dzz!^~TSY-|YT>mB-&4c8B zTNSM?RFQ6z8#x^pgnCw2IkhS;$lLF-Q9$!xsbjME`%vN^njtzM*;DY7Grqpf_*sB| zEq#*SbGg9ZJ!%3eE|H<&2v1pRlvlozd3{%48E0JU_t1>_o2Q75p=FLjPA|%vua`{i`Vt^2{%6g4q^8rOna8v}Eo47v~nUmd`qo|Bvquj>n`=i||CM z|7E{2Y0}GbXbC46$d+*h{Y#!;2wcqHi;l1l^&dMXDD`jZuK)j!KWKmcUl@|ZS#6N3 z`TP@w_P?h1K!+?g`J4y@SuXrWSRR!{nm9%rcsKPoPnp#w`J-3BQwxNYvN8@L6kQ@* zFGCejxx-07>p41s3~NVcXX%W#(SM1;Ak$ue2^3UPQj&6&kNV}Ok)}Fq^y~E0Dl9Cl zpq1h;5+67QbDM3)IAe*n16}+q7!cGTF{zJ>i$dy=ikOoFio+*Tt5Xe zbQhYp{q6Q)P@H5tB2NJm3ruc`1vj`?CSg*{#l=sK!mq%h2pA1dG3yN-`%fNah$9sn zhcL^sq^~Z0s4z}hwQ&W_R9v1db&G$sj1pu% zgBCfBa%N;^=l6REI>?;C$G0}nSX~W0shC8ROi0orK$s{v%?>(q;f*Zuee55WvhA{b zW=JrwUMFW429`yDIi^_)kVHcwlBA1i@QqtUUQQWTq?Vb7C&K(k0Tr<4g^nhb=q$`& z$42DiFR2_;sK$>0A2sf^FbU(i9aDkYsUuAuaN<)-c79F0fYz)eo&)u`IVOVX@4ff> zadII;WjwE@)vb+8#PNB?qtx&Rzhl!=#WD_(KBQdinpkCM5c>nsJ=q3^({;bw=%8mP zp4(F?^m(qBZ?q=54U@*1a1T4AZPC$yA=92Ndqg)xWR`8iCd9Yf&joWo%y<+f{{(~h zt)n1<$m?`|QpkRuXQqxtIN|8w&5Y3gqSo0OInnWW$TkP5j`n*2{R>QU^3wRPKPSHl zDKa8r3hhkaE-O)LpzrK{bM!j*h-*z-J5Oc|OIx94e-hPu|LlLyV$&5M-g(~a}pu+mxz{=$6BJi~=d_uEn3 z?I|(#%g|BSqDkIfZA_R$uN2+)9e^7L8z9j4&fMpv*w_ptkMngI>~$aNW1QZlJ=k}} z?z5_;ruxm4$vo@9&APE`H8{sCrcVtGu}Dj0;CiA@H@ojEh6=k=4p_oDnX(hy$3-Sz zA8q2i+-Uva%PfNjSc@!KVqg;LK ziMo5Py6iyTZK%YNFCKOv9cTaA;AIf zx=sfw1}XRpBC3kq{D2ES>rMEkNzF}no4A7DQ2*w}r}xL4aP*!H@H^f0h}Uv+$5Z&;=~K3^q2(34&8 zBnbW4`?hxY!PwioL2>fnY8try@5~$=;g!K$Ytl+x3yxXj3a_*NCn4a-Qdh zhw1{?Xqz6?g*p4B7mK6!8C$j1+@EHeP`oK4Lx7mpi`=xa^u360M(RPqw z<0@D4YJdX}4rQ&MYUL4!1`Db2JOL>wk6xyV+u-!#&&uJ37ieOEyE3WdN^74$YnF`#je`Vj*fp^V$so067jdEYFjp3@_)qc zrd+fox)XkW@3wD9S1$k0re_N=EbO11ojonJ4x*O#OXya#RZcnHzYQrcMvFx{yOkT( z1XflhWYrE+dLa}6k?|L%UREc-iHr65p%~TMo3W-A%&-~Wqc%Kyh2db(fx0Yb?Fo7n!;F|>?+MTItIjhmTr7Ax z0yl?SR`SG`A(CM8=TYx6YizO@O(E^(%*{>7*M%ETjzvy*l0(b&iDxmNakl!1wBtY; zn%dku*6S`5sBDgi!9+fI!N{yNrZ&_P z|Ine=MhC9d$*mzLTro9+#ND~+8}kb1A~yMQ1E8V&WN8}890hZAa-A1ysi`p5spQ9j z&!g%6XE&HJ^|5VtG$kk~bB5vn|a+nu9?;xMml@s@Fyx zeMr05xeeMhSaArWqQp`Jv+;EA04n$T+rOgS9MmxU?kV;4iZNBW$dAOK*ymzPeoo%T~MSlD8N0d8B?-f3O0x z9%dm1*|Gi)i`*i&9?9~YgsCfjOGOO!1Q|a+ekOnFY8noUHaYM_ ziF9IUmjy6l`e7c$_X9f_zW0hF!94OIp1BA9JUeQ7V{WvCJd=cNe#H`Kxr(!sGyJie z>xM+SVBq`g7q5$&-fq0=M7vGHtM9sbSn2=zmBtsi?1Qld*9o%VGpyg){#_$@|lzoep-gfS$DgAVIs%Jh;@?hipZ6} zC1}6ZBxWa^d8#tYgm!novprU_2R3T4mglkjuI>I>6w%v+?+Jti%P!$diZAnrnglg1__c zgSQyzVHFn^a&?7xqUlE}C~Jtg-2}xWZZf|+Ww{F5?AjxOO11&@mM(~KZZm1BzUzG^ za?2zPP4C}p_E2yt6Zr!!Nf|+dPq%la<~|o%9_SwScwAjUVlG>5lishD)F!oEt9{{} z7y4_ZD_Gv{=(*1)xH-#!pAAd_8^?&ba@?&q*eVvz^dw-^cAG# z&{h(3#ccSM_M+uh$m`f4eXJ$eZKE(lZ(*)B2{+?4AMMYJg{^I}RFD&w_l!%gI12uG zVXn|Oc>?Z3@?RJQwq22fJ9&-t0|LJIp<6$u?@9prDP+Y;uy8O%g;~i3xR!2bv$8m` zaqzGhTEmgLkDnG)sUAH*sbC(7X^OBBJZKE*gRyb@mg%<#N*(MeVU>Q%?X609DuS)F z=*w(XZ=evzTj`CCJ{gTWZp}a*F|(e|jjFY{piD>Q*C7H8Bd(t3%bu50)X!-AOM3ky z?!>CwW&N^*k7T_HTSS?Iy;V15MhJJA!@I3|cZ!vbZ?*#j`ARjr-tjcw$+57`3FZ-k z%=L3(omYKe)#bD$pRQr2;D^#>rA26?(uh|SqJhx|hJN?mJ|52od1WwB<1_{h&nDx< z3w}Hn`=-_U4@lguE({9WdFE@7O#S#|YC6Ipd^uwL_&H5HA#?VAh4ZXmGBsr`Ceq=H zfql@GF{S{F=yv?PwWAlhVq1oM!RnHTo~HbiM0@LUTm4o~-F*H+in`1FqdAUFYdD>C zvT70%)01QMFt78>VBOgokIt`zbIjp9tGxIJ?HQzUH-*VE=GpZ8sTo`RWlYfqzJajo z%-gf5!UFni6}u2q843&&X!_EfV{)ejr#lRdyN zyv$bhzIN5n!1wAw4$d-jX7O=SV)>akZr)P5$;K~HE=z9+L?A|K!%?RS*r0Rf^Ai`bTB-d8h%7?P4iACNcJ1^`(s#qkG|Lp&|nfceWn7`ueolcSYr% zZ}h``NI$`tIcU|@ooPzU+;Z6 zI(Ex7B{fYho9&@lO?AT(hNA0&XOrle(dH)C`CAIt^6cr=_AS&9xrgtaA`=@a=f{W(yh(4IQaol~51Ujr_SA)#vXQwW{T$ zb=TijT0l?DN|^4+?7?Rb3rlmM7Zljn9a}+~{yeC?|aUPET3UjfBI& zm_k)8IR))Vco_EX2EGLdf=bPT&;$iT0zMR#zs=Uof*;S?LPGsk%;gxRq)-ZWp!o)j+)uF4(@%f^uf^tKHhmkTrwYd2{M>f~}C&+-Nzsqo>;&78g{9be%LOiI- zx+M6#wjtekMrHvkNvQ&bWxg>!D%&V$XV06c>kUJV0~KO(v_&|0LINokf*lWjU7M_V zBc`)4KdzOSs%6Q4=Gl1JrxTI~Y6=07UkX#tcDY=@moRp-6LMZ?&d^J!%c#1`F?^#d zebi<+5{Ko#PaHoKv~fa!EOC7X&aLra$j#R z?h;Xz{AVlM_3Q$eR)Yl}wJNy1vvuxxNBZPPPV%`L&PvCXLpMB3#3i{%=PP1z+Ne$Jnr~h&6fta;Kjhhe~_AINUf4kHYBJ zu3%zf=1?z>PE9euqIdfN^a%XSladM~n7;6*P--bFpCWRPz(*BrIDoPWQzYXTRGBjS zzTV+K-jM3AmZvV6Lcr*B1T1$gI;e;>+c%A>J?lWVy0i^YS7V00euKnjzcky3kDE_q zE~Us^U5eN8*qd#;AJcU^@=Me{*4MZfU8-UR^ql;Bd|kmZvoSgtAp4$}@MRZXp{Q`} z(f^BAw@-^J->_pV>g{iR#KGlnlGDqG192X3l$#NCa(E+(@Guw0#NxeRtJ(!n%1;I}6EAjT(aWn?J zd=5&yZY9o<(9Bf{BQlx2*-1}}!IybgZjx~x~r61yugtA>2%!bQe ztNEg{@Qlm6ASWbD7R$cLoOXsEPz zX0SeV_Ki-$&w4Weprd8rr!H?DS&Z9LmEjVqvOvsg{Wxe5PSkFI(=8@e7w3 zIXpy5WES7>ZoX$2&d$o_o?idL-56<@CsYz-Zc_j2a=;e67B#v@6py1BV?vXJcmUjh zqQfi9;Su}IFHQ?uxx)++VDP)q$b=Pjg61_ zX*h4+zd#4@6v~!4g-wbiXifMpf?)IA8+Sa4iQ7@K``*j&IUFclqk@f&=wYJot6`*$ z@8q5f`3}AUd{a00uBqSQ_&ZKXy>Y;Va}#3`5iFvqN0S&21u04@K;onA6zO3OsL)t6S@`i9r$>; z70L}PX^V4L7y7N-f)z!nmJq}|3K%>YDDF9I3Px!J<+u#^^!S>)LdMhZcw(hi8-%~g zJ@)c`DM9D3EQ9&(F(|q>&%7zA;pgo+U7O`;tjPZW;5WUG{)BZxo_pUlRj9qyd2AdLG zc1ojEiIO_{v%M+E7y{1%?iF}|YT@M*bcdyr7BOz~(CD-Bgwyu)9p8A(fl2Cp>1<9a zrK=#^4UXx*ILLTfxVh8)2z}86g@xH|52xpM=EXQLPIq7lVD_bRw0SZ0(RQJC^?oaS zJ?U(WdJi6la^xFe|F~mYZ!U`?(7w$DQ>Jk~Go55Ud7O=UT;w^kRMW!hfil~3Y_52t;8Q5_&Fa#gfn4G+LM6)Kv zs69MyZKC`XZP4Tz-6x*H0vl#Ah=Ma-R7MFxR>0UJ=j4}XZjhC|lJ53Ny@};#%nzS! z2{=X9E$#*ylQ1Qw{;8}`>eK%0;-VcZVl?t(OfqzQO=JmIJw++2mauKut$OS{$Y2H~ z?3B?+N2_ydhs{On`9*sY24`-z$?6pud#iblJ#MH(IeFAm7jACX^S+Zi1r?Vb1A{-L z4{r)Uic$ET47oSJk2(3j>wt*?lZVWO_*<;Oc}Ih1%?B$!C4|Nt7Wz{3iw}S+3r(MK zNaQs6bKuIPwFDX$NZdX!#W4+2u(3$@XB&0l4(v=-73ba=7r9}=h5q>y{k#eTit?8br9w~;b)KOq0>8&Xr5UB#SleV9VDuAY z)(+yMJpeb=_-kHJ4m{aFO?Ym$1>I|GvuFZLF`)+(3JHLwp`0Si6XtP^4?>K@3&LyRaq*|h>DdKuj^F_~)K0EkPaeFH^8tuldVOV6u17ui_CEu#R zA00L{qeM6p`YOttEqu$Ly$+`cgMxyJ%FA)JWh^24s+ennpHDWPKeO4aa%>%(Hy_|7 z(5N%XkQw5p&WaH@c=7AhII_R!zH)AOc)_itP&XSGGb(?>MDWIS6GW8Ztkc?B+?-oTp+^4M zKYW;uP>-A-QP9S2CAwK6?yXE`D1#y~|8O$J^z7Xu!yE5RjtI(|xU{h`2YZFXtp^Bo z{KZ0S%lW?{x}n7ywZcLQ*ph-ByOyDe2~u(#qET0`N&x)d4@F%iA`^g7oMnCQj%4|h1VEX zaRNjefe_{_3jlEr4|l&@zxD`-U0AWCyf8HPlL`nr^`{W zto3t5f&boa3lk;^5G0hEO*_x|E0%#yucTz#Zmg_%@edI_e_W%xY#I&!fOt9nb5;y# zgzjaCGJ(ys`J)C|?68#Um%m!yZi}JW_)je$^89}ZEcoE}G{wVLcBgy4IJGokij^RX zO)rZE0Y!E}61E2o^k38|Q#qNRFR6bnUDxnzb#K=$yKhm|thW#m5s~|bE&`40(t}(R z?VV}FG<^Cpb^!o~MiLj+w7z)q;q&6#9UF7cJm8&tX`8≻FEe*!+ZqYytZ3@&isl zya)pP--Ql@FdH4|-=zs8AV5Rl-{t=(=tz~;ud9=uDCV#f{o6mk--JU7@9(hq(lHMW zQ{Tl89wQzgMTYY0pD+92s}E$2+_HNtMc=UukCuab?L`U|Rx4KlBKg^JKw)D42-8Ci z5hjZJPKq85(X8dOY^vE{m7SlzNBs+)iHWJ{c1E(Z=6+Hb*va?oH1UFZjWbo+Fu%V` z7e$C@E)aAzVEH=vy+~6-13FM}cW>`)c8|;F^-(ot>~ruR%?okHNSPWNd(Y)S|5GCT z^%z3tEJ(jbBEGom=-`E;(>{|+LYypA78VyDWv-t;A(eQ+{Zk+KmllYiAT7baiybJm zX2-uL;2puPxxGotrcH;wTQAyraw{n^3{x_E;^>drav_XDVwuu!#c_bu zkS@+I|4Si$_vUy9$_e z1qV=508;qU;>$5tSqozleM^A(0DToQ$`wj&{MB*oS;%0d={~#U5LQdgPDysjD?_R3 zOY^PkC?%7{l&+g)u0htvanUgw!^is*>Y~f#K=ba4>wxlj^(2+s4g!B7uL~{8JB+vO z#v8J2CH>CNpAE5t1!Z0#A~yw$w0rogk7iXDCO0efN*a+gk52{zpcqO~MB7j+Y&sq_ z2=>$9CiJ5O#rEW~JTuZ)+NyF)wBhu!+T3%g{P_hFKOCO!#+a3_u81qEjBRP}Kq&l@ z%e>4uZwicKwl8|z`P75XesbNHX^cKAuW;C1hbtyEI((5-l_42l8fqZN+j=uZ)L88e zF-sZiYYuNZX`N*R#n?`sIG&B49eQg!D0+!jwrs4j(0nU4G>2=pSQ1pB!3n?mjWL;f z5$$r;y7YSQG4Ev;-GH*eHJ%|PfQJ8Wa_M2lJcXe%{?m2RFhV92xoab^)}C6HrzXJ= zk=}-Y(U;1x^Tx3P7b<1?>t;v|yuOm*hRof5V{uX4wk`v#I*#<>=Z?{K`Zz;Z2*@ae z!ixp0Zt{%r&OBM1inRwy?p6P@2!M2KrNMa)nwM*f{bD8{0>861-deUT%J;n<6%~Vt z?Hq21yUdqwF38pavbkRiM;I}F+WBW0JDU%O9$jz$H7()y zu)wrN&7dnza?;@>@vS*m`-e6-fJpbidE$D$WTxcx>lY)eE2rLZd@$=%k0aVBoFz%! z?|2f4>C^P@bZObHi+&MI(@LYOgN#kgTm4k`t;$xj z40r60W-q4M8pt-aA;Ut8yY@DPguuNS5t=vC$nI>XQ~k+?JD#@V-(%1DeNYDkU&FWT zxa?ZBg^3tRn9zoYDb03RZXa5!TwGCZTff*J%iMK2{#N+SMI2fH?$rUprujMB56UtT zEmGr$AcfL>^OFYIZ}74@l?DY@p6|!(lHxl7p!Zv+jgGH#4~wZc)&+T%j9%xKbb=%b zS+df^1#H=g-rc)Q=%BiA%B>bL;wY3nH#>6t-n7oAPm9tq{KD%Pmex*xNSwDTTIvDs z6Gnr{+Yduhzb*QxB$);2<~to9Txwq$ck>N-_0?0H&cYassc-AJ!mO`wyOv}MC5Epv z_yERG-`#FESs}u8%8^`?63oU%X9%ij;n>?{)Q^4%3G7~xQg%l$P)FYBch55$+m%v^ zMy-5yK!H=`t!IrqErny`wF{sHw0C8&(f%q!{*FxW6@H6DVWJ>XLO5R`0Tmo(`DCfK zIJC)j!r(Od;Kp^@p)Mt?0F?}x>^rrmO1q4Db0nW64Czniiqe)J$L%XH$x5p{ngB*q zqCh74(0dh)DAp=#&1lNTNm6E+P?ba>l@vTqU4u-YsLYJ2PG?K1#fvySN=i;F4kwmV zqYL!U-#WS*G4^u`Gs zJvgVz#KTnj{>#Cm&tE2Oq_*$Fud!?q^~y{2UT!iCSa)M%2*07(^lw@1?(kO<-F?vJ zvnWSywbjc(4oqjCG%QpISmD=LyPyX;4NH;ufE#c3%>RlPMR3|t za?_H#tGcGVt+5)fW>B6WJ_}+simy!Uqi41ltU^EHi2oWpZD4njCS( zhI+mzq3#Jn=vNRTm!@Tr)(hp!O(OHR&)1Xf^zspEB?ED>l2chCFCw`EArDp`I8K|5 zcqTV=*oKNCb;|W}nka;4E#`U5EON>@a;AFI;_~3FW}IBB4<1*oD;$rf_|xky+>UVD z43?0-c!&ZgbSWADyP@pD&h>t$9rx2o-*Yw`Zx;(4pWwCTjcgWeZvW5Nh+hcAG84Wj zrTe{y@6!X9;WQFQRLz4NIqlteNS}O(<%`;{LNQ`&hJdWzu)9lim!*A0L89R!4H8`^ z8hCnw&HU1mG>htpxJl-21k%Oe_U4526Y44|YV%GO415nIH)wE+rTRCd7d8%xF^cZ1 z$*(_uHkGi~8Y*&TD&6bTP;#2nx2KoaT|9HkQsl2TIDMkD;M5g;sx+es8a?Yjb3lfF zBt!?EHju;m2l; ztvEx5-fHP4HHAj81_?;jE>l$>94Z9

b_e1G~x7pSh|Z)TwP#WQA zw1h#rZji6Gp!MuwPHua2u+ic`-wB<&4EC99u}*ywFfwuY#wed?3cAP++kzylTl*@|F%TKtXPk|*dO_-ER9^XY1pH*64Dg|=cnovte z4tp#wB3-oNi&2f6)DeMx2GF8^$xfuK~qGS&eD9wzk=4eyL~=d|j_`kA!C;P}YqpDwgA|h#& zfs7(pc?fhwt*sWt>u-FxYhb?QXi~(~b6!*oJfrU#MQV4hd}Ybv?_rirM+1tk$tQeX zA&CoT#xGD`!^n)8Bw2rT?9n78cav=3%_rU=4R?l|_&y>OoIsuXy&kRe&wBL<^p|NV zutvu5s>(bD@!QSiNG5$*5gP{v6wH@sk4-QzidyCt?^D>GD%p>RKhzNLXY9(cqG7M^ z3~%raMh!>~NnsLZM?rS;{i0DEQbk;Jyt|KVQ+0{9t|v6;QkRWJh`JHt9$9j1`oRV( zCQgG}hrig}@Zeg_+Lold=17|l1Lo?2E4_E>31m0gURxNR_)f&wEl^ z#v9-a`}HdqOdyfJEUMS`q4##xE|dPdSH)ZZTwEHDOI&2<3$|vXZFZSA<}0rq%LK#Zmy z8RgQqs@jzHlB=h`n^|YEKZS1)9#;*@#5AvDXodTqehqFdo9!=(UEIuQ+t$>YLnPbVXjS-dap6)J zv^#Op?k4OLdzj#rr3+pco5zMhu&(@uHy=w+RCCN$D%N};ADS~^RKppgix1X zFX4)MsgXETb|3+_e^@qK+z=2vdXT6y6AydH4F%*J+Un^d810f8G9ljUPKjuWAjH)1 zz9Q7NC;-?=<=4Am<6qlJu=}8wS=+i;ykVd3d|;!0_eSfFbxh(P5G!j=T#xd}qs06A zH7!8U;@7}#bTaqvN_Qk6O3m~e<1=SLsOZs&eHj zCrH1b9D-RFQ3)4iGH|V%Ix2&7q?H0ukaQ;=Y|=^%}G!zcXVi?FD(^8A%-i zF|{?|c;CK!(tcU2u1<61FY7BSGc@hp^SW4CQ7ijA+v&(E`?hI&sv-d$AlbYN4B31a zOJo)!7s5F)nWUzlO5zA*q_*7#rc`CMMmPib23v6FfZ+#bPB%>_=`T$dQbff}&`{;K zELNNGFBx00KICiiU`LAIn|7nz-9D-k-Xhzb*f{Nmk%wrbzXg~5EPv~=9f7&%?RHSOGSH#4z^D!J0m zar5n{%C017Hv!Yk-&h)6koC%#;GdoHT-yO_7fFlO~gu-(J zu@qx|p0Tw*@(*wBZwkzO^?~EP_qokqaNKM3?IWgEjB!l*jK40N+nBO`D#PYA6-bga zu*d&Gy3t`mhe7JJRpyZxY-_gttJ4c0qAE)=$$z^jWi)4OPrN7Ym!G~( z$UCm>Wuc~So)&30c2bYA>ssG9zj}|C2uK;W`_pjmZxv+$j-jhAWS`nC8#=B`N5K8o z8Gl!6sbbQ{*r)yURSjw|vYN+=ld3l#s1^SAxc0_fNBf0K>#+zNqk|Lr>+9H5j;uL> z2^_NL)}*T4)Uo#o*XHHlfK~@uU(ZKrKCY<%X;jhdY37?je7nhCj8ZDfj%8L*A9tO+ zW3(Qrv{0`s^$-kbI(;G!@9DZ)B}Cb_?5UX>Lh6dJA6Lt;yB9oNh9_k>Rsdu~$V)NQ z%W-n|n~J3|K z)hU8B&DS+7q{}V8Bgiuh3_Rh*mQ!{>PhgE%Zu3%Z>5I2S|RA{S=@2F54U2=JtT%wR+L_mGzgr2L!dx9g0n8_!m-v z(RWv~bDK?pW@vvKvi~9O9iJ={#UmydZ^DCiJG3h(X{gwGg&J}?LQd(OD(?Aq`fFIMpom(r&z}q z0dmb+MQK9INc9*^CAa`l9m9Fw1eiUm2fTWsz-(iln3D2Us4%ri9<>KlCg z1_5v!#VJ0QTkgl2G~N&$Z@DkRcPLVek-{N8;gx%QTIBf*OkE{}@LlOkN`|4FQZ{_= zZ&zt2!tvA!6v+`dYnC1O+c3jcjFG%FhQ3}OC!}^ux^ZJoZ~EODTzu-`#C$J-;gc_c?_-FFQ zZ7R2h)6fcZP)XfQ%(cUQXJm^6xoAN0COyA&U|G<`xxJy}9oQ5;sj{ZqvsXuK$N1Ke z9v9ZT;~4UYw;kmm?W4x;qQb-EIO=PmHbZvWEup>rgA=3AhcyolH;MiR)X_8}?v;-Z zye52@x|e6ojwfsMWnPEhFh{UYIiD2gcwfY|*uE179gzN2{n5cWH-WEM2Ldb3ak%|a z`r|kwdl#>Da#n)qzEFR=?~T!p(i1J~D0}DI zyRUUp**;prPrg&bPD7S~cH|J*udJ&3UE_7wc*jo4#EThvJO1iVao(RaO2bko91YQr z-|w(L49@6nd0C?6N6PiTcst8A54Q)`_J!BYxTPhNrl+6kjG`o5*RC;5(`;GdU6Hjj zqcJ5p#Y`F_7u{DozW190a6HqoO*jV5Ui?JL^clWt!neNNgPq2|3&G(X9LD*+?#{dG z%!g=cUPgbr9qdb3$r=vcFFV$L3%llsZ<_*mU9NTeqhl+DKMO=@regdn;te*@_}X6- zuY8?o2J@Vnyw!SZwseNaFr_J&CJ)c>r+4oDVJt$vW%rmc)f)DL6XBk_p9lYaS&y8q z_dbn%S@+~8ovlx9*5jDkZPZ?EzVna*qA2MQj5eG5F%?*4QF`Vb*PZqm(KeLmAT|#& zHym=DZKg39et6(HGCd5*aae6Z=`)S3_x%>+f$tiAA6J4(;T_UHhrjJR<2lmL;k}tZ za*}9|YHi-=cScq@kzKo|M_aLdp?>;DNFENw^|(r%R!mfP&o(#XoO##T%skHHh0R*i z)sy$nf8(cr=s0pw;TCxN-4Qh4!;-`D&1^0XFPi?HFZ)+LeCO>DQj($C7P6;KHNDz<;JU?o~=}<3r*1-pUWOG9XE`N^t8L4zOBgTvDV>}X~TE; zvbnj3#9v$u+GkX&kIlnnomY%_U0yiK`JO9Jnqd6xe}A9G(qgY9n9&X|T^4wpdRDqK zp!VOYyWb(x=h&<5Lq6 z#S^3d*}cLU#e#?*A^gKNXsmyntb4h@Z%A;Q=kH1yWqft1Dbo#Ac$lH(Rb_z zHSvIoQ$vE{NyT#hSWCt*nRNW9T+|i8zu1C9uDAJ#s96uFzkg?vQu`i|U2BwxWgFv2 zR|DFIg}Z&|oNKasL;m3;J`K2Q)&6O!H=pN7u#3ybvy5%ffhqcXzcO$?VuWQiO(e2K zjPqeZ?m5K;fX}IqXZ8I+nLk`MV0hTIKI!?}^;8j~go~ie+?2*WrKO^n7eQ~fYK#p< zy%$g2 zu%0@5bn)%?C;x$tkJVj|Ft}nDlW2FV3-0g-q(`#89l=Qe`0O5gr z6Ix)3l;M9 zT~(NmYCn35P#`jKsI~# zV=5M+Fst8*w|O4TUT}1Nr;t9)e9S7AH~nTuQ>(ZCl1&0;tq8^LRxk}tFnrLBUlpFt zZhno`uM+g$R;2;3{d;%hK!Jv0HaAm5pP#w@l`|08m=7W?3B9P@HhoL&C%54*@78=_ zcIA6xNEgd5HyFz8cCti1vgXEqpOC@vqDVbletdVaWljP1#{RXNB;R4Vw^{-VZlKS3 z*v6uCS4YW|^$NyonV90-uM87jDqD(byPzl5Mn~VNH!2-lNp@a@ z8u<0~F<`{#rNLn67jdLV62o(60h&!ghYk3mE`=OlxS6>VvX^c z9XWhVVaQssqOmjy3s%yRVqH{N?G*>qd-3AS0muC>iZT~9L?jnns|8NtR|B$jzsg#o zUnx+L30A6(-b72E2~9PeQVdI+OCgXog-nb{pkfIREe0l3xJbaN4fv-^#9evX@@C}2 z9HxmGR(R}Tyj^KgS9LHMwG0~&s04kQ%vDFQ%mhnrg!ULIey6DYid2br;f`X6P=Q!Q ztS}*>A;bABMFywZX>Ju&Rzi*(39oSQ#~4@=kM?L@T>(xPUxwqaU81?U2#RbgGIthK z&wNFrc!n-UOAMBB|0=N(O1q)7(!oreTu#W^6@YD!UjYuav`CiP!~*qjd;$sZr4b!< z-K^!WFkw{vG1gcz!qI8+S)&00Ak@}Ew5qkD7 zq^|_M6-ip*Wa7kSr<^Zrd`s?Ll>gw$QEaY3>p{9(@+=c0J)9CmI}hnzV)5_%(jGC1 zT0Zk&o{|OP@L(Rhl|lpTCfl;0eQ0#Vq;l&)t0W3)Q5=$U{N|F-Ze)&A%cGRizMlk_ znKF;M9&dal3o4c)TN!rj%*>J)1Y$z%>?&F)$5hxLQtX(+B8j>YK?RTzZsWI2X{ zL?6)6VoO1h|IdL71}%!1ln``_XHNer01lhi!Bq%18YxobCVI55a2~;TDWMCrRV!BK zHwbpFcwP-k+!;f*i*dw*Zn)3W;r&TeGZ2$M1oEnJW>fF_&(tHC@N?nJc!=V&RUyCVCj zPW^?$m~$Kk2BF=x-nVdt7lov7nUGOyBrcQFG6Es|urzu!(D&~QPr_ye5Uj>TFiocy zxF$es&-j0Tm{@obkvLZez5QC(+wPtEq(|`Gi|dAQKLaN7I_9R40!p@J`NRosDU)$C z#_k&PD8DogwISrs6Q_RXuTyx*fHFZZOyqXuVl$7+|E4WDYYH#zTU<~Vv%CQGbVMpk zum`NY$l6UjI47^mS=}(J82#odh-qm-AZ(6(8e(CpRw_`8^yjjA>X;UmW;4Plzn&rT zJFe%ChYlwSj+#Iq6b*7f`S50Ii@E4k_QDM>HX$1_H9Y@!dwkdL<-5n>65-4{z!OE& z%SYmPTDW~rT}?M*3eMZ;jY<)iYBnq~RI+ljp(ZX|}cvz$%B`y=fo?Q9d z%X)M7`?N?`as16;Toxm<0oJ0p30C*=iKSg_1WG(ZPo)!1ym(Vu2q1e#RAgJZyol|{%C$I+^@FQa!#*O zK*W-p6#6vba;X5VV&2qpLF1Cr_iT+@J(gD_CFg zr#?lL2PlN_hne}SV%Pcgm9?jT%9lUW$~|m}HNHEocB{zxBIIWZ{Hl3N6UJ@;6%r>la-E)^AD7xw z-P7Ln?&*Ns>aWH1$^D{0Ry0qWkr*Uiun9+q1iSGx3M2Z(hts46XG>i&SibY;+SOGA zyUg--24_WdGkTSyV(VxGVC)-poLP6Gd{5bCf@O>>u*&POnG_*{BpY~JUXffqMZk*( zQ!l3@?G26=nBZcG&#M=fi5BUjc|S}b2qEZ63z3zGiEclTpIU$l7@-?2exA4TAft?9 z{X0L8m~Y^N$JOc*hM!81cs`P$DsVE7*M^O45&5LhS(AG4`eS2Jm|&N(&$+CDu~aSh zQsI`#NN_@AV!fkL0kGr(5evkbA(Eaj3~;5b{g;zckTa*<9i2#DH3As!z?t@oLBcGQ z>2X=`pHLMK6_YWhNv&A?ci91mh6d1Ng)7%F4p+omD@jT;GW?ODmEAP#utb9{j_zG+ z&$;}*r?z?^KqQZ2wnZy)ehB)c(;Ck{-p?~;@WpDzc1bfLTFCQn6C;+F)f`iOygyw{;^{3scb?(5S#tBD=5s8x!2}8(J89@l|xlV;ep@#tr zmCZD+U2)&m=hZT*#n}Cq6BA>mrOh2KGH`HUQZU`Y=LNI-GLOOXJQvGSzi zR|DINLV(GEfheOR`kbMU!%Q#Tk({ef=HX`w#u)8Bp+@Mc5#belGK`>lB9CO8aJ6tQ zEFqH`WBHntmlu`0WBqCRBY2_jB?Z@8p}WR{vN&p^p45eXl*h~m(xF!X zMl=?RAp~7GM!Z>1s@K*o+S8-4{n~V1;12XJPOSl`#8w)9z{il*o9#RVbVFuwO-@$| zm&b)35oO|NQB0tB!2ibf?<0qoWgfqbF6bg)n##GBBU<&2|Rg2=X}N+>^`IC>N22?`)ELS}2!@wlAp9 zi^L_vzjMF^Du)zkk~t09xA7QBod zx_wNz^PH8e5-E~TZ&)4RPh<|n#f7!f{f&?p2V12kDg=zf=jGSLhVAa|9)+1GV{DA- z`K)GKYm&cw9vt*$?N0~*4MeM7h#kfzEKduY6)Mn5j32p5PCb7xrp}7J;KLs~F=~UwV4_s7wZzb*|MZ**b zuABCn9_Mfa81FDdyg1(b32cj9pS8X`j;R*D+k^49%nUOv*blGmcH_k}5&TzP1AKz9 z$~XgYE)7ZY2znJ@3-$W8*swB+(m;#~ji%B-yQum=1AscdX8dX(*=E*E$&4h2em;mR zK+7m(Xt0Q}f;C8lICjV}BD4C@N8?88Fu9pC&cA%%Q_D$8`|xzSAO#NwD*7d~=mliF zfy--2Y4|#TtaS-lgTrOQl!>qru;ljztzxN9W6&HQMdET+Lqvd&Xy$a1Ic#|w-if0W z2MA7jvBMC;fNOntcyn(0WZ{uo_T8($PKkVS7W}IAZ0+>)VyUpWjgJQ@!h)gRtyaGT zN%^EHnN#KY8?!i+`m4M7CqpwjNxltn=|6xUI;~&N?f=$RF$$3|waDJ<3}DWZk;PZp z^j^at#|#iGg$~aO3r8jxiG+zet;93^We zL#w44YZ7+-}bPRWqa_K zI6{MoVxK(W6_@?Z^;vyIBu27SEH(T0;lG~dxrh=W_kvUt)WU%(H4XFzENCK2+u+fU z^0Pex>3GvE#QX2;=?H7&utq0%E;D{N6tHDx(Lvi>E9(DY#1viCU`irSjEgIY2f60& zU;1=4S^fs#{|vweQ&3+!>I4ISYG|_Kd&7zim!0WRy~gP;<%yg~k`$_vGLxq5`)M=x z>2EQ{cV18}ZOb@wrKHlqQYfT`>kQFe%$(IWb&>ED`4@ z&kD*t)OR77)A&u}1BrqL(7Lz;IhGcVOhMZehLMhv6zYrynEUnyRDvoQ0e$!rd;(Dp zxuMqKVJd|NI*3Ei0*%B6(wq&S!y&nNV5HNFym>f!yq%6^MN3i%z6M(p217l%7*THz zSJyJPvT(;INiYxF=wZ!YAIF!ZFtQ0oWBtR`ovv2D+WRD?Gn@X#e5OUt;d|m^1E5l+KLAnI=uKsz=aXnq_j;!%t=7#{U%kcSDTP5e0WA{F78YUg4m21*%7>CtooBn zHyTfuP|@P<3l2w&1aou;4(eBgTzBN&U~!2dU!)PHecXvCGRXde9joWKETHq##p%=7 z7Wlk;X?B`fgtGa-6bpwN2iTyL976?@$H^R=IwEJ{G_%9 zm1tIjY1m_?=;v7ePu7bUVrf|+8AWlE0g*DTIa)Gft^z94=Uo*JkDlb9BKgCj@%urn z*M9c0re`UxxDHn_4M@@I4_IO)wiDg~?{H=+i?cv7$Db&0dv}Vq_)b;u)NDK!+M-lUIW5d3zs(1MZB)JWl6$j1+Ie8JP+qtLV z=BOySGC|@i<(6;CB#ed$afSobm+A{V*xTWa z)=b+Kyx!nZp(n*zF~(nU2n~j$wtR1~4t%?@vR9>zZ@BQ`BjPv2l8ld>kkgpH3RkSQ z|GnPn{@w91)BN(a*IMc2LOi{pF;UpC8|8#E$UHYH!8@hg%-74-{(it(w|r^5j{JO+ zWDSOCTu&+Yz31xd^Phdw=M{E&x&)fWJ%sijOD3LaQs*s4>UMjG@F$6>l-?s2Zy{j_+`{AKZs54Xb&N2)`G_ z-8Gp~^HIQtieYYjLH1AfiokhjO@9bXR!@urL*rW}pW60!=^t#>6pIP2`3$D(f_iS| z_;&gTaw9`|hgVR$D6}SO7?oGBZP>_aex`H*kel9n?pDr<>G7%>&2O=Ue z#dturR0JvFsR5I&=DdixIkv8@u7>AZyi^eh8CgP{flwJ2ufHnAfrP34!{7Up%0_)a9}ayMr?1iauxz-CpYG+Rc ze`~O+BBE0kqUDIRlNqhXMx-;lP-3Jg809L$um1qh(CiR*R z?&<1JR_yH*<5~+w6WKzJBRsbdHab*eF&^V+`@4lIv5xK!w0d*>0g{sF&F*eM#&w)@{}>5bL{$-VGj-WX154zqXTY5dG!ga6*I zz?+0n>GXSVQ`v5Nr|k_SJ#bJ^@=`}f*nUAXr$>Q#J+FIeJibk9e%E0{D+NlR$F3=b zk6#yV=iwVx%u^b1+_XO5f9bo{7L-KDFLe#I5z>RmWwd90h~OG~vfpP|^B+`S|nxMaTRIQCKAe>>0A@5F%z)q_>Aw$Yxp6q>JetvdFgNbl z3L`1uH5wlTgTMthiGm*G*=#yqx7hAVTGeFzcZ;6{do?A}1h(tu{i9@didjCx{F!}v zf?2bu9`Fh%q8a7OQSD;Iu%Xm>DwD6>_q29<8sxtZ5)Cz*8Cz(#D<&aFtq==!yyK~U z7h>-IexAOehaV27(y}Q#l==9GR#|JVd*WGlIB@)vq7q^E2ENTx_Wk=bnj6rtW5(zF zX%rC!?vmO5lR_bW=zJvOKEqyFxFvx&d%jCK-y}w(Z_6sGu-h%~P*VFCH$VA!X61Q@ z_dQ~ag&5?`qTgUoJu_n84f%t!+8O*idQ!vZp7bn-H7iY(ZH;%L^}1w3CW~2$VncpY=}uBk zXqoofcs--JM6XA7mZz`s`^2naaxNTr0^AI*FR%pVw=9oSLMO&k9hNs?#58wqfV=s- z+^~~Le^^7`Y3zEICf`f2#Q^6KzS@~}1vpX}@A4?d#iD0TkvZ9>BD=FI3M6&o) zwQ*2iuGGn~exsSZ6EgUY&0Ce<_fWB zB!Bh^><#O^@qO=HPBjszT9GR2niG?%$qK0FA$KaC)|{uN%=wLPsU!Xyp(JfAm^n=~ z+dr6ts`KG_01Cc2OU!;qyDNfJo$F?)X(j}-fHhS!ay)IP(cl+sHj&iP=0KfrjROHf zF+4;WSYpdXI+YX7Cr!t#mW`<*(P`OAY>gWX#gUCu$>ebigmKb(sM;W(=hrV9lO%ex zqeC>7bnk^cu(`ChJ*MK6;{?1~gHC5u-VAOiG31?*fzy8qHfd0zYD$@EI54RWRfMU+ zyTBcma@B1WINExAfCwfj_pG!_RGJ)hq4>=pLNAYOdD>7^@~upnJKLwkF;Ab11GVYE zC*|VgHEd0XA$v>uJ&io%r%8#9W!4+GGO}I~jrHsPWn5U#H0j*r@Id5x(s(aZ=OI}XrC5_;Qe#B-$4PS34(pB3 za+LJC(AHE%-1ylwBg13c1M9I&xhH{cJ(3zR%Ciw_)AQjt##gRpLn@_g&(0fR;Et6q|U^QkJ4|+ zhlk!3n)B=8=+>4@Y7%d*+S~8oU@vd*l_8(~P^s&J40zK{39gwzWjsBvtJa8bp6V_H zy_9K}R)6SDfITK@H`pvDwaSCkxkNR}?P*E6cjAx+mXl%iN$L5DJQSU%jKKE*Y-9fH zL09;ADVnBzP4a9PZH?h~RZ3f7)Eu(0Bx4bb-C=nk{qN<-z=Z%Qv#LxXI4m`vhL_E* zJjP7*93Jg&;-Ykba|vVj-ph*<-XUwq$#{2w>a(1I)beR_hY6Zlg4Jw3YhfJ!J+Y2= zRpdlJZ3955_F!@^!Nx+Ls6;*VcL{a@4(I!v2Pnzo1{F2G)&4fyx zr9G%Zn?8CG0ZTLBr}x&r9~8p;$8Z~8^?>8O<>TnQHW}hHrj>FO5LvMzb{4iGF$?&Y zRB15#Xc{z6rjTyUWzFf*>a5|S4859V79mX|9II)`M3K%KYwBV8;7sUk(ZPf|VLZfx z8lBK5*NrzvuGCSAWd5Zx$1F}=gIsTmq)tmwv|@+#`KPiZyZfnZqLVH;Q;$2*2K*r$ z(Oc(wD1ke5y<0(0@#kOnFdv22Nf0IC;IZqHHQVAWSc0mmE?8jEVv*$m-8DZMB0H}xJPBA{ zi+GGEM68n%h~He%0gF~cCUv>946&miCzScQqMWA|D_=fnY3?#T^&JVVR_{Nsd>;Q=Q@UBP;sef# zPQ2_5-Q{hMUwz#J*q2Eu-zVW)iBsq4kD_{OL(I6i*TThwP9DK0*x2bx0(*LXZEkMH zMdd|lhzcvBG-%QV$3Q7tJgTV+?bS2FFITjVjIhkWf62lY#A6o;yhC6q?o+h|dgzfip+LzgkmV&Mu0g?HHw=+4^3$ zh)pgKav8N436iHB=dbPf>JGwe`yahIplz$43)3$-=4^Ln*nW5v$4~elFfi5e_%VC- z3QW*HRljHE-MfJ3P)qDbVY!Pfz{Yb%j?+BJ^ypt`ual893gf+ZYBv|+bNqKweV;mz zvFrU1sImhI2JhZ{UGY-SFLAHi_&}GE?E&7z2mnRz!@EG}mPtQgx7TbY>fUJEQ!sY) zs3$&Qp!^URy&N=kT#^Ha2rUvJQdIKc&+PKDI1_+_HZ5eoral7shjM`enNh)7NE2^B3^*_xDHkZQrz$ zxt^_uO09#*$ivfvT0$qwV>S5aEx=E(2s-K(rnmj8_F!Z=D!NeAoW}OTBQs*V2a)s^Zb|+p0uI}-E zR;l{9GhGW?D{~@5EK#y~RG?;Co&`xvHl}H3f7FEwM6Ck1d04o7InYOhfp+Lf7**lF zP(lOS(1CiPt(Y^`k+PKVz;puGg&9 z`g*#~?o9h1->vV0pT>?)(uJ7FI!D z|69=fziCEzKV#&|f{QkLcwJsw(^{(3yyrW%I%)Cf{PO0%TK#zs9aYJ^q`v;P`?m%x*-y#KORv!Eal}1+1YX)9&Zp? zsQ($&00#+Dc;c5{o69N04;3Ks2cMMxgYH z`p=VJDWg>XLq+2FpV|L^ruqN60j|j|^?g6Ajpt;k57jlqkV(zNM}m;nDFDFGDB*`niTN8adjT(KgI^nEDiPJ40$_t?oJp zDJOs46PBJ^U2K4LIY1#j=9qWKYmT4}(oeMVfd*VK5Z$IK8ihM&fq#D)uK*1cVIhYfHr-uNI?d7|UOR#wMTXbQ`( z|E>iH?YB6lA80fH2Bc0nZ$lvk5_+7Sg&oNBvNmyF%cGx@u5^U+e^xQJ1xs4hgt$^Y45 z;MU(78VZrYX_g^ZR-~IuRQ%6^If~)$ZQnS0JatXzPJjCaW5Oxe$pw?p<=5h;=pauB@y?qkqgXjN%cqRD8XA{o9xfJ+V-ms%yb-MM){8U1jV{TUQd zdV(fx2W{pG`ol(3raRv81sYdouzw|xOsnesZ25hlpCBT?P;tc~p}cuye%?=mSvb8t z-6N3HvgvXc9MKCI?*REN;NljDSU(xCXeTu7!07>@2n#M_zTzrGBaz#j(bOb}5)Gc% zAGug6TEp3i6PQlG`>BZJ2fdRyv5_$jU@Yye^rJ(>68~h()QZ{(Z&LXQRF!tjqgy~i zc|d*f1Yc9X3~PRWuFfeVlR)%8fFoHXD1s+qsj#HUI3|G8qXnYzG8)x#fDnSUk4MQB zIF#vRBmVDAZqI%;lr2|n5$nm$uDG@;O`h+A63xS=CG`84E_*5f!e@fK`vwdPp4O4d1Cz$z_US<6+MEUB? zLA^T1BK>~$oL3Z>xlrIQ;eU%xZ= zRL03e^IXr*)p2QNaW=kj;%DB0ae*`=G%pv-dFck6&pY~+D}0mj)V_v4z5(67H_+u` zQ(tWMCj0fVPTRugA?!3Ji$Cb3>Er5LDo&l48XQq>XEya5L+#Vsh9~~Xvy$%~b@;3P z3#sEVd%pf{dI@tQ=pM?$kxUVf2mn9;IMax{w0bc-C6?Zj7 z&W2KT<33Uw>gzyp%gdH}9l7;F5A}F`+9v|cT$+AE$o^8=>ow1e#@k+D`--sCvEJ#F z(8G+sKZ|(|P`WvM70vDbf(ZlvwZkRFqh^8%^q=@bmo3eetET#AqGpoIUL0P5IqpEh z2bEoArS?1-xxO2#6GVMV$L?co8p@;M#^Ste-8<^4^W1UsetN^xlTo?kVBdykVCvXs zG<%${_i}Ny@Zsvv;N8yWA++q{Z73XrCfdf=kQiGJzwiy4{}@>hOn4iu$@Z!KJr*1A z5Iy>%)BoVSS@I@Q9XUOI!cf41mAapaUp&c}t(n^&8du|Kx!Ucd#$J@g3 z83GlL zyB2JGJ9qIa_O7&KFKa`rc+Ctxez!zi@}C*qeO74H<|lL@_BNC+)qX~MJYCc6edTOV zh=>yYJFKyJx;~1fN4@zp#f*cT-JXwSL%>YGR9~EL{=L3vMC5tIbk+6j0ZZHNc9t4j zPyMKsc@OS(HCBpZLaf+zN5_>9j+u& ze!>CyihnHR`;AZBxq2s}W_x^Fdku2I?r4{v)oFi%QYN}}_K#`(g?2?LpStJ7Y$D|I z&iWg0EormkV6-#9%C>(k^mij}@fI=mVP2aBELM)+%m2T%NUcsC&|@&@+;O9Q zP7YsUvV$HUGEE6zce$v!Ln6EJse(tB$JrjZOT0`38m;NiAd{Xv+htl^S}I zdNZPh$A6YsFY=oH0u4$U^ax4~qLkNYP1H?*&P>Fx1B+B0PPEygQb(|sDtow}=fKaI zNguCN+KkC@h2ZPY*Vd=9yGN~E+AiSSGo5l%w=jwKt|f7MdKUMsWH`o3(%Nn}Dl$yvDEe(?vB!pLwe4vVg7t;|rgb;HxCD zH8N|)=1b#CXGEMFz|=*>G2{4(Xf9!BjIP`f`ufU-O;3#p(`5vd$xL5`xpnLq^qtD@ zht|>ROzuoQ-mW#eN?#r!3o+;_Lw^4)f};8eM~puf!#dXg(XL^&EhZpmky9ppCgHmh zXW~5Ho@{b1ZB!BWk1LhA<$U08Z5(ad;`x>k>+CprqbqX4%8>6{n+p%y0!`eB3BiB^ z2(Hs|?S5@s1nkO!;#K)5W%G2P0N5ey(sgqJ4VR!bTrL!Ce!=bl+h;v3F7#PM!8O8nVg4+-7-0qf@rG0NI8Hp*~mzkqGj@3s?bMk>B_`BfBaO%+O^Njs8fX zA5v5e+7_qR`G0iwb^K^0X}Mdu^|HO67! zvZNR7Qrxtu#WFmmO}~VY&OIu;%3qCD8NB3Fe-ZlLr&saZPyDIsn6nC7fCj_a+LJm8 zuy6mA)YVgq*r&#GQtM(&xtR+5M*-dHz21N?P+AuLe%iCOF0fQ6(qMN=(Gry%f_i?# zWZ`1WbPPUci1)|ZdWo&MTSkTn;jHyEXBe(QnvOz-g0S4|jERo*4$tWV^3H?I^Jk($ zLv`3MwIuUnW8?q2?zq{w9jtmVpd#kylHe%x+imDGU}_tY0I351G4-89?6*1JDTPNW z>58NV_+`_1&7OpbPO612$1CF{C>|fbMMUkGOcA)7>>cp&o15J zF6eNYu>6lKv4lpZzG^EPd=548)Ks)pUj@6&#H>1m?L5AFRcsXc4%c>aN)s2FGi6j7 zO}~g`U7cbC5)GXjJ4B#zF88s zVvE{4)FsU{zplp@_0_?pJPCnuL(tk}YEiXZ$6UUxMukvCJgx{zm8`k%;lj7N3-FGhu)OH0q?kM-J00_cYqB@84wp{ATgTeetOW!8^zPtMupAo-0 zLij6w;{|T(w$zkH76mPn2H z=qTH;?rHh6A^V3nFU1WtLe(^nPxdpD%rmzYG>hEaBcA~($7wCz9*Po3B-6RIg7Pp@ zA+cMVO+0qdJXgDYBc_>onzr*V)rxoKao>zzn9pesjQ+}X;DTGT@Xl52HH$B-;-&RI z4Cu4Lx!^CphsDYvLR^yC(%Z%id#Ni}_>OjyNOlMqW-b z$=AC3@8Y(hG0_Bb6|?5*La%ykhFVkC+C5MG zzRu-Sqwx0o2gjY?@x2lvO5Q*<|1w-b&xmK~9mLTNd@BU2XFb;*4%~V0cFyYX6X7xV zZgy@5o8!aK zUX#f4qV@GHm8a*=2vaJVzUyv&F_|I+pe?MPzOry=#^LxAxZgv3CN0sKC41kD+`kpz zF3sJ1Y4hhWS2gBS*XMf;AIHl8dwJc4neT>~Cy}LXQELSaSAgdIA_#rhN7D`Kl_4QP z`_IBrsN$QK#=MFvIAPdEhz3&t-|30nYv%S!PNvn*bm|RNB)I(d9*V6^{$`2$Jtts$UoY>3 zDEo<(^f#eAw~>68CFt!rcKcZm!ok3R_mZmgH}^b0+6(hIwl8u$sLGH?r)_T|S?Ep4 z@}}swiJvYL@@nUvIh$SL60=|8EjO}oxZ`uUK3|)dCD2+ES@Oyg_m*34Q20sIU+jw2 z2bJ}_nX)-8%a#|J(TRYH?!SdcK0o2iswlVj*HlAm@KKqS5mymUjFn^7k14~y-MbRt zI!pNjT!9_g9}_uh=G3Mdsa4+f^6Dx}+Dc_#FuvA7{`5c)mdo13z3OVgF zlJX)~k6AhAmY2BwlJ>7ZeaDzCmSF0vPkn<5Kl>+L?vcooBu zEAp1RuG15#tks*|8)Le}?q}x|9J6?h2LQJe<~4g%HU~AK%BdffEYaWaU3R>+jt3^P zVr%!l+j91BY~k*MS07tD=nec-o75_*PqZy_zf+#}?9B^qgj}tr?9*G<^9#`0Q)_Fh z;O5G+U(VI0rqeE2KKZDdp3QL2y7(Wvt~>VKg@q-2p;ddgFz4c!;a36<)y#-b*P24$ zsbIh2;^EQJUrg6SK|ukJL}V(*%ejtp81$1b-{mAav3WKn?{({sV~&K%zv7<@>mBe> zyYv7F2Qh$3pD`&!v&i%2q@t*6d-v7arg4W9b`@h2y|wa!^Fls#|5l=hzZ*nya!sy$ z3{cls<`*QjOf&FY(*rFU%xlk{xAqbc@+tp?{3#8cBsIep zr{mh6wM&2e*_X+ws`GDT8C+zUAUCR!6Gx|qejB=d9XGs!<4{!Q2qe=P$& zwaSTQ6PuommJOEWoT`%l?j$p(e31+aT=buI#lLm3{?BIO|BLq17w;Ca&Xr@|R%M~ua&TD?4THvriW~H{lYGZa? z_UT)NCo}Mu5B1;tNd-$kI|nn8Yz=u)^JL8~W9g*%aJQ|^`ZCflh%A%`(s*`KGibJl z<%zfX@?LHHXZCi_ZjU}Av))eiyjk8s?hTrNmHhU0w|a;yFUMK#ZQiP+KQ3*8NcT!r zlCP{eBy5i7KyDgb5?|d!b5(UqCK5Ubjc8>j>%JvPN z{nTMv;@~p=D^lUH%^zM>#?Jm9w1B2CUYiSmQcx#~=JPvDxbO?Fu&Vv{>Xh*#hmEsv z;{nNTXzV>4Ff}^7J=QI9dVPzX)6K|d@pgWddWLS?$2~IlKWqH&&r1nxMK2luU?9R_ z7Yve*2JWAAzFmIpSAts1CqDYeoZy!CQiY*xr+YlLjB6u-gX;RWeIi7Yxu3El0cS{W zqW*Bkm7EMR)S~_958Y3WE+QmWbOF=o`*SWQ8ztxg8hu+Tds=f-60$o-;Mk2~x3LSW z`Zy8V923J1pFLQm4ZOG#E$kN;d9oFS1-%c_ z_B|@vhQXp_pkw=<#^%eMstW8tPwy+T?@nvTRezb@pYrARm7n>~aah9+c>{J?q$Kyg zfO!p6AC3Na<7^#B`$et0+y7AsUue%z6=dLYymh_*Sc_Pw+$g?UDixwss_WyvI0iPK z9C62TDV3<7j5%-zGyJ&Qdrlvmr+}{w8Nj-XXvw!&BKdVkF9Z?H{I zYP%QTgml`o*sdQREtURd$qfK7JtqfWWba@x%O!Cw$HMwAH&t48+~~yZ$NNLXUbBAX=1+}?fWoTimCgQcSkt`7gHrl4^xG9 z7vEpLc;%zx*Utj&ZQ(Wy8GV1kcJM}u^KcJz$nc-7{W8$+PnOZ3eKD5o0bN;xbEDVa z!=b2WQ(BKSGfz{vt!Ml{=vl-rUsL~qjW8=c`gw;NbNBLGT`ahrp_~zRdrYcj?T*R3 zY}Q-RsA9ir92~dqaV4S6<4-wYc#$(ZAcPUuQdyRwYFG)ydJb~B+kNU$4Q}=nda&T0 zeMEFtJUZjEBwAmU&=1LaJkd^%*E^oZySo)?mMj_BG=7Tu^j`nKlUez8OJ!1Pm001i z^7y>YYgU(>`EHCDpOH{Q#(C@Wwlp2}HdIg8m#k)Pk$@9TE8URSyd$4_%zPtlmiN$* zy&1A#{n4)yee!5-U!d$6<0Ckc3Enpz}DeR?~o*u00_W3yP$Gf~MU@MSRJ7}Sw) zhaF`LJse>zv-=KjmA;x((eNp`UiU_4J8rAz5B}vvMC}QsVtn`%+nFv_$eX=BNwf87 zrV9X6tDpM3`{sCTL5!hSrSn6(Q&Dop$s032rweVcjS9?+nDZtf{iY4hZ#d>7lmeGG zo zZxUsN>}{$(rlfEjoh9trz;=FKnbo(5JFD06c1InY!GbTI=^rnge{TUo5Ad_#ndt-T zv+=W_&@kH?ddnZ+Ig`4I(Db=bX;9mQ4Xw zo)E4%j~#E{QF`zWF;<3)Q)6I=wzb}Jy@E%V8EbRrVmR{z7=5Yv{SkSW92FYW0_0c} zDlJqh_*mo?RSMcXZvFp_62m)0AlMEheYp z;urzK`@U_aY|7IoxO@cW`Vh?IecnRLNC2V7cx#i6Vxr*2k5aQyTxzbEAo3B>3*%Kl$aT$oc^1)FHghu zV{)^I~?c~3DRNvpf1{<-iQ{TG{l|P@K^3ura_5IC?H3NWPxFx^@dL7RTU*#@% zYkK9%{TKU=x8@FKIIEYK_Jj_Rvpsc{A++k2hS0OkGdHq7gkk4KmBvOUdCoIl)V0^; z9AQp9cqw42AmFxpY50`{QY!zK!0Ud(L>1)~i^h#f&*(=kutAH{N|>M8Vu+7_*15ku z*knH^9A228bS_Axg)HI6@A@OhOz&XTs~9NVLL%!cZcS>g3~jpx(ap%+pPos}h=E3; zrp;inwl$uI+tRK<$du=A6cQ08Mpkb{gNq{c1_=l)oJg5G>%`xx3Yy{a*|jnH01Mxg zKTS)sq__W4ll~@nZexnRuS(wG{3?w^1UZY2eSF^TCpn{}H0(n8Vw4_ZMG!5#{W&^Q zcesUDw`kyJ!9?tmb5ddr(d(j4i=$Hc+I?_RXl8)7EJ|p|W_pw3>zx->VprZS9oll> zaEEPETo><2+RjkyuHX20qB3R&&wK3WY6}CfiG_vPj@ErBV%K}Uv8tsz(Q^Nhgbuv&@2t6QO?&_CHb?_BPqRD9_TT0!K$r9zO8nkh8WOMjUXL<(7Q;oX z_jKJ4wlg*O(@L30(}s%TDG`=jf6%cie-T1T%wFX0qqwT=TH5IGd!PF8p(m_o^~bZ_{TCzrT3mbj#4IHQ=<9%gHG`}+Cg z4>kTE?(MHmjGKNCm#>i`T0xGJrdq#uW=aAaDUpiH5R^W5&bn%3v=Y*MRG>-?vd^Y}N-X?yXfx2|pxTh#OBskJe45i$}hv z`4HyEksRM5;=WVyZt_r^97zb&Sr(X^J5{K3@E6;qxL?1?-Fq?&DgQz3!cpFQr+%Bk zAhzmzk6{(>yI-J-SE~0zDu|QJ%&VBA@EX{W40nj@J%~F~d(zL8Hx+!6VqCITx8N%X zugJ|7fT{ewcVy$)vwT@h+`nqaOvqw>ss}$IW^Al*-?T7(U#lPP-+9?VwXM+84(gM}D^N^)sr1!)#aQXzzbZA- z>{)69L1mXd()Z1b3$b6+kYS*@nzzmu?@f6l3O{P1bZ)($Zp}VB^tNT{YEnQLLZpW3 zIp+(MbT=RPIiP&gMgXAE^l?3Uu-bLXtGwSa&-R$%HPYVJm;IiNI6R`SVj`qBLw;Ue z&xzA)M~C;f7C~Vh72`ft#|7d0x&|G--E`Mm(##UN{48qz>>ew)a=Rcz)DBn`Pq_Yi zyzep_(*4c|qYv{;@;D<;S2Ffe`HXI>#^>45GZ(jo9b(-+UU8)So-!W9HrKD~HEsz|{*gWkZC43a~X&$vk4MJL(WIc{jTRR1zZZrbc>IAK)&Lh`tyh z$97wS*L~K>-EYEA?v*nlq&=tO!81v(=Yv1YR5bN zEt8}hKg*tKT6c>%d+ew++oM2&;OHM!FVq83bBx`~EETsABKE;N!v8X4bZ=bdD9Ui0 ztdIBCI9~qy3F-!P1)dAD=S_OvbC4lE*3>~%8y^iyJVpI3Y^lep8q5! z+fkEK7ZJXNe^1 zjrMyjmmdgqc<{NMrR|r9S+ao&GhI9U%jv6))fL0J3A1a zddA>yE)yJY`@M>gdVgsR#V=`?=8U{BG}9mZ+5b#QX0(QCvx4!4&!kZk z-r21%x160>-PZ*J4(Q$f`E7zN2XdC}ab%+0^!KhrM=9=TUSvS+G%0{?d3s;hMp=El z@h6+E6-FR&d@1e%ezW~U`}993aZhROGJVYR=$qXs^VUm=RvmtbG0&#vT?%Cg)9e4H zU{TxqOZtL$MAn6{M=iT~273!2rPsejw8V_x13%6ValQ3wKjSBtF3Sm5m9`D)Pw9;6 zdM!+O&TbWMq4Is|gJ{W@Wq#==43Z+W?T<)4%U7B1!!4Gt@0YRkJv*58j1`2RIsKj< zqfYsuaAH#NpoHymT-wk^VZwr9Z}gSLQ3V9i$TPoDnW0QLiCwCg={>Sp=xJ|bYh6+v zx-W5+72<#|a>~w&G5;nKq>2=xul~itU6Pu4#!*?v05ac@4i*aeJ93=8OhbUklx`~3 zuY%{-fI_qnXMr`N_sPgapQvj!ZuSNuEQNXRE)uRK0PPpN0Ke}|KYZQk!(D13XHt89 z!HjDsx4t^3{DQ}q`^@rp-wPwQ2i=#@n1#LfFTxH_(buoq1zwyqo_A{Ki)ni78ei|_9Wtu@aZ7$#A43Q*XilJ@ zsDJ>v+STQ|^i=m>y5H}~ofiM_kX27c%R587*{pi%FXXzG@b@j{Svdi5!zZ&sggyc@I(p5NK`Q5$_RlW^dutr_ zv}crHwlQ1MajY$9pE4~7kK2pj&x2eMP+99P<-`}Wm$5=ugTc~ozoCzUX zXkeR+f{fJ677s%SEhu-nMdFhK3)14GodYF$)zO};k_9!r19(Q6#kjUCZccew!34Lg z6DG3X3-75*O`3QcD|L1S)%1Ic2C)1l~I^(7`{cmJ!tz z2SSKT3qUX|FkErzhO?F?{#ShV^ijE##aMRZV9hs94!f?mZ=9|ZMv zZ=(-ITOF}bYx{MOd=1hICnve;e$zPhPUxujjW|D_0>C2!)h6|HR8$AQ#+Lz&ZT=0s zxXfe9;xiZLg%cKPr%;COK`%RXR7fw&K`l^_V+)zw61H_PsFy$^q*@SoM_@ip0n(~Y z2tsf88PXS(mn%Sn&m`M<%)onyx(}=tzNBZX;3Ww` zhBEs0bzbt3lmUeMmd{z6bbG$}RGn)e z%(T>)nw;a<7Dnm>?o*yHuh4AHQdvDNj)CPfBO0Zy4f{e+7BKghCat*Dk%RKSK6*#= zystc~V2gqUxm}oKo`@BnKji9fpc%n3-PXK^eVL_yoJOKTwDlS@y;QWsjF4=ryJ6>@ zW=Au}dB_(QPn{|}ILklUm2^F|0Jf)xpJzOGZ+5wnG47jBUng$~!cpaQPXetp4Udx= z%cYTJ7MWK!BdQ=nM5&p>Cd+w+%q1&-ESG=ki0Pez+*Y-+EOs+l?edN+B`*iaMoW~ zWy}+5$E*VFX38x|jw(2L5nqGsSj%!f)fD>|GwdpNtCVLrMR1r5?TDRzr3#G{!_6?G zSX5TpMo_nXGyxqetw#DmKC(Q~fuNIFb(}OTQMqar{qb($DvANiO)m%6fX=QvI=I=L zQY%us_e4l!bsbWrbu25;brVSKtIH=iO;}`TU0@!6mxg);tgQvkZO*6HV|aCZ3461L zQ!{c38tJ)UwU~XCKq-rMQkH9Dhz+(453X)%mT)sTT1D#`*b_qP3w$xha`o*574*A+ zBLauRVPK4}7;1jj^Wb1g>8=t9&?+LifsiHskcL|}sJLKYFXscPKgH_~dhRS>3jOt0 z+kn+n93j9Z+e@))9m79w=y9!f8|h+`9J2|^3SptxQ`(ZvrWDeUR-9{U2RhzQz%D`Q z*+-HE!zcR~NbgCl0z8YcVcAwL?50T=IN;;}Q=X~tnL8V$Q|a}%9zXRj&Q2IEo+zCJ zd6|I(dOF+IbPCkH%wb_!4?Z%JIDb^g;=2(vGNLBVcO-n`ChT?Uc6eUv4S}K)T zW9O3r!5c!v->y#x2*xv4`B4%P|iCuGnb60_8wGEP}Mb@ed z5oBNz)SYHhKBW}DN8?<3z7S_O^68`5>|7T139WIlY=k;e(w+d>w)nDLJwx0rx21ZO z_a;M%?evMQ2S!Y`8|=qU_^%WQ;73)pGr$@!jlTK`0VZ`a07r4zqJsg>3(GB zwWw9^G<}q%>3z4KlwEK6g{oIDs>eT&y?s_i(K;jh>e?)Huw1ICL0AXtFPdDb%P!EH zqSigq9Qp$5^HMf&@mXD#rMrLZ+HZWQQg~oDYZy>VlTj>{X_0{i2hTjeGqp^)T7pAVAbqrtfg@lB*0Q->F0bD@M-ot>GgIw0$m45oZ5qSZKX5?vofd! zhKQa>;_rzH^bWZmSH+%DRS7`Zj)~Y#QFgZ**QWDn^gT96D=8{tZ}P|x^erTu)NsQs_)fVgdilaY4->4}V8LSrkU@jc{qQMuMx|~R%$JVca3N7a zo2Wi!>V2a^eBc9NHHv^NE(?!xjz0z~uFdqR{ z0MRkENa=~f@&bi9lD1Q+L}8{}X{w)MU;O@-IMHgVg4XW|jLB@28QQMpnLWFdznO zjoveX&uJCs(U^fIF&_;cISv&)rW10|;uR|CW$4Z7uN7*9Np*lznburl+~}A*LY~mq zLegx{08ujls}#__xR#Ys6;`jY)J>Tct84$ZNs^s)0#~I&znyb3<07k2E6HM_v^ovC zh6Yh1bNWlJZ?^dhx+9ZDEPoC0}Xqw3BoEG59qN)vHk_ss!7~ zo^30XhS29s*Cr=F!bhf(cgTjafg-{)?eQQQ1xngj2(+<=Ed_8a_!!Z5ZN*cdTG?y< zItoZ+i2P5Rdm%b0crnX#^;3Z@FHkY9Ol{l_ z#W!u>T4+#rGMi~pE&0fzeie}iL8~3>IE4nMJi;e!Q++5;G|(&A^hV1sm_SH>1+6o~ z3*SPnF^OCK?J6oaqP2|zrK!`Z+i#`Pei`6$T1npqB$E@=`^hKRWc(aCS-oy!h58E; zs>&nfj%pIJNjlH8Hq6y|1Wq4K6js@4S~rL42dVKH9IIYegI0Tx_`Fa*5#k!hPOdte zM5R@m;N4B?ngRWV1}!pNtLMGEbo*_Hs=xAquN?e3puiRnug8HGCV-tsp>NgP4D>8) zH`2|G+CB6X2O%gG(#*)5Mt0|5)u75=G;39HD2&7HScpnB*wJXDhu%rGX%d^uLam+$ zW!p?2mIv?4nc^xaSpg@B3-u#e^m%27+c4TsZl`4BqB{9{WdL>ifY(iiT4tKZa04qq=k?Ta#dbQ9D(ag6nKT0 z>su$2e_g7d8ZZ%)^Rm0mRb9=@HCTHPlW40V>$80Og^{h5b54MzD7ygKsi?xi@9iDo&T6L(H@!y)**&Sv z0#ystXm7mk%S~AoUU{u68G@_;O#T9Y+JBkOU-?QKJAzuyyy= z=qs^qrpWg5lJRqUw4q&%ERil89nBhN=8ufXY0=Lx%0Wg0H=)LQzJ97JXM5yS6*Az& zC~qmgz7Z`WNIIW>)P_iMRBm*vo}EvX*IT!71;kAwq?4nzo2^T_iy*A6X;fjXpu9W@ zRoFVu)vs@_{^)ETJS{zNI%&8GF)m+QQ&6xIbv|d-PseG?^_l%^WhZw%tB{ZlodtrQ zN7I5p|Bt;PU9?Hgp6Xd&y)q|fcYPy$MgtcQn~Scko5I)>Jeo7QaCSOr`pBsKdNy;g z26oQH>C;B_xkmN4ZX*~)msuDmPZ zh_PE`IRynDLlF~ux;Zqjgbmj_D`$DHW%Z5fDoBjw8(ZXb>*kM+!XqMjCTQ?F9C&5| zxYDQ5n1#tVw#n%pZyF6=IL@3NeF;J3v>uO4O~Bra(`K8!&A@9~n}lC3&|r|fx+igC zxv&K?c)eo7YB0ts)~c0a>^zPVPL6tDG8N{N@jF5T zDoTuJx(M@DQP|Or0j^TC0)@3XLba@n^0ES=2(+i7s@!%{S+glfB&Rr# zprIn2S)WH1g6hawXeU=S@l@Dh4ubykiP>+ve_94s6bX+q&*Sbs^t{N+{Cnj_(dkpC zzMgu(&b&DPhcol@_WkE)Po27d`u%n0#l^q=x%>IMuNO|8dUxiW0`ua3&`-XebiahC z&)70se3zO48e)PvmEc`b;^S?f_H3(!bw62HQuTucEH7G?$`9FFtVAS?M zoPf6r&4K^fyypL^`T4KY>c4s6{O^waPvFk~ej@MO>u1W88>h4$KQLx;)&C@^^WQ(N z|JJd*^Q!&dqT#=yhWa3{syAHYn4(^rkFnEysiuuK&eV(G0xw$!i?mzev_f=7=Z>{QISQGc-35t2c{|aRKe=~pg zx2FVuB)%*eGrp57PFGS>%W$quXTC)wlC>pL`gw=H(@un3%{s zi&CMCMx&8sK&Z_}1h|-&w<5E4t=&*TF=@mY=GP9w3=F8RsmTD!d-%Q~5ZKaKTUS>p zIXOA7FI$CtfuTfMSsC*YfN9y#*YBIm%N!gW#GsTNbh%Y?6^udW2ZgHJ+SwxQXminpMf>e>3kceG!pgrca_Hl0%>mlciSePnb{AE~u%kwV$f8H>-EI zV)iaUWX(%uWMqVw=>q@#`+1$)ObUx&zzuKg0IDxpvN~XIndbn&d2079JTp_*)YNqT z1gn&@o!fFNIwod~K;I!?f(CTa#@@k?pSO;RiGc?96!{aS8P!Yd>+7%QOWwY%7% ztEX2`SSX&Am4(OSwKO#~%`GfOMo0I5U0O#Xke_*xC8}Z=HrQ` z2}?^$y1KfV%*ruZSWK3S4dZeX6`NtRZ=ab=EH%FK4{^xbGu7TW%;?zIzo=L3fUd@P zR#a3NgoK1NH8oZF;D?zcv7acnnriZO`G=0oPL{r^yafaTkrfrND4VNH-l-4)1U@${ z8T+UAGj(o_ctl3ko6ZQ=*@k<}b_S`9=@}W`7!{md$NTev>$#C$bG{SyZ{Ob9953si zZS>BvVCtG5pRuBx8+&_ut_y8Ir8yrXnb!T`QmbY~<{`qtO%)3Zi)#0|CV3?#93sQL zk9nj}rtNUq$Iq|re%?PET^OXrxnxo@wl!HPtmeNn5W&t@<+nY}yg`GYGnv}ICa<9I z&k(1+zj-7kCRSzN&s~4(AGz>^lyKo7_fh0ObMp@wR=Q*G8yi6#GB-@_Bo7Y{Cn&g# z=QlU2{WB#ybInG`hIV1*?*J{SQbj@_RiKIr+`d1hprV5Cq_Hu`-`_t)$}AxzC1uus zA%wZQf;&?GfdT-n=b%vNJ0O&tk3>qijF+l(t|TJyaJCrT)%73GIE45xOSYXVig(jH zmiD4!3sSgI@cp+~= zK)J+b!O29(9P#;1sE2<J zoT`V|FtfceIgI?aRh`+qb(nR+*K9Z(l^3UxP9~H0_xCf&8Y6MX8wV6zM!kAkS)5?s z=)NvD*|(s)PE6P~v5`cdYosiNG#-?12Qt)bl1YPRNr>*kdG99UI|a413ZJ>9`?7)1 z;fV?HqSK4V3Z6F}sa2qR=qo(LAB(S^>QnbV5{@|oH#cQ4U9>^}2gxFu#H{v{WB&D5 z@HU|~*;F6U0&Z1eV`F%BBt_^rmuy@o)HkQrL;Ue0F?4=7T@R<=5J=LkvxKV8=oAcG zG1G6%bat_r_tFZ{X6g1~q{MG&bW(uUkH@rS+W?%P8bD-hoc&P}1bF zb7TT-=BFfyTv9&JTw$3ZlxDT{D~uV7pdxe}7g@FU2!cU;PQ?Z?#Mh((wcZE$`6Ug`NvfNm)?8)g2acenI0+NWekk)OWuJ%zTE$d1$Vq>WPG%u1l3b=6nFYuBE+xNKJIQ?koUzkS!r;zgovND^&; zvSwtr3~1jm3ZH^f{Hwj4t%G;~n7%G6r(onb3gj#YcXGpgYveLp0A@i1p>>=6qxsE+ zH%UR8!|BcmaQ;apxUg`t@pYGxp}8cLk(DXASE$EsR!tV0Ro`>da|2`W&cy~HkVo7A z*Is&v5wEUnh6uYa-nC+o7`xg_ujEfJa(GJ?4P2`5D8p}U4pxy;9d?kQVvL<1vlx|? zuTxQp9(v18tVdk#u53nk`cSk1+My|7bX2JTnWrScuGNUph>@0-P#8yOXh~>^Mas#` zrgv206B)y46>bqjaj{bFo{)y7-W6UFifrshM z*kviJy8zPl9$AIp8~&ion(=MS?z#sDyLxKKaiiH}(rD5J@7;KT!2P9Gm85hLQZ;t@ zs@dHNn$Vc;$5fFbreg2z?jD|<&BS7{BO2uhOKpg$%RDIs&6|;??V|ID`@pvlfyms8 z!t?W8L+ynPB_)iGkLTCbiLH(3iWirZ=s=-RrcSX;Vml?9(Kq_I`vQxsY@%`8>=!@? z(VI%{ls2Of02qL){>F98?iGbvErNaH$W=4R7z1$z zcMQBj#1eY5l%n$)3OI+MOuR0CfYd@OM3$sV!Tw%!?e3ODy5ywJd&~4=Kh`>Bs;9Mb z3ia9MNt^k0H4PYuj^)KU^wa?Z*B2f8#=IN~)vA{jHmieQ5TfAHS_#^*gwPu-{(APV z$`TW!h?QB%YEMs#APa3zuOB3NsJiXh1@r>LO@$9e69`<13kDz(?bc>Al1d`zca?&1 zv9tRg3K@z9_6|5-YF`d*F!%&Em(r>*mM@#l3OeMWq9|?BpsMBj5rWj<&`nUZ!_=%x z)$xy=S@L~RcC_2nNxw~hJ9K8)a?(copyrso&})!2k%UDyd#x}IA8SxqZ2Gg<(a30< zbWVC#I|jPo_dqeTHu>Nu6!kuciG{|T56lL0WRkU=+}xjy{LD5spfl3FBod9}sNHDJ zRTm}oFVdU@JvTSKaVbK73E)+H0c(){aWE4JGl4EV>p=YZDQoJwHDSc!8(&LP5{##?C(rbvS#HfZwmIx4*P{V~#u%lL1 zuh7nNe%LNEFS^ai zds)C{guYS zK^VVO^5X-}_xK^>r<|*=8BeA>+)aZdS%{Oik={760PluHsJ60k0)Jm!8J9$D8OBAC zQV4aB6;^Za2eNR2VQ#iTSRlROEH6YA(4PtzAf{C6^3SG2wx^O;fI1`d!zpq!={TnM zPK3*UAs$fCpv-Uxgrul%v(3zx!f@^Aje284w{&e6nm=iRu{XW7-E<4YSYu>M2K6L_ z_%i82}I1B2v(t#!!%9y>%r@0 z0>2w;86c2=LAHlE@Ryd2~Woi?9Q{ftEFWS8t;Pk zOIWMlzBD)jmk;nA0R}QBlpJ1Kh(Z&$+79HVV6UBmjz9^pgA|?WKr>U-boBX<2QTkT zHA6)-OU5kg%H_Pt9BWANuH*z~@05d7Ll6)?*WBa18X(c>&*4DH*c_f5`SLM&iT@fe zN^fSG)X8&zs8CJNB(tqz_NLgPU&_9O>jio#+S(@T0;$LITdoN4LhtoSSNE1sh@i7n zVQ#J>aIP$n0#)_e-3e(7g^0$*MDmQ@=h#+Hv1NwgT`C)k6*a3X0`xa$Um;k(L7l^d?pIpjla<{n#C!AP%mHZ!HJTfVg6F3vzHzp_#S6`-G4 zHp7H|t#G+|VRV6^wym@i|8>mhz7OK^16nW|gD^+h1y2p{*VX5fobX18N7&d=C2?{6 zpRW>y=)c?>M>DtN$LLf_#p6zyS%Y^y}7Ws?MtRn;Auf-e%-qWpPh zA$cflh>e|dZP$siePA|4_9$=5O^3%`o$^4bm^G9pWK&v%GeW7AN!XpfI#U2$(_5dW zb9t1x#b(+en0uT7W=-eoeC_Qh3nr|J<&4E1%?P3LpmG04ZCCyeRojQ9Qnu-lgeci} z*|(vTT@A|CWbjyK&{(oBV+l2svKx%8$k;;6gT@+SETOVawg_Y2jbSq0)ARoD{sr&- z)A^hqzUTY>e(rOh`&`#K*M%SzOgGW3kUI@`M_rbq^IV(YqX!Z7DZopfva&Kj0os$W zWEXmkC{!cxx&?US3+BbU9~KZ#Lo-Ycg@1w5A)02BllnZ-Ax#EvY+bxCFjdMwkrzvG zz|!gT96xv@WrmUkqm3B)ZaNER@!U+36^1}_MJ$A~GD{cTR*&9iT4ao(Mc8*0y-7_? zKBRjo+NJ%;Y&HqxuV2fQ(`k6$+sH?qd+|WfFk{{tH>1B98U98UxK8k=RQF6 ziz+Ro^)3t#+;hc+uApEh-}4Bpw!7oog``HfGI8au@s;njPaLtUt0^ng9->N75#c5~ z`+`eD&I3=+6@=J>+zM>g)}4}aGl;9rq8X&P&KGAP(Q6!v-sw2ltD=g^kqnK}BccYUZkgB39IUU& zT!05nyns&zkc}{M_E~@(=#d7nlDK<&4|aEVpUg}*GZC$(gZNMKn%#m1r)|n1eoSHrFB%dKPx1ZI$6U;(` zPlGre{^~L^Fc`nyb1_9G#3sYeebAoPKJN3f`q_tn#*f179}kkq&}Ma1glj(eL_FC@ zM%|pudUoeIV}KRMol~i=S62wjexC2Ws7BD|i63O*AIhM|Ry&vd2T)CMaot?y4KbcU z?~5wdRqW{lYKPw#zM#LmDEhGAknHnP%b3wnDBf-}fj@UG(YO z3GAZAW<-s=7VJE!zGgzc$rOg(R!Dy)`@6gnN2rXcHFWr;6A9kHD3)=RW$0jf^spNd z)CckTR;L4_xv6RscBXeYQWr1m)&*#GEC*vWz)5FqTRsiLn5xo+9pp3BOdE5~oR%BK zG(NQQegOZm<+8}bpE+B6&NYsgsdwn^tdM?>;Xfx5YQS3_Q1f_1KuZm=7~7wA%a@l`I_zg zbJg)jOSupG#F2I?o3&HdRWwYRs#YftqMBeRM6Bk5xLm5@cqt34i4z@Z_CPwwhhC; z4}5>GK`HdU18QPqa8>}TtO=U^JjZz~bw_orOQdHzgF0Yya&a}0o<2j3&(*S|U*q(q zb2~KtI+GU`r3G5EzT$dvUECG_&!V6X*1y*YAr`~ipIVGQT7g(je@IZ>RMMh;nXn91 zy=cc-pcnr|P6PSF>D__yl&6)ljf>mX?Y9iBcYLBekc%3Lt0;f37d*oTPuJl=+^5vBg zz7yidt5Tu*3U6bCm#U9JxqB{Ez;tg~FC4{bwZGwKHLBEe z5b}#SGrv&DGcbdSz6A)BncbpZZ!Q9l2hR*?HOrk6Zyn61(f-GtEHdwl z2aZ{JOf@I>N7A$X8`zA*Gv3&t{U3iWk~JdN~0lqK#4>7G%X0S+^qzRf`OLE!@()WSK?Ilm)z)*cHX$mxKkEW zO^3tIYlr)WArV4tB=Bi7PwDbNy5K}ZOaHg&pryQqJpo&Wormu6+zybRl?u=ikBEO2?BNlo?(ZiO#8T;{u~IJSj3|pK{*}<|Jo=Cu4W*#JMXhum6G;2IA0r;JbB?y8 zy*V;{@*9;msb*wD4Ggr)?of(INhXvt57$;ltRHSFwa;6=vfyOpQ4Fp|(&|GT3tsk zTaT@o`ab-Uw!J$M-U!_c+SZh32V|q@Tbf=cCg2lFhYd*${@3qZ2d@*M3?D=f)^5W^OM8b{Do588Tg=QV%|idRu=R3mWBH9-Og;cosT|g zQ(r0^mKItsXm#bUhejt&ffn{Z4iV35s41$pBnj#chpp8f%l$YO3=5hxUTYlOPCd6V zSEtDRS?P>-V=PitnL{L^P409?A$&r2efKcVpim^$n2Cw$VPoKW6FFUdec1BZVLOD+ z2+I2?TZ);gy_=_|s@k=*guk?S%)r1@{^wf&2{;^nCgwJO0$ds)CnV&1=!aHV)g*M_O1CeKEwTR3zMmITkNsaoKzSo+8w%Lm^ktUFN-cmdvRRP^IEyYg!wb9F0_2 zm*a1d!j9QeW3EktxD(t|kUw_yawtlIZL=Lg^cfb%f?Ctb<%^7H_KvH#nmSOUM!yTo zfK0@`#eF-IadLZJZ2O@z%xw}*D~6HSP|OJ3b7Pxlq#s08q2{@7VC?S_+4+`XHX)1H z$Er{E69$zyE5!Vru6UT1xD^tdx!Takk`gxOD{3ET^Z?~r>l^||y(2S#e6sE|MyVZc zc>8YK;AT)NYj#C8=lD~WNE8XcDL zShW?)CNJqk-=p*7IK(rJLI2SE#Y#=tLnvxZhUGUH&8V!IZyB2)EjgI0lP$8haueRRJwQruZ zhSMm0isn@!ueq*m5SqQ{r=xoGFs-y{A2CjnXkNNZt-mJ3#)i9en3(ahysWGMkN4ws z74?Nb8rAXSVUm@Vo%huMNTArh1*iR$5ul@H$I~Pa41kAHHfPM_d0d8Y5SAg}it!%+ z$^>*(Q+d;e)iXx2)6f5U+wn}O>uus9>seeX%a9FY{Y1ZP{iN?Vu9CpU74LW$OJ56N zeDeTcxAdga=YF=ud>I&sSP{JeSfc=nihts(^W%z&;60eHadC05y)zqEh6PAjjbzM%#R1Jy0n5{QCMjkTn{O&dkj%diypCX!4}jL3GAb zTTJKpI8RJW4BLeZoNRyGzTV<+1~i<$-k;%O%vJQec4%1yFfRZ0tu0yDkVim3JnNpK zhK4b)Z6WW@ZU;Xhz|zvva#+U+Fi>AjW_Gr4ve93OM1U$2y&OO5OBnyhof8nR{I?@O zQ)=d4j+*r%@EqsQEUm4%xVgmvv%)@fS(Gt~0Wcl2w6=a=ZEYZNNt3(8qVy8*SV&Ih z0G260D>W@Wy*lDJlffAIIl|S=&H?{5UDP!P( ziSZM4e!w0EP+pyVlG)W|pa}*uKfm*F%ImrNzcDzV*7_HQpCBCeNutwo8SyV)vOFlg z1k6;JoS|Gs2LkViCq2>31wz~#`m7AeF(r#48%2RC{uE-K|3W7m(~sy_-JjbJjo0S- zZ^-2MqkCr`1No&tMj+4tJL_cTtPiwZH1)o;q$H?A9>@u>0CF;ecYcsrRT>JS4VPLp zjNV8E46NY1hEb37^xk#DjElQOA{FG+)Tm!&a%}bLv@UR}N=TZMhv3I8l0@IwTm0KB q;AVKEBm3XOn)58f|Id?Kk*_ElhIjlwqypR=gR#D;Uge#?qyGc^t_nl| literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530004757891.png b/README.assets/image-20220530004757891.png new file mode 100644 index 0000000000000000000000000000000000000000..0ea0274e1fd32334deb11b9320917cc6372b9228 GIT binary patch literal 38309 zcmdSARa9I-w=N1Hf#3=51P|`oI0Oq$aCdk2pp6sUAp~jMT?352O7PNmL{PBp4VNRB0)3Wf&N^Z?C_v-^0H?)d%Y$ zVPHPNNQ;Yn^T<3}_B7Bj&3$=+ruhz1rkT{7N>Ap0ZOI3OBsU0KYHA_9A#cKJMpFNB zMd$TY4BdeDdZMEX{1vu=^qx^vb7&&zr#w$`__0|2r_K z-qC&hJK{dmDu(}?CN3Qy^KTNR4AQrMlgO2ne`5Tb6&{Z`hV1+0KWqHN|8K7jvatYB z;TXS_G3J$YBsE|*037;2acUgFZQjoz>a#yO7?0)SQ||Dc)tnFHQ=f9-zNTs{cUVxdeaQe(L;typio8L4PYJhne{M zLd0Lm3^a2I2OPK@6ffT}#Y zs!`JrL2C*7NRLx}8$!ikJ#5w;{B6PACbxtP$9|AQ&=ER~^?<@R)7~AgzPdFM?OoLO zW{btE?;BH=(x0%dVoE$;pn1`Ax3)DnwNHK%bG0em2>ctvve0eTY=&8{4-m<%2zwPL z(v`R`+v$d+j!Q|TvX5p3wO`K)LH2M|eYYGSc!sUW<3^Cv^h_7w6K(T2l*j+F3{PX+=UeJCFW|qElyG-Q zyG~FR$`Uxo%U5m43=}#zafJxyQ;R>{yD~Ju@5zxssMLo|f|C!>tm!9Z6rTp%b9(c7R7JZ<55v-bA3=tHd)j_j+9w_P?${5 zete5gV(@a}RhDcSMX*C5Sdn4}v+y3ivD)$hFBC0X>bVMrm~;AQxj7xz{}NZmNm)7) zcCuo+?Xf3;zg-|UadGv^fFscT{r?Usp8na7Z!1KKSjtGtmdpM{(KYq#lqbi1x>&%Qwm~FJKE%2=o zm*uWO;o`2}b5jhX0<+Pve@xG!l06ks;}@?`egAFmN8eNSvN;C| zig>=W6OF;kA>!LeGj{K1ogG;S_3Vu7!%e~C{Rx7Hmr-lb%w9f zR5piThADARROn}eddR20cAbq>V)ZF;zOqd5y;Vuk-noi?XGGs_!&$*Bk;aHYaL`-6 z*1hgzQd$Xq)Qka>tWaH4Pw2`Cn<9b zKFwmOIvpUE#FfbWeEf*gNRSp?`WlZw=+i=XLsY0PTs0er)~DJK_TQg z&mB<o>Jx)z5tcZ$H{BWuur2K1p z7vpX#xCJb5JR4!s5K3+#*qqHdckwh9d^Mw`S9}5INOX&fk_8ISo%9^ItW~9>+p@Ph zG!bjqemIAIL~2(c7A3nU|0tRZlY0UqxBTSpU=VvXjvMg-G30#+xDI-)G(R0OkJV+8 z%F1hW&SP|*ISJv-HoS=cq4T@RQS)(K-M&@$ zMLh;#hJx%mUZDb!tQk>%+ryvm<*eRdS?-k^4Wle3ql^qoFL(L}JN$@#OA5utxN^c( z(>pYwK}@@ilK3g-34tequd+sTUp6IvTo2Q!wa~@eq!{Vuo2zK5)Cuw{Rjtz9o!zapH zeEJVrnR(}hKCS7{V?0DOn9o4(3Q(^-kH&l6u`u+hh?Lq?*7NkFSj@l(C)MvB;NW3$ zhDj~|!4)5Wch*!Zr6B){r7p7ETF-pF8}DYf zdB4IVfhtmeQ~yw4*y{|b4~NRp%RSV_%Z}{j{;u|s z9gF%cUT8q?I<;93sQK_D)_HW~oCjq@`5$r4jDF@G@cle*COrwFV^|Wl#bK*+nwcWUcZO2Ym`X$bq*ht zPCLOI?={#C_S!HF;Pybw*2u%#9RDklLdu@CcWgifgQF?ySb(1PTLK|PDOaQF{Dd^? zzU?<{=RC>@QbHGx^Gd}{#=8!??mG^5Ro~)a6|6`S>^gw`q|ZF+(Xuo+XE;%Y3+g1h z-j~#@^wVM&>-O42b`fSPgK+3eU5|&Mn<}aQ2tThioXb!SHu$sQ3^!?h{&FA{BXA4z zO_w(c`0F^fyOaAfgWY?tLHZbq?Nq2VJ~jKz9M(l;Q-}hNyqT6Up)Q^Q>_nW zQ@QY(ueFKuF5B&e!p2BO-&7yd0x!q>X4qw1W}28^AR&T*LEnxHjq?6qm~7Or1=Oe!#GAN7XzcCzjtfC2<1`#16_NY?{AV2r6|phsIL4Orv`b? z%uvA@oKYV^3-naL$3&tFg&M{=W$EMO6i>HlzT`x86~YWjy+05dV3eR|fQ-g} zyTY($Lx#c3Lz@5e<({6M+L}MScTYdGcEq$Sb&D2;y;`ctcsQW$u`VYMnXzk zT&%G)pQytYw4V}7u}$v9Rb;&?lPvVav+8vZqu7(^Ed;r;G^XXLK%};*;Ms^zkaqNR zNSDKvGx!(V+!e9X(bH3CH`54u+yRWbBHbU6)j))x#gIj>Tx++T z?)K%Y+g6Li6S%TDVwg-|zDfEgL8-+5{kZtQFJ*#1 z2cA{zFu}G?u`wMTA4S3wG-bdn#ER#t3L(Wf3Arg}@TK9CAIyRkp9NbbAxr+!Qvbbj1NUk<0JJMA ziBC9so%;9I;#3HJ9+tC=bw6|3R~>D;YgQK~?=*>Nzi|cdjBSDdgWx5yVjfsy13E`3 zN?FP=@#_;S*%=Qf(X6I}#@GUN_2OlmpMG2J|?cV zmgH@0%bpefP!90z@2vUGsC;zIpAlDF%B@ejIM4U?Hh&ll6qh`ZkRKpogT8P1w2N13 z5&CZ82;T?_|Ku|j0tSg|ai8_&xEpr3Af2b6l8@kxee{Be^Nl|J*ZB!w&#y=BOX#^T z>7UPVE<^ovq(02d>!PFuy@z}BS?7DcdEn{e_kg?G`P9zX9=uOsbCTEEie9x55!t(6 zWylUI{#~yn9dL#a_?Fd}jW_JN*MK_%ZM6}Pnh0rZeokJ2NA^8CP6nKNCW85f$&Oz& zI@qjlNl)ZBnX~LOVOKuF=~_wJ7p#R`0T@;;mJsi~8{qrUk)9qt7Pt?TW7A(GwGjdo zxfxxLU3w7^Vb={{{H;;zVd1pjmO=0`?a)v1a34jy_*(W(t}uVY5cPO0^AOMYW%(Q7 zAK&O5q0yLSAT)BmArm^z`Y5Z0siqQ~J)<{#^5HrAldo@~*l~1hucaV{^27U^+kLD3 ze1tHAe*DeuW5+fH5?)my;9fcX?(Z2oE^fWS^3Dg0$q2SVr@4DyDAw-8`;RA=lM5fa zvCzhFxdM8_X}Ut9^;%Y;k1f)4pH1(Vd)LCd40$ITh!>$SYMGAmvcyji(?G&Xa6|~p zx&wMvH1XAyn}|8hG2`-EdF{@GeSINhw?@L0p%_LCIZ~Lo59Mr<9MmoCI49Yb?om1rJkx^P_8?s_P}#` zy?pm$vzaNKuVxEg*{%NAu3f|&g(utlAas~7OOHYJ&X;A5iG6Ta7~y5R%@6+FwUOL4 zAt)Ov73%=xll7WJ4GdU|+*(K4&g=&m=IMH6If9UcitS0ETa4MuH?cm}%!Q7YTjFD2lx&+sK}e6+lnyGxiW(=t|ckvm9tEzn1BAbu@)qy=vd$ ziNPkL6}U+Hh}M|x5F_u%WIJ7#+}ZtvuD)*N9r;v`mOWvZ z6D!QuV{?qUkgYXv{}@eXep=P`Ku@81Jvd5V&R=L2?|)3H^x5`5I6NF28UnaWa>7^# zm(*8Q`RNNh1PV&TO7&afrIuGynqaY*EIA;(5^*hhjcbs(Mq6!A@{;9}>umJ!kgdUd zyjeQAe2vV+nM-5M6Y1*Kbj-&sNK+EP3`fyG3%qK@j+cEvMK36I9Anycx7a_&c_q|* zZ|vM`sr=@=P%T>z)4)hXVCY3vfs!-!<76Zr0j|O20wvSSqwSJ|DRnUyJ$(z%dD?&m zl5SeYYoSOelsKOkUj-Yw{@eBx{2u>kF{`%?L8x~){zG|&T5a<$RO5@~CFjfNVSKB? z>gAth(*7J(9HVyq|OE;4in06}t zA}t;D$S>(jw5Er1y9t6@%@+F07PbV-c8li{7iW-(Kcm0?oYZrj2xXH^U72sTyE=oR zZJ&A5ZUtdlyw(>}h3{Dcv^q+u4&9c>Zp5pjIaw;*w>`f6)eOQ~5_}=}ZbxL3>-SFx zvwB>aU5N6TX5T+le)74_7uo8Wt2XR1af;6z8(h)Vb7D$^EP0!;QD>{nGSk98us-31bJSX&vorXc zV@9X=Bq=QWq0XWn=XDeS<&v^cq9~g^)f`VwdWtMVaN0Ti$oY%0cp8x40shHvZ?OG z$#UMbi?v}nk87M8FmR;rHmQ}p20z#6!jgad4$puH9w2ZP;MU0qF;DC&WVD~uZBHqI zkmX+;nU1he71G=zI zDt^z|(#&YN-!?GdX7`}fFws(v?-=dPjYnnA$sI0~&#f#-EKaA4RfEuK1)`TWWOXD7 zu_T@B(1JqI`=FvU1(U!yV~$#E+-gD60`?uJ>oXoBI=;EfR<>kYT2Sb?2gS6Fe`$o8 zGoqMXI+&AcEV(sSE>>+a)#H15wPinphl3HmSd`g;o;|4Ehcr6j!eZ6yd+_jJ{x0Rl z+;)Ez$NE5f;Ghb#p^Ouic4p=INo8_%1&aM=zky24jbDYW__*hY{V~E(E<&An4e{0`@Opd z{a>6l=i`1?g&{7qnV@tAhu2cGljUYWLWvppRGWG6f%fhEze3?aR*SGV0( ziL=1jOeOPxyn{KzwGDhAlr%|{IrJm`O^vfw5oPqmevni_`s}F3IcMHC+MK2Y({NP60(+>C(^7W`F&v`N26NGQKU9-NKvz@!T?slsI;TnYJ3PIC2*r0EVxWphW;Q8|2}nI_B?Z;>rSf|}S~R0#<0&pI*bFCZRT)|q zE86I`t@A6yWYd-gyvjcMfUX-SE?Zi&tzEVOh{N}fKt@n1V!QoEi{t!3f9les&X;Bz zi$Jkb>BJv#IFi4hvO^(T#xh~z^2-gjS(8$h^OB~LXpmGJBxP7IY%_Zk6)yQmsYbK= zEPma)_w`u~ej|Qsb0KH|^ocPNF(7ZyISf11y zT*nwKF&f|PG6K1$+aard9Y1DCp5O|*5pF%ugyFMOd%(CUW+-4uA5r9BElXRtcrjtr z((Gqm<_?D~Loa%shylc_@k!LCqtu!WX^xDltTOpidYr~V*>ux)8FUv#B@iPQE2bcY zOs{Zd3e&I2XO*bPx0A0?M5_Wo*QPc_oz79cz5V%tOeG{f3}D7Gb*yi8#^V)wp-%K?a6xTrW_ z!66Jv;#q6RMiZZC+I_l#lC`6A)9Dx6vIMo)_Qnhb3(N2`*`rjOYh5QGifeXya5ot6 zBWCUot;h@XJuQ<38VWHcJ!rl(+FuM1M%$F06g1KxMp|<@uRxnfP5xQLz&^?_imE+L z+;yzeONmctO4Q~G{;9yT-7S;x)NPWBR)dl%T<-9*KHA4{qWoMg{I)^LyR|XZRoR`F zTL~EuZi2UqNC=pIz}4Qs7MSCpiOK0phV-31O`nf4=50>w#DpFWgI4cKPbux-P@g*_ z`A_z5Rd>ILhgj|R8)p&rCzFYWw*!#K0zZFtX2ylzD-(wfcNk%LF(sI8cA!>zVL8)} z#nL#LXy3_0^)9gOydT|UP&dz<1%c{9QQT-k4=$;b;Z%$XI?lbUjeIvB4oY)N7@|rk z(i@RtKWDbOaWoHU)@0hN)S!Ao`a3>Be=TF=5mny=jlRS!Pjy zlDVfD(d_%m&JT}&PMcn4C@(Ze7rvZc3{b4A5WT=f3H^;@dCS=!MlWkk>xB&k=QD7e z))BDZj{0b9@UaT1^mDCQp@vnYLkA?AuWFCffs+M|za=#@(k9Mff<*5q*hD zuZe>zXXJ44kaE5@T7{CYdivm((xoHz6mE`$6;K{Ca-F^(TY`5asU};TB#&@PTWz zvLb)cWg}Xve|A{b#|@1YF>R`?IcJ?hSz5}0Bs+RPzZDb((q9%g)g_EeCnlO}k2I%9 z_$*($?uzq6a}3CB51?;I3x`rCEVPGHMXs*JrMOKPMmQ|B<*)bdkaW+{p4J$zGBunY z1UHzy0dQTaX(3kQ>rIS)F33L6$u5gCSG4P_$3)rWu&vb!%a1aUf{^UZk3iami-1zg zhmZUI*;~vn8s5W^g$m#>p$ETnG;;dVNUVOo8QYMRPvYt7mwl%%f0+HR*t97e9y3NE z22t*ulX{cAC&{@e1W6)xegu}ZfFG|`Q!;QSl`E68dT-_JP=kiwF&j&8@`TVm&yJ44| z%h;wn#sEXFZ86`rw*ez-xCat-yq(o23hq(Ng1)?%Y_;K|cp}M`#A3)xJ$*#H zre;w;0ycls^FIKw8TRdda_&)E?~Gtk@tkYem_#%Fsxn2lCVfB@(#HW76bD*CS>maq zyX^3uPC9B0ov%;LF@5C(u>5_vC_)Q2YU^`M%*r}dvW7kh&>Z>0Z);IZkwCMWChJBb z))`E?QH}RC8)B!09$>d=4J}GRv^szGlsxnCw)>%%YgiaCvN&Nw6!f;Vgj`J9Ng$Q5 zES2ATDmO#t0+u{%v>i4awq2%emyx7rwX!UC85XA_)U@1~=t)n{G@B;AWA;(n@#h7* zY-Yn;GXj^$bT(=_Gc3o`oE{18Dk`gz?nZplwC$-@=`j(xYj~QvuT6CVGZecz*Ebn-(QsqE~9lpx)3q&t|!n#?TEDjl5sDuBo|idq{bB3F`jKWwF*h~X0f*DK z%91P_OAHv9N>Q&m53zEpl*+9xjDX{W&t76(a_N^1?bocz_??CaL}kw!O0I40NG^eh zBhknk-b`2IxEA_pUS$w_?cdVB!M=*4=I5^IG#*$}h6Ut_6Re%>4S5 zIrrK3RWtg={Y@S@l@`-`=Cms}YiOyq zG#;*rbEy!Bk<@=igCOTry5g%I|im zmd(}03fVKSTN^aJEd=gNH#-1N^dnYyVxS^=!AML>>n)*wy3Y{ z?4Q~h-RhI>w5$s{K|JFAQ+W!&Ta-;uHKU~zid{%1~a(a&sR7Y?2!2j zKT?g&2}zHm;-t1^f%w>`Q&1IP)b6P}Hn6WC_H0fc=d4v#O-Iarb93GeBNO!UFZDcd zXHcf!DX6Tc2g&4hX8Mhyif55)WQ#2TdAosJBgH#9#DkzsS6p0XV%{Fz#!4{|R=<9~ zMz5TSDc}m2R~eU8>G^6m_<=3cfD5L@qSE@O(^m=zD}~gP;*_TWWII=oN9s$)yA19W zR*H%6dQC{zFS5U}89C|FJGB4mOv0@U(B#tnm&e{(ea+DSwa&2rGx^;A&n;8`qf@2% zwQs1m)k2SvbCV=8U2a| zc%TX~Nqm4B(++y4rtG^h_hITt`j|}XPRQesGp)R%_;im{ewuD%N|m)fAm;FNjV&ht zOf;Q~MqKI18JV*>663|3;=gGXfeL4R1^ic6xf^S;fK%lmDl9FHJUOxR^7ej>hW^$; zjk?wy)|{HF7LV~j$Ta5k7;j!+-P*L}ba_IDX+!c!YUlNJB_BH6ZF5yj^77g{IVl8zfGaC{fnA^Cq~5~R&dYxK@ae;QB2+c5jN>H) z`U`wPQ>4od&Ws7;nC0qgO&ms#=+h@VDrXQjt6ASMN)D{cah~DjWg;Wr@2iYclbxe= z6gHH-LvrPM`Uw0Cp3H3N;kyZcRw{vPN|e;SWNNJv8RZ99#&@2Hg<=))14gFtw<|@WO^J|A1o`L}(zkVoR0u@=;NZZ*)|QHwH!U#{%gD&6YThOoZ20IWG%_;6!NoPPxcF5@ z25E3`P=g^E_Pr{N6AdUXJyCim0A5Rs%nPBd$5^~9HLNQ`btJ%mJImGdXbB3x>gjB|+PvpyKV_TIC%{DbI z)99y)ht61IFQ1R6O!L1(6>*YQWj@)j3wRKzVT_uu{zEF1?~!zhuMA8{Uti%>ZS(Vk zQ&Us(L?eXEk)+{ zk<@{rbImPunNKTv;EEtQ8$JHe{Z72WF~j2gFMNZgCHc35R5r!w(&>kDPJ!Z|jTbN8 z`&N4}6I$uC%xA1$ zxw!#y8C=!QyYlJj=~WsGTU%Q!ZbuqU&d%o^{5(Wx@$vCz4^J-c?m1v#*Wq7SzRTin zf|6CI*lzO}(hl>8S$WDUtAjWNJbIK4@#qit@81Po!Nlc}YO!dS&FP*!V|q|~X&qY7 zt_sh_DIl>+4J-Vf?$2dzInrRXBr7nR+;x*h@`>l|E zn=Sb^U>Yk|CaK5Bx%1GONBB8a+-VWz+G$=T^P9Sf>6w9N83gctr)&%CT=hJV_0G7F z{kgMZ7Xt{}p2hJXr(wgjG&SZl7M15D6m6?p7y7A}h@9wZasi`z29qBhR^_iWw;o$9 zNK6smzR_U7VMrFkud1w!y|{4V0{|4}++UubrlzN1f!W1Q%{sxa?Qi$@@^es~3tcZ{ zb@{Jkou}9&x7S_^fYCz&fAh}?JyRYsg$zbr)(=Jed%zMTEA*L*nX$n{lSOHslP+fZ z*H-T;#8!)a?GeHug51W0fqTj3mk0kf^OpsgJaD8yYw)1h>aQCEMr_sZo#`_p{@c&i z{(snqZWLVuwCMj5ShgQb5%?uil%hO7d#+WII7wmR_GKD3rDA z32`bQ<<+HuWPiZ{F-@Tjp^5}MuvtQw%9;tC^EGMerZ?Xjr)%9*dGJ6=Is8o$CX~7h$ z0IxQ|i5u>*mCm+0A|#)F##Z3^@Tbx%WxLkK6tZk6PX6BM(@kxEVFK^H@o*Mq{|%au zZGM~*PrT)3jWo<~octrPA747p?4}DVD+eQYb5=vh=Lls{6Zy1&`Q$H}pR&YDvupphM8(CzgLzkR@XeSF=SP## zZ&BpyUdhDv_O?g6-m6n#N{M`>7Y#P^-7T(%MI|NVAKn|_!N2;PC<4xiI10)5q@*ve zrd3=V9vTY&irv!E(%~g&udgSjq~x4GyR~KwCeY-7zp%jTQBFm6da-9fE4S-AZ9s*b zk){6U`a0X}4%tBrbbqCPq2#P2i3aa>=T{kY1-?4Y5V$N3 z#uwC1A16k7fF#@gf>I)N&@s5aBJ?jT4*>hVu!^}-;w2>|tvfXj3=VeLHNuU(@&*<> z{(FX`S5jzJYsi&>7$REN*jQ`3$aQgfd4A`UDmz{d9v>ffoOs8w5<6(py?dFJv4}F7 zB9;21Gijzm&x?Y~1`YST8ja}}&fkr~GSzW=QC^kn)uP+()wKJMZH{J#-44Tv?HqlteJAO?!pj$b%WcU$6VI znMa2s0Ey=wCD9PCuCDGwxcDmyYn0FA1<+w3jZaPnt)9NRqRq>@u*k><;aZiyw?j@& zSW(zoO`27ybMft*h9ptDWzsml38ca zFe|>t69VnxL`d8ZVXbTgb4kXG*}L;3lek2T$kx@_)`KBSOWQnlM}~KLRoNg;0eMY3 z%D2x}ZbX)nhDheiL;W{Hb3|>w?<}>@8I!y%Y;G|B@N4EszzDel8pfyv`bwwFa;g58alt+2>r`_ffBg`a8nmyW*IA}`OTzatxW(I0KV9t+5X^IsXZF6|@eJ;Dfex z*>`C6Qla~0TH+pv=30|_Co}J=ckXQ@zk{-j8&aLybgZgKE>?GDVYU|eACE4*Z2K#w z?e(!_py>+-v$pb^=)I_PJPe-euPNC3Y>!bUy?8ZWA8w(T9r9TdLkjN=Q>C1~0NFF$+GKnqdn+MVNcu zxchJI3jiw$7PKE&Y}|-Q0BWTO5j&SpqgqAYt=YD_cdI9pdZ z*%g(7d#ATBNtE|pYytLyet?30 z9UXVlx!;g4uO&3N(e>v8P94|fl)Ig)m$emP?zkXi&oe@A*4UhZve!-=U>+7RcFLr=@?w@jVn$yt%v`4t9S zVqYa$Cv4#Y#mNDl+g+V!GYd{PKZ0ot*)B=b`v=}~I})27X*8#qXYa2^0C!lAo&@23 zBKSY}B@0{_mq;#+oJ}}JUC)en_~XYudJMgcu6XwMt7dt=c!O~3@u!t4lTEO-nVJZf zs#wt&6S-lz5D}%NL~Fi&8Vq$$V36h#o-+vuPF`d9(FUtx8^zkR9^)NnDxGX{EjSTX z2z_`a!_OZtY7VB%d3aJuZyx2{y%TtSWV7WzVD( z0~5{jspJBqlhNh-6n-zaW>)YzJl}f)c^O(RC6|;bf2zwHaMMqS(OB%BjS4_jRe>?^$ip-$Mx-J*V zgxR?NOnX*2Jp*3@_Zqze_>p!PHX)?txl$iOsYeXmiVgOUtu@>qY%WCg#4q*qJR68L z9chutpN{)nFct-Opq1CZ97*zOnc+2W*iIhDk&uc_`)Q7eLYNxDT!n7AW=;Bkl;QWE zj4kq28`2YUotl8N;ZtP+vE)k<1njdbzYppQuy|=ycHS@GO{T2wCUHD54=}eB-SS$vqgpRPCfRR!XW+^59V!XxzWs$jqJJ`=7m%gH>>t3 z*?EjTyS_d+O>8-{$cBpD3?TzOU}$KMp95Q$m(UU~*%+kKJ1&5^h)2rH=85GvI7pen zR3^F?9uJK-Ey-UrELf!$UBVkh^87IJ;Nh8oAo(JFmSfT%-sP{l^h`0sAV-sXN1^9` zi%o~H#34{(^xF~OzLc#Hv3&(P=1%kZp(di27{AX;Ju$P~XLNIZzvIS7IJ)6JSLBY~ zC&{ZyoKNYTUj@?z+ARJ^;ke%bRD;#A~G!Y#<7bOf~Ir~Bxtg@3t6?z)Ui z%S>O$!Y3>C@mO9|Y_m55M5w*kHGa2^Fso>>(qB5-(f|BMZTLIi!a$oh$!4Du@($za zW#6T}^B?lv&Qs2f`}ti>Udd?a-mRm{mwKEll${4Tu+K^Ah&qYP)>Ww*%4Gi`Zp_)k z>?gU#pdE;sJeQBwYK9qJ|J<(%@#63<3pPUnu3V&|@`2st_(ussw@AWRu24!{hH6+E zqfa>PGO_%BguBO}Fyft=w3QD!MfPt=mpQ;v$z{n0f1KNHIwETlM~=!}#uo^4g&Jp- zeH{?|z5EbHgkk!KQcyTZx5ps3MRcA~*k5uMJggf-0UhnBS1Yk|O`fw`ms|PwPmX7R zkJc+2nC*jH;0=vn29^h_q86t6kk^LU@5hE@{JBjj7~W zq`M7_L`8t!K8kY_2%YK7@HeA?@BPx3kZYnNhYfkUU%y!5Z00TXJfB#S%5il3=#!JZ z&`yhTCpY^M!ahE8g%Ocaej+U@yzoJYHsco5=FaM0F`h)ItlhOiAm;j*1D3Tv_Jdr# zb6oV^D=OKZ8aKNaf3GX9ieN)hLU=FD#86l#9NXFu3YQT(-eVxT&)1M<%vsN|kDRK> z7fpm#yE%Z5HhnGWp(V783YvTF*7Mr982nuR^VjEaJadHB+0(5|@a3T3VfAsu+wN?F z6-WVZHQrIHr==ug^fH*+1o^!vM|c`7C1v3U(hPAoOFBmx-W|j1qR-5~y61jp3-sUa zi4)#LmPz_AlR=2)y9}LD)%X&Sf(Ub#MO9Zp3Ir>D*rvVTiU1a;?&JImdq0=^oR7Q; zU`^dVhG1i3Q8hcd5t%$e%rdjPlJQMvO>&#>dF+pQfT}1ToEjCM9632%mr;I?J)au- zBR8GhOgp(umS!F)ld)qfrxF4erXho<{#)O2zB9B2Ms#C2VY%AOc?6fZAs_EbEHI97 zD``7Njr6yKPEGVwkCf?m!Y*AMn~;6P z*h?IA<>os@aP@{fW9%w_75B%eU`Z}=4l254ZB5Hb79U@3IJr%FIU%&VADLEC0R#8h zi&;YU1ogo)L1JDwpu$om-WfmuDif3Y#^r}Pm&p@F%pZgJP_~6JMU)f2j4U8Q5i*XV zl3*56UI=BgOZWfk1u&MRyK8DmF{q2Xva}SZ$CMhC>otiGIkF@e_e=PL0FS(E9(%rW zVx^TS5(vR5aqsM}u3gqZp-N1mHdd^2IyhebrZyjk`%RIxHZg+8V!<)k7^qbx|BC^8 zo-MdT<0EP^HXmiF+vTeymO0$v4Ty2l}a>fKlTq zkCUSWm3n{G@u9{bKeI?|zsPjfnbc_o=ZlWgJM02pEW9HkKT8C2g5$TCn9_qBAM>Or zK@3^J8jKLf%{}t8h#97>hjl?_={~%@pU-3BPok)j-0eLLblfpT9jMV#S4;@}r=SYA`wgN)2)x!E^@J{9sYZBBTnnFt#72U>Pg`}q%ZrAzk% zT=M3iAH2qNv-EUIB?+H36}xt7(aM(1$_Nm2>s>8s#p*O{UDC>VzHw<0Abd_!k@fPy zPQWjW0V?1FN9$56Uk;6sdSnEBo_%j}d~zsukm6C)N*YP>N7TjF+gG;(n%RcE{kzb) zXOyf541WH`b7Pr|T-*kYruR+1k^$rzW2uXrwX?q1+hYZ{iQ6%o3Dk7NBb+!qA|+9u z3b&ZHnuLHFQs?V~`m(S53dJU_MTOw z)ZneU#u6}sW$(B|J*iYApJ^NLRmfZmW=l@%wZyUxrk$o>gnZo{*E)dQv-n<;J-bT3 zsXjiv=&t2#(|h;f&A80<`&PQ1^v*N;ByYaA)P8?`YR2k*2QLgWgQulG zs?3E%-{*{a$FRQ*3gus9S|dD@*PtAqlo(mT%;X`agmwY%tm1^f4XJSv9qpFc!sxRE z^Rx|93spSxtq>{@N=G>QGy@BPBu3{8UxrJRf%~R(Eu>b;BH>hC@cNyXS`{P2YmdN1 z&voufhcahsM2h4h(Xe1^3fY8re99x{cLpf_Z`&ore;Xg>?rtF*mGMObUaWNh{;c#! zd0?5H{Lbd^O?$Pxj(yLLrn2uBV~964N4sbJ<{!QY6aBp2qq^tjZ2O{PJm;ISDM{pW zF&W6kZX_K2{}A_ED}$~>nsv#z|-Y*x(2{p-me>F@OFTbg|C%(<**gv83tEevv(7T^ZM zZ+?Y(-c!y_M`0i&FC%F1*}0g;cQ}RmD$VRvS*r=E&G^hUcxqj-OV_RKj|_ytB!Zqd zb;8MJ=+RmRw{QU0zqVqE* z&RAum-}ZHOU7x?&SQ6MRNvdzE*1n`&IY{XlIB1khi8+lmGj(`E{~YQ-pUeUc{bW4h zOOmiKEpD(uygM*->+Veg0(T&%rp75HQI>VeQ^xi;KOlRwsnCQjs~)6%Em(!5^bSTB zX#&CV=9S+;wrmB!yIDlcdsCjl=&1-A!l@62*d_@zr#0JTR=QH<6;b`kS3!q8@Kt;I zLW>U@oYvK4=l(wCE!|0*r0+*ndqWA97-1mRw8hY8!SRsgN2|e?}Pwb{CYA8h*CcwbSHcvuV9=(CWquZB!AkVRE&55HcT z$prd)8GMxv-q=X5_+;l=Bc<`pG|c5Gs*K=2h;7@$zdV zhWE|pD=pkTq>5%oPSX_Qlc}(*?((9};0KR+VJMvjp;>Q3(N2T3zV#+L({h0@_oQPV zXN+&iQ<+R&K8eJnt#)*NXSY+<;&3JiJ$dzTdm{tF@H;1E%>M*oV&5QLi4WKRg0A`( zn&t?WSC*ONtr|{0SD3O^AG}|VP-k@6XPn-7_>V-^JkzGygv5H zhv0}qcGaPY0eaNF)qOp;*SRj&f=gl&)Ay6^x3xmNrc9ajY2%8rW(}p*GXI5=e2nj- zzXpgs{TmZD=PpJ=(>ys=(Z(~l=@s<;pzf->qLSq=N;aN%Xke9;pb_VYo;JbM>RxZ1 z*W7W~58`yoSTr!E1#jNG&5jj_i7-u$@Pd|t=ne(Pfh?Irfp6DiSm6b3FP%);d|lDj zz$6i?2ABXN4s)jMsJRwrJ@A?DzXqsZmNt0*Ih5yokT9AnR_}LgnZ>78gV)DL-+Hd+ zF0oac{~buSc~PGZ_1Nu>8Ek!;4f@WKR$c{f`+YO`s~&5)HZ_h)O5~;jX0ey3^`7Le z*-nOV-JO%Yk|%Si>-1)a_;@UiUNY79-S*VT``e9V@P4G;^bZ>nRj{0v7W{ZW$3C+=U5DtrSv{lRJKeafJ}^M zPuq@FFq+d!`3SQmz-H!h`Qsr;z)(Ido;VjXLc(5WbOWdvzO@oJw;@wD5UMbb7RELl zV~ja8%Yj1=#kI#haWJ<^3qVx_?U2K)8QiQFu*b*+2?7$o=f2NAe${t&Zj_H3NS=U(U__DmjV$knt{skUPPFy{pjmKi z@cjcc8b5|5K9Y5Eaa`D5kkr=3yNlx!MvLrtoXkN+++Ck`Ulexia9|*?7DvI7&|nF3 zOtN(p8_vzjzA5^JPgggSYg3>m=!R8sm~kjg>Q@KX9d=#UDV8eh-xJsEzCt5^*nzeD_S2|4Bb&i%=38H;AE;w(IKL=nWW&E>!2zw&m?Inb~7 z8j2g++Tt-d6B-x+VHtbVn}c;c?#>ND{#!}m+Kr*qY7GL}V9Mi%`oJh*p&C(YM0A8m z-d87(QC<{2w?Q>zM<3ajW(RI@=`#TlgG^shbFB$MD~Yd=rVXSE@)-d%c>u35lMKB9 z;Xo}}abkKQ`6B6<5&yF@&dq{;%k5s6{n00Kn*$sT0#5bbc-%)gp&E44;iifkd2U-V z9!BE}g^xqVYB!a%>1GL6 z?`S2gr7E9?nmXQxhK!Ptz`8;|D!Nm@LT(=xyDWEv+$Gzb$#L8eg8Up4Q zhtuvvqm=`02J8LX;_JI}O8Rqh%lp|1=x>r>`%&QVk@G;HCllgl{v?5l*y^#zzet!8 ze$#b3h(pE9TeWn7(qY4X?)3WwedCdP7fzG7yUEN}ztI;Sx8L;~;&gN)E3GzzkwenM zQIv3{905fD#u{BFO4br(jh=qBv#0u@>}jE`&VWF?jctZqY%?oBWORw4u(y6&niK%6 zYAtRF5OX4DZ+uX$WEGF8#7{bB5^I*P5jCYcMUaG%;uGoVgz@G5t^0)G94y@K8~dxn79E`Y#0Tes^v^s6TC|lw~k0<-RM^DKj*e2a^$` z_`mhTNtZ~H_A-i1t5qc1xB7UILl8q_n< zTJM&#-vr3>MLfJV?T&1dxpc!PWYn|g>3&E1OSJA}*2sTM_+gZ!dZ-ITZjI)>FQX-A zO#7nn0Y@c?-Mkgfs@Hi3YxUC~`PqF`&ZjvdkQMqwo>VW;plbkrcKJ*6F}u0|vKj(S z%*&D-|HTnPh6dIcLbBOwS*`W zA-;7lDy=x40fX|eNkYptOV8&Z1yc`L&lKl8_ZQL$b&dY@!|2v{PjUsC5G4xHnr9D5 zmPUjPj@itH#eR@eI9@^V88@A0H@`Zx+yisvhJ%aa+wFNt^@kM>G~*=iyWL=>?b|cR z(QSArzT1poIHJW@GY8aBa}Sx3#BdL_I^(LK`n3lnp1@cF3w}(zi*y0N1nk^}b!~$t z`2)wSoJ4_mYH^rxOQDl|GDs+p2lUD#?7m+^Bo>4w=QW-IpE*8Q=ocK<81s0hiXnw3f0LE2G)WToV}@WoHBT< zu~1x?J#g>UO>XtUy0QhGL2EVnK37y(B*3WKGCM=Ju8&<{tECRhq7)_i5KOGy@qXdT)V54L7@WY+iSB%KY;IBJ{#*|e+&g#K2CeK>%8`}-{1wI-RGwkyEQRVbiF)p6s3$oF7!hw z-_e6OO8xOozcsnH&i%UtKLYDHBtWTXP#KXxx1TA9{9%ZcQLilq^4UH)D`{;^VWFt$ zANTi&G^g5bZgDu?<81pI$v%w5UL_veSr)lBLMWrjpC;aX%JDXuk>&S`Cv2K)?+*6Q zth7|scPSu==ZX_nq|LwEz`;WT_I*~sb~JA>N_cs6#Tf+-RPc;s9yH5qgds!RK5gdo5PuM#iQjKgy>kuE2+)V?P*iii z6eMkpHC=+8dc^4GsjaJ~}&g;vZJbl@*c|BY;*JIX<~4n}Yx`w`rp` z?6m&kQ>7I%Q#EEtq)f+Y@Hrq@{6U3Yf^OkB8m{7rmg#=I8g|5crewOf+FY&MnAm)` zd!zMoa@@eS^CrxYGKdE|+t-+F2?GTCz2tNoq-(S4kZi^-Xy$@xB}ROlQ%u8323uPC zD)I(;^ChaZDF*(DIKJ#(T^Y$3R^|AYd>l4SMN=d*0Q%t7S&D&1CUB*&JZYckvg3Yv zoNLMkh}otmL2Gb0%1A~cC^_%Sv-;wY8UZPDT+5cVQG?8L6{vJ7fdj2CjB4SWgR1Gb z?68VYUr9qiNzCT3_M=OnJ4ev9KW_aAhU)`rR6_Z(hm$!k9F2x@y#u!O5pH}Qneqaw zSP@JKOV~UWYkg&sk4t~#5^i9v_7qR6qf<5XnKD@QLpESpHf&9NYQb8|d&6pxg^`*T z5Ps}tgt&E7B#&Q0&XjZi^yt7;>CY8(J4dKP8$|(Q>H^^8h;#0#33+ite ziqk`d>!(^Z=trL)WUq|{P$iZ6Bjl_SkX?i4)ba8dz8`WL0#l@ao-;1r;>r+PTZiSDySbOl2a;K?XSkhdJ+&CFRO09BpV=_HjYWzz`+ZgFa3m&)K z+JJ&)HVmedmZ?#RXhqrRNagWdXe^cg8@2UPgV%-jBFkS2#mmC_dO{vbAl$1gd5y9z z`hB_U%0#!qoQlRzvjTA7*k4W;!B^3i z>3-+fo7xy)m$^1+Q8YC-OZ+DV0Gje->ilUMRB7u0?~1;<65D+VXRq}mUL#jb1ho2_ zKlV5sjN`~N_NtoJTLth;d0HS=UD2P-nUm3oI0~PotWZjF>4KTTDQ~h;=?UBu@R`Z> zU-Sx$t6H;oN*|R9AT#0g)uK=+n|8LElZ+1GAB=^}wrCdL#5g6+e|mESc$8s6N6E}t zE4weK*)OWF(oU`qD0g{tDRWCi>UDLp>CN4>a&4<6+a$=d-!PN=?wN zG^@l>4#%|Cg!z>jowo*8;?0+;{#ei7`Touh@bd<1>{!(=zQynCndkiVqr|AKwzxGIPy4>30X|Nr{CQV zx0bS5v<-!e46_a$wjC{Nysiiviq0gD31KLNZ%*9-#cg6u*_8#gWD$u-bEA)l3uS!OWk(AN@%(&K*^&WcVzI4x-3?;nj(o6&9`X03DN zwX`ej?~2+Dp-X7K)h7&39eLDpGZe5r$L5|1r4<|sd4~ih< z7VQcdauEq$F^~=r#FBFoVIlwZ%^U^A0ATV>?y~x28YeuGHx#wie@f zI4NsvYE*cdvE)JP%$8+o4~z70q2TVfzc>27|6-w~DH&cqRy-i$MsRm0CsJ>$Yd7b8 zdihd%7jg}r&pZPy?x*CJ5M$)QHNRt%3$0H*|5<0XZGGtjVb|6DaK7n- z66H$csx>CQ;^jC$PR}q+Hk2<$4_9u45zd$yS9s^!pw?7eBJads5-BPqzn4MX;`k%U zQ1vFYhK5TdLu1Er_q1eZ->@YI_r@FMXORiA5buE_mXe$#BMkaFvHDMb^k_+W=&_$B z8tR$Kx)6c#5vrsi>{{PB&;9BARY?_2bWz#&&Uz1Hmh=y)|Aou-1P&?DgOR`*Au+=l+%Kmra=JHY6?oKJpdyA;7of)Y^?U9jm6AX8^aAV zci;I_Cm+PZoyl9|cb#d{9-9ur+n*&!=74rG#Twqnb0L6^gp<)Jh^68DF@*8t=yyX( zy6skmav`NFwlZ_%ytF`fzOMwD8pnNv0Hz!uBCv-Fb9BV7Yq?!^nQ}h8pBlcL z`>~}Yq#7BVFu?-Sq-Rhw9WOf2!B;Gs5wc}6w>bBiCqO- zAht=Z;R$d;smpgh;WaqBRHwbC%fsBxqeLdS@A!zdN=Nhh+;{(!^bYD~XR$V&QTZZJ z{*KIt!r01_Faqx>J9<8>H$6^da^H$`NDVe!C^I@tEu@x-S9^W-bP_cnk~b!EI4@1# z3G42X(!jprf(23i_b|bS9BrJBX`yNzUD=Oo_;!OYhFRobsDw)It0Q4NvpqS)bi++q zr}SLf`A`;9QGJ*~gfZsLZ?SqbGeTr)l@T%D8e(an=ibw^7*C=e3X{g;;m0Pr9RV@ZIlH50-h8bL)`M|2!)7V$uZXB~9|NzT zt*4jrx&PQ`-`P2lTsBq}N9L#6lRYrK)~FGoqU}8^dFvhyxM5S$Z357u=UY#=lqkbN z!zx-c71vWcMWbmTJdB#<^M)YYnZnwq+!HG$Xhg+JyScr~-!=qo&BM%}m@?%&A$`8S zc!TaG|MdzOo4m4nwCv_e{Y)hM=F#3q*UQ`!!1tkU%toL>F18I+;7Zr(GFL`<|_I_Xa07eRbeC8YkO>?y8ZRzPMIjw+Jm6 zZE42NNOp5x%?eadw6db(x@HH1n=L(J;|c4G`fh2e4~4I<-|LV80`~N#>?pE#F1)Z% z;<_G0^yEF^>u)rI?Kj1EU?RefJqXiDr48_}z8X(G^?P*OQOA*M9u~t2Z!dLOp6$fp zY&a6cF&yp54ZD)6oJDNnh})6dTMl_rCGouSdyc}BeT2>tH#o4H5r1ti@J@=l&NR9A zh+5{9Ztq_8Ng6n8&M}=RA1{s`q^8Lx^hY0rHOH$Ne-klT^cG^sahaaKUigXM*w@oN zDv6JVP45jDlD;$_qRS{k`S8A8v~~NvjV6q74I;f}evT5AptROiA?nSW829o!kjA5QG1Wh&sNyM5;7Mf#6 zR4cm;0)p;a`3?C`YZVJgrAkphRJ}6jtT2&II+e=iyceGtXONIxHV!Pwckvi**)TuN zBdq&nhYmsBZV@!7WG^9vxNy}X(Ql>PG*(9roslYD_+6G`QESu6mSN3}c!L{T15^3{ zV(t^@1q+I};!HLUX}x`RdpBt)OYsp)i=ZB`G#IgcO+f5D+nX z6|N7TU<-w%Q&&d>)P~*L2b$=-2RA^4%V;!i&8qJN5j|ew-(ATo50~sua#0ahltyGe z!F%BU!2&4JiT}|Wsz61(8KJfPa{aCL)nf8h>>r144{*`u?#Z0}PTT;&oeK`VUm;6k z)ENKS`e9#NKctJBVyQyKXP1&%wj0H_3E}zoBO(Q9MHL)7X2YfN-d!2rMnZoLusu#9 z5O(X2Lnm$|50eyHZdT#U7%hXGrd{NGsR*h$kL`hu9IoRQu}}d)iK9JiYUqZb)0HQV zuq*3QEwg#1JW)Y`iY;5{#?2lxQ)!6wD)bLTo@}^AeoeM`OLP+S2XaWN;&k) zblll~$X-DtHIm=6$zlOD9}-r~`$c#AmM9<3wl1GHXpP7N)7lcJVw4~sj(5?)bP~C} zgx%4Qg_7wViL8clcdtBxqRs z`iJ0a*Z??V6`jd+!j_xvwB7bAeH^x4LFxve)Vo6LHeufpb=&pRHUqPdW?6s0C7zfp>UE$fbQ|9nEDw#G^P74L|ih9&*B zXHZu4Le}|tFPN3phYj}TbPpebRr^Ar-^HHCwE^`jg=$y=>y@u{&(_UmwLkW;K-dd= zP^mMs-Fne!JiI0^PvKedTtLn|E$+FM8I>^#wzVe0w-=cGWCdg43MPV&Kps1Rt-o`} zldPJGPk9g?zHC`xZL+nfo$B-Km00AeO7xC=D}hIAoycnm#-w2 zR0`9$ZlkXcb?abg!;a(1C*B+9tGykh)TreZ-Y3`F((6cME6ZRiXD0pYgNlmkLo1<3 zU5edyR_7mP^uO;Xc_h%MuP6Kr)V zU63_|r}Gh~wFq}okIEYYIh<^wlhX|C7)7!~tWE(fpf1`dB?*ehAEy}*IJ1Xn>~{QpXubTNEN@c+u71ck!?`<58(4Wb{7R1zFd)z7Eq zx~V{x*|=$*)Pj91jgz0ZroZq(Ho=BW`nxY4@slJP%7O;O#c zryHFfkF$GpxJQ^5fU%zGt{xHb`ZUTq!M@ACcB>E6`-H3;y+GWaH$tnYtNu&V0mYvW zb}hoMblxdZGU2lrWzTDAyA77dq?@Gw{U1PmI=~sk+W`3}+WbxN0U}(frpr$!vfYc) z=E_vHNt(a@GbxQOC*dLvU$CzmzWqq?Ql&%2{~IsopuBsNL`p0t+7VG*ZczvwFl`o2 z3t`t$C0zQW_77J^q&$Skv%7L@)b*_Cjy*o-PcW7Hy@n=-k82cdS-}ZbP&9&5`)!|a zoA7_l^066Dqpl_qAH)za55XMB4nqtM0e~egJA*sLzF*Z%pM-=%z-H%bq>pWwS=x}% z9Vr85<>Ca19Q7^Q7Cfj6uM*+f=C~1|@TuI;G>k{e%*8g7I{ROCNM@e#vr)n((x>Oh zSvetj1w#2eM$ttPUGF^I|NH&Pl%pqXXA~hPTjrpM1M~gxq_lZJqHaa8sWN8R4i1W( zyV?IfTV6Fqcb>Gmq^b_yJ}08GXwqa-W@P&^zoj8!3h?!MsZ~!B^hIxn*IQSZoX_J6 zTiH7TO)+q!(V*w#%KqpIwP2YCX1~Dbg3dRxYazP}u{*~DJh#;dJtGJTHIf`p*$5%R zXAv@)S$yDeKS&{%xJYYCYDWHoX(wA@&fy*;l&cg%T(8{RbN~Ld;n4%4^{*-6OZo7_ z880Zri^+4q2gWU9VLFc8;JvBUtbuK~zTdlRtEB62aj(KbxloxLB&MW^I2Bvq25sAw z@dw7;Vtf-v#Ce(gaheG^ct&t?jJWL(#LWV)wnKD_lz$&n76Z{>)Ne$y-G7uWztPWC z5g}1En^25Y$V^8|tsTPR6EQreU@gXZlr_m4_K~d2mUTXFlE{^`FfQH65`*;1n1=j4WeWg%1htx$obf*;PfaYP;}a$N%orh;V7l$_k8ovPYY}gS=d^9uN9fL7#7P zFsI9pRe7^ndHo58EQ&<@K{`d02ZywvoqGaBlI5|Nr)jdKW104^Xmpp+Su=S{>~6OE zZHJLG;ToB9?XmgaYCe_qA%oq=SX_IjU}PKIq3@I$kK zD<}P&$BmA>7J^ayv-gSp%ESxMH*U`Jk#pU^Gn}1jvy>FH4HQSQ-Yuc6J<41Vf|s4N0ST=j`Fk$@>BHE@0QT# zqXR!Vd;@9TcK@fab7D?g%HrjZ*dJlaCxz+n+nqk29ZY7KSePVOM6;zT{G+JH?_Urz7LOl{9rhrhTLD(niE|I9AA)!)S!m)oE3T=4w5MxtUnTV!=U$er!$@p4c~@1&1BFk=_hNY29u-2zKd&_3_7Y zUwX#B)*+A+l5l=%%S&zyx_*J7y6NY_;mghrU>Fvn(rs@{LX8ZA*tyFmP` z-LA=Q8E_&z*!o_no%WrvXU?=`X`^ln$&i^UoR#CIxPdKZtEgRnfx>Sz8jvhRg>i$0 zLptx1xE>C!ST_UJFgic1czn{jwc;KL9Tc4#@#!fb^@0K&b=7|R^uLTUpmd%q9~xUl^b(qCvBNNTc1{XpQ-hH z9q30|{6;fUQEZZ~H{l4^HVwC0G2_GXTgo4-LYl* zfQc0t#2HCn4Q8MxO#rOk>geJ7D`o2z)`gzVhLt53&$Zh{j9~qaZ%Z%8Q`Tmo>lXBj z2v_2b5@6jo3ye1(zMj3Q^jZ~1KaT;OZkYjZG2gaNF3!C#*hw@~`cjv;9XAj9Idi#N zu8PF4;6rhpFG`y!;`grqiCTMVym~)+9(x#?7rI3XgOxmlERh|k z_N=;rO1Vc}{<9a_qn9om6&$R`AZ$}q>V~d#u{Kis{_1%&t78OFruF&57HU${0g31+ zL+VZEy=270cB==DAnm_V2i_OU;%NgJEQc1GIgYbAw(;NF!X(zi%K3Mb30C972_tze zZZ4Cgla-0@bvb@gg0g|-T*~!M%-9ko`?N!t$IXrxJ&-P0?``)3wjlH&?aId}C?hAj ztY6~VZfJWo))^1LPIQbcOU+#A+o9y4&4{|97|gXq`VUKZKIoHug)FhUNx2)&u<~bF zdMkee{xNt*9dBRy3`=bnQIs#V&CL9!M4G&qtSA>j3W=vWR{gNaZdYUb$t=}A^fOg@ zG#(T<@^dkN9K{nNoeO`VagoY6G}0LRG4#Q2u}9p~tZfs@HtEosR-Mx9%3d&WvQuM`F?8jgnjB@P6{aljLa}& zxa|Zoem+>fn_apU(dR>~Ef z-ek`@P?|LGl0l$Bm+hGFvD;E?DzYMiWXwGmLpxJMhl%f#DBS<UfzO%7EIX|Ch%;7-06GLA6!__!a3qBE!A z7}-#QB0d1+LXisDvL=c!svwjU0JgCef^)-}tyvFf|cYSdRfzq+LD}7RjRYE-|anE{jn?kzKMkj z9E1gzMPR<8hXbZxk9dfxaiK*>#8eUC@>id$IsaGXMpvD`XyD$#jP_M&!51aqMmv@H(eM4clyl!__a@2lSvq6s z2^Pc44*b!6*d5%{Lj`f-w6P|WZ*U^v(-Z^wl-Fa(PPl5Vct(54#Xn5YsxXv~@5Uz7 z{~6ll*I)*+%y+`F8> z+jT)eLl&nlRz{NxZg#~-Q(DaScsYA?IJ`&$i47R|5DC=fdrV=SKW0{(DIN_s^}Qez z8_7?a>yc!Wq_DHb>5}prB{tGW$CTNAHg>r!D!%%M$?9%Rz zd1}(0e?dCj(2i84%*p?6vV@0fDf*C6C_z(f5S~<^3PBe?ZdyM7MZc1uJZRlz;!(Y! zd8+8c!IX$yjGkvLe$<=1)&V8jN7k~)Isd4~8%!ec_twV91OZE}M|C1>%ed6=Q_HFf z#i_U@B-0HSkQD->&sQ7K!xFiDw?nu9$M7{+<93{V7*pcfbHE19AE87x)M(Hu7Rg+R zl6wN_a#YPgGc%+wUy7J3F`FkSMZZ<~^{cBdQoK#mP5InGeOfQF^giPMZ{3ayrTvd zrM>S`K?H-zGf!Q~`^wX@zLr8aYcNxO8KB3%u7<&+R0h}WL-D^E?JmT>;8RX&aq0U# zhZi^~vG4%EIXCT*Kv_~|@pm4hc}g%V^-~O-4L97MLLQKa-ylFl_noG6>J0b%!k3#- z^kEPgf*BrjR<)j|BRWagaqz4pb#dTz5MtRl5>Hs9^xBS(euH_J@ARAYZ?Vm&HHT>t z3ir8wS@xTbB(`kg788tfVC@iz4boA3Q404vH^JXAq4XJvzetv~sndKE^;qHzD1(o! zi<>89>Im*f(Sj}JSKHU`-@P^4S^`fZ$wcZ98-FRfB;&+P1dUV;<=pf2e2%QC{Dmst z>Q6;=bKZKfU3Xa^j$Y<+EwFoRT%IuF7b17!q5x&L`G9v7NlmMfiIW`(uESYensb_LY;|j5 ztPpDhNU1YDi&RceHunCP#(%SYV=`UYn+&6olUkE^fiMf3*6(Zh1lCocMj!M!1*>RE z8g*GHLmcY6DMNT7vsVBoh$ws{?;xxfgxTBeATuCA26r-8HmK6#f_UY#ENvY|xcb-# z9GI(q-H}xM6~;o6j$nrypvbAvhi!se8vih6iwT~8^4aQsbfc2;v^yefZZ=gtW|P5` zLF+J8USkl3*>}!;v}2Hdf#ch7Hk0Z>!&I>Ndw?g@k6b z#MbmlO?TY&44$W8I$(3E{&=ntTiKMY+6t~*S~NSf8Pdw>uSx2YLBVbrtNF4LPGF{= zLht=K2qS$Z@XZX391|kiR2};VIm5$SA0b&#k-HZFKUjvXs>6Fdu;=pCLiF!zGFr{X zlcv|TnoVmNBCs=7@^Sf^yRAF&zRkuFz| z52upALQC+fL$0s@U}$SC($8PaL5FGH`IN!7x6Kpno-p_@GpN}nY}AJ1ZGo)o^%4CGC z!)T95i5f#Usc-@0EWs?6L?;=@@(AK%Q!~ahL5W&@`%S`*_c38@?l(#4;3aDcvO_68 zJBt-m^bV_RyK}#B^ahAyN$*~OU4K8ttINqbD^vS6wmL#@>*)t`?%b(@(L{Y(P8P;q zNNMpCwVXDDa64GjkR)b{($&Ut;-wUSK-@%WdL%S z?31?>2F^ipkQuG|5?)RidRKUna%G%Pr(-5-F69VxrBJH3PIOE%1Mr$T@S0eRj+N+Y zR{Wdms%FzUB9?v}m*i_gKz)vGlyyh5>PvN-0J_wDDxD1D=`~y-$kviQ^}XMj*t?it zGkuwg%bUXAsGuj02koA=Cr7D^3^=gW8tKwK@I5W{60^;8>=4aWzGNk5n+I#1mw znqR)D(j0n)|NK6y#m3J;mkS8xQX)$2ThsA+lOkAoy0jzWQ5>=6%u66k&yiVH$K=)s z+m#&=aN}<*#rk4mRrFKjwnPzH98{kWA?EJPX}cF}h%9BldKsseZNM;(9k6LmBp@ZX zlBK2}i{fcaPi$~HoMfiZsvG$8Tx*K3DKAj(>&xqmfX~^OZZqyVd>Ap{v?`rhuJ=p9 znAl`XFsjKzU~}R|KFbxKb9{LF8*=1EHWm?$z?cleY@=>bG8D$S8_}lxu+lX3tO@Up zPY%C9)~x?cc6~ym+H4UiC~GzkXme94!k&@fuRDic8=2rd@(qhh^LO4~BrM``lx#)l zZ!9Q9V=+A6h_BLBOO^hby(OzUaWqOhBbDhgwgkHn%>wQp#m_T_qKSn=s>R=3j^B;ZGtf>OQ?Xp$-&G?L8GoV+6MM1# zoM0KO@Si%T+AQ3TRg1{z`rZ2I_H~$jYK3tgVMBobY+racy;Y5WF z)zWQ$_`}n`o)3DzI~&;3gVvkpp?2I3xi3uy%~L0ob=lDS`~2QE-j8(^nJN_%E0rXo zEx2TXK%}UlaHm-le3d{UT~JT~xW>DBHHrXEBl=$X-=Sdmm%w0A0+=%5sE@%p?X*(7 zS!Fb!5|8hW8ui2jUbLA_+S@V!Tszt#KdQC|FLEq$!EDH9SS~E&%V0OHWSr`_(clX< ze+*My{qk6dy}D7(BzSTPMr@S+*a&~-4wMad=PF+{qXF-m(pMwB%mdyx4zr8w??XUtk0I0KRy>3Y6g_ zR3z^=G?^snutev$*6p7DKi9dqx)xM2tgNhj(LBW+cXoGo|Azr;WySL{n1Nt$>!_@* zE^jnH?!FSnu;+PA@oT(l3Zy9WHO0J70DBgje!^ zt!Oy&i+GvIta>=A_6U~`xe(l|gMv0kuc0V9F-|KoWq$O&#{fF= z?&oi0#$gMvtr5Q5|JY=ZZdCVx%_1|j&)|;@cai04_=i@_4|NTpD^-yiTjo09M_`-t zFp?S4i~IOb((MRag6@LeS^w!$b5wz}&wwkYx8AqrnzSjz^&E0&g5%W(2-Nj!y75KQ zLcOz6!y~6umW;mUpHtgYdCcZRxw(iN<8n$|{)=tdTboaWxtblhkeO~TM?pqKMgMa% ztk1_kj5c#zQ*ax1#P)bi0k-0A!GOb?|M410F|+bekvT3b3H%!;;q8Gd%cIV|DCiq^ z0mow9>26fL5lsmZXs()wR594)=efG;va1gP9!0mL1H27h01Gn?&H9p@lrw9eMf7sW z$#8py;NXGoWVbNlHoXjG{SzLn72%4i?$o4kM+W^~87JR>TY>%TFYR z0yxLyp5LBzO6k(Uj`KaQw0GmWM$s`zCB>`W1ak9VAz5( z;v(uB9x~&3qvvbm(&jTEF(LWps8u|n@b`U2JivngS zxUY~im0Y1^a{o=OvolN6EclT4%)@>~z{WZXV{Jp$>z>-}x%6N5FA=Rg5V0~O-))FO?Z$RGHOumy3hv>|({U0| zN!Vey-5kxsX(EeXUS{`+vgv0G%lsYdI#r#mzAG8yOl0xX5&1Q4aW9Hq^DfB|=pmF@ zPC`U@r#NBo*sR{@{7h-X3s-+#v8SP&N))0@7_&f3mjOfcJjNTkafIpE@eqS-v(}KY zp==7B9QRI~vYcxydfSEpMV4X-d{58P(qjFT|`jtGC2W=`P|9 zs=t;Le%fK=<)zC8&ia4MlN%W})m~J4J%c^yKD4R&a?PI=+@bw?^9-JhFp+mQM1no$ zZOUG-w>27>)e~LxP_GHd?We*~g4DNW9Etlji#hA;;Vxvm5dhwZ%ATJ@nL@a%+@9hd z_hb~u07dxpFX04CiU@nmFR-Wk?O};^mXBGsjMzuvtIoq1hGeR(>Q=*5a6SVydS!^y@%*RvaCpE#onNx_;mr42jBz=nkWyQH4aIo?m~;+-j_eqw?q z=7P9X-K*=etxJ;$UZI{3w)%UfTmGOX-)oMmF6VfDYI!z{Aw0I_8TkD@$t31q&A<;Q4 z3d|l!qGlJb$Sf6cT{U7{p0zCmHpO*q8377nYFJ#8O4Iqv7TxRO!W%Blq()~Qcpv%QGH$JdTG`T4X+p3uQQ6T|FOGykOI7;ibMK+gwdfB zBMcqbpsM|!cPnW^uvIz?0QXzwl^>HC<4Z7A1A$&yg&|2yx5~UR?8;j|hqj$>?3JGW z#QZY&g|@5A;nZ z)zF-2d5@eHZcN}Y{+bDz8|lis)Y=MJa)MS0`_pkNMK4l^dA`~=Ce81Gqu#!H7nZXt z`mV<8A@j-ey4iJ|-oAWuXwG(a&RnTy8c%?-U%Hn2`xR!555s<3`yNL$2Y36;q7c> zcQ&fOFZUltF$SJBz`(Czu7_i|5;KpDi=n#<$HG4rUtOeJ9xM;M=m=4OUtDY0gN{mj zgl4EnZz5l;fjs`rqwNDv4F3zul!%=aE3n6(6w5LmIzYCu?%Dn${}-bUtLHMd#irrH z`uYZ$?H=+N#4@-^KKBIpYjY^eP%g33AxM#f!~+B!iH4Z9ITj&Lx}Hk4OQOCY7=Yz{ zv{9U!RLIt*V>=LHc+&*yNeDv!%GEJlRLooFJt}$mC!jB4-0{sdJK;gxu!p>L+&}x^rjN|(^Eh!0PqUg}0Z7R3*e+49@%P2{90BjOo|G1q>+PO< z9nA9p##qZMi?s+nig5Y<&(Yt#rpK$LX=bHrVIaA3$Z^3pBBA`AxA?Bg?ve&4T~P;B zVfjkdk@kgCo3g3{xw7Me)Uo@+E+dI7C!o9)O>e6AV6f%;^RKs$o8Rk$&<5a}L`XD9 zghUpKy6kT1pn3gZk$3_0(q?9N!eU9?TFC>Qfv36OZPhbCQTspSwnVr-QM=>fX8rTo zo(#Swa~F>xQFnC0PcD<5I^D_i#C`6Z(gfivv|R&q!^sGkrW`K&{DPQqnX1n%s4Qad!A2@R$RdH#SC+un`p}KBzg-P2ZIoC{xY7dVnUxBOG6-k}ptS^x7|M^%s4HKcBe6gg)<-y3%|<{bU3j6AHimcg zs+g*_*KO4(Q8ubJI0EM17wFsI%0So#=ptauJIq6z1UlS`*BoxGictolDO=6;4desp z4G)9lDjz@`iSDsLu&qSC z%3aC$ctHV?q^*PrONabMnP<6mhk&)c?)rRsemO4U8hGI#ynLhM!ripOf_GzVb#Rr| z?yJ~Q5KyY}LbVm%em{r2?O7_&#S&DL*h17vCwXXGPlbd4;%L=8dWu%$suwO=E> z-B1P=zQ^U?apI%&CeTno^(tNA(YysL1&H<#4+%mW6}x;FKTOI8?Zw-t)Lda>zk&(n zR^_oKoLk-3X7mFw6j9X|(wK}gs7w;J@h&u86mlmdir42ej67TKMUPsjm`Pken*P*j zExUOVpkK>=H?e>4O^|TOHXpA16x3#!9a3( zw%&*n!w7014FZT&H{ISpqii&)cRjVIXVmS^#r1eE?CUVJ&eeJW5;wmvq$*aG#<71` zIDLFB(DNkjDcp4Q4%{Kw2mCwC(aazP^#&3z{t-(&gLTv8-Bs z<<_GF@=_BfkjtF@#{uzQpo>*g#?1@&hQ!O!H5{T2rzroo1ZTrV?rSi+1a>Lqa1B%b za5g_B{w^UvAl9E1tjS#t6R-JxAn7iw!)5j}zqK)E*-Z*7z#9A8k6stxtSd6Tr?)~b zIi+Qx&B*SiooP5~I$;4>)A*vpyOG~B*nC`MAx(i92-{2y!b2)hZ+uNk4qD-@t9`h| z-1X!a*(S~9an&gA7@v1sLVl!2wNlyHXIz5h?9)@nWj73dc+Jsl1&Q2qogrJpAM_y8M0q^J14rOJ zSI2$Z;~JV%scC(8q|i7`M=d!VZ21{sqXE=cM%(n+v4B9!nqt)H@t4RzW$6 zR%!)K25N75xqbZW>L{Pqc#Uv9KQ!C#K;`KhcAlSqOO+t5nZ(WW4}{fRb;;yO5j%zS z{A{}gMdh(2NV`eNJ<93D*@FX3_001>u5pvd*cY6s*YwY1 zfn@knl;^tujTF)%JK>Gl-?-L_oXp)=TieEox-VYmX$HJ4+fYquc1BlK%%+*h zC(YMPa4mp-|d{^*JXR`RfbeeGzizJ{e{*4l0??iq7=K-%cnF9|GGe-`R7!+2OBn z;mKOynGnSv88aRMN&Ncz_xsXG-Ok0RWMq9Yh_vl>?J6b0)qZGJarW6+l>x-)7T<)r zLp;Lju+R0|07~&W*J{Xqh82@#?d>bh6T<&YSyDOgm+-XGv75=*PL^(=x3kR4h~nA| z;MwX%2&^eO71?;lJn%>6aU|S!PXzGiD=@UdnJgivH9Y#lo&#Hk9nN-+iZpHSl$~EgHjg?jqmSUJ?fVQHrXU1gXo=8i32cC->xn6bz{KYe~^! zQqs%@n+Ivp_mVuCZ6L#`O94WV-n_t_jx1qAuCn)#rmgrTLi={=apwrfn514XdG4?8)*SL?-~(Ouv09j6Ym5N=fCkaDGv1$~ zgGqm@>G>cRYVI{6*0vBf77Bz1b6?bzCYO3}EAT`T?(vKZ8f596a9_6D0D{ewLoT;5 znch30PR9w8upcicN1vi(7-pH+cy@ugUbYBmf18oe$!gD|umjW$(Cgyl23f-wql|El zzb99X`N>(KNr&xJ+{h0oevUxhP`tPHYU?YPs}!q~lhc+j&*RLH-8nHL`HPH$_h}KxLJPJQ^DpWK zYq;XaMcAr63Tjz(hVSwsUj{jM8n>|soo);(She8n>z?~Oi&Yb2vRF^m;T&=AtKe{U zwO^zEWQ%yrJ>p$QNfvr2A+3*T%(mx@yQORV2s%&IqC7C)C>ib$LLOWF;Cx{5i6J{5 z41Ax;{_b>hv>WQxK4#+~{_-S9+`>3P#XO}W-I)bpXt3<>93MUPPuTka=@lYjlU)h$ zX=qDs0%EC6B~sCP%6B=|lWbCtufC+kP-A++R8l_dTXnsJ~1 zw0V`&QB!PJLC3mF!rHEPG0z@ot&W1Scbw-9;NsWa?z1^FVMZddEuZHKDGqcmv$@65 z)dJo%PQrLFbKqgdA_Xh{^Qo|IrZ$+|^6Md(M zCJ;qMus$jyI9y@ekzq*h=OB4mdAar3@m?>;UP-AthTyp`TA1CQkOREsQ$k%zXudRn zw_siq$Q9a6`De$5dwjuu|1F!6D@vD$NV(`Jzs}5n9UKIbKerCDqrX^*63w}YUmUue z)70m$$UZU3gSml*y+oHF4Q*{cK0doXjncvgTfS`&`Cz{PU~5E63v-f2`CokovUW>^ s2O7PNmL{PBp4VNRB0)3Wf&N^Z?C_v-^0H?)d%Y$ zVPHPNNQ;Yn^T<3}_B7Bj&3$=+ruhz1rkT{7N>Ap0ZOI3OBsU0KYHA_9A#cKJMpFNB zMd$TY4BdeDdZMEX{1vu=^qx^vb7&&zr#w$`__0|2r_K z-qC&hJK{dmDu(}?CN3Qy^KTNR4AQrMlgO2ne`5Tb6&{Z`hV1+0KWqHN|8K7jvatYB z;TXS_G3J$YBsE|*037;2acUgFZQjoz>a#yO7?0)SQ||Dc)tnFHQ=f9-zNTs{cUVxdeaQe(L;typio8L4PYJhne{M zLd0Lm3^a2I2OPK@6ffT}#Y zs!`JrL2C*7NRLx}8$!ikJ#5w;{B6PACbxtP$9|AQ&=ER~^?<@R)7~AgzPdFM?OoLO zW{btE?;BH=(x0%dVoE$;pn1`Ax3)DnwNHK%bG0em2>ctvve0eTY=&8{4-m<%2zwPL z(v`R`+v$d+j!Q|TvX5p3wO`K)LH2M|eYYGSc!sUW<3^Cv^h_7w6K(T2l*j+F3{PX+=UeJCFW|qElyG-Q zyG~FR$`Uxo%U5m43=}#zafJxyQ;R>{yD~Ju@5zxssMLo|f|C!>tm!9Z6rTp%b9(c7R7JZ<55v-bA3=tHd)j_j+9w_P?${5 zete5gV(@a}RhDcSMX*C5Sdn4}v+y3ivD)$hFBC0X>bVMrm~;AQxj7xz{}NZmNm)7) zcCuo+?Xf3;zg-|UadGv^fFscT{r?Usp8na7Z!1KKSjtGtmdpM{(KYq#lqbi1x>&%Qwm~FJKE%2=o zm*uWO;o`2}b5jhX0<+Pve@xG!l06ks;}@?`egAFmN8eNSvN;C| zig>=W6OF;kA>!LeGj{K1ogG;S_3Vu7!%e~C{Rx7Hmr-lb%w9f zR5piThADARROn}eddR20cAbq>V)ZF;zOqd5y;Vuk-noi?XGGs_!&$*Bk;aHYaL`-6 z*1hgzQd$Xq)Qka>tWaH4Pw2`Cn<9b zKFwmOIvpUE#FfbWeEf*gNRSp?`WlZw=+i=XLsY0PTs0er)~DJK_TQg z&mB<o>Jx)z5tcZ$H{BWuur2K1p z7vpX#xCJb5JR4!s5K3+#*qqHdckwh9d^Mw`S9}5INOX&fk_8ISo%9^ItW~9>+p@Ph zG!bjqemIAIL~2(c7A3nU|0tRZlY0UqxBTSpU=VvXjvMg-G30#+xDI-)G(R0OkJV+8 z%F1hW&SP|*ISJv-HoS=cq4T@RQS)(K-M&@$ zMLh;#hJx%mUZDb!tQk>%+ryvm<*eRdS?-k^4Wle3ql^qoFL(L}JN$@#OA5utxN^c( z(>pYwK}@@ilK3g-34tequd+sTUp6IvTo2Q!wa~@eq!{Vuo2zK5)Cuw{Rjtz9o!zapH zeEJVrnR(}hKCS7{V?0DOn9o4(3Q(^-kH&l6u`u+hh?Lq?*7NkFSj@l(C)MvB;NW3$ zhDj~|!4)5Wch*!Zr6B){r7p7ETF-pF8}DYf zdB4IVfhtmeQ~yw4*y{|b4~NRp%RSV_%Z}{j{;u|s z9gF%cUT8q?I<;93sQK_D)_HW~oCjq@`5$r4jDF@G@cle*COrwFV^|Wl#bK*+nwcWUcZO2Ym`X$bq*ht zPCLOI?={#C_S!HF;Pybw*2u%#9RDklLdu@CcWgifgQF?ySb(1PTLK|PDOaQF{Dd^? zzU?<{=RC>@QbHGx^Gd}{#=8!??mG^5Ro~)a6|6`S>^gw`q|ZF+(Xuo+XE;%Y3+g1h z-j~#@^wVM&>-O42b`fSPgK+3eU5|&Mn<}aQ2tThioXb!SHu$sQ3^!?h{&FA{BXA4z zO_w(c`0F^fyOaAfgWY?tLHZbq?Nq2VJ~jKz9M(l;Q-}hNyqT6Up)Q^Q>_nW zQ@QY(ueFKuF5B&e!p2BO-&7yd0x!q>X4qw1W}28^AR&T*LEnxHjq?6qm~7Or1=Oe!#GAN7XzcCzjtfC2<1`#16_NY?{AV2r6|phsIL4Orv`b? z%uvA@oKYV^3-naL$3&tFg&M{=W$EMO6i>HlzT`x86~YWjy+05dV3eR|fQ-g} zyTY($Lx#c3Lz@5e<({6M+L}MScTYdGcEq$Sb&D2;y;`ctcsQW$u`VYMnXzk zT&%G)pQytYw4V}7u}$v9Rb;&?lPvVav+8vZqu7(^Ed;r;G^XXLK%};*;Ms^zkaqNR zNSDKvGx!(V+!e9X(bH3CH`54u+yRWbBHbU6)j))x#gIj>Tx++T z?)K%Y+g6Li6S%TDVwg-|zDfEgL8-+5{kZtQFJ*#1 z2cA{zFu}G?u`wMTA4S3wG-bdn#ER#t3L(Wf3Arg}@TK9CAIyRkp9NbbAxr+!Qvbbj1NUk<0JJMA ziBC9so%;9I;#3HJ9+tC=bw6|3R~>D;YgQK~?=*>Nzi|cdjBSDdgWx5yVjfsy13E`3 zN?FP=@#_;S*%=Qf(X6I}#@GUN_2OlmpMG2J|?cV zmgH@0%bpefP!90z@2vUGsC;zIpAlDF%B@ejIM4U?Hh&ll6qh`ZkRKpogT8P1w2N13 z5&CZ82;T?_|Ku|j0tSg|ai8_&xEpr3Af2b6l8@kxee{Be^Nl|J*ZB!w&#y=BOX#^T z>7UPVE<^ovq(02d>!PFuy@z}BS?7DcdEn{e_kg?G`P9zX9=uOsbCTEEie9x55!t(6 zWylUI{#~yn9dL#a_?Fd}jW_JN*MK_%ZM6}Pnh0rZeokJ2NA^8CP6nKNCW85f$&Oz& zI@qjlNl)ZBnX~LOVOKuF=~_wJ7p#R`0T@;;mJsi~8{qrUk)9qt7Pt?TW7A(GwGjdo zxfxxLU3w7^Vb={{{H;;zVd1pjmO=0`?a)v1a34jy_*(W(t}uVY5cPO0^AOMYW%(Q7 zAK&O5q0yLSAT)BmArm^z`Y5Z0siqQ~J)<{#^5HrAldo@~*l~1hucaV{^27U^+kLD3 ze1tHAe*DeuW5+fH5?)my;9fcX?(Z2oE^fWS^3Dg0$q2SVr@4DyDAw-8`;RA=lM5fa zvCzhFxdM8_X}Ut9^;%Y;k1f)4pH1(Vd)LCd40$ITh!>$SYMGAmvcyji(?G&Xa6|~p zx&wMvH1XAyn}|8hG2`-EdF{@GeSINhw?@L0p%_LCIZ~Lo59Mr<9MmoCI49Yb?om1rJkx^P_8?s_P}#` zy?pm$vzaNKuVxEg*{%NAu3f|&g(utlAas~7OOHYJ&X;A5iG6Ta7~y5R%@6+FwUOL4 zAt)Ov73%=xll7WJ4GdU|+*(K4&g=&m=IMH6If9UcitS0ETa4MuH?cm}%!Q7YTjFD2lx&+sK}e6+lnyGxiW(=t|ckvm9tEzn1BAbu@)qy=vd$ ziNPkL6}U+Hh}M|x5F_u%WIJ7#+}ZtvuD)*N9r;v`mOWvZ z6D!QuV{?qUkgYXv{}@eXep=P`Ku@81Jvd5V&R=L2?|)3H^x5`5I6NF28UnaWa>7^# zm(*8Q`RNNh1PV&TO7&afrIuGynqaY*EIA;(5^*hhjcbs(Mq6!A@{;9}>umJ!kgdUd zyjeQAe2vV+nM-5M6Y1*Kbj-&sNK+EP3`fyG3%qK@j+cEvMK36I9Anycx7a_&c_q|* zZ|vM`sr=@=P%T>z)4)hXVCY3vfs!-!<76Zr0j|O20wvSSqwSJ|DRnUyJ$(z%dD?&m zl5SeYYoSOelsKOkUj-Yw{@eBx{2u>kF{`%?L8x~){zG|&T5a<$RO5@~CFjfNVSKB? z>gAth(*7J(9HVyq|OE;4in06}t zA}t;D$S>(jw5Er1y9t6@%@+F07PbV-c8li{7iW-(Kcm0?oYZrj2xXH^U72sTyE=oR zZJ&A5ZUtdlyw(>}h3{Dcv^q+u4&9c>Zp5pjIaw;*w>`f6)eOQ~5_}=}ZbxL3>-SFx zvwB>aU5N6TX5T+le)74_7uo8Wt2XR1af;6z8(h)Vb7D$^EP0!;QD>{nGSk98us-31bJSX&vorXc zV@9X=Bq=QWq0XWn=XDeS<&v^cq9~g^)f`VwdWtMVaN0Ti$oY%0cp8x40shHvZ?OG z$#UMbi?v}nk87M8FmR;rHmQ}p20z#6!jgad4$puH9w2ZP;MU0qF;DC&WVD~uZBHqI zkmX+;nU1he71G=zI zDt^z|(#&YN-!?GdX7`}fFws(v?-=dPjYnnA$sI0~&#f#-EKaA4RfEuK1)`TWWOXD7 zu_T@B(1JqI`=FvU1(U!yV~$#E+-gD60`?uJ>oXoBI=;EfR<>kYT2Sb?2gS6Fe`$o8 zGoqMXI+&AcEV(sSE>>+a)#H15wPinphl3HmSd`g;o;|4Ehcr6j!eZ6yd+_jJ{x0Rl z+;)Ez$NE5f;Ghb#p^Ouic4p=INo8_%1&aM=zky24jbDYW__*hY{V~E(E<&An4e{0`@Opd z{a>6l=i`1?g&{7qnV@tAhu2cGljUYWLWvppRGWG6f%fhEze3?aR*SGV0( ziL=1jOeOPxyn{KzwGDhAlr%|{IrJm`O^vfw5oPqmevni_`s}F3IcMHC+MK2Y({NP60(+>C(^7W`F&v`N26NGQKU9-NKvz@!T?slsI;TnYJ3PIC2*r0EVxWphW;Q8|2}nI_B?Z;>rSf|}S~R0#<0&pI*bFCZRT)|q zE86I`t@A6yWYd-gyvjcMfUX-SE?Zi&tzEVOh{N}fKt@n1V!QoEi{t!3f9les&X;Bz zi$Jkb>BJv#IFi4hvO^(T#xh~z^2-gjS(8$h^OB~LXpmGJBxP7IY%_Zk6)yQmsYbK= zEPma)_w`u~ej|Qsb0KH|^ocPNF(7ZyISf11y zT*nwKF&f|PG6K1$+aard9Y1DCp5O|*5pF%ugyFMOd%(CUW+-4uA5r9BElXRtcrjtr z((Gqm<_?D~Loa%shylc_@k!LCqtu!WX^xDltTOpidYr~V*>ux)8FUv#B@iPQE2bcY zOs{Zd3e&I2XO*bPx0A0?M5_Wo*QPc_oz79cz5V%tOeG{f3}D7Gb*yi8#^V)wp-%K?a6xTrW_ z!66Jv;#q6RMiZZC+I_l#lC`6A)9Dx6vIMo)_Qnhb3(N2`*`rjOYh5QGifeXya5ot6 zBWCUot;h@XJuQ<38VWHcJ!rl(+FuM1M%$F06g1KxMp|<@uRxnfP5xQLz&^?_imE+L z+;yzeONmctO4Q~G{;9yT-7S;x)NPWBR)dl%T<-9*KHA4{qWoMg{I)^LyR|XZRoR`F zTL~EuZi2UqNC=pIz}4Qs7MSCpiOK0phV-31O`nf4=50>w#DpFWgI4cKPbux-P@g*_ z`A_z5Rd>ILhgj|R8)p&rCzFYWw*!#K0zZFtX2ylzD-(wfcNk%LF(sI8cA!>zVL8)} z#nL#LXy3_0^)9gOydT|UP&dz<1%c{9QQT-k4=$;b;Z%$XI?lbUjeIvB4oY)N7@|rk z(i@RtKWDbOaWoHU)@0hN)S!Ao`a3>Be=TF=5mny=jlRS!Pjy zlDVfD(d_%m&JT}&PMcn4C@(Ze7rvZc3{b4A5WT=f3H^;@dCS=!MlWkk>xB&k=QD7e z))BDZj{0b9@UaT1^mDCQp@vnYLkA?AuWFCffs+M|za=#@(k9Mff<*5q*hD zuZe>zXXJ44kaE5@T7{CYdivm((xoHz6mE`$6;K{Ca-F^(TY`5asU};TB#&@PTWz zvLb)cWg}Xve|A{b#|@1YF>R`?IcJ?hSz5}0Bs+RPzZDb((q9%g)g_EeCnlO}k2I%9 z_$*($?uzq6a}3CB51?;I3x`rCEVPGHMXs*JrMOKPMmQ|B<*)bdkaW+{p4J$zGBunY z1UHzy0dQTaX(3kQ>rIS)F33L6$u5gCSG4P_$3)rWu&vb!%a1aUf{^UZk3iami-1zg zhmZUI*;~vn8s5W^g$m#>p$ETnG;;dVNUVOo8QYMRPvYt7mwl%%f0+HR*t97e9y3NE z22t*ulX{cAC&{@e1W6)xegu}ZfFG|`Q!;QSl`E68dT-_JP=kiwF&j&8@`TVm&yJ44| z%h;wn#sEXFZ86`rw*ez-xCat-yq(o23hq(Ng1)?%Y_;K|cp}M`#A3)xJ$*#H zre;w;0ycls^FIKw8TRdda_&)E?~Gtk@tkYem_#%Fsxn2lCVfB@(#HW76bD*CS>maq zyX^3uPC9B0ov%;LF@5C(u>5_vC_)Q2YU^`M%*r}dvW7kh&>Z>0Z);IZkwCMWChJBb z))`E?QH}RC8)B!09$>d=4J}GRv^szGlsxnCw)>%%YgiaCvN&Nw6!f;Vgj`J9Ng$Q5 zES2ATDmO#t0+u{%v>i4awq2%emyx7rwX!UC85XA_)U@1~=t)n{G@B;AWA;(n@#h7* zY-Yn;GXj^$bT(=_Gc3o`oE{18Dk`gz?nZplwC$-@=`j(xYj~QvuT6CVGZecz*Ebn-(QsqE~9lpx)3q&t|!n#?TEDjl5sDuBo|idq{bB3F`jKWwF*h~X0f*DK z%91P_OAHv9N>Q&m53zEpl*+9xjDX{W&t76(a_N^1?bocz_??CaL}kw!O0I40NG^eh zBhknk-b`2IxEA_pUS$w_?cdVB!M=*4=I5^IG#*$}h6Ut_6Re%>4S5 zIrrK3RWtg={Y@S@l@`-`=Cms}YiOyq zG#;*rbEy!Bk<@=igCOTry5g%I|im zmd(}03fVKSTN^aJEd=gNH#-1N^dnYyVxS^=!AML>>n)*wy3Y{ z?4Q~h-RhI>w5$s{K|JFAQ+W!&Ta-;uHKU~zid{%1~a(a&sR7Y?2!2j zKT?g&2}zHm;-t1^f%w>`Q&1IP)b6P}Hn6WC_H0fc=d4v#O-Iarb93GeBNO!UFZDcd zXHcf!DX6Tc2g&4hX8Mhyif55)WQ#2TdAosJBgH#9#DkzsS6p0XV%{Fz#!4{|R=<9~ zMz5TSDc}m2R~eU8>G^6m_<=3cfD5L@qSE@O(^m=zD}~gP;*_TWWII=oN9s$)yA19W zR*H%6dQC{zFS5U}89C|FJGB4mOv0@U(B#tnm&e{(ea+DSwa&2rGx^;A&n;8`qf@2% zwQs1m)k2SvbCV=8U2a| zc%TX~Nqm4B(++y4rtG^h_hITt`j|}XPRQesGp)R%_;im{ewuD%N|m)fAm;FNjV&ht zOf;Q~MqKI18JV*>663|3;=gGXfeL4R1^ic6xf^S;fK%lmDl9FHJUOxR^7ej>hW^$; zjk?wy)|{HF7LV~j$Ta5k7;j!+-P*L}ba_IDX+!c!YUlNJB_BH6ZF5yj^77g{IVl8zfGaC{fnA^Cq~5~R&dYxK@ae;QB2+c5jN>H) z`U`wPQ>4od&Ws7;nC0qgO&ms#=+h@VDrXQjt6ASMN)D{cah~DjWg;Wr@2iYclbxe= z6gHH-LvrPM`Uw0Cp3H3N;kyZcRw{vPN|e;SWNNJv8RZ99#&@2Hg<=))14gFtw<|@WO^J|A1o`L}(zkVoR0u@=;NZZ*)|QHwH!U#{%gD&6YThOoZ20IWG%_;6!NoPPxcF5@ z25E3`P=g^E_Pr{N6AdUXJyCim0A5Rs%nPBd$5^~9HLNQ`btJ%mJImGdXbB3x>gjB|+PvpyKV_TIC%{DbI z)99y)ht61IFQ1R6O!L1(6>*YQWj@)j3wRKzVT_uu{zEF1?~!zhuMA8{Uti%>ZS(Vk zQ&Us(L?eXEk)+{ zk<@{rbImPunNKTv;EEtQ8$JHe{Z72WF~j2gFMNZgCHc35R5r!w(&>kDPJ!Z|jTbN8 z`&N4}6I$uC%xA1$ zxw!#y8C=!QyYlJj=~WsGTU%Q!ZbuqU&d%o^{5(Wx@$vCz4^J-c?m1v#*Wq7SzRTin zf|6CI*lzO}(hl>8S$WDUtAjWNJbIK4@#qit@81Po!Nlc}YO!dS&FP*!V|q|~X&qY7 zt_sh_DIl>+4J-Vf?$2dzInrRXBr7nR+;x*h@`>l|E zn=Sb^U>Yk|CaK5Bx%1GONBB8a+-VWz+G$=T^P9Sf>6w9N83gctr)&%CT=hJV_0G7F z{kgMZ7Xt{}p2hJXr(wgjG&SZl7M15D6m6?p7y7A}h@9wZasi`z29qBhR^_iWw;o$9 zNK6smzR_U7VMrFkud1w!y|{4V0{|4}++UubrlzN1f!W1Q%{sxa?Qi$@@^es~3tcZ{ zb@{Jkou}9&x7S_^fYCz&fAh}?JyRYsg$zbr)(=Jed%zMTEA*L*nX$n{lSOHslP+fZ z*H-T;#8!)a?GeHug51W0fqTj3mk0kf^OpsgJaD8yYw)1h>aQCEMr_sZo#`_p{@c&i z{(snqZWLVuwCMj5ShgQb5%?uil%hO7d#+WII7wmR_GKD3rDA z32`bQ<<+HuWPiZ{F-@Tjp^5}MuvtQw%9;tC^EGMerZ?Xjr)%9*dGJ6=Is8o$CX~7h$ z0IxQ|i5u>*mCm+0A|#)F##Z3^@Tbx%WxLkK6tZk6PX6BM(@kxEVFK^H@o*Mq{|%au zZGM~*PrT)3jWo<~octrPA747p?4}DVD+eQYb5=vh=Lls{6Zy1&`Q$H}pR&YDvupphM8(CzgLzkR@XeSF=SP## zZ&BpyUdhDv_O?g6-m6n#N{M`>7Y#P^-7T(%MI|NVAKn|_!N2;PC<4xiI10)5q@*ve zrd3=V9vTY&irv!E(%~g&udgSjq~x4GyR~KwCeY-7zp%jTQBFm6da-9fE4S-AZ9s*b zk){6U`a0X}4%tBrbbqCPq2#P2i3aa>=T{kY1-?4Y5V$N3 z#uwC1A16k7fF#@gf>I)N&@s5aBJ?jT4*>hVu!^}-;w2>|tvfXj3=VeLHNuU(@&*<> z{(FX`S5jzJYsi&>7$REN*jQ`3$aQgfd4A`UDmz{d9v>ffoOs8w5<6(py?dFJv4}F7 zB9;21Gijzm&x?Y~1`YST8ja}}&fkr~GSzW=QC^kn)uP+()wKJMZH{J#-44Tv?HqlteJAO?!pj$b%WcU$6VI znMa2s0Ey=wCD9PCuCDGwxcDmyYn0FA1<+w3jZaPnt)9NRqRq>@u*k><;aZiyw?j@& zSW(zoO`27ybMft*h9ptDWzsml38ca zFe|>t69VnxL`d8ZVXbTgb4kXG*}L;3lek2T$kx@_)`KBSOWQnlM}~KLRoNg;0eMY3 z%D2x}ZbX)nhDheiL;W{Hb3|>w?<}>@8I!y%Y;G|B@N4EszzDel8pfyv`bwwFa;g58alt+2>r`_ffBg`a8nmyW*IA}`OTzatxW(I0KV9t+5X^IsXZF6|@eJ;Dfex z*>`C6Qla~0TH+pv=30|_Co}J=ckXQ@zk{-j8&aLybgZgKE>?GDVYU|eACE4*Z2K#w z?e(!_py>+-v$pb^=)I_PJPe-euPNC3Y>!bUy?8ZWA8w(T9r9TdLkjN=Q>C1~0NFF$+GKnqdn+MVNcu zxchJI3jiw$7PKE&Y}|-Q0BWTO5j&SpqgqAYt=YD_cdI9pdZ z*%g(7d#ATBNtE|pYytLyet?30 z9UXVlx!;g4uO&3N(e>v8P94|fl)Ig)m$emP?zkXi&oe@A*4UhZve!-=U>+7RcFLr=@?w@jVn$yt%v`4t9S zVqYa$Cv4#Y#mNDl+g+V!GYd{PKZ0ot*)B=b`v=}~I})27X*8#qXYa2^0C!lAo&@23 zBKSY}B@0{_mq;#+oJ}}JUC)en_~XYudJMgcu6XwMt7dt=c!O~3@u!t4lTEO-nVJZf zs#wt&6S-lz5D}%NL~Fi&8Vq$$V36h#o-+vuPF`d9(FUtx8^zkR9^)NnDxGX{EjSTX z2z_`a!_OZtY7VB%d3aJuZyx2{y%TtSWV7WzVD( z0~5{jspJBqlhNh-6n-zaW>)YzJl}f)c^O(RC6|;bf2zwHaMMqS(OB%BjS4_jRe>?^$ip-$Mx-J*V zgxR?NOnX*2Jp*3@_Zqze_>p!PHX)?txl$iOsYeXmiVgOUtu@>qY%WCg#4q*qJR68L z9chutpN{)nFct-Opq1CZ97*zOnc+2W*iIhDk&uc_`)Q7eLYNxDT!n7AW=;Bkl;QWE zj4kq28`2YUotl8N;ZtP+vE)k<1njdbzYppQuy|=ycHS@GO{T2wCUHD54=}eB-SS$vqgpRPCfRR!XW+^59V!XxzWs$jqJJ`=7m%gH>>t3 z*?EjTyS_d+O>8-{$cBpD3?TzOU}$KMp95Q$m(UU~*%+kKJ1&5^h)2rH=85GvI7pen zR3^F?9uJK-Ey-UrELf!$UBVkh^87IJ;Nh8oAo(JFmSfT%-sP{l^h`0sAV-sXN1^9` zi%o~H#34{(^xF~OzLc#Hv3&(P=1%kZp(di27{AX;Ju$P~XLNIZzvIS7IJ)6JSLBY~ zC&{ZyoKNYTUj@?z+ARJ^;ke%bRD;#A~G!Y#<7bOf~Ir~Bxtg@3t6?z)Ui z%S>O$!Y3>C@mO9|Y_m55M5w*kHGa2^Fso>>(qB5-(f|BMZTLIi!a$oh$!4Du@($za zW#6T}^B?lv&Qs2f`}ti>Udd?a-mRm{mwKEll${4Tu+K^Ah&qYP)>Ww*%4Gi`Zp_)k z>?gU#pdE;sJeQBwYK9qJ|J<(%@#63<3pPUnu3V&|@`2st_(ussw@AWRu24!{hH6+E zqfa>PGO_%BguBO}Fyft=w3QD!MfPt=mpQ;v$z{n0f1KNHIwETlM~=!}#uo^4g&Jp- zeH{?|z5EbHgkk!KQcyTZx5ps3MRcA~*k5uMJggf-0UhnBS1Yk|O`fw`ms|PwPmX7R zkJc+2nC*jH;0=vn29^h_q86t6kk^LU@5hE@{JBjj7~W zq`M7_L`8t!K8kY_2%YK7@HeA?@BPx3kZYnNhYfkUU%y!5Z00TXJfB#S%5il3=#!JZ z&`yhTCpY^M!ahE8g%Ocaej+U@yzoJYHsco5=FaM0F`h)ItlhOiAm;j*1D3Tv_Jdr# zb6oV^D=OKZ8aKNaf3GX9ieN)hLU=FD#86l#9NXFu3YQT(-eVxT&)1M<%vsN|kDRK> z7fpm#yE%Z5HhnGWp(V783YvTF*7Mr982nuR^VjEaJadHB+0(5|@a3T3VfAsu+wN?F z6-WVZHQrIHr==ug^fH*+1o^!vM|c`7C1v3U(hPAoOFBmx-W|j1qR-5~y61jp3-sUa zi4)#LmPz_AlR=2)y9}LD)%X&Sf(Ub#MO9Zp3Ir>D*rvVTiU1a;?&JImdq0=^oR7Q; zU`^dVhG1i3Q8hcd5t%$e%rdjPlJQMvO>&#>dF+pQfT}1ToEjCM9632%mr;I?J)au- zBR8GhOgp(umS!F)ld)qfrxF4erXho<{#)O2zB9B2Ms#C2VY%AOc?6fZAs_EbEHI97 zD``7Njr6yKPEGVwkCf?m!Y*AMn~;6P z*h?IA<>os@aP@{fW9%w_75B%eU`Z}=4l254ZB5Hb79U@3IJr%FIU%&VADLEC0R#8h zi&;YU1ogo)L1JDwpu$om-WfmuDif3Y#^r}Pm&p@F%pZgJP_~6JMU)f2j4U8Q5i*XV zl3*56UI=BgOZWfk1u&MRyK8DmF{q2Xva}SZ$CMhC>otiGIkF@e_e=PL0FS(E9(%rW zVx^TS5(vR5aqsM}u3gqZp-N1mHdd^2IyhebrZyjk`%RIxHZg+8V!<)k7^qbx|BC^8 zo-MdT<0EP^HXmiF+vTeymO0$v4Ty2l}a>fKlTq zkCUSWm3n{G@u9{bKeI?|zsPjfnbc_o=ZlWgJM02pEW9HkKT8C2g5$TCn9_qBAM>Or zK@3^J8jKLf%{}t8h#97>hjl?_={~%@pU-3BPok)j-0eLLblfpT9jMV#S4;@}r=SYA`wgN)2)x!E^@J{9sYZBBTnnFt#72U>Pg`}q%ZrAzk% zT=M3iAH2qNv-EUIB?+H36}xt7(aM(1$_Nm2>s>8s#p*O{UDC>VzHw<0Abd_!k@fPy zPQWjW0V?1FN9$56Uk;6sdSnEBo_%j}d~zsukm6C)N*YP>N7TjF+gG;(n%RcE{kzb) zXOyf541WH`b7Pr|T-*kYruR+1k^$rzW2uXrwX?q1+hYZ{iQ6%o3Dk7NBb+!qA|+9u z3b&ZHnuLHFQs?V~`m(S53dJU_MTOw z)ZneU#u6}sW$(B|J*iYApJ^NLRmfZmW=l@%wZyUxrk$o>gnZo{*E)dQv-n<;J-bT3 zsXjiv=&t2#(|h;f&A80<`&PQ1^v*N;ByYaA)P8?`YR2k*2QLgWgQulG zs?3E%-{*{a$FRQ*3gus9S|dD@*PtAqlo(mT%;X`agmwY%tm1^f4XJSv9qpFc!sxRE z^Rx|93spSxtq>{@N=G>QGy@BPBu3{8UxrJRf%~R(Eu>b;BH>hC@cNyXS`{P2YmdN1 z&voufhcahsM2h4h(Xe1^3fY8re99x{cLpf_Z`&ore;Xg>?rtF*mGMObUaWNh{;c#! zd0?5H{Lbd^O?$Pxj(yLLrn2uBV~964N4sbJ<{!QY6aBp2qq^tjZ2O{PJm;ISDM{pW zF&W6kZX_K2{}A_ED}$~>nsv#z|-Y*x(2{p-me>F@OFTbg|C%(<**gv83tEevv(7T^ZM zZ+?Y(-c!y_M`0i&FC%F1*}0g;cQ}RmD$VRvS*r=E&G^hUcxqj-OV_RKj|_ytB!Zqd zb;8MJ=+RmRw{QU0zqVqE* z&RAum-}ZHOU7x?&SQ6MRNvdzE*1n`&IY{XlIB1khi8+lmGj(`E{~YQ-pUeUc{bW4h zOOmiKEpD(uygM*->+Veg0(T&%rp75HQI>VeQ^xi;KOlRwsnCQjs~)6%Em(!5^bSTB zX#&CV=9S+;wrmB!yIDlcdsCjl=&1-A!l@62*d_@zr#0JTR=QH<6;b`kS3!q8@Kt;I zLW>U@oYvK4=l(wCE!|0*r0+*ndqWA97-1mRw8hY8!SRsgN2|e?}Pwb{CYA8h*CcwbSHcvuV9=(CWquZB!AkVRE&55HcT z$prd)8GMxv-q=X5_+;l=Bc<`pG|c5Gs*K=2h;7@$zdV zhWE|pD=pkTq>5%oPSX_Qlc}(*?((9};0KR+VJMvjp;>Q3(N2T3zV#+L({h0@_oQPV zXN+&iQ<+R&K8eJnt#)*NXSY+<;&3JiJ$dzTdm{tF@H;1E%>M*oV&5QLi4WKRg0A`( zn&t?WSC*ONtr|{0SD3O^AG}|VP-k@6XPn-7_>V-^JkzGygv5H zhv0}qcGaPY0eaNF)qOp;*SRj&f=gl&)Ay6^x3xmNrc9ajY2%8rW(}p*GXI5=e2nj- zzXpgs{TmZD=PpJ=(>ys=(Z(~l=@s<;pzf->qLSq=N;aN%Xke9;pb_VYo;JbM>RxZ1 z*W7W~58`yoSTr!E1#jNG&5jj_i7-u$@Pd|t=ne(Pfh?Irfp6DiSm6b3FP%);d|lDj zz$6i?2ABXN4s)jMsJRwrJ@A?DzXqsZmNt0*Ih5yokT9AnR_}LgnZ>78gV)DL-+Hd+ zF0oac{~buSc~PGZ_1Nu>8Ek!;4f@WKR$c{f`+YO`s~&5)HZ_h)O5~;jX0ey3^`7Le z*-nOV-JO%Yk|%Si>-1)a_;@UiUNY79-S*VT``e9V@P4G;^bZ>nRj{0v7W{ZW$3C+=U5DtrSv{lRJKeafJ}^M zPuq@FFq+d!`3SQmz-H!h`Qsr;z)(Ido;VjXLc(5WbOWdvzO@oJw;@wD5UMbb7RELl zV~ja8%Yj1=#kI#haWJ<^3qVx_?U2K)8QiQFu*b*+2?7$o=f2NAe${t&Zj_H3NS=U(U__DmjV$knt{skUPPFy{pjmKi z@cjcc8b5|5K9Y5Eaa`D5kkr=3yNlx!MvLrtoXkN+++Ck`Ulexia9|*?7DvI7&|nF3 zOtN(p8_vzjzA5^JPgggSYg3>m=!R8sm~kjg>Q@KX9d=#UDV8eh-xJsEzCt5^*nzeD_S2|4Bb&i%=38H;AE;w(IKL=nWW&E>!2zw&m?Inb~7 z8j2g++Tt-d6B-x+VHtbVn}c;c?#>ND{#!}m+Kr*qY7GL}V9Mi%`oJh*p&C(YM0A8m z-d87(QC<{2w?Q>zM<3ajW(RI@=`#TlgG^shbFB$MD~Yd=rVXSE@)-d%c>u35lMKB9 z;Xo}}abkKQ`6B6<5&yF@&dq{;%k5s6{n00Kn*$sT0#5bbc-%)gp&E44;iifkd2U-V z9!BE}g^xqVYB!a%>1GL6 z?`S2gr7E9?nmXQxhK!Ptz`8;|D!Nm@LT(=xyDWEv+$Gzb$#L8eg8Up4Q zhtuvvqm=`02J8LX;_JI}O8Rqh%lp|1=x>r>`%&QVk@G;HCllgl{v?5l*y^#zzet!8 ze$#b3h(pE9TeWn7(qY4X?)3WwedCdP7fzG7yUEN}ztI;Sx8L;~;&gN)E3GzzkwenM zQIv3{905fD#u{BFO4br(jh=qBv#0u@>}jE`&VWF?jctZqY%?oBWORw4u(y6&niK%6 zYAtRF5OX4DZ+uX$WEGF8#7{bB5^I*P5jCYcMUaG%;uGoVgz@G5t^0)G94y@K8~dxn79E`Y#0Tes^v^s6TC|lw~k0<-RM^DKj*e2a^$` z_`mhTNtZ~H_A-i1t5qc1xB7UILl8q_n< zTJM&#-vr3>MLfJV?T&1dxpc!PWYn|g>3&E1OSJA}*2sTM_+gZ!dZ-ITZjI)>FQX-A zO#7nn0Y@c?-Mkgfs@Hi3YxUC~`PqF`&ZjvdkQMqwo>VW;plbkrcKJ*6F}u0|vKj(S z%*&D-|HTnPh6dIcLbBOwS*`W zA-;7lDy=x40fX|eNkYptOV8&Z1yc`L&lKl8_ZQL$b&dY@!|2v{PjUsC5G4xHnr9D5 zmPUjPj@itH#eR@eI9@^V88@A0H@`Zx+yisvhJ%aa+wFNt^@kM>G~*=iyWL=>?b|cR z(QSArzT1poIHJW@GY8aBa}Sx3#BdL_I^(LK`n3lnp1@cF3w}(zi*y0N1nk^}b!~$t z`2)wSoJ4_mYH^rxOQDl|GDs+p2lUD#?7m+^Bo>4w=QW-IpE*8Q=ocK<81s0hiXnw3f0LE2G)WToV}@WoHBT< zu~1x?J#g>UO>XtUy0QhGL2EVnK37y(B*3WKGCM=Ju8&<{tECRhq7)_i5KOGy@qXdT)V54L7@WY+iSB%KY;IBJ{#*|e+&g#K2CeK>%8`}-{1wI-RGwkyEQRVbiF)p6s3$oF7!hw z-_e6OO8xOozcsnH&i%UtKLYDHBtWTXP#KXxx1TA9{9%ZcQLilq^4UH)D`{;^VWFt$ zANTi&G^g5bZgDu?<81pI$v%w5UL_veSr)lBLMWrjpC;aX%JDXuk>&S`Cv2K)?+*6Q zth7|scPSu==ZX_nq|LwEz`;WT_I*~sb~JA>N_cs6#Tf+-RPc;s9yH5qgds!RK5gdo5PuM#iQjKgy>kuE2+)V?P*iii z6eMkpHC=+8dc^4GsjaJ~}&g;vZJbl@*c|BY;*JIX<~4n}Yx`w`rp` z?6m&kQ>7I%Q#EEtq)f+Y@Hrq@{6U3Yf^OkB8m{7rmg#=I8g|5crewOf+FY&MnAm)` zd!zMoa@@eS^CrxYGKdE|+t-+F2?GTCz2tNoq-(S4kZi^-Xy$@xB}ROlQ%u8323uPC zD)I(;^ChaZDF*(DIKJ#(T^Y$3R^|AYd>l4SMN=d*0Q%t7S&D&1CUB*&JZYckvg3Yv zoNLMkh}otmL2Gb0%1A~cC^_%Sv-;wY8UZPDT+5cVQG?8L6{vJ7fdj2CjB4SWgR1Gb z?68VYUr9qiNzCT3_M=OnJ4ev9KW_aAhU)`rR6_Z(hm$!k9F2x@y#u!O5pH}Qneqaw zSP@JKOV~UWYkg&sk4t~#5^i9v_7qR6qf<5XnKD@QLpESpHf&9NYQb8|d&6pxg^`*T z5Ps}tgt&E7B#&Q0&XjZi^yt7;>CY8(J4dKP8$|(Q>H^^8h;#0#33+ite ziqk`d>!(^Z=trL)WUq|{P$iZ6Bjl_SkX?i4)ba8dz8`WL0#l@ao-;1r;>r+PTZiSDySbOl2a;K?XSkhdJ+&CFRO09BpV=_HjYWzz`+ZgFa3m&)K z+JJ&)HVmedmZ?#RXhqrRNagWdXe^cg8@2UPgV%-jBFkS2#mmC_dO{vbAl$1gd5y9z z`hB_U%0#!qoQlRzvjTA7*k4W;!B^3i z>3-+fo7xy)m$^1+Q8YC-OZ+DV0Gje->ilUMRB7u0?~1;<65D+VXRq}mUL#jb1ho2_ zKlV5sjN`~N_NtoJTLth;d0HS=UD2P-nUm3oI0~PotWZjF>4KTTDQ~h;=?UBu@R`Z> zU-Sx$t6H;oN*|R9AT#0g)uK=+n|8LElZ+1GAB=^}wrCdL#5g6+e|mESc$8s6N6E}t zE4weK*)OWF(oU`qD0g{tDRWCi>UDLp>CN4>a&4<6+a$=d-!PN=?wN zG^@l>4#%|Cg!z>jowo*8;?0+;{#ei7`Touh@bd<1>{!(=zQynCndkiVqr|AKwzxGIPy4>30X|Nr{CQV zx0bS5v<-!e46_a$wjC{Nysiiviq0gD31KLNZ%*9-#cg6u*_8#gWD$u-bEA)l3uS!OWk(AN@%(&K*^&WcVzI4x-3?;nj(o6&9`X03DN zwX`ej?~2+Dp-X7K)h7&39eLDpGZe5r$L5|1r4<|sd4~ih< z7VQcdauEq$F^~=r#FBFoVIlwZ%^U^A0ATV>?y~x28YeuGHx#wie@f zI4NsvYE*cdvE)JP%$8+o4~z70q2TVfzc>27|6-w~DH&cqRy-i$MsRm0CsJ>$Yd7b8 zdihd%7jg}r&pZPy?x*CJ5M$)QHNRt%3$0H*|5<0XZGGtjVb|6DaK7n- z66H$csx>CQ;^jC$PR}q+Hk2<$4_9u45zd$yS9s^!pw?7eBJads5-BPqzn4MX;`k%U zQ1vFYhK5TdLu1Er_q1eZ->@YI_r@FMXORiA5buE_mXe$#BMkaFvHDMb^k_+W=&_$B z8tR$Kx)6c#5vrsi>{{PB&;9BARY?_2bWz#&&Uz1Hmh=y)|Aou-1P&?DgOR`*Au+=l+%Kmra=JHY6?oKJpdyA;7of)Y^?U9jm6AX8^aAV zci;I_Cm+PZoyl9|cb#d{9-9ur+n*&!=74rG#Twqnb0L6^gp<)Jh^68DF@*8t=yyX( zy6skmav`NFwlZ_%ytF`fzOMwD8pnNv0Hz!uBCv-Fb9BV7Yq?!^nQ}h8pBlcL z`>~}Yq#7BVFu?-Sq-Rhw9WOf2!B;Gs5wc}6w>bBiCqO- zAht=Z;R$d;smpgh;WaqBRHwbC%fsBxqeLdS@A!zdN=Nhh+;{(!^bYD~XR$V&QTZZJ z{*KIt!r01_Faqx>J9<8>H$6^da^H$`NDVe!C^I@tEu@x-S9^W-bP_cnk~b!EI4@1# z3G42X(!jprf(23i_b|bS9BrJBX`yNzUD=Oo_;!OYhFRobsDw)It0Q4NvpqS)bi++q zr}SLf`A`;9QGJ*~gfZsLZ?SqbGeTr)l@T%D8e(an=ibw^7*C=e3X{g;;m0Pr9RV@ZIlH50-h8bL)`M|2!)7V$uZXB~9|NzT zt*4jrx&PQ`-`P2lTsBq}N9L#6lRYrK)~FGoqU}8^dFvhyxM5S$Z357u=UY#=lqkbN z!zx-c71vWcMWbmTJdB#<^M)YYnZnwq+!HG$Xhg+JyScr~-!=qo&BM%}m@?%&A$`8S zc!TaG|MdzOo4m4nwCv_e{Y)hM=F#3q*UQ`!!1tkU%toL>F18I+;7Zr(GFL`<|_I_Xa07eRbeC8YkO>?y8ZRzPMIjw+Jm6 zZE42NNOp5x%?eadw6db(x@HH1n=L(J;|c4G`fh2e4~4I<-|LV80`~N#>?pE#F1)Z% z;<_G0^yEF^>u)rI?Kj1EU?RefJqXiDr48_}z8X(G^?P*OQOA*M9u~t2Z!dLOp6$fp zY&a6cF&yp54ZD)6oJDNnh})6dTMl_rCGouSdyc}BeT2>tH#o4H5r1ti@J@=l&NR9A zh+5{9Ztq_8Ng6n8&M}=RA1{s`q^8Lx^hY0rHOH$Ne-klT^cG^sahaaKUigXM*w@oN zDv6JVP45jDlD;$_qRS{k`S8A8v~~NvjV6q74I;f}evT5AptROiA?nSW829o!kjA5QG1Wh&sNyM5;7Mf#6 zR4cm;0)p;a`3?C`YZVJgrAkphRJ}6jtT2&II+e=iyceGtXONIxHV!Pwckvi**)TuN zBdq&nhYmsBZV@!7WG^9vxNy}X(Ql>PG*(9roslYD_+6G`QESu6mSN3}c!L{T15^3{ zV(t^@1q+I};!HLUX}x`RdpBt)OYsp)i=ZB`G#IgcO+f5D+nX z6|N7TU<-w%Q&&d>)P~*L2b$=-2RA^4%V;!i&8qJN5j|ew-(ATo50~sua#0ahltyGe z!F%BU!2&4JiT}|Wsz61(8KJfPa{aCL)nf8h>>r144{*`u?#Z0}PTT;&oeK`VUm;6k z)ENKS`e9#NKctJBVyQyKXP1&%wj0H_3E}zoBO(Q9MHL)7X2YfN-d!2rMnZoLusu#9 z5O(X2Lnm$|50eyHZdT#U7%hXGrd{NGsR*h$kL`hu9IoRQu}}d)iK9JiYUqZb)0HQV zuq*3QEwg#1JW)Y`iY;5{#?2lxQ)!6wD)bLTo@}^AeoeM`OLP+S2XaWN;&k) zblll~$X-DtHIm=6$zlOD9}-r~`$c#AmM9<3wl1GHXpP7N)7lcJVw4~sj(5?)bP~C} zgx%4Qg_7wViL8clcdtBxqRs z`iJ0a*Z??V6`jd+!j_xvwB7bAeH^x4LFxve)Vo6LHeufpb=&pRHUqPdW?6s0C7zfp>UE$fbQ|9nEDw#G^P74L|ih9&*B zXHZu4Le}|tFPN3phYj}TbPpebRr^Ar-^HHCwE^`jg=$y=>y@u{&(_UmwLkW;K-dd= zP^mMs-Fne!JiI0^PvKedTtLn|E$+FM8I>^#wzVe0w-=cGWCdg43MPV&Kps1Rt-o`} zldPJGPk9g?zHC`xZL+nfo$B-Km00AeO7xC=D}hIAoycnm#-w2 zR0`9$ZlkXcb?abg!;a(1C*B+9tGykh)TreZ-Y3`F((6cME6ZRiXD0pYgNlmkLo1<3 zU5edyR_7mP^uO;Xc_h%MuP6Kr)V zU63_|r}Gh~wFq}okIEYYIh<^wlhX|C7)7!~tWE(fpf1`dB?*ehAEy}*IJ1Xn>~{QpXubTNEN@c+u71ck!?`<58(4Wb{7R1zFd)z7Eq zx~V{x*|=$*)Pj91jgz0ZroZq(Ho=BW`nxY4@slJP%7O;O#c zryHFfkF$GpxJQ^5fU%zGt{xHb`ZUTq!M@ACcB>E6`-H3;y+GWaH$tnYtNu&V0mYvW zb}hoMblxdZGU2lrWzTDAyA77dq?@Gw{U1PmI=~sk+W`3}+WbxN0U}(frpr$!vfYc) z=E_vHNt(a@GbxQOC*dLvU$CzmzWqq?Ql&%2{~IsopuBsNL`p0t+7VG*ZczvwFl`o2 z3t`t$C0zQW_77J^q&$Skv%7L@)b*_Cjy*o-PcW7Hy@n=-k82cdS-}ZbP&9&5`)!|a zoA7_l^066Dqpl_qAH)za55XMB4nqtM0e~egJA*sLzF*Z%pM-=%z-H%bq>pWwS=x}% z9Vr85<>Ca19Q7^Q7Cfj6uM*+f=C~1|@TuI;G>k{e%*8g7I{ROCNM@e#vr)n((x>Oh zSvetj1w#2eM$ttPUGF^I|NH&Pl%pqXXA~hPTjrpM1M~gxq_lZJqHaa8sWN8R4i1W( zyV?IfTV6Fqcb>Gmq^b_yJ}08GXwqa-W@P&^zoj8!3h?!MsZ~!B^hIxn*IQSZoX_J6 zTiH7TO)+q!(V*w#%KqpIwP2YCX1~Dbg3dRxYazP}u{*~DJh#;dJtGJTHIf`p*$5%R zXAv@)S$yDeKS&{%xJYYCYDWHoX(wA@&fy*;l&cg%T(8{RbN~Ld;n4%4^{*-6OZo7_ z880Zri^+4q2gWU9VLFc8;JvBUtbuK~zTdlRtEB62aj(KbxloxLB&MW^I2Bvq25sAw z@dw7;Vtf-v#Ce(gaheG^ct&t?jJWL(#LWV)wnKD_lz$&n76Z{>)Ne$y-G7uWztPWC z5g}1En^25Y$V^8|tsTPR6EQreU@gXZlr_m4_K~d2mUTXFlE{^`FfQH65`*;1n1=j4WeWg%1htx$obf*;PfaYP;}a$N%orh;V7l$_k8ovPYY}gS=d^9uN9fL7#7P zFsI9pRe7^ndHo58EQ&<@K{`d02ZywvoqGaBlI5|Nr)jdKW104^Xmpp+Su=S{>~6OE zZHJLG;ToB9?XmgaYCe_qA%oq=SX_IjU}PKIq3@I$kK zD<}P&$BmA>7J^ayv-gSp%ESxMH*U`Jk#pU^Gn}1jvy>FH4HQSQ-Yuc6J<41Vf|s4N0ST=j`Fk$@>BHE@0QT# zqXR!Vd;@9TcK@fab7D?g%HrjZ*dJlaCxz+n+nqk29ZY7KSePVOM6;zT{G+JH?_Urz7LOl{9rhrhTLD(niE|I9AA)!)S!m)oE3T=4w5MxtUnTV!=U$er!$@p4c~@1&1BFk=_hNY29u-2zKd&_3_7Y zUwX#B)*+A+l5l=%%S&zyx_*J7y6NY_;mghrU>Fvn(rs@{LX8ZA*tyFmP` z-LA=Q8E_&z*!o_no%WrvXU?=`X`^ln$&i^UoR#CIxPdKZtEgRnfx>Sz8jvhRg>i$0 zLptx1xE>C!ST_UJFgic1czn{jwc;KL9Tc4#@#!fb^@0K&b=7|R^uLTUpmd%q9~xUl^b(qCvBNNTc1{XpQ-hH z9q30|{6;fUQEZZ~H{l4^HVwC0G2_GXTgo4-LYl* zfQc0t#2HCn4Q8MxO#rOk>geJ7D`o2z)`gzVhLt53&$Zh{j9~qaZ%Z%8Q`Tmo>lXBj z2v_2b5@6jo3ye1(zMj3Q^jZ~1KaT;OZkYjZG2gaNF3!C#*hw@~`cjv;9XAj9Idi#N zu8PF4;6rhpFG`y!;`grqiCTMVym~)+9(x#?7rI3XgOxmlERh|k z_N=;rO1Vc}{<9a_qn9om6&$R`AZ$}q>V~d#u{Kis{_1%&t78OFruF&57HU${0g31+ zL+VZEy=270cB==DAnm_V2i_OU;%NgJEQc1GIgYbAw(;NF!X(zi%K3Mb30C972_tze zZZ4Cgla-0@bvb@gg0g|-T*~!M%-9ko`?N!t$IXrxJ&-P0?``)3wjlH&?aId}C?hAj ztY6~VZfJWo))^1LPIQbcOU+#A+o9y4&4{|97|gXq`VUKZKIoHug)FhUNx2)&u<~bF zdMkee{xNt*9dBRy3`=bnQIs#V&CL9!M4G&qtSA>j3W=vWR{gNaZdYUb$t=}A^fOg@ zG#(T<@^dkN9K{nNoeO`VagoY6G}0LRG4#Q2u}9p~tZfs@HtEosR-Mx9%3d&WvQuM`F?8jgnjB@P6{aljLa}& zxa|Zoem+>fn_apU(dR>~Ef z-ek`@P?|LGl0l$Bm+hGFvD;E?DzYMiWXwGmLpxJMhl%f#DBS<UfzO%7EIX|Ch%;7-06GLA6!__!a3qBE!A z7}-#QB0d1+LXisDvL=c!svwjU0JgCef^)-}tyvFf|cYSdRfzq+LD}7RjRYE-|anE{jn?kzKMkj z9E1gzMPR<8hXbZxk9dfxaiK*>#8eUC@>id$IsaGXMpvD`XyD$#jP_M&!51aqMmv@H(eM4clyl!__a@2lSvq6s z2^Pc44*b!6*d5%{Lj`f-w6P|WZ*U^v(-Z^wl-Fa(PPl5Vct(54#Xn5YsxXv~@5Uz7 z{~6ll*I)*+%y+`F8> z+jT)eLl&nlRz{NxZg#~-Q(DaScsYA?IJ`&$i47R|5DC=fdrV=SKW0{(DIN_s^}Qez z8_7?a>yc!Wq_DHb>5}prB{tGW$CTNAHg>r!D!%%M$?9%Rz zd1}(0e?dCj(2i84%*p?6vV@0fDf*C6C_z(f5S~<^3PBe?ZdyM7MZc1uJZRlz;!(Y! zd8+8c!IX$yjGkvLe$<=1)&V8jN7k~)Isd4~8%!ec_twV91OZE}M|C1>%ed6=Q_HFf z#i_U@B-0HSkQD->&sQ7K!xFiDw?nu9$M7{+<93{V7*pcfbHE19AE87x)M(Hu7Rg+R zl6wN_a#YPgGc%+wUy7J3F`FkSMZZ<~^{cBdQoK#mP5InGeOfQF^giPMZ{3ayrTvd zrM>S`K?H-zGf!Q~`^wX@zLr8aYcNxO8KB3%u7<&+R0h}WL-D^E?JmT>;8RX&aq0U# zhZi^~vG4%EIXCT*Kv_~|@pm4hc}g%V^-~O-4L97MLLQKa-ylFl_noG6>J0b%!k3#- z^kEPgf*BrjR<)j|BRWagaqz4pb#dTz5MtRl5>Hs9^xBS(euH_J@ARAYZ?Vm&HHT>t z3ir8wS@xTbB(`kg788tfVC@iz4boA3Q404vH^JXAq4XJvzetv~sndKE^;qHzD1(o! zi<>89>Im*f(Sj}JSKHU`-@P^4S^`fZ$wcZ98-FRfB;&+P1dUV;<=pf2e2%QC{Dmst z>Q6;=bKZKfU3Xa^j$Y<+EwFoRT%IuF7b17!q5x&L`G9v7NlmMfiIW`(uESYensb_LY;|j5 ztPpDhNU1YDi&RceHunCP#(%SYV=`UYn+&6olUkE^fiMf3*6(Zh1lCocMj!M!1*>RE z8g*GHLmcY6DMNT7vsVBoh$ws{?;xxfgxTBeATuCA26r-8HmK6#f_UY#ENvY|xcb-# z9GI(q-H}xM6~;o6j$nrypvbAvhi!se8vih6iwT~8^4aQsbfc2;v^yefZZ=gtW|P5` zLF+J8USkl3*>}!;v}2Hdf#ch7Hk0Z>!&I>Ndw?g@k6b z#MbmlO?TY&44$W8I$(3E{&=ntTiKMY+6t~*S~NSf8Pdw>uSx2YLBVbrtNF4LPGF{= zLht=K2qS$Z@XZX391|kiR2};VIm5$SA0b&#k-HZFKUjvXs>6Fdu;=pCLiF!zGFr{X zlcv|TnoVmNBCs=7@^Sf^yRAF&zRkuFz| z52upALQC+fL$0s@U}$SC($8PaL5FGH`IN!7x6Kpno-p_@GpN}nY}AJ1ZGo)o^%4CGC z!)T95i5f#Usc-@0EWs?6L?;=@@(AK%Q!~ahL5W&@`%S`*_c38@?l(#4;3aDcvO_68 zJBt-m^bV_RyK}#B^ahAyN$*~OU4K8ttINqbD^vS6wmL#@>*)t`?%b(@(L{Y(P8P;q zNNMpCwVXDDa64GjkR)b{($&Ut;-wUSK-@%WdL%S z?31?>2F^ipkQuG|5?)RidRKUna%G%Pr(-5-F69VxrBJH3PIOE%1Mr$T@S0eRj+N+Y zR{Wdms%FzUB9?v}m*i_gKz)vGlyyh5>PvN-0J_wDDxD1D=`~y-$kviQ^}XMj*t?it zGkuwg%bUXAsGuj02koA=Cr7D^3^=gW8tKwK@I5W{60^;8>=4aWzGNk5n+I#1mw znqR)D(j0n)|NK6y#m3J;mkS8xQX)$2ThsA+lOkAoy0jzWQ5>=6%u66k&yiVH$K=)s z+m#&=aN}<*#rk4mRrFKjwnPzH98{kWA?EJPX}cF}h%9BldKsseZNM;(9k6LmBp@ZX zlBK2}i{fcaPi$~HoMfiZsvG$8Tx*K3DKAj(>&xqmfX~^OZZqyVd>Ap{v?`rhuJ=p9 znAl`XFsjKzU~}R|KFbxKb9{LF8*=1EHWm?$z?cleY@=>bG8D$S8_}lxu+lX3tO@Up zPY%C9)~x?cc6~ym+H4UiC~GzkXme94!k&@fuRDic8=2rd@(qhh^LO4~BrM``lx#)l zZ!9Q9V=+A6h_BLBOO^hby(OzUaWqOhBbDhgwgkHn%>wQp#m_T_qKSn=s>R=3j^B;ZGtf>OQ?Xp$-&G?L8GoV+6MM1# zoM0KO@Si%T+AQ3TRg1{z`rZ2I_H~$jYK3tgVMBobY+racy;Y5WF z)zWQ$_`}n`o)3DzI~&;3gVvkpp?2I3xi3uy%~L0ob=lDS`~2QE-j8(^nJN_%E0rXo zEx2TXK%}UlaHm-le3d{UT~JT~xW>DBHHrXEBl=$X-=Sdmm%w0A0+=%5sE@%p?X*(7 zS!Fb!5|8hW8ui2jUbLA_+S@V!Tszt#KdQC|FLEq$!EDH9SS~E&%V0OHWSr`_(clX< ze+*My{qk6dy}D7(BzSTPMr@S+*a&~-4wMad=PF+{qXF-m(pMwB%mdyx4zr8w??XUtk0I0KRy>3Y6g_ zR3z^=G?^snutev$*6p7DKi9dqx)xM2tgNhj(LBW+cXoGo|Azr;WySL{n1Nt$>!_@* zE^jnH?!FSnu;+PA@oT(l3Zy9WHO0J70DBgje!^ zt!Oy&i+GvIta>=A_6U~`xe(l|gMv0kuc0V9F-|KoWq$O&#{fF= z?&oi0#$gMvtr5Q5|JY=ZZdCVx%_1|j&)|;@cai04_=i@_4|NTpD^-yiTjo09M_`-t zFp?S4i~IOb((MRag6@LeS^w!$b5wz}&wwkYx8AqrnzSjz^&E0&g5%W(2-Nj!y75KQ zLcOz6!y~6umW;mUpHtgYdCcZRxw(iN<8n$|{)=tdTboaWxtblhkeO~TM?pqKMgMa% ztk1_kj5c#zQ*ax1#P)bi0k-0A!GOb?|M410F|+bekvT3b3H%!;;q8Gd%cIV|DCiq^ z0mow9>26fL5lsmZXs()wR594)=efG;va1gP9!0mL1H27h01Gn?&H9p@lrw9eMf7sW z$#8py;NXGoWVbNlHoXjG{SzLn72%4i?$o4kM+W^~87JR>TY>%TFYR z0yxLyp5LBzO6k(Uj`KaQw0GmWM$s`zCB>`W1ak9VAz5( z;v(uB9x~&3qvvbm(&jTEF(LWps8u|n@b`U2JivngS zxUY~im0Y1^a{o=OvolN6EclT4%)@>~z{WZXV{Jp$>z>-}x%6N5FA=Rg5V0~O-))FO?Z$RGHOumy3hv>|({U0| zN!Vey-5kxsX(EeXUS{`+vgv0G%lsYdI#r#mzAG8yOl0xX5&1Q4aW9Hq^DfB|=pmF@ zPC`U@r#NBo*sR{@{7h-X3s-+#v8SP&N))0@7_&f3mjOfcJjNTkafIpE@eqS-v(}KY zp==7B9QRI~vYcxydfSEpMV4X-d{58P(qjFT|`jtGC2W=`P|9 zs=t;Le%fK=<)zC8&ia4MlN%W})m~J4J%c^yKD4R&a?PI=+@bw?^9-JhFp+mQM1no$ zZOUG-w>27>)e~LxP_GHd?We*~g4DNW9Etlji#hA;;Vxvm5dhwZ%ATJ@nL@a%+@9hd z_hb~u07dxpFX04CiU@nmFR-Wk?O};^mXBGsjMzuvtIoq1hGeR(>Q=*5a6SVydS!^y@%*RvaCpE#onNx_;mr42jBz=nkWyQH4aIo?m~;+-j_eqw?q z=7P9X-K*=etxJ;$UZI{3w)%UfTmGOX-)oMmF6VfDYI!z{Aw0I_8TkD@$t31q&A<;Q4 z3d|l!qGlJb$Sf6cT{U7{p0zCmHpO*q8377nYFJ#8O4Iqv7TxRO!W%Blq()~Qcpv%QGH$JdTG`T4X+p3uQQ6T|FOGykOI7;ibMK+gwdfB zBMcqbpsM|!cPnW^uvIz?0QXzwl^>HC<4Z7A1A$&yg&|2yx5~UR?8;j|hqj$>?3JGW z#QZY&g|@5A;nZ z)zF-2d5@eHZcN}Y{+bDz8|lis)Y=MJa)MS0`_pkNMK4l^dA`~=Ce81Gqu#!H7nZXt z`mV<8A@j-ey4iJ|-oAWuXwG(a&RnTy8c%?-U%Hn2`xR!555s<3`yNL$2Y36;q7c> zcQ&fOFZUltF$SJBz`(Czu7_i|5;KpDi=n#<$HG4rUtOeJ9xM;M=m=4OUtDY0gN{mj zgl4EnZz5l;fjs`rqwNDv4F3zul!%=aE3n6(6w5LmIzYCu?%Dn${}-bUtLHMd#irrH z`uYZ$?H=+N#4@-^KKBIpYjY^eP%g33AxM#f!~+B!iH4Z9ITj&Lx}Hk4OQOCY7=Yz{ zv{9U!RLIt*V>=LHc+&*yNeDv!%GEJlRLooFJt}$mC!jB4-0{sdJK;gxu!p>L+&}x^rjN|(^Eh!0PqUg}0Z7R3*e+49@%P2{90BjOo|G1q>+PO< z9nA9p##qZMi?s+nig5Y<&(Yt#rpK$LX=bHrVIaA3$Z^3pBBA`AxA?Bg?ve&4T~P;B zVfjkdk@kgCo3g3{xw7Me)Uo@+E+dI7C!o9)O>e6AV6f%;^RKs$o8Rk$&<5a}L`XD9 zghUpKy6kT1pn3gZk$3_0(q?9N!eU9?TFC>Qfv36OZPhbCQTspSwnVr-QM=>fX8rTo zo(#Swa~F>xQFnC0PcD<5I^D_i#C`6Z(gfivv|R&q!^sGkrW`K&{DPQqnX1n%s4Qad!A2@R$RdH#SC+un`p}KBzg-P2ZIoC{xY7dVnUxBOG6-k}ptS^x7|M^%s4HKcBe6gg)<-y3%|<{bU3j6AHimcg zs+g*_*KO4(Q8ubJI0EM17wFsI%0So#=ptauJIq6z1UlS`*BoxGictolDO=6;4desp z4G)9lDjz@`iSDsLu&qSC z%3aC$ctHV?q^*PrONabMnP<6mhk&)c?)rRsemO4U8hGI#ynLhM!ripOf_GzVb#Rr| z?yJ~Q5KyY}LbVm%em{r2?O7_&#S&DL*h17vCwXXGPlbd4;%L=8dWu%$suwO=E> z-B1P=zQ^U?apI%&CeTno^(tNA(YysL1&H<#4+%mW6}x;FKTOI8?Zw-t)Lda>zk&(n zR^_oKoLk-3X7mFw6j9X|(wK}gs7w;J@h&u86mlmdir42ej67TKMUPsjm`Pken*P*j zExUOVpkK>=H?e>4O^|TOHXpA16x3#!9a3( zw%&*n!w7014FZT&H{ISpqii&)cRjVIXVmS^#r1eE?CUVJ&eeJW5;wmvq$*aG#<71` zIDLFB(DNkjDcp4Q4%{Kw2mCwC(aazP^#&3z{t-(&gLTv8-Bs z<<_GF@=_BfkjtF@#{uzQpo>*g#?1@&hQ!O!H5{T2rzroo1ZTrV?rSi+1a>Lqa1B%b za5g_B{w^UvAl9E1tjS#t6R-JxAn7iw!)5j}zqK)E*-Z*7z#9A8k6stxtSd6Tr?)~b zIi+Qx&B*SiooP5~I$;4>)A*vpyOG~B*nC`MAx(i92-{2y!b2)hZ+uNk4qD-@t9`h| z-1X!a*(S~9an&gA7@v1sLVl!2wNlyHXIz5h?9)@nWj73dc+Jsl1&Q2qogrJpAM_y8M0q^J14rOJ zSI2$Z;~JV%scC(8q|i7`M=d!VZ21{sqXE=cM%(n+v4B9!nqt)H@t4RzW$6 zR%!)K25N75xqbZW>L{Pqc#Uv9KQ!C#K;`KhcAlSqOO+t5nZ(WW4}{fRb;;yO5j%zS z{A{}gMdh(2NV`eNJ<93D*@FX3_001>u5pvd*cY6s*YwY1 zfn@knl;^tujTF)%JK>Gl-?-L_oXp)=TieEox-VYmX$HJ4+fYquc1BlK%%+*h zC(YMPa4mp-|d{^*JXR`RfbeeGzizJ{e{*4l0??iq7=K-%cnF9|GGe-`R7!+2OBn z;mKOynGnSv88aRMN&Ncz_xsXG-Ok0RWMq9Yh_vl>?J6b0)qZGJarW6+l>x-)7T<)r zLp;Lju+R0|07~&W*J{Xqh82@#?d>bh6T<&YSyDOgm+-XGv75=*PL^(=x3kR4h~nA| z;MwX%2&^eO71?;lJn%>6aU|S!PXzGiD=@UdnJgivH9Y#lo&#Hk9nN-+iZpHSl$~EgHjg?jqmSUJ?fVQHrXU1gXo=8i32cC->xn6bz{KYe~^! zQqs%@n+Ivp_mVuCZ6L#`O94WV-n_t_jx1qAuCn)#rmgrTLi={=apwrfn514XdG4?8)*SL?-~(Ouv09j6Ym5N=fCkaDGv1$~ zgGqm@>G>cRYVI{6*0vBf77Bz1b6?bzCYO3}EAT`T?(vKZ8f596a9_6D0D{ewLoT;5 znch30PR9w8upcicN1vi(7-pH+cy@ugUbYBmf18oe$!gD|umjW$(Cgyl23f-wql|El zzb99X`N>(KNr&xJ+{h0oevUxhP`tPHYU?YPs}!q~lhc+j&*RLH-8nHL`HPH$_h}KxLJPJQ^DpWK zYq;XaMcAr63Tjz(hVSwsUj{jM8n>|soo);(She8n>z?~Oi&Yb2vRF^m;T&=AtKe{U zwO^zEWQ%yrJ>p$QNfvr2A+3*T%(mx@yQORV2s%&IqC7C)C>ib$LLOWF;Cx{5i6J{5 z41Ax;{_b>hv>WQxK4#+~{_-S9+`>3P#XO}W-I)bpXt3<>93MUPPuTka=@lYjlU)h$ zX=qDs0%EC6B~sCP%6B=|lWbCtufC+kP-A++R8l_dTXnsJ~1 zw0V`&QB!PJLC3mF!rHEPG0z@ot&W1Scbw-9;NsWa?z1^FVMZddEuZHKDGqcmv$@65 z)dJo%PQrLFbKqgdA_Xh{^Qo|IrZ$+|^6Md(M zCJ;qMus$jyI9y@ekzq*h=OB4mdAar3@m?>;UP-AthTyp`TA1CQkOREsQ$k%zXudRn zw_siq$Q9a6`De$5dwjuu|1F!6D@vD$NV(`Jzs}5n9UKIbKerCDqrX^*63w}YUmUue z)70m$$UZU3gSml*y+oHF4Q*{cK0doXjncvgTfS`&`Cz{PU~5E63v-f2`CokovUW>^ si^!uwOC10s#TRii-(-2Lb|F`1}e$f`9&Fxyri)1cVPHF2t|sns&P8 z=Bad-{`j%b^wPGZ0x2%`1q$k$vKliar6NM5ew}bxU3mTC9_KG-Z<&{u`t+k(CIwCz z4J*#F>G}EPdDJo#BP9f|P(n^9jeBmxjdSmb>o+2(z$91!Ll0iOXf9m0RgZHM&di$D zi35jmc@7Q^m>zndNvHJo4;N?W>Gk!ffgOG&C1z=ZT=y9S6RlD}OnqDH&@+MnBth>l z0r_}IEl`HQ@H%fpZlA@c+R!D-e*LO%sHh^2j?6JJF-cPSOh;)?9c^uE^e_SIyg-=~ zqE1dM&MoP^y+Zo>`jsnZNn`urI#dLK-##SB#c0{xPkpTF(M z;dc(CA&(qiUtjOwf70JCvTDsLE-p??MmC}Z_jjuQxms~uUES=$0unCnc%$8pZw63H zUESSi?PYK|^y@r*c(b3*B=bf7;AbS3Xo{{3>VlfE`LQ2ZxSk&+T(fL2mHm(W_3&+IA3keH@ zHJ2MqJEccO!JRsDQczGNHhcb+){8@i6G*;lUXi8k*Rw`R_Oh0FY2# zUViRT&W#ISRaKSPEcNeT-=6)}m1`w>uwQYpDs{q*OfNmNz_FRRg^%wLHosx7es_;` zr}-~=+rI{?bX;Cuo+n{8>x5a=ERAy_2s7w?$0jF*C|;H@S>Ocyq7>M)ziB_#YYA6y zkZktPN=jtZ)G*RBm50qT7blJ5nf}?TRY?Yuwa)%s>WXzZN){x@#bnf;zT?YI^&;S#G`i5a&PG=v;HhsgUp{q?VciAC}g zOUm>Hb;SCNOD~?qIc8dquYG|61)`~aEV+RNs1)Sk8QHtv(S-kObng$XK&)(((S$sCb%?L#-T z4+#y8*X&ayWg`Fvwxc6GJKN>by)_B>g?+=K8Efq_ve>s&XGj!V5T52jJPa13hn_w{ zKf@454UMLAe0Pc)ygx&9sFnQaZh4p}%-*do=YOCp5RpZe;p$IUuElBS`}VoaUbw}= z_2W)-G)D(CT)EPmtmKIJ*RSt`McJ%!@lu3@3A#0T_iFiI(kHE#(|ct`R=A})PmqZw znn^=B6Wrq3?;IJ8T+rlyY*@&Bx#)=ADA(aN^rrxbg#1Ct`*jrG_0->*2SVHD5>Pw)9TbK?ZU3T`BfZrNxi} zHKyV4{k$j-SCGf##JI^1R)?=mAh}I-E??a?ZeJ2@e5ZE(hM5)Ho?l}{!Bz7;C|@Mz zK~7YheHsoak_T!3fd3g5RafV<6O$IdQCW$%tV|dg`85Ls!kgbjg{8S1Shqo%nA9B% z>IxnS6#x-Vf;u_rNN4L;@iOcge~>YXUmd18 zIeJio5)P`oFGnGw(-B7q+GU_AnJ{@eQFVK5S=&2I-)_4@h%a^8wLYTB^pk%j4x$Qy zatcldQ2OAdaz0A@%REElGpZYbs_Ug^uyo#zUuAAGFUDRvc z#@?!{6OBfOn%%iQ)k55ZA;W>^s>2q(&l(b%c14DfYRlg0Z}uB`T<&NK&_6zDS9gr1 z8!fDBh2H-Zt=Z9X05Lnij|5o@j~;*0oXJ=Dwc!Pbpf2d=a@c}P#C;TwV-qj_w^EUX zi3b7`Zs0xLnV$b>@o`#vz~rNLGRTW0SFu@MSNZ#v6j8?kTTrCGDlZyuz~hi>SIh*=S%n-e3O3oN|(MwP$F&&ep3rOOp!gp+`OVj-Lz zGu7&Kka7G!SXkwoZ~nz)ufi|`u4;IO8t`sst)n(`tt*H?Vp!!S$Yasb;y+qScs-9( zfWGO<<7Sb8^(?;TCi~rUDs!K^mf(b>LH6&-{(P1JgLvFtt^-1Ix_xd9IC)3zlX87@ zh2e62D}V&IaQ8occT}tcQ9A2Hw%4zT8qmvRzTQm9INHLhR&BU;*xkE(%YMny4-zJ+ z)W57`b(q7vp11l0)8fyLgo|<@)xMNgr`GB_TGh;flx+sc)DUtVae0EDBR~PmL?sK5 zCx5)-+d_8Nc~$!&@O|OBgB7EiZPRu#L(iKUAFlfMwJnZd-kS zhDlW0OwY~G#Kp_gS6mOq=vODT1D@N`T?*8@H+%;ai|cFl_hGy1h4sF$3}%(GA%i!c zSBRh;yX;Pvv;OLXoxhAzv`$IbbUG5(w=c55Mi;$ z!H5~IHOn;akC@o8cjm>=R9b-oExCjko~)&X5d>=nu_$4|4IzSVp#iHQ`MM`i&CA5i z)v+<)L2itoMujr};GOh9+~+aw=8s-7zguO!=00!jwtresGXJx|8i$L0H2zZlKhD=5 zFDmz(5Y3fA4M0EMS|ci2@HMMg^S8?nqjEJKQIG$nMt*{SF{JON-}omHC-t#!opdA-sL*hkZT zq>ARgM`vM~LrYt@KUxDTvkIwQBfq*1_ik4HFA0XD&8cAik z^HNZ-ZrhWzbdE?6RkSWv${f`8FW)VbH9jOBxO}e%{AKNCx zDs^Jhc2$WCb;o_&>pG3#b_k8Xp0{`KDZFs7wu*d!h30088$DY4_}>ggF2@}u@sC=N z1jLR1f7e7IfjC0rLNKAbA(+-}#4wgLQv}Ge{t6 z{&}kee#;^5`u`m;Y?=l8E9+`Xp-zOk4J4c$wT1#5!vhBgs{D_|+nBlLu#bX4OG?n|@}nqCxFH;!bLMhyd%JbBpNceINzqJK2g z3>eLaq|R6Ubc2CRS$xHak@}yu17mEKGjvW@j~m1_2L7;G2`#fjT8E zRNk%~!ymO{QodnB?sF~*cNhNoU(2s`IU)a^#L+D=!L`pnhAnhwg0rB7J5el6fEomu z2qyh66_ES<#6x=x?SG$mcLH_Ne+is5S1ilWErgj{_niSiq>`Y-QD8$=L;SyUB8GOm zEyMaIWet9(-?Zr!J_-&%7Na}{fC)A8MD+k*;}HF_RS$8mP}``1g7q|y?f-(~@kcT; zC#u7j;(5qmz$Rn!Rv#LNKxGYfh!Q!kmZ7|8Ye~E@?vgeg?4I&d9wIa43?lBcauwU zqDx)&n1oD894yJXs%Rh`<6L5c8$w4JJF^=7F>DmShKd;2f+f~B_yx7tf6X~Ddo=TY z4VNWgq4@>16Z};62Tht=$bC^utDN@SjKNuVT$iPxe1+(9c9;cLr~paziITSRv6xea zin^=@d6mj!-tv}^iB%8y2hR)H*S)r5elqN|8;zWd;WwY1g9q-x0=yTjicBu)h2IY$ zE}Ld+eK$JKTsrU16;Era1*TYzY9NrCMQpt*KAve8UT3)HO$9F(78@^6KAtb%P%<`y zlvMv5Mfo?1OY1Zp(0a?t0iFALI?pY{Vbf!zV>>2|gm<&Ktfe5c7y3m)+W8ulZg(-% zp0Xs2P1_lZiS$9MI(!BNthMF}1#ni@i-kV0OM)a$UkCHE7%#IR*hS|ZEA;_cer*?@ zz=E(zQp;5Ugm>#4I|Y2~mm)Jj&R~qxV$Qz(`Dm%PE^Rwf=Pfy1G^}WtO{B}jen=j< zly9Nv4f%AjpNbPs9;%R-$?g8jb;3p`>dPdyE)%bjduwF$A_S!qFiZQOXFFxM@e3lkGJ zpWqg)v!zEkPKbHSNCsC3iKNXz6v+Yud;QCHpkA$g^C3BeOX~=y*GPjQh2({5_gS35 z#C+R3G8x?Y=EKG5?`lLvlpmQ=^Q{`Lo8v1(p(>S8o+3Z~2VmP@^T|=A^2Ma`AsySG zLGJvg86xmgrowm?ee)YO;ZYEcI}lQx5J`=Q8$flQ`q>)Kw;hEkgo7d<(;XVGb{r-- z08?^W<9<5@O)mD+$$RE-XSxR^bk_ya7gZ06M1FG2;z~sk(P!SqYfEOkJj=zDOci*NyOUL_qwC7*%bMiuajH4B zw&n-M&Q?pkBb?E;jkO1af~yq85^JvNn=|keL|~>Im+*M`a0~CiE?Zw}VS7c_~ z4!l-lutG=X`KH!c-Oe6-w)6aZm;uf@Cisk@P?kSwKP;eJ(caUlEg6BPz=Q=muk(;CMGH@nuPfy znCEXjwzNK<9JsdGb5*h53~7Ah7b=V#-w|c|_LbpuZ8{7p?W$K~DHKv!!Nrk`t{q+6 zz!_VuXhtnQQDi#MP6z|@(VV^U=;8G)?_tOWL$tqJBMD=t6Wctusy4|#@(kIT)Xw7` z(|$lljLM9UJ1>39FwdyQ)(#-QG&A(0)bPQAu6l27NAYKOcPiSqo!coTCB7#=X-npy z7^eeE#B?X@)mua?R-7G>2cc>kwIOPVB!3*{gpA!woo3TZS)={jlcC8Gc4zWTR_BCC zM5X|+1}Xe$<8yCEephs@GMYyxSlGXL%{FG1Zohf5m>iAhf(Vl4!?b*z$f`OLf8EzP z?T{H~9KZ?jsKl%imSMD6*=_$$e4?_QKqSfaJytRU0~Ggx4K}B`^o-w^dkE_-(p3Mp zC*)syb;udGqN>Afp6>(E*F#70LK&~n6+9mf^V}Ly9jsI1>gtrTSK7$|zju_C-)26x zx;P8sW}bitw4dSN-ye9)gQ=31z(XC9xjEB`NQ^A$*19YmMKpCwY<7_-XN=h?0flXdCTAywjC`+)NI57nQvsuH@0CCBEu* zIlTpNHQp<5-B&rvt)Zj%Y(3;zDYiHywV&R+UJgyrvleA!qqUFK(6tSCJD}u|y%pMV z?^&cvJXb?JJ}2_@uR?vT-~Y1i{;Zbaa}ETCRbTmGQS;-LHr&*1D0>z&cN>c-w3E;rU)8`h01b{3y3arI!^?L~Ysu3^(zzb*3IA=RN zX3Xz$y1DuyQA`QhyH{zy<(cLTJ!8C2e-%I|Q-5Z3!QZGyyQq<3dTLodyg;wnz zn{G%(-c*z9y~CKm`=U|*K)Spnqauk^fDM@4gH}t!6165)?NJzNywO&E-$t*1(_mx@ zWAwx7xUcBVH;KCrNpv+=p#b{z%j0RLA}g12@Z)W6AX!64FmFTD;NEGp^)2eWbJDcdRLR*1*&LSy27BJ|_)30$eM-0e5u1_*eWQ*|(wJIeJU1@Vcr!OtK}9wA7J6s4&pQ|4CUj1(BsxrLGL_ff#!r5x!fP9l3)m z1i~in1eaX%oHBeZXMxE{RsbU_EM}A5F{4}YxdqCT4VZU~oh}x^%*Jvvup!VHA0rT$ znRLXNv*fp1wo^kM{fe%P1qeYR^D4JE-E_>OG5Y^OT5DCIlk--i;cATRP53}6}` zgt1TXP6#2}=+1sdO_4p{Z);$U)3FU4E{3^B^-eqThMl9IECr0pkkNX`9vedd3P4&$ zKm#Y4L3$d0me76G?K5gHXt<+jnoqZp#OI6K5Ot|HF4eOWdbsc5gAkdpPeJ9o0XMz6 zm)-DNlaprwk=jY}eo=4dvIgA1wT^@uh*Fr+`Huwz=CUE=PVa)YBg1+maC zH_2=pq1@EJf++NaRWlWq;L8q$=l z9Mk!!(l;9ehPq#4%s6X(?K36f;$nIN`d`%45kw!_x`HFOn2iIsiao<0oIUyUHhPJW ze#l4|B~W#)47gMoXuvq;#_V&8KdsnQP8{F?8UeLHe#Z@NXYd+sZ5CgX8x)bu#fYL% z%~xJQYspXRK@ky4lXgrP4D^{rqtdh8A4D=TA;TTEt6Xq4JNLC(J-(K*v(i)biPX+? zS~P6gI(;i#87PmeK-7rgKRx2cD<6=PLKPb(q~h_1f*2`WyW#M82?zseR@j7BvIzDJEQ#%_uWXCOizK36mN^%7p4dE^5YOX|G3OlWFaZfhe8czM_=a` zy<7lKF|TX%_B`sS15eLdG*>^oN)%^}&{93#RfEZUIN5!Bj|W7vs=WtlT)vFn`mGB& zS93C2M?(y3FhZXRAN=~h%V(@% z^7R8NSqq{%ac5NC=(%P_+rf5z-9Z!^ha7M$4Orv-plyMHRz3i_LvQx=!fm`qT?zl_ zeDHu?)M!^4X*78f(v-ktrCZ~ZUo!@@z9GFkw1i1K)RETAMR~naPg_4Tp7?l@&6vAX z9l7{yg~H-(-n+@qoj1hl)$3Q8#B!OTEKE2ek~#dj`#0v3he6e_gU2C88P`Us@uW;e z@f0t3X|<1TyzaAhY%DH{iHP(IOH7A!)Fk1YWEvlYqIT!g7);SL)Zjmze)22%gp}bj zl|_@1Mzhq`naShbK}=%fGCj-6{CY-M{49}X;nv1Os}#BE)LD#n1P$we0JEZB?=*OkW~n)>feE~#>&=gP~*la zCzM5&Cr`8n2;n>r-!eT6StOAx7kw8;v63^=WYm8Lg&F*+1?Iqz(zs=Be;mx=dhc}H z?y*Wj4!VRwSj?gMbR$V4tU`D28RfOn*gOTX6`y)s1qB>XbD8g#&nKRf@q@E_4GbRU zloT>x^jYLvQc1rgjs1~49B@25pxOAI^cic!p&Sqw6h#$`G-RK2Uu%U+pHF*UUph*S z-D{yuG)XBahNL2(<)$1X>H(82XolCtvNw4?FN`kvAxH+w<=rL^e+aSQZTNJ;T;&|B zbc2KtH9NfqW4#6$+!`((^RR3=d3nF@T3S}fsHpZMG!3?PB2_H2x@1nG@N!eAy=gy% zB}7ooyhH>At>$J`66IC#0_|o#1DszkB$$l}Q=O4fJgZ~2Ic@f~!4F4YWsj8LL703Q zX;O;$AQV`ZSz#?R29&$AMla*Et*KrzVLmtZvHL6H&sT@NIZRYm*s;y;tn%35W8)NV z?#!S*q|6kNu^ zvw`S@J$zK`8qrr(sI&7kvl(n6ZYIP#1+pY86bVTV+Vp1wGjgI@Ml5}8VAz$OYa=X5 z$_gu|M-+H$+1uh$;s)QB8=2sPpxu^Dt&8(Z>x0L~Gh!@6k+(uAa%ClmmX;p8t^Sl0 z>au%YFtystKn2JKsNriUVh=ANemHxXk6u3(QiOGnr*jSv{=>f6BQR1vk`K$&oW8Ex!PU}oT4YdJCOUrO!rNdpR8nta$*DlFhU z@k!gW`CMdX<Kz2Ho^$85qIeUI3LL zoQ415?Yih41&X8R=Lz9(y@Q93(_PyliJr@rkfoD|;0vs9tv^m0L0TY#!zP_Bz#{dr zL@E!QG@so*?(IqbIdn~sFMe?5CmRQCZ6DGW9#C07U$_+H=#wo2IeCNEQUX{T;TtYs z1dRzZ$F<0J}lXgAK%5HaUQ(K!Mq~wK;#+;|omCIJ8Myd}G z)@?A{f^7|9eFQF^pTwb#_SFNGzjOYVed|TZYT5(M+gl;0SP>H3(R0+oaZ33QA%`2i zg#7slor?{mbB+HbwUn^Di<|Tc58WY}&$|r6gu1wn8MVy+)kH~bL1~$Dn4EG+>=P@@ zEO;%4ZscKLEi70i>=-5NI2C4e?{dHdb*O8XOpk-L!Pc(wcgmw8*kRkPhej{|MHZ`| zfJj4c-OoDYZmNYz=;V}?7)v=YCwJQ|9T+sobm39w_Pn_Go0BxJ2X*NZ?Qx{6`|IWU z{p$?0WGSe-jynW!*snUp78`wdhmV8TfK)=;rHUTop z%+kp&i?SehH^V(MP~mBSt+}AkYC-qng7V#czh-EcHhG|%M2$GoYJcq(-x0OiK!Iww zmpPwShG=|&Z!14>QRR$)UXN$yV84o*Q~%J>lSMI;+~naLzXnfTNIfv1vg^8$C!;X< z3!tqw(Oectrz4k?POYbPmBO$O?s6r%SnCWV>U~!--jFjWWD?Pp?Pz^ef-e$GWnhNJ|cQ)$5)P)2g zoiml7g@1tp?f`H1%`1=j;f0ctJ>0BebtD_vRl8R#c^|_PzVd zIq7kHsF2~fZVF?+6KAHCJGoW?n~_Yw>Nz>^sH0F^GxjE+UtKWIuT%9sRk?nUdjpMjFMj0cj~ zt1BhaGOe-35xNMcu#I&NmmUD)sAezdg*?oOw8z_PfqwJ*ZDe>a{pu|C@_35}rJZQGo_4G~pb@w7qpk0TcPT1^ zHJLo**EuPyev;yBEE{5nE7ev_+&KFc!z)YLYF)s>`!i}D#?ok5WRLS|CnB1t`e1}n zuGe+-!ivjBulG$PF?#_$Nxt8-KWVr1D1j4oHPtq_ZEVhD4MF4Cw7-Mj!lfJP{+%c%X zMZe&wY22;c=b$ms75TLD`)6Rny`7mL)1-GxSE(8HWoYfUzMQiNlWbZSRMjHy7v)-X zlKYXR_lR%Z->GnhG{-3`-lhzI(QR!VO*;dh?3; zyH-nTPLR* zSpC9~rPrJTHWU{s*4NWSF6JB$w8_hUcvt%!VC_dO&=vo~!b4+}3Kg)@ z#%w}64$DO;An9>InzR+ZA`@}`HWoQ)Bq{-+sk@OXdRz2rFv?A>5c)zn=~*A2#8OO?~wlw|+#B zjav6h{M5B2b}I~g<>9ije)YAsE|@{nH?-ja6~pJ+r)|GX9Z+Q?NC5>(F{{`ZleO^< z&iO27WHMx6ZBNvPH*C`vL|HT%obOriK7EnQ#!fn)u3EHWD=c^ubc?XZi7dqJ+0A;o zdKP$mBai~U3c(KS``l>Nm$Tn5)*T$ddC;4CSoQR1dI*5gp1Fn%cc#kEy{ilcU(OE^xB1;HEN!qwR=_BGQbUK~xG_5e9t_9N zTBhawg#Z?Ob^HbEH?E#uW49*TXwNC@ZPv3Z%vL>qI~=Qa1y<&UpoRfj`=f0s=#@vS zE0-Trv{hBez@|Ni?IMJ_Xpg1n!Kq7Ew%d^-7P>o71kgHP2UjyzIKcx#y+d@#y7%3s zg~$Vw)|+*+`biNyWzPY_7Ui{*LHzIJ&mPrw|_J zhn0H_({zYSXLrcsw+(I1OOA)W5Cawq&=B*Ic8i`3VR~eNx;{ADb;AL!)%rd7?el3n zxO)u#SHW{6j}y+`rkw1o5}xH2W+`_dC04&a@!rZ4@`%782es#4*gqgIjxLCf3cMB& zd{Io|krWa`%A;t%q$Jh{%Wzfc^}iyHmK@Nx$5k!UaaYZ@14?gREiKCXB-1oyB;&DY-fy`?x&)-lp>w$rXFwaGVl)1Z z&U4?jpTHsD-s!Y5I2^qmyLzHivQ_OCjddH0w_#6nMm|X2bqP|YLiNOKx!I%xo-t)! zj1gnf#%@n*bow?P8Blj^2pd1hUyd*ENsjR8d@Sf-vyhmh=?r>;De+TTKAyPeOOqy6 zO?~l$?S3Y9+=0@au}J|B2}Nu4b+lhAp+<)j!}$VM$6B7|w0LzL1Uc)7W1MH^j%Vms?*J}Ooe!_OBIZ6T z3?c2~0o-T+m>pt|46lTP%;iDav`%~6x3NUkw%Jgd59JK@8Css>4(714-9;-ID~IrMj=+ANI37TD0Hwk~(9T2LU(Syz^*AlVrXS z!h5>GHbh|=cTBOn;_2Ki(mfro23T^*HMt@$Y(I3phPa6m`$E(yR39&GsIc zYrktONymF7i~@9~e^8%Ty!)(UiQ|HlMc02%aj7^c$FnTRT7w`uwg|A&V2Mw2kfPXs z%sNR<$QT{!aBY0}RZ(s0i%WmVV59g}Y?5ld)>qMf&1{3hqM#xtCGPO^<0X}4)TnVs zo;UsT44eJ%yiGs~e82Tzx4hWAz|@YDZHi@%#lq=ybei}&t*^KsQL!^BYTRjId1M&r z@Dmt8LvYxr3rx#dO{xvXlzBY%O|&em+<|!3|7<%&x6fSE*dQ3kv8t;@v)R#*o!dNK z6z@Ay9i8DBGB^p*5KW)OUFyN=@CL(uV`wn$W1M2~>P%p9O~FuJQA- zh8Q^aA2-3)c42=d_SFkZ-#Zmqt6dzYOq zc|DFcQpA4o%JJ5b9v0bK1t5s$Vu}y!qjc)pIyu zFkrw@9ck6^$jj zW4|H`YqqoUP%HWZdD(;5gfZROW4rTYq_w(^wB= zzHqlc=v=XtXq$K#VcE2`MX%VmthDQ|WU^1^BVH}xUCv5zj?RhHxF+N7n6lHA;R}{g`#8hNs=nPow7|gE+ymVcf}_xyl?mCWnA~O={@( zit$ojVNmZU>tWGI$LIKzD%q)7~{FV14k%zf{CY2|*>JAYFDI+P(0^$T!4ys=?uG#+WVl+FfjW6O0W z>iSuT$=Y8XGdY*i%dSI^JtNTeb_WST;*pu1{g#EWJ5}#P76N~oXMOkZ_`dC`i4(He zUKR*aXFK!s5NQ1_BXCE?t{5X!J14xD++?ndZ1gq!q9w9A3Y|J~=W+3~>QsM4R(N=v zTT}4Hqqs6GU!H>!7eZtI!8LtrE@3|G`g+CsG__!D7<)dT;g&RSOn3G05s2q)$HinH z=OJ=DL3vX1_HJJeonsB(;lZEN2$qjQsXi!eAxNg(5mpQV#gaIqS($nm(mvAjAZvVI z%A8#+V`n<}>?~iqqjbH&?teW<_ox@;-)7EgGuO1_L739gUX=nO%gj(?l6s!GE_R&2 zdBtXP$}4PV!R7~i?0nu%kwQ1>uysVaxksix*nC7#?!y+7)IaP!;9KahJWQ_+Q93Z* z{8f9sF}es|D%-8_t-mqr`B6rBZ?}3=N=I^k-bZ67Z4mLE>m3e7Yiad9K$d}<(s!yg zwaf;4Q_K+g$U;B#b&>24nHazu8KL8g85LPGYkYYKTk zSDK)k^Oi^7Z{1^i+9y?ffBvG}SmqY^-Zn`>gHd6hm#vzMr*?zIl-(_i<^+Z3y$tUs z!g;4+?MGU>F?`MU4I4ZJw&!R373D8O2iOWcT~;HSrlR3PHnuwpj<>+hb7(C(=_r0o z_M{~pZe#`C>Rq>HZl$h<3>ZCiBePcrt5g=~dDx4!Aub!=lW*E|E`wabGzK6}H&*&% zcx?>sqpitA`U0#K#W7<*GAFK!) zPk9p7(+6HpXSWvQqhMKf2WFPP62Ok>CV8hs=`q(_JejaBAL~xDdUvISdPl_BTowq9 z9e!p8wi}egfI!vz%uM|upqG0l4)ses-ro8}jMdC^fqAwUb~I5-y`xdJx`bIQPtzS( zO>4UJ0hcM`A<~DL={N+lpUkoW1KD=v*sD)2}DL|lxy8cA5R?ez5-lv2Rak0txHmlVDvD)q|{Y2;^|&wnTrvm zs?$=IkekfNw?qx+v6)AAXW}CSWGkv>1B>90eD`hG)OelE|GtXs8;&vI^0GvY&E-OI zCR%0?{eh5u!dl<;DtR|m3;Ej_#X1dneg=CldL8zLnqZ3?xB_oeiW1XrqP8@mj`BQq zYs8F~*kt#7E&IXY>q%9%Mag}q-$BFMqyp^Fjn+dFs4HHM`BnU@zJ*-<%fisGHA76Z+Hgiz=@~LZqn_qA*R!s6j4-^n`B`|BfoeRm*ZIHvc(XgcO%BIT*NUgWo1X`&|#0(a3F%P zj>s=+L;x!);?82`dqy)WQ&lw_&a!qvjs9x+GxwGM2&sPU*5p>a*Z1q*4f8rFt{(XH#e21Uz+I?Ulw_*uAwUgJ zV{BMlH&?0psw2g;qA({J*^+2U6bQtM$suw7r=kZaR!qc5(nvSL!BoZDwC3Xq76tpc z@qUDcYAlB2X{llLaLErS5nWa)K5ivZN(x?UvbP!+yOnHmsToew4+|DDXWRn)zFi*p z<*!7HZ> zmhhG2HHD$962ukoF5 z#a+!__p`et(Hqy@jJwFn;qgRW2PynGb5QF1#Sxk`vkp9-s!#7h6}(X|qCe=RU(q#z zQ_`ZJY@PI*D0p|3t6Zn*M^Kgas&r3jPVKID4NAyS!AP9=Ia~jGx>ao+jqy8~N;M+^ zP))WSUL69?I;0WmwvH2%%aP-Bzc8HlhdsUT{FIE{?ffzQ@v{b7i&*ekTiZeJOv%x21FkMFV}S>`G0B{JQpseb?&KTH(^e=Vp14y! zm->naRd=8`z zy>DRz$-bTDW^YT&Ab+GkKYO`)Nhda|5*h!_KEW|{NBZm>mjF_-5SqcFPc3GkvQr)1 zsY*hUi>IgE=i06Uh$Mna@i8xr@Ce@5zMZbrMGmlHAHP%TW);tghFA}{DS#tk1L@^T zXN-|r~VOAS)-&c(~ zlG-{DTEk{2o5m;ROMD>-Vq^iG_l9C>W(F<2Gz>401=_8gz$b-ow@oagKM?9N@M0}K z&$FBtBf^yOw*K-?u#~VD!(6?$*y+iO_u;_Ze86?UHQ|uqFu^{dmwO8X3tsc(Vyq(l?*4F;2UKVJPR3v06riwIp+NHJ5XhTIZCH4pO&H zFPwkbHz!hT-E%~GUu8_`NscGenqLIcGT1Hbh;ae5c8fJb z?pFOah66iy{GmOp<=zA1?1IFGyy@vZ3Mtry&OYU=4uOB*Kl;X_-vf)yt~}HoeITD? z0@@YTUKooqRVEbt1qKFOo@^#^&yIPl2jR=D3wAa^{!fi}R!_$&ESF^|rlcQ`{=flh z_@t5LX<(jS%s4Uf%kcKP0~pJ&Yqj+dRXCj8M_Uks4$DKd^|9--!&_+Dz=^*6)ti)* zM)Jv6=uMT7eWIg2!9-Sd)Dv`uG8qVK&E2-swvY3gT=ej)mjsvAmdB)N4bswCM^?P;EuWmg?=} zGLrjZJApaC4I&zWR#mC3CBpeK&}Gf+YA40VXHBv-)CKM|sURtlwI+tcGNr3p`lF~P z3QEO7=3>)i_JcW(um$BJ;xv^zz997HmV0gG>@`S9ZFq#a>kyAzs*2q?@p{(8RlPtU71tJs>?;u&5AaZZ2pYI7B!w04 zZhI~C1I>x_U*J*FiOL*$7!2gaS?cZ~QCmD5AeDx%9%<)+b_&v29B)b363)Dvirzca zaRX6aAoMArmOO6OoES3rJZVC2_!gcwQaJ@=Us&U~7o}P{Ami$OR%7$g3tXw=(t?k* zB(6!{4TVw<{V;}hjzg#+Cc*ff7#ouzs14`qpD$hTFk(l>(jRS-U!P)$%@8vZZovIa zq8P7Y@N(fE3=VC29EB9U>u|D`*BF0W@V6J>Rd+_d*%}7P6rO3)$YhEOqFK^`b^){) z(}Z|2puho5H0mvI{e4F$=exFbQB*$;nMd3r|ZrQ&k(>f++UW9khLXMnhvqR4?}Z*@rG^-GnMqWT2Z>pmxz z>l*~GAoT|$9`%>O9^)}|CvP!Ge`wKXd~!jUCtqr?L;Z{Ai^{9M8Ym1$-O}IWh-BEH zqu{+?ATVMFM}vErsj~w$*85`S5xH={sK+Uc%bBKZkVsVZZ=tgf8eV6}j^kd+5l@VM z^YY17WN1PKx}2#B@j9*4UrlGBJ@z%37?mQ}7#eQBsVHO%e%p5#C}_s;K3;fzl$5;z zkq%bHy?EMAeB5lFTcv+vbozow%sk`1_%LEq?X-ZZ&3omen#6j35Cb{PhqqST{bcaw zE<_P9`Xy#^DX7oPDF>n{H_dTDLL&Ms&&U)`xdv`P3cCW6825H^l`;+oAx7Bu+g7Jp zz4rs2+npvO7AIigyE3eK@2U}Xn+Z$GY?n&=BkL>bk3M_V*U6pMkGSZ|_ido~5PYZ*YgqMX4Oo(=VVvKPz^{P!53b-Rs2u&yYUF@K_T zVzPy}#g$U~WH06c=DINmkU*~hN2YfU1}1O^%yNOBv3BUiUqHNEiDK-YZRcf=t47In zhCV}mx^Is^&pv*-S#U*++Rrm=g-6m%oNx<@Xz#Ls3a_n$*JBe{$0Fm=dh_#_d7mqv zgagI}0v*kTq1_*(N36!ZPl4Y}>Ul>-d>$!y*S!E)6Hco>FL|vuh_0-jLf^evL$<-F z9yifApI*s2x<^2~J?+TA>Kd*(J3g53$^mhtATToy`!x5SdpO#grxcv5dnMJEu)ZnK zi4CfDV7JHB%SMDbL&+S`mIenlJOdvcD4t#PU3_43tf)8IO29TBv-O#BnXqE9;iK3H zJ&t%+NC^aAj@YX2VAyHjk@&^1S(Q`?$;WD}G!z)5PhI5^?DJR3ks?TUOR@Ls>yWT<_2lLToAE)41en!$RROFqeB++;N4_EIP zU0JZT3wI~!*tXfRZM)-6$F}W`ZQJN19h)8Qc*nMFWAB@D-tYa!9e0fNqkgQawW?~O z<}*#W%EK}Wu<;$>RF?#*khV1djMX(wvUio@ODR_R?(D4-n`-Z&zjz@UEsY_t9Enl>@K2~wk^ zT-WsI)m2*Nu7>oo82$_c)rd1W{XZ%mK^+w`enSvKhtPgY_W^AD)!Qxc?*>8vq7YH_ zh#g`mpv%l|MaPYQ-T8X`j3m*h@y|2Jpa`I?&CcbTW&jkbPf>{Hl)KhEBx8;Pz)m!9806N7to z*eMV!vOa>KjI$Pj2}{yfh!5vupImgWJVz<0&}cF>Qk1ddH07R=5b!&0E&(V190foo zyFEn%nCG)!>eCj+8>V3!;sR%m+ML38`-QB&9z(!q82hMY?cJL312B6=$$y)QjpzXk z{GK$0&|`}c=jYz0Tm)_#wJMy~C8uu1n6e-hsKZB7a<($i>RsSU}pX4goI!fr_eev}q(QtZx) zgU;fEd%2#!FvTS2=6#ab3Zi=!QF}r#+L{KPl4S>k&stI$FpL3+|M+)k(rw?=j{j)< zTZU_TWX%yC{6Z--m54}<(LkTP%MP4fb%wk^7$3ne|NXh3H|crCM?xqRXFZeU4b(m} z>fXYxktXj7wr**=5qRU~Pyw9u_Fx}mj**-g=HlyNIZdoAtG}C3&OH74)(Kh@d(lBG z1EFm;(P6{s%O2OG!by>w#YcazP-dR-jBm`?03bSDdn_JaE)|ViX;V&|np& zACby?=|1VpR2tYz!0%zJL~+Ze<65r=LL+p@8Xpnv7#(e(&o^vNd0 z4%(}|?%)pAw?V^V;`cWB7QIMVW@nio)Qi;08&&8&NsWHMK~RnTf+ zJUUrLm#`IEYr%(l$nN1pqhiAEMoeL^h0ptu{qo}CaP!W80X2k2DID=_ChjAt76g=k zKg<;>$st_7v|T@ep0`Z-!NbRYH1bu^rm%`vN!pK?Hxom101C!i9!q}dd`I0ykmd|> z`wpGgE#>d!OUVK6=wzl8ch^_nk&y;8iy7U+E(;=!H~+~$uhgeW$WR@Yyxq|cpV8f2 zIu50kEI8r&!-*#)-U~vTf1-;bl-6ChdD|ibUQfRA^`jXp*501818?$y3x)gp2?y?b z?wK)pc(7s=A7n;dpn`I zRIazVG>kZBvP9$}B17XTl@VGog&v@tUkci;uglX`i_F<06A2Cx{B8UJ)ZT%=pMip6 zjlU%Qf`|VHXxvwCwmM?Q|@_uz$`zFF~1zQK2F;->^XKiS*+IMalZGE zI%$X($GkW2OeH0s^O5a1nkQli^tUi(zktTeZ=zStVkop^YMEN~s81IRxdrw3x+Y4^ zGqbxOxG!yK++8v}OX4r}1uI!%FK8HAv$uD&JP#!zTC4!9g1Y+#MUL-ZU}9EcFfmz< zigJC8ciUtgsadJZjpVp@GzIP-zlZdr9^00GOweWh#`81x?G~$Cjit^gLg}7kxUU#ALnN_> zM4N@87|qfcqxK!2Rh==S=pH>XpA>gxOy*gmzaEm-8p!DuyM#4{T_f$txHrX*zuf+W z>)`ta_n5EKA5|D~-nO{@uTpnf{)^OpAA6HM_#4=>+OK*~I@mE3nG{Ke} z6XvcV0vcrJc|4lct?<@!G}G>{+7>kB-e0d?w#oFp9%0^{8)HPTF_1GO_Lqzk1=TjC z>2=uaQvXtFol`Ia71C_Vj_fedAmi%oKIS-x#*AHU@fEpPkD1FHUlglrCi^Bvemdrn zX5#$r47)vrznmm7-g6O(y3(J>X1)wv6x$V9x3rzBx4L^b13MP zkd0BwHu-e;J42H16f9+9^!>TUdi_3Xc1uri!Le+o-(^VEY{#)J&sc5#@sZusWe`3k z8#*=5laY|44HcHQ`Mrp@3TyLKl`-%tV2u53&Qtb|4YLt7zx7KuEm;;jYs`7E%NBLd z3YQ1Rj=>YDzScJzhpcGvjOPdXz^);wB5TyD>bMO6uV7Yh+(0Lv6+uJ&_D(4dHF=^f z?(Fxr%i)h4o@c^dOK+m`613aESc^9}#Qhu}u0)=_ne|wQLc&sl@&Qux&5--`qeuSs+6!qIG;SPr zlD2*zJB7$lhGMoIw0%XJ?@HN|BHu1G%wo&d?JUs!+C2+WjYZ5?1hDFZqo%z*$YE5T zXqclLSM9}}VC0m1v+S&-yvwcoY9uhHv5_Tj?v8mfZSN1>l3XTXC~D%$E%xht9(clE zq53k+<99=S|4X!pNgjAuvgQI)PP5TvZS_~GDzZ<@_s+6S^ zZ_n~CVtYR@9DA?jcm}~6K27t7(DDeVyl2$IeK`^4*Gb(3h06juV*kOqFu%Mv)@8wm zI{O+%tWFW)BRc&08n3G-fA*q9a!XCjkXrM22$V)pO+r$;{VBil^{bk)BYFZNyr7=l z@uaAL9=Y7BYfG)P!<5O2N$X659}RzicS13C;+%p5)NgMuQGe6hk*@2+J_|ce|?PwP&$aIAcUQcUrz>QTjVG42=L`CLLMrdnAxtD{g{)zZo zaWyb0X`4|86Zn?kv1|WylRd(&rBi40SKKrbjEX8kM$_typwAslwa0A6(Liu|(VpPs zFt)5jNj2KFCUI&`Z`&0`Z%i0epk#%VZF1oRn#t#XoLhkZwzj6v&dzH4URa8;KXvJv z8ZZ<2JULf%W?x>~cXYb7rPmrw2HR+#swYCBz%1sA&dB~mDABW}>55 z`clMT#7sx(yw8yr=B>3j^16*^iIq-zxiOCzi1gUnd}ar?|K(nyfc{)1~2QdV{EFzovITt$C?_UJ&Had4v2A z|8}t~ybwqym^*Z+16x7+#1zY%JZ?0b0tS!wt%oz!lvjQw3SYe> z_3;VR#-z#`Z-*1f8_Ls8mk*p*f14s_65Qy1(e%tnWQXSI+3GQ|=5?l=HY>N3=A>eZ zDZk8I8PkB>?B2x4ur)_f?(#%lnEh%gI{a;ec5^|@`srC_I$eyPF68`Y-cIMlBAJ4@ zgPK#|W_l9d-OQX|`$f5dJ&Bdmb^hT&xyK9@{>V@LIG=urD`P>&Bq0kb63{bJ%Bh(v zoGqu3z&X<}2ixzfdwq9Kq#3(hWxM*+m*}(~>c5mCy5!tejq-zI37Dvm=Mh+(Jg9d<<-8=X`QPMtO-#-jG5?WT@{f58n_)cgw?ML?k4c%|l=D*A z45e?_d+VB$ePB#YNjWqYSklB8zLV&2Pii~a^|af~uoYvDUjD0h&Oa;RAx(p(MV2`< z{?p8vRbN+PKz zfkPaLn+L9XkE>Can;)bmNZgxFG$=K>(d?qWj$E4cN_b~ftiw21do3|lcS&qxM>vUO zlvY)vgJ|s-uFhP;@Q}ZuRYM9lIpmI(8eBD~UZ}B(`NXPvbD~O{tMwCoj1WJhWqbh0 ztNiY|Gi(iPN6AO}fh#!*!vt>U0-pkPRZ)RgoWnh-LN&a|d!|gb)aPVSg;Ut68AkF# zd?9S6i3Q(@V>d?siR#u~vFV#=L3=yi&i-ifFFidXk4-O{RfQIjNq964J8og$Yb{r- zzvd^xz8O9nS2g`rGo(9#e7}^shtjudb{a`4%p^7X3-`Ylp*ZR5av6#Q@ryS*E2-)nI?`lnjr*_z2nl4zVV-E}VaW|2?uCrHkJZ6fbn7Es?()?6)zWUZo|7*Cb5~beu zW^3D7L;0qvF>)+uFx9{424gVA9CHE4pvU107ZH&$eKIy9Z#JUJRb+_QO^qK(??ozt z3Z?J&pt0}Bqrl;Pajq87iYL^QsFm**Mx)Pt*W)0lAf?~Wv7?oV>SXmr8KhdnZlUYl z5K}eABAP7a0D@l}4Wqp5QgUJ?3lgXCy1C2WKYD|)y#AVn)#yij<+CfS-OV9Pw=v!1 zA9jwsYedr=urDiEBV;1$$|mo`x2|4By+~K{y>X91HHV7Ro@zIq!aj@lW33mc*6SZg zaFVlh`Yd7|xzl%S{@2 za$Mr;>I}#C=S$!W1%p4dv%&ijU*ZnEVr_~C|RH>_P}m56=kyWeu1ZI``p{v_AL6PPXlQ| znqgBx;X*>?O+|yG5_|s^s16hgDv(B1hzP=xbtISfIxZ2QoCzhJxa?6BMP05l8d#Vz z5X$l`v^-f@vn>7eG#xV(TvslT;!&Ee$QkW)x)+XPiG;6I7hkX1AKMVZX*!6I@OZ@HmbtHqRK*lsFOtTiReC{Mz^AC`Lw6e%ty{lN1$tUMpg;J zM!{)Mh|=H`Bu6C<#1;Yt;T{G5=@e zT_CD9SE4z6L7gE|G`4RFhtAg|4!#>qD2z|e$W4i_e2Jvr7#!5xwMMBtm0pmVZem&5 zOmjk0sUwBw`aH1a>P9Gi|Ad_V&B}ZKjJm1PN(57cNJ+tdhu}-bBgcnM{#vXNj)}m^ zQDIn@&5G-`U6AN%D6ShqCj+G zPfKb$@KJ~u2QE3b8d|kgM#&69Ez^gaQ4j@dkrSF)$2Y;`Zik7f0hRs+q;!pVj>SG} z1_jDvlMIe?bI9T7)IH?{8*ODy4o)dc%Y?SRxJ|=B&%`~&;j&sNt*Z4uZE0_}_*7QC ztiyw>+gWkn{zI9@n6k5bb?HC!-I<%Cg#u@`MNrX^enAu^gy}1ZGXq6cx(8FRi*BfQ z<+$;UI2fmntsfV1EI(B%G8#MIf9M8AdrTaY;p!JsNqoTj9{BLV`%iVX?-KlniTKv>JM zZoDNebS&Bzd{^sKpf%856k==CK^KDp>}&P95$*-tG!Tp^up9Nlqpf=Ky7OO|8KwQ+ zX(+}e$qOd%0*&V%aE|-!cUHGi?{j4|tS5x`-FPQ#%Fc~5-yQ%j`<=JMbTuK5^vgr0 z`M9qydh=!1z%MMTQ^0z!fi;fF?mV_CN9|;czYg@kfGacqw{Z8ICni#PnfJ-toZNsb zfNytm${V)15z(2U!@yeCOE7pG;C`s4ogjH4aqz6RpS3uL+Sj+&_5333Y1an9Se!B& zO?Y+Bp-cGb0d9;dh|8cMS&2qX6NUpyu=JxZ}K=V=r#dVca7&Zri5|^^mUD) z7_yZqv(@KC{HDcC98|bhrQ>UdQfVr%Hku~?%|`E*&5NFt5vbCN+USJj-3}q^Oa>3l zJFh*bzFW^iq0c;snNsy=WSv8pxbh;z^?eQY zs{_h_QRvTp6H2ud8%HC?&eZq-&X6kVc!dkhT#BzoQ95>~Lq zJ_VPDkS^1;Uux#uk;~vggpKPxs0~2*`G<9BlFy~`2YhX|;9F_md9rP(1)eJu}lhjt{Z<^-0`RQqyY#pBjj=hSh0XVXCZFWU@xJUCmkX>3~x% z$$yV9E9h1l1L2dlcY#FOT&n7h>>5}oiRqo_$#g4`584t?qVc51s2q?*hLSX?F&p6< zvJ9JXMUOZ3)y4=TBdS7t?YOxq;j}z}mH_!Kg5=Xk-IYC$2D4fa4A8u>ZUO2$X>WbSJWx0UGjdF3h>x|(eiwo^drO@ zlkn(@r+U%k(-8}i6nxa>6{UznedMmcE3b8#CFu{(?z#4{4uPb7b{2%4OGh8@J zN_l_y{T;;3&ohEPs6^WhB+i0)E(H8hLa{_SM2?j5o>#Sfagn@^tz0W5CL5~ZEju+t5c%t07Oz`XxuV!bjyvC)wD$NP}km+kEt!^X3IZ}V17#DCiWYTWIUl;FDD-3Iv)5{&IVDW~l{k64dkG|}NYr7@WFCE08CKDgwq zX#fc=koc}dr#Og;0^Rm-%s`(7&t)nm7b_Jkk|3wEIfwf;p4?=~uaKjCkbGE)y(l;B?naRi6 zqA`gj@54}UsGoME?8zmELM1cPY)9PfA-G3Y-Z5fn3CE-buWmho+pYKIj3B=kENzdULP^$N;)>=Vh=EY*Rpi}3lZF8yEar~2jf}AFOo%$dMOat zI*sg3Z_~h7QIERGPOyBts*l_X9g$^s+=LuP-{9%!g@@%j?e7Q!6u|p;4Wcq#jmZ$l z5pschAYAPT74BLT0}--A4oF2g{2g4_R62TGT5f8O{7OR$;&~8C_18i68fOR@P9>Pl z{z38ZjE!@%Tm&&ThiKw#X_=MZ(_;Vn)`15*Y$fEKb@|QD79`2t-df$Kq9fS{bwV+a z>xm4G!{H(;izg@5axay}mt+pQUvr$4| zC+H5Q+JYcV9wN{YJRA=fw7kwH`A%P@e+-fa;qQbvu*ON_7&*C3`@16aKKrxZX}Qf@ zrNZ4K6|9`C0Kb1H9vfmD4=GRDD@s!+T5q=+!FZ+3+Yv$Vnek01rk?S~!Qvl`u;2#z zcgALqJM?odOMB?x3^+v|nh?MG71l4r^T_!|OuZ_Fy?5Vxc+70hhcgrRJ05;(>3UQW z)2UGCtqTZ_b#OLxWI{9JmDh7>n##4^G$ZpU3{9FP4ZLaCDfqJi_+f<|&oDtH_ybtD z^w`+Aptve7?}z{~`)qObm(t=GH9LPz(j*yE&8E}`I!!=8fH|`%_oVp=)l$5*> zRO*wPDP>%Th5Ds|e}d0_yx1MiFG=m87*_`(xl%zgWK>r!ipz`mR9vy~w94$d`(Wxv zhcJC9zNe}BdgJdai>4;oJesDf(}>V1J+w9TD-V(f)OA+os`g2Cl~WbEpC+N7HT_jr zb8>5o+g|h6VAiY{Z3(SYM^AS}8+M#{IuPCKtkU8t*=qR>Z*qL_-u=O|(PM8@=%ivW zPvB1=-Ku)1j1e^oPQ3N_y~#>NewUd&@yUU9i8PJCIBww+d9RAZieUyQ?A`wDxX zR-gn-Lq@PZlN1dW87y?oW63MSr^F!=pNp%v>c-jYhj}^mxGLmglQ{|l-i4N#BNH*3 zE4D-)N2Eh4gA-aRnH{eTwgBN#d?%|fF7_W&Qn#R+4^yDLGred4f0E(w$Be<_N| z>%&v|_Qp?nO6vxG_V?N!%rBQ!g6CduEFS6_v)A`eRyEJ$9^eJO&1`L8WP0zA3Gm#+ zD=RfglGg;O_`hLfG@J6Ry{Ph4+0vixW_td-gNz=Zq%m4Vu3Y0ScHs2Orp5DmH>Wyc z*S}~T_uJ-j6i0Bn{opQ(e#Uwfts6mJxhP%Xu0d~q`eMd3vVXX=e^<7a289dp)KGOu z!41_f9KTEeac4XVmiu(`NBR2wKx>6grjmveT@75H_gfwjA^$33{s)=xuk`4~oAmdk zCw$McK&WI@5(<#X`{^jEeD9r?kP8svRuG1#{iM^^*@cMPoHtXA_0?ZdBNFk+`TTGG z940;BBM^8Oe>IwSEhJ0^mgVwojjL7$BcZIf$Ncg`_y8E}*KUGgl&T$*(hEfkl7F7L zD+#~LgC4FvtHAWcD%SQ)8VL7Bruhg(3>XixQ}8CywsyhWs1d#8X)9m71&nTO3C5e9 zGUW7QNQ@L~f@eZS__5#MiT!rbl>Cid ziyk(a*QG*%18d4)OJ|+7!kB6&?KQcobQ8hK^2Vz4wj`;pjbMQz%^WJ;=_ZRHTYgWw zIUV0adV)V6GbRj5i}`Lj5=?FR8u=i?c%bsVBs+wyiS)Sm`o{_2d2KDGV$FZ*A^=Pe zFE1pzD2D{0A5z1P+f$dRytQA(N1^nzqiCC3>94&v&SOIYRKZ~`eb4Xh@2#GhY2R^p zxeqisuRE$c?GfnTRI_~_Q@h`Kpd@((thG;SN(1vO+Q2KQ+=6Y;+0Ez{pCpp+pP~`; zPu-}gyCSF*1}{WJhN_#2y!2COTcAbN;e zos#AP+#7HBfrb9o>;}3QWvjiRj5<%(p*Sr!+he}SHMJB!>(b&u`(&GY@I`JyfOH}E zsMmW$e48rTjKcWoCayRK;mJR9_KP3avWo}s8LtLA>09f7nulzj$4@lUOO&zv3GKiN zJs4+YG4w+x+it+U2A`GVZ{9_36-9<{q%HTl=!2w*B#xd#K>k`QoQx>$L+9M`{WnS# zdsVw%624Lg-z{(4-9h`@^Vu~P3$49?J(mwln1Fu(|E>NR6F%%y^py#E+gxJ>*0u7} z@ePjdCl#UVL5g|3eHRc-q|ia@Q}6kzo%g>uTvSC?AF#h$NJoo z;RaJg_VP3^4=zS@sIh8o|poM)0{; zTdYpcHE!#cM(D!`#|Jdd5VM*l#ed);CN!0lx(t^J+JN6#r_zpmWl^RUkZ>w>Md|d@ z<1PU7f@ZX6ZVWZPY1mjQ5&1*kmVd`wt}nVpY{50~+TYuDGkcjs>2-_keFuW?AA(a3 zNIf=|UhLO@>pOgbjto(1cxukpejgOTUMLA99BwmYZRHjO7>-XiDe9un1)HlpV)oCmNvlG(6Az@uE-6tm&mrAcf2O&q1G_>WY0R1+&CRj=5mJ<*og!H=flM z3?Z=p!*`U;2lx1Le|ph6&A%=o#udZrQgXru!TApO;d8WG z{cGa(Os^nb^a5TJQ5g6y6I944#HOkOhnGD(D$Jf7ggWrsMwgM}g5z&F zBVy~;$N>0q*fgnNS4wl9*pO$Icl4=p zET#bSI#vCnLgpIOta`%Hlry6Op9qt+%Uw_aE`2(_T-xTy9@g7Q`d6mX52n-;yFx!B zJng-7H2T9G0Y_-*57}S#dU8vf*zjqYv`o0>+uIT=Q6r<1JBP{qyo-;YSX}ag2{}FO zSe2pv5J&GXAHi{)g>C0BJZ&eGcwhi}k!V=hH&U4HOLt8M)}+gjK|A3>f1LA#h}acr zeB(>PL#@sP1(o$D!HHOALMfh&v6H6^$5tYfqtR^bn;F8W+pqPAON;?PgeuBv(4@ed zrbB}mq|!th)jAkW5PW|wkEkI$^+wX0r)zY7uVlQIB^}z6xj7)cvgF49!ajMxx~>#3 zPWqN@f7JKQ#LmoM@-#fH-YGX^j!fktmddh$I9KwEEQE&;Z`tB!CXmG;1yo_uLOf36 zxeC$>nPJiwE$S%_e%@qFS3Z&%E;}%G`AS``%NK8`!n7yA@0W(kuLXPL2sbWQOLx$uYIrKhq0!s**C{%lb3Ohr#)q$i4k=TvooV`r|w3cY>)< z)u~n}uWB&N?$;Y@FPV?p`yVWEh=C#sT~kMB9483f~LrjAlH%} zQXOR-_6FYkq#_>HU^!hycQ1o*T6~scz-@R1 ztMMa;sRz?HZ>ieoS?#)$Fa3z$#3aP*&i!7uyljdw!kOe41QbltkxamRhcBE_cIn=a zq;ZwcxTiw>EdgNpmQO@qUi7_N1sdW-{eCd>C2NpM0_DIrK2vQGJrd~819NgFUK@9U8bTldq zs}*W|Zokx6hf50`la!x4GJD&EQ_M}!__(e8B zwwA~Y?l?o=j4(OoOSCkQWEzk+O7M2f3R2c}acU5Wk|+z=aadYQ5{t=%dv-V&Og?O; z5oE|ML4DDy{->{2A|aL~$pg&7lWB9=p2I91rLAtgk>9AO)KO^n3s9M8hs|2I6TXOs zn>HldK`@d}vgC$F*w(2wc+1sAKhDFe(C-jKN7UR1P zM$3(Gk7r1Va2Th=;sTI^Pv>G?FARV!iogcY^iKjp+Wps6s_L)i=M>XMO(zjemlojK zo-yU8AmQEO);?LymtXcB$4_%_u;QL&AM{_K8BW4R&Ezdfuw4()57R~vwPmKtGL70t zn@$wQ7dU>9OEfk(wXu!Nehq>RZAe{@+REm>&}-b=lv@_6DeH=dzN zWyh{lkq2%5RzV%MOVpfcf=w)Nf6-nqhPURCe=dGDW(wQnM#4Y?~Z=v~n>r zo*bZDulDpn9v2-{C>-8Q^2{35o_*PB=j@2?vv3+cRSSU-kL`UlK9JiH$C|U`5YbmsP;NJ zA=v)e8~U>1Jv$sghGXV9QAq27L)@HSlLu@1=M!VI`YFw`6!xJyWvG2OIyJLneO1;j zIM^V7;SI)HUG3mm>HA5_8CQ{C*P5GqfjoBQ9m9EI?&=3PUVp@>0k5EC+0z;s{UKr@ z9}i7QXE186iZv-;X@X$ z=Kxb;S0cF`W%!qf`&8flflQe$Z+Mde&cVvtwJQ{^(@!U>Tu**rT`OA2GgXQY?{W2U zS^c+h$*S*M&Qa{6e=wHsSLvGg7n2U<25dFaM;1R{jZZFQxMY#VWspMjM(Rc<$Ay@L zN-Pw8r}!#muI_|&J+nEdyk&^WAX?;CzPzTR7&s|v{wrn&E`TgUcWz0USoi={bmU*+ ziScDWex=YWi-(2m(T99TG`VzwVQp^pwEb(>zZ5SNl~eR2kpj7`@+i2W*cRMt}G z!WAX-W^ndTJ#55JmT}gidfFXW%ObIg-t-+yN~bTijfM%|W+4HVr|~K$U&47JTC4Ke zA1L;hS{e?xnWu9-=;^_iwO(zs5r;2~6oB}GxKviPCP#KaYuD6b?su2o4@gj%>c3Sm zx^VoZsg7DiBC6$Ht}VKdv5M8<{Rh9l?$WMhVX`fF5}`?vIy-Ab$XCKAuCA3VtQQ_i zt;m^XnS-5yJCiHdsyzsn8t0_`0};h-?lRc96QU4ViHJb70B37Z7_E#%&DNUTVX}mI zhC(*ebjpUYuM)3Fbw!5PeoAZ8B_VaFq+8c4DXj#kXuLn1UUt?!p~4N<3yf% z+(8N>saJ12)zr~i*z7SO{Qi9d3xGgs{4@&2Wu}q`Q3kaR-{LMRAFH^ZY|$1pH3rXr zjS!SiL{@b3VS=$Ye|C2*kuuZ9p;=1=Qz1eXbgc2~*YCE~;7VxJZv=dF9tmpwZJ4boIh=rG~_ABu3-+R->Z76p|GGKzqEhE~zSn z1M-*i2n0~AlxFT9l$eY+sae|=AGp%k{ng`G;+%FYi)1SMx$Zty+9X#(dj|#6;~-m&I9FBG-Z8%4*0xPI3efAXzRsc3vhq00QB1-)P;g2CY4NtU|dn91hi0& zCmoy*%j(k8tVHF;((5=G(__(W>haevN$a{B18%Ix4@O4$Mu(&Rm?~D2^t2qn1AqHX4tAFLl_xrAo9^hRU@XZzc>i1c0*x|t4ARsUq{NeHZ z#~>i3Hb1X>^tV&@*N*Ux_A?6L-4S?8o-p750)sgqwf7m=3sn9%1Mqh1_FQIWYB3cG zySj#nedzdJ%q(Se@eJ>C=N&h#p&r& zW9}X{QM2hX^2#~C1Lx&~jtutYm3t;mBH^gZu`{&c6D}3d<3qIE(k9;g6FS*cUgP{S zg?W1Ho%{LHeZ-cSa`m z7a3qy3<@2_(=gY>$TW5hQ!qawRziif4G60F$sj(^0&c)j{2JhGFB zn;H1kyEE9-I^FYPL3S8G!~1dSG^M1_^WvE~`3ExH^ZdlZ>$TlPA&+k=6wo_Har2aT zd1mH02@w4Zab0@Pz$E+k008h(_keufXM102-*-%oe#V$Z#1b9`Uj@X5${%@N9LQ1w zN%rnB0tRc}g9Cv1MA_zKvy?x^8(ErV>XRt=TL*7-d^fLBg;q*@ju75k!S~;BrsCOO zCg^jjhci2mh~p4LB9YGxb*Pm|`G-%IsPRY$j`pLOorF5uPGMkvi@d>hcfNUDU$^qy zOyF85E3!GgTIGRi0|uGF1K{){pn?;xE6nI6FGM={T2^pHg5jWeceDYw=_Aoq#N0qZXzRg6A8n;k2O4l`Y9>MLu|TgomOrkdi|q` zm2|J26Ly6>p}rRy;)8f#N(Sw}R40#MldSBGOLP1i>Q;g%u`RUAc8fUA2g+Ij_R;-k zFKYb{^jLrxDX=$TV zM|5{e0%V%AKC+~!r1*;UHb;QAx9g+j#@#~5lUD+brt7rZ8 zIIV{hZuetQjKZMxt-~kq^VaPjgIILi;lkIipjQXqFre>N?mZL)l$urC`ylXUeG5bc z8t?tk@TU?G>9`wsA0+WlLb*68rub60@%D0z^6@p`iNrT*i+%ym``BNK?{e4Y4{C4U zA!H!&<@=z;pKvfc`0z?_qMZDPHL?r1JRk-L8c@Fb@m=PQ#y?JLbKO45^i5RgrAm16 z?GY)_zWz0HCRpH_8-&yIk{K`v1ncKzn&Yg+`Ns4<+~u1(@Uq9N&NisbnK#d4KtLcuJ{a(R zOTy$#Rv&*kg}c=Wj ztI%lR6lLVUugJXtA&s?Q9ngsdIAaU3uSOYU_PR3k#;wxqfB^aCB@DcN#vwk4rny@p zlqQND<=kpkdD*oY1lq*M)2fHR91DYZg=I81Df#7Fl|4@S(L{uW75x+H3zlXS# zNy0hq&W*{Y6Ggjp)WCnJDBykNByem1;4?OQ;9ZIm@!{hAARi>K^`u9Z1r+MbuU;L7 z&Zp}`dOUDVc}{JKTnYrQ_t;!59H|G)r3!H=O?etfu^vghJ>9GGf$x_Fdn3@w z+zBPA+h_eh;7gAwhCnj;Sr*I5`}7y(lso~0z)jx(Tj_`y0zl2 zpkT=^o+`UrM_gQzQQir=_F=S>)a90F7`GDONINTQ`~0pv1LCx4rqP6(U#fM6q}RU_ zt$zlw^RhE~$2DdD;iK+;nCjrO4*|7W&h|dN7lfW3;-xiBz3;*8T;9Oi@rCl7RH(I8 z7<)X4MT2gsOpf{!DL=}V(?#jrQVX_P`IOVnJXGUStH#G#dRtF>Y_q;j^VIjy7ujLu zuCaEi3M!xD2zA-kp$NpS0ZZSYIY7;#iG%RP0y=^P@zK6%rY+jfX5mWALyJs4c4VKc zqFzC{hMVD1FSiyVqSCihe@M$kdQ5=9Vd@>i#6cyhEUNYRG!V0}(C7Fp23@=3vU{O< zu~kV>>e7M(lAeU9XU6@_=k3I%O09~4_2%|2$Dkqs!7U*|`WTLRpr!cyJZ_G-JMyAt zmBb0+E*($UDab|s#;qGFC}>GcgQVB?un7roN3iOWorZ}G(g9ba}KoyA!K4%7N1Im^DsBaEPAE|J(u<~ zKss^Qf^$hQ_VQh<*ilvu)LIZd5N zkxhu}7E5qoHVH+|6--kzpOkG4SkJ*s=WpfOw!XV-wSf6y#^2rrlh;pie8ScJa-q+^ zS$hoJ_?qRC&1{L$92Rr{tre0sy1 zBsU|(BX+BsSku{>I66;f;7@N?2g03MR^RF_bMbw10b6hVtzJ|1V9oj2vx+iX;_*3= zO{JvL6@v8kE^mT9&K4h^bu-$N+}pu9a1Ko#2xqAa8!_x;?EK(g4~aSOlBA&61Savi zjM%@T^;3aw%NxAT{zY0!vX4DTHaLg`Rn77q_^A-`wL<+AK%oJxo(7qM4}H*Z?FUhuJJe4XF>l$Vk}H;_@H0nRrGTxC zbG#28A8BEw4!<|-Nmx+sMXaOUxO{8j>HlHxEr9B5mPJu4!Gi@z@Zj$5A-Dz!!QI_m zf(H)}92UVLz#>49g}Y?o?hDri1b4WL{Cn>@_3FH{&pY?XyH)qAf~qxN&rDBuPj`Pk zJu_?krt8mKh7Ru9yM#VVL3VxB@+8+nNUr)3yX!4?Vt%&XTjWc7A7T`%41U>P?pn>i zbS=Tt0W=#XQtyh;ihpvVmJ5W4kj&m%UqBxM)Jk(JSf@Rk+aY%qBRu(Fj(~%s$3{ya zjT{VIe=oB5Q9woX6f8+8=hKLF-0mNkV^1X$DW#juBVU1ngm72c_HcX@8T9vYNxLAA0(JitWr*BK!js9A?!ibl412ydZ(hJUPUw*HZN+%--*2Gk8 zjuZXc6&B%Z$@=hB9a!~52SmhsnSQsp@fqJ#ywnzSkjzuHUEVLdBujggR-~dU(obLo z1h4;~DQA=LSH1sG!828JO%dbUS2bUBAyrF<}3^dq*pX%W%m!D4x=x!)F(i+83O{=C*r9^ zW6V4;g}Qb}-*e>roH7BWRKo_g&FtyryaY%u&Zf3;s;42>)4$=x^N?7a>x=N*$q!j1nN-QP7(n*&?BrVvinW->?Re`O=`+iGi0aF>mwGP?R`EPkM&0Sm)3kzxH7ZxJ>*4;ck z@m?$pJ&mEI-rGl+rEF$@!$n{iAOdS18JI;X>U+Vgpr9~mQ_I4d`vkV66K-2uU{G1} z^Jn+<={CblG)Ga!vN5ao%me~3*g3oDPb@I7U6CQDiu&?7yXxlV!A)>#dQOfZ{ouo35UylT40o^n1f_^6GPD0OTIv&QJD4Fzk2AfXvNFD|j#nag zG)4Hb5rz`;aOVYpeIfW$1noV)S=mPsq zneeURU>efa3V`Vd-ps=H^zRvyr<*a_G|Q@BqF<^(Nf14@u+X%*`A0;3y;Q>YBaR?7 z7W}RJ0wd~d0DmsMqq(uZkjq1hTcerp=3JylgBwOL^#a>V`+aJ9_$x7jBl9Z^7>y!( zOa@0r)ahSNH;diH*8EPE57T0nhD{5S02MOIKU}dm8rX0$a&sD*5mKQO5aYewYD4y! zSgZ{U6}l*Ixf6PW8|kz&n#;2A;2Gt_KX`GlP^wu56I4|g&VJll?5_$cDq>exjXBd} zF2kSZ{`|{g`)SV@BliCOew6$Bd%orv5rXI{n81wh{;bLP1HwHK(wg6G!f|tZ`drps)*BKxu6R$pJ=-NVBGE~EO|+Oe4#8Ar#X zltHT}HM)DTwF^?pNK2!DX%5e$W?)xb{SkQ@ zi0Y~!$%{n!-rWNmWQyb%ycdps=6tizH<|Zb=BY_X6^^Ixu*+%TL^ehZ2{4!uxGG)U}gb7myEN~)QqXWiKYI@8J7n_t(G~b`Fk?nbr%Q*0VykrODg1k1p=ONTd z0}ESruKXml>59v|sg5%FW1gEWTTe9|Vi%~iTe<-L7uu~iQHPdrgwPA7WR2NO1f zBq^)@G8NQIv<~saT2D@soDU(_|I=)6{;eR-^FGvK$|gB13}*5EX8k^tO+8t^<@43Q z=4^fAt0#o1mqwdJ^^il}QYQ3k625yX`Wg0piZNE&v@F{B-O-H`X{2Po8Ry^Z+c<%a zmX_B?!zpN}#h>c6{Z3B``d`@P|6A~XJUxQB>l;!2l8$9z*Z&dz?#MSdI5;!>nFfve zJR*O?0{nOH@4r^cf`=+tgZ}hgFEH}|Hp~9ut^Ix4{ihb7jUxf?RQ_VZ&!WFRl;muZ z|2Mus{(HUt|DA88e~u|qF#O+q@P=~@$ZiIKWE*OD^BenQD!lqJmPvNk)3-Bi(`aEwjS48kjf`z32IY} zrsq0ZvhC{Xq#=M^Yhv2!#P3Gm-Yig2OYrH`DYrBZZXBDwF>i#;+>IT<|eoS}f6~4G@&*T@G7Wq%F6SdC(FF1e8l|wX=)t3MLcRPO*H<)ihXH zJjDz3faaA|CJpz;rr0CU6scsJF^tNUJJKy^9yDOiR|*ex_n@-ISu*Hf4r?_=0J1%+ z%kVniP9MEFHuVDb%(m)Sp@80WCx$21y>fyF>x@Fa}9&5~OqS~}xUc~mW z5Jcyz;x-;cA(=?X9=n=0h37RaK9)h7G56NQGDGr28bY!^$)w$D;1is_BoaeAgEoVY zHitUgc14Ze(dG72pAd*{n)NWv!Me34*|ZQ@>1ElRK$#*xfx^PYmrPY%6F+=)61%Xc zS%zO?KJxnpTx>ns5o9KmolbmzGKz#YnDszFI437__k7i-<$`I5{o%&eZ@-&lb(J+y z9PSfZ$F;Y`DQaGX$7s$AJV%X^mnmu4z_B^2(c`+0fb-kkBA(n7OKS%l2~~Zp&+pOZ_qqTS;=}^;yOwAwdZXY$Qi!E-ncshFKPz0q)swJd8bP zQ##qw-=u3ba+j?PYT|6`i0RdtKU$aT=7`oo1b(d^iNZWGN**g-LGRzDN}b0jt0$bN zWy_Fn24!jtnk9%z5~2C3c~$I=(h#38`9gWn^oqPBCXSM1Wazt03`QlQFyZ85=imjQ zw1LzC3v_O-1E%>RP3=<=$YK z@a-nssU5WPcr-{ke7hLCGv_uWaT{2U7S38D*r*OEj@=hr@_jgolL!SQh-pG*P zkWQE%NV#S%ROx&>`Mkj)hmV+>_(RktZIDH*G?zGq+x-oZ1_2w_L#N^I%^76=lgOj3 zCYjq^1e-z<)A&btL*H|J#&dT2%cFv5;tI$7Mtv5AD*61m0#qak zm>E-)AiZpx5;=AfD%@CHO#K7m!snr#p&u_&)et4#2A?w)N~HVL$b+=I)2MW_k{Cl8lfAN`Umo=G;c{P)eAM*~+mD&UwAsXUmq6;Q!aw*}jDvv}DTRUz zoX#hrc=ZA=dhvH6m0V*X%nCcO)pEv&4Cjajgx9DGP)L>Af5p1rQS~TX`w9R4Tb5Yg zy5XIm<%xMprU*t1*~U)sp=BsBrk?;U9YF*41cj^9D?r+}WEOX$H6-%|~!l=t>8Y94c`7B7QZFj}kn&%nZuuy?`&=%LoUp1&VdMEX0*jIB*+2x`!qJt$>P zI+_NW8x@V-C^&o+I&fs=8Uk(SY=_aQaFRuhLKl0*%@exo_#Rr*FBW2yeV$()2OU+M zY+9;RvpanP$^t-1+gDo?_=gW;`A{o^m9sLuEPfuPJm>UNbRp1D5|)b-w}g9sosM?A z_-BinBq33kFIQ0N)EuE+4VpniKO9D}Gwg_IUBi5|=*p9;3D-d-l~MZCv!azc*zJOulOsA{5+sa`~LClaRh%pXxJMyRyYox=N z*M47~rgGY!U3!i-xY=db?LBwV^Luzk>!Qku1`wOZ^(;iiO^{2fbFf z{NWmVE=9=ZBFfi+KGJu!(t=n(g#XKxkRkl`Rl_>=rMvV_tihUJu4JiNVXJi0Vk*7f zOb*lFh_dUN_w1!Uc`g&d8+L!^t_Q!NhgXrElhy_T{s1GYb`c>7Zd<9SR295scdRBX zM^j(J3^L8ET74ag9Q_TG1r&(L7iv;N=UxtMYLX+%5kzu}H0o8Y5DSm<8_vwqg-NNn zK>x(aB}f+_j^6&s`s%dzmcF&O>Dzl$PJIQ}M;TFhOZS+8Dsx&x(T)unnO$2AdO~@pT5>&x zKH|#r#J$6HV8jL2xmVo7C8>p_O4zTS=&ufqk1fNSIzsopqJw=$QSC5eK^YZkQ% z0 zmeD5pW?aRQETif<==$~Ev1;%D@dGu5Tz%FbA(zevnC`j6ovp%$d&G_!f~yxv^R?v@ zqL6|Rt_!_cTMVeZAqE~X9%Jh9I704m3Vp1co-%x^R#sE@QJWwJmvh?lLH7GdUcm?n zKUe4UD~X`&UH0=m62kZopUGjH=vtcQk_Odx=$%h$Pq`8FmJTURixJL9mii74Uf*P> zQ){i=^?=-mhb__t0%HhUd53oS4E7c~hF1eT9K23{itS*PpSE-j+Kgv)w@_(LVvNs3v`KsY-y)r!R z(9Jc--dw9(%q$iUsWW(BxqK)r-q@9*7s5Z^~ma5Tgo+uFwsZ<$N~+M2sO>3^YgRkdERQb~-Gy#&c~R z`Fk$F$$8h=rTf@eIu-tok<-sqZf#|N?zeV0{|Kz=KoogWE=AF78c*+_Li=5w!vt1! z78R$HfxfgTgO-m1DYWx7Nw*&ExVrT<_7>zlGtHL#FCD3-s#5QLkq1VV%C9)Li$L zyuj?6s9kDsxZOP*9;_6*3`JGRx(RC{9G4U)8wwTfw8;TmPcIJrAAtp2&hWE_nm?G#s z+il(DC>a*Kg2pfK;1CijvkIrPbI@i#E;@)PAsw|y-g7MB(@rLYI8!_sI>{X!jhTXH zO*_mi!O%Ilshzm%Aipqgonn!ewrfJ4T~xz`P=Im?wfMO&M@ywt!lwRfJI!EcvmKTT zLy6>;v`1$0bDgKi@k*ptg5zU>s5aGOufjQNV^hc<|;51n3Zh%wZw5UfR6?)2z!-%(s34OFPTs3 z=GnplKmFYP!?J>JKwOV}#{2S+LvHa`jTbHr=>3K(ejXN5HG@?@C%?Tvw0M+Vlh=~< zoWLQb)7Lfwq6oq5P^a7FQwT1R677z2Aq&su1PT#QY55<%}#x_fc1C^ zv^%e@*gdzHEiLnZN=ZoKwk&dt_k7n?$aIILNbHUBh^y@2MsEr$nD0=coQ)>Ljn!Fj zV&Fwdeh%xBL|D99Uf|PjYaN=b$b2|FfCf5!?u0(G*xLVUqcAvv@8Co%g_vf^vG8qn z5D(DOUTQ*$GM<)GI6K#+hdEx>IyY&}eZs7)Uv$?SY7xm9*-sJcesm476QKa@tp#C6 zYGkY~Q5AGzqn(eqcfQerjwu%JX^I+GnT{K`!Y!RkDEO_}fU_ z7j&|PMqA;#X4$AijINnh?P%8^^sMU}bAz^dw;_u}pgn{9HTF>4+e0s-$X{G+r_h|X zc621`XtiVSFbMcKnMbQ()}h^87{L9dlv4#)}4$!n||7s zX&Mi1UY5F3a$mec+BN^8>Gcp}>>lMQh@#Zzi_y310|i@%i>`Cw5zV@!sp@p=D~~Xf z1o=XVl3QLj`beK zO`or4D-IWdBZh1Kh&XGx_;@NjnLoB3WD{k>8GwNq9#S9HBq>$L=e!AQF%y+O8&0Td zDssAap+4jNt{dW0AkUGxIUXH!o`GvFM#xAzJUU z*sJRh)hVr>o_+m>ByJ)l*a*%_Aqhh}04T7eA&C;^8u(P{Mwh@xxAV~R@1kmLRR2UEKXci_s(xeCZ6+Tt3VhYA&4SDGT0XAVK-@fjGJ24g|X~O4so67 z&x8!o<=o=Y2A}E~%)T|0p(E`G!yh@T7`I|g)VF(ofPjliS^ARntES&;7S)Qae%8)# zy8h*ARv%B{{+1aL$$I$@3 z{4d44qQlo0#$ldP{@u8n$>81@A|bE_(=&pa(J{CkstNZ*y9>%~ z*vdO!b!^kE;7&PUeH`k&rOeGQ#5tH-SLb<8bqHHyUxH4c((E4K?@-K5545*4(;1Lk zI)mKKv3P8fy_H3MV_;csUPU1q)_^ro@zr`IV8aCXwxA{ZLL;$G>yu5Pe9Q8;w;7Vv zu|XYRy=J}qx4{<{DTNAs-e>6w%+q@_i|Y&JGumWL;w6rsfc8SWwvNU3dw~lwHz;sP z>d!h80_tKFIYorPlWwo&!5V!kPIkavH6Ev0GKS~Ktj>F92nt{xtqc?E6NJ8M`0tK0 zugh%DM#o-Lq-Sj2A$8+1%!5s{0`I9+veWVw%iA|x{qB!Hdhe>miTes295Bq|y~(I$ zivK=eq7}9a<~DH_l)mH|T~@xaS-`ls98FMmd06AF-GaOK2Wv2@XSHd4^1-K7adNOo z2TM_WnQge|wU4}>i*CLee5LREVss{*7F1gAII5Y8{S#{})1W}xz{rQdYTD?UdL;1t zH6ZXDw}$B>;Z8mmVq`ZzoieL>1&^^uMwm-dj~m;&1MK-9dd?ELqTwGZkDNJZ;nd@&7aWpstET5Uf+1TB=8?!c+4-DbW12PZlaxk5StIB;P+d4DCydu zDMGNHoX9@2+j96Mj=bvzyStgd`+yCwIXEe-@bOWj@@tykAyYFaYL8WT(4cO)ZlSn$ zX}4Z!G$6r)Q~%&+J&j!Vn^7$bYtY;CjMu#q?G!Ek-h0fPE!cS?uk%Gb6A29jdyW;* zH5@J;?lJB2$ZQ>I)(Yip&IMl<4Y0PmRK%~Y!sQNg4>&#hWquM?wm#a;Kc|*3 zu2a^uyfF62%L7<8TYCO3R03x7_S?LH0v;9&%&Z&$vZ6{VNlKDDt_e9toUJ=1x{`u< zl-|ajy(ql+O|OI5S4$!9e$wCtR3-l`ge@CcM@z|hyr?=oY)TWlL@PGn?+cUt%5*80 zGC=VBH3_MSuVa+c4@sUxYT-w;N)fT%Ysp~QLU}53lbH@2AHgKaNZehh$;Pk&D~T^4 zm6gt`B|TpYUHyQR(ru|mcfXc4m5tYGVM4ix&UxtDt0Qu10q69&Dh^s1EDpaTgX(Qo zmsJpWusb)!@Y}Qe}}@r>T9>3%N=fuNq$sktznm6T6bIlvTy~PAhUS z$k?ZGp;CEx5=nkg>BF0hT*rd@40N=-bPRh}bV&pLfva4sQII8FI=Z@|-+rdwf!#}a z?JabC1X4I-iLn=TlZnC(n?SyfY$B!fxqAzf znqvlan+tWP#{6Rj#Y1Ukzj>zJo(zsfSnl9pG|5^ayDu1M;es7Ei!{XRcU zpB4bKus}TP`S}bax?cW=Zfo4j14>t=rOq!cgKoE^&?rgA-!Xfdc6nrcUX~@A6#Riv z#Q?8tC-Ve}ijZNErnzMT%5J!>cg6fXp5du&pnkLFw-nglG|}}1_DP~}?e+_r4lq(x zvS`VmMJ+5B7Z+_tNHCYqvCaWrqU;88e!Fw?Ku80!83ew!mY%z44|uMIWAYZIP^}x! zS}QBRiA{+aKs}WLQ?9*h*Vwnx^Rl$}I!xBKVWO9yk^34uUT{YUUu)BD_M{zesRko= z=Es0ItcWgZ+%h)##It3bC>m=p#;CS1cybY!3muk_BitkZX=5j3QDnYPTn0&kBl!4* z;CI4w{eF)6FH|4x)M7DQkH-8lYWpJLbG1UfWTN(ZI0#%6n7_W0ymEtOoD3R6%mxCnZIZJ4kHy^>DO_9$GPM#5m6yu zQV|m=)!dwv(;i999L?5uX9@e)9+!o(SO=!xs3g{gjslcQ2(^EOS??bd6}Oq5$8`M( zeD~;mU0%93Q+tE3DcGZv*x`@pCMiKZ4}@t{kXOR41fb9+`0$`&RCBW;FB6&7AKMnFpq&73^z-*3F)Jv+KrQ_Of0Mq7U!Q6`A=h%J@kA<^ z+XfS%MnGbrZejuQPPawY+as&WE@4wv3^CjJ203Ej>}({$6{IwF8zL^T|k9>2cUVO%HV|;e4JE zmqI+W?vS^CTZ@R?lJTP%D9!8&_zpVHBm1#L`5X6$9DnGr*j|a zJGW8lA2yG`v%E_y5WX&K0 zB%vE?iS>nu$$QdYJ=S>UI4A0bwOj^%ApPET=9Wg{Vd?tSBRPy(Q!)YPEdmuuJ9P-# zR>z{Poonnt{Bf<=)(MKC@jBddKXTKcNC}EyvzY3iWm3kq0?Mh>nLowx@!Ip z7G`EyRaJ7Z48k54%qC|{Vm955@eAr{)CvD8Q%U*Gqo+Syw^$b;7iELtk}AUeZO+0`mA1J7xXZ$ z7@|(w_QjQ3rLm65+liEN?3F21mttyg0Rfxobz|Yr2n>uoNdzhRWZ^mJ%R+ff!ITLT z-qEo!$?qac!mqmN<2m$EaOHUtZ0solXm1TI(J_mUFWrp$cwN1>uO9gJNuI?Wu~n@< zSd2{cVG=KJI3FM>uxZQbntm=(?emcMI^;2J4=rHe9J$6%h?Xx@>u|Pk@Z-b?apI3L z&dPoh6UL4aLMr58Bz!jdZaMc|M8o;CZVvj-?Zo}YmuSxxshCW)Qltb$jgHw{ zw-zDMl$4b0#==yCy?T1CUfvZ)kkRNcxbB01k$;u-KidiNM@D&Y+a}YLQa+=8hx6AX zkWTuJDuaOasXI!_wbahqzu-Tspw0YMMk&gm_k=y{xhimC`Kxd(=|3MZayxrp@UMy2`|{1VgO5$3y5>-lci5&TVj z2-#!*d*tUI*#9%pMJ4mvZY26Udh{w(f0y)sLZE-v?!Oy>e+@7l;0Y|F_zNi) zx^Q^Sfem`W1{c*&!~lsSjY;X@Xn%s?B$&PBUg^680!Hak`1tyIZzRYl3)omK@YdP8 zf?4XZqk9a#%@2f?YcL*XANe6K)TuOPZ+mZ?dIQ@YV9Dt|f8HL_iCsrp*hKaRTW#n_ z5-=yoI_(yw0`_hCpTXKA6R0?l$i=puE`O7*2-qYV=%Gjj8HGmCgUyzz5!UTDLuR05k<)T8L>8csPgq2fl`05wc)12 z_2Jt~u}7UtrRH6GKIeTUTYhW4bEdXvQY^6^zE;&$p8B>B1uo}A^lLx!wB3-$9@0Q} zLLnC#G}q8Bp{iIK|&fU6#)CGz?16UoqUD#vuq zn7TNAOw89A1ar)C)UsZ@(xs`{@rS(_wVa-wF5y{x_uoF5##bHL=4`jFIl8R7muXEI z;l$Ke`GrW?GRkiZlAfPt;nqgp+da&^!98jQ@U-m(NXTUnxDTJ{xATX5@T+pRrE!5B zSceSpjjEV{7X&t+fY8Z8kjad}{!%v0$%bv#m~zA8FT3Wc@mhSn@0Jl#HTKGNcDA!& z&4$35H4d(945cYsu+BL5P**`$8bHFdKxSgANOOk{qhb^%4Ud;kx!1<8PV~!oBZTt_+^DF1c=e)hEl^I5qurM-PDd0!F!Y! zXqL!e5=xa_4*40JB8!6lO;E|)P7KR|JWtK_)63mDsdA77YP$F3wTXx5c?e0*G2PX) z%tH(dRwdo?V&_^Jb1>!sGh|j)fivnurWvJBFAz~`4I_btJ3+fH)Vxfso6!{N>m(GC zOjPJSa-FsQEhwe%z)ZpvL!>#x&i(6wuE!4(cjAiTc|-HG)-H977n?ttox_WSv;yR^ zcJf$LNG3cjYtiAqg-p#b7nfBe@PE>ci1fEx=IQS@L*3dRVH5nYS11Z-Jl(&ux_qv= zfm2Vb0SC5Jh=eH*SiovrUk&PSbOIXzr|=`Sm}fsp^iLh?#kfxs{1i##!xfSIcA zBQ%Yt)-N<>ssu6KAVPlyc!-^0K3pIgu8vuKvKg6T#(eQ3uQ;iWs;QJPXCpW85zX+n zbL7hW9Z5>tSIlH%K?5{}fMg#f;o+9Y=5%B%_Y+-+KNjC$MV)S;rq`#V$05jZ3$jP` zj2#ugkEZRhOKfASki{)RZ_m_sx9Rr9Lyi!ciAy6wEq-~+vAy3}8Tsltrg2_T@5>xl zgYyvT<4FatqwVFs!^bHZNYV&rbzSt;@X<+XoA>9B{@0#fUFTBLWOodYr;ke=CmVRe zQ-P#>e!p9qA5Cp{cW&VgZya;Bw?ULthra~27YjA#!9e8J9!TJZt?q0{IMv!#_vrW*7W!|9HJfc(neI zO@#za5xBpW@?z-EF5o^#g50MJ^osd%Rf4W(7v5?%A76ScoI#FP)^)wTWYU=y0)EZ3 z{>Je25Pjwm+cK4TJs2<6>pq+$>{4A&5gMK9dLZ{E6G2H!rcSQwB!;?p{9dseN}T^^^m z(f@v62^<7(&lLoWix%XRP`a#o<2+d6B}5x|2k)&+2=C}A*n(*t^jy;1HdtFvk-pk; zWuA#$;ng|#C$1H@jx1pb_oj^4nW*y#`|MmVLGPwhz2+UvdbR@wQ*Mup!F@U?jXzvB zpc+k@{m0#;ITp7!e6HY+hwDK{k2LgVXS{#U1*mWH#mag7WoifEgFmZryj6ZUk0TJh zj`h9TO<`HQOxE=}y*co^iKFYsx3MfXA^d(?L5_qlTKhR}OyuPSnUSvtz`iKr+a;=3 zpC{;k!SgpE`Ml&p>w)k^@<`40QvGQvB+v-p3NT;Lhip7NE=qyL>{bC0^*=TrTaz$x zk}7=H@8(m*dhyeBuaD{jW3Yy6+E^g>6i017pB}FxkE&e1E50@|qicApBYHt`x%f!v zXElLFFjTq+_3(xUHC;axM+t-6nZ&$*kf(k7vd~GI13ZqpgbaJu+oczawV^1Pl?vA; zle4vj4^~_F#1Z2n67VJ$yy*Pm9E<-Wl<6GdCfoIOi#x*j19jG5u%V|V#pm*bTt zB>Fq2+u)Sp;ii?v&U@u{(f_uIA>e_@Zi%d5duDmyR_xr^VEj(`;ifOJy&_YyJ?jW| z)I@!-^sRO4Sw*&Gg@E#Mgrp>^a3eE4C1Lh2vy@f)Oa=!(K9->aJ6Yy8LTQ^hWd7k; zj#>)&Qwm2OA;j|zsh3Q!I6J>pn%{(tvP-f%jP6%c!abA}Ol>xUf+(J@OrQ`9J9UvMsM?fO=Zmm zaVYOKyorNb)k<{2_<_!K$vV5gduTAyTee`OG96?&=R98576+L8uy_K}L@3i78&7yc z`iY)thuMMlJr_!^DK|Bq7JP`CZlYH~D(QkN22`&*Ij}iMDmp*Z@KGLk7jYnbzfvQ7 zx{P_sEUx)1pd&jFluhop+t2O51V7{dMa=tlQ_po=-A~Zps+7R{WdeE}%&FEh`?XPh zFYN!Ae-^8C=er9}=7Lq-R4MCt&T-LV`5N<#OIX9Se756Uq$*tub|m51nVZXiQQX^+ z@BtALVUix*MMXC3UO@X!4L>_W|@ezf->#7QZOfM*ouBmqs>FZRv&McqES<|LhY% zqEbb9yr={asul}R9jV3gle_D9>DRMr#Ws7T>fQYF&IH13(wWdsBsFV68~5Niu;0wbxEYCe?-Jc` zl`9WeG^qu(ebwngGLJUe0vaRi-#ufzHU=0gp| zHX+aDX!isLy7SqOwF?{XNbO`@gy1>Zr_FXf=zVsv44yI^qTg~$|ESIWfPBfG z+>%m7#4K8b!>D+1U}~2aI?)=3Pp7ALYi4g)7+}`Xm^~soXex9&%k#c~S7e}dzIVGW z$1&$z4FCrF)FozIFpp72(1tHawy=N}0 zyS9?2a`G|ol6RWB=QI4A<kiX+$F|PF_ysM+&3o z-~3UR1`ZT`Km5W+W+t>j-XW*wv^ZWgts5r6>#}N(Y7MP_Tt%KcD`L_jcXRqqQ(Xub zDf#uYcCK2is*Nvt&fSbB4kuK?QNZSgc;SGah+u;&*KBkU&>S+~uL&KDC7&6&L z>7bU zPlsW~mE#Xz}ma?X0+sH$9rP1+?xf^qwFyB(6fp9v3N(sdLZAbiT)9;w!s-_-YmZ%*z&kG1Zx_Y&!Y~39y#y66f;$dHm^~)u$4D zYD13_9NH;<2*&d^WoMEqE`x8M`?ZUo4M}d~CGLxemwqw7Zh}awFw39y@279QU$-o2qdsE_gWKL zJl}we2P8im;?zn|XgEB-JO+y_Ty55oC_<@xA&}oU@ehH1m!xv+q zEFa&UHRRq;Slzmy-u`|Sku~$f&K_B0q(X8VF5(p_6Q}zksxScQo_4x~*7));G16>ozitXb5j9m-dRD)p!(M!Y&gDIs2 ze8&wM;5$h6(Rv6Z#)QwzN!qsDAtGNraHi!xBxcbcOYFWFvauET`K>9J$C9z?josuD z_2OvvRNHOS-AU!qDv;bi$+0Im%_9pOuufVIb$A1a8Lfe`J2qd|-0eCBl6IlvGV^|c zg0jS}l4h#&IDR2m5E*t4yNjh+8Vh|-dlRu$|A5KYcKsZvk1INq&`zJUdx)uFtEJNT-Hb8N z@ZLS(rk()Q+0<|z>w1|=Ip-=sejlBwof?TNX8v7Zp0&REvP^6}BIiNL!J*2iTKQxv z-f1q}oEi^)&(;83N%t7q^l-Cqmx)KGSBv5u?S0f|2zK9}_jX=Zw#AL9{Q;d;IV~Q@ zIay*c+|1_-44O>vEZ&owcJx6e_upsIA_!k`u0c`GKVU(3JZ8E+FoXHyRW$DAc#T~aElR`&%()qrDAR$`z^H~&FD-)Pty)}C)P=RsWlj(J2@7xLI`srSa zjn$<~t4Ky1WaA@1I!3%>C6BF*mH;Q2ve^EC&nrzDPenQWn>{Aj&;xY<0JhpsQ+Kn& ziLPu+fLuw&o=5iIsn_6@f$q*Rxs_b zC$0BWdaxbj&IQB4k4IOUt%Kja3_r9ad|w>7Iiol7fvqLko>QCourBv6RYHl3#;Ar5=L49-b#sxxz zE1X;&=Dzn*(FbM~Ndv!2U2nl!{3^F=~9W zE~s~ZHM>Qr?;u;;hFdnG+1a>1lnR>~6u4xNB?|K+{39)C|ivJu_i zk!Y++96-A{H$jSb@uD9Qxi7U z$shS+V`J$S9s1%({kDZ5t4TR`)B_uHh-)_4h@1GaK1T|gvH zm(GJWQ*^cJ9hOk*GXa1t$Hxmt&_Ufo!`ZlkVLK6-t(jTqP$pl_blqOy_OjT+y4d*K z+<>jYX@;vlK90c1>+p^;v5Q+G5KKzJOP-LSgL+87xP9wIZKd;s5?_lrPvYqmVcV6| zVaw$*UMpmJx)*lgrD+(kfGNOxD}ADsz4U<&_EoIIV263!Q#CA z*U*av$6~e8tl#&r!yH^scUgpJT?BdU=etu_bd_y&&&6;O(Bq$6YYp5;*lxdQ*HUWj zSNdiNggVr?xivMXe}eSGxFS&se?s+=-E?7pi>>42z`VD=3jNd?2>uGVAIrhkW&b?? z67YdU>POh7fH$><5zS`w6L>BFrI_-sh&~fWe>j#A8w*UODxG7S0gToW9d$SAB9A`9G9> z_&&7<0*31uVRU`V&0Q^khslF{;W)Y$6G#ho7E;o4yOC4+muNTHROlAkDF}6+vl5M8 zHQ$)FRVLWtXurB2{Zd2o3S)eB*6S(IpPT<@EzL5CfE(}MqR79SbpL~Zu%#LVI+F!n z*s&NkwNd+x=r`ro8Coe}=GsUh+Xru={w(VBORY640bn3H72(FO&|mZewpGif;Qo&G zM!Aq<()O4WNvt#>$rsYTTn$Fm3QgF-N5!-AMVbt%Y4q=(3Bv`4mcNQDdd}Rg<#j${ z%IZ<8Xe}6z=a}1phK+W$R2;ECNw1`AqRUWj6}sbG3^m*IF(ORQU{os=AQ4kp-MRj3 zy81pnBTuVTHPcZd1g9HAN{;T^S5J19Xe&zjD~*U1&C(Pm#ch!_mRK!#Ji{TE-U~~0 zKt`U07E&H6k+L_1tAIwdw|p3``3wbiq|s!1l+@?mcSw6Qv~;B98d+AUxNzeY{$YkXH|ITpqVU_fQ?Nl1!gC-z0Ix6?l(hM=G7pS~%Q>8ra}nTe5Ia6e z5doNc3sbx0ho2K7Z=&?(V_e86>z4PH=a3ClG?`;4rvD2<{HS-64YqcL^SR=e6(Kz5MTQ_hv5U zoSE*f>Qkrcsi&(rmFT_4P2WuA#-+H2mB-wjmUyv`c`x+2k=lBobK%fnuyX{t^hUB) z>6+Dl(Th}35EM>hF1Xj&ugRhN2zE|>LvGDQ{c&VrC(K)cBX)gf&2TzrUdd(#JZ z@DWW7q15I;N8D>(#!nb>Ub^Z2SoYU8%W4ji8L~Bs5ps&!e0~%V((Y^9qII1D7>#W+%xZ>tQ2dwz5ISCjrjZ9ha-T1yo%?Z2#E&fV5z%mP+Qo!A<1dIs+U z9tQ#uhNDA)8WT43@VBH5W-SIR%!kWu>g!ViVRLHH zexQWOv2@1d#7G4vnAw^}1&5QWC729eq3sfd5OZ?hRG7()Qt&Gu{r+Bva)Zvro?Pg= z(>QqM;oitIW1munE4}1_Q1F#wbb+&VHp{i|4bRa6BAT#Ad}M|q3r>&waR~o~MM_dC zad0~30t1}qH77td4+lYv9oQn`Cx6#F_C86JJp?xvD;u|}?@&7GUg&GE&nOv9FCJ!K zU@Rt@DHa7zQw>!@`c$h&$MU;UtQDVV_xmnUlZkOv?!x3>`D|A) zAD7oKE*5c0>@2G7zU}1fbZ3GZBDp5_dQ&NQ1}4#XKevZ3jwx|-Yy9yf~ zKE$w4O0X(8?9L)epFo=(lZ5bTgp9zvK&50$qYSSu2Ibnd1%rw}F%k5hy?pK(HAcN| zf8FZjolo5}H4wOvN2v(NrXlrWh>1y<*rRXrShWS6YzCt!EzJib&PLLs;_wTxOIK+O zz#Z+rYwdxF(U5>1m7P^hs?oEo<24!<_Gta^!^8eE_>qulzP1l>78R3-A+g+NK8|F# zcT`wl%Eg%ko(|*3&dKVRV}VcK2W$qz+>%M~Aq?tSB$nRZ$qBYGlAMamuHS&loZK0O zM?T($DXS_Ux09s4Yi78APjIh+J~COgBUCp_@1dqxU4V8FS%ZHT?)IWOr7oN>H><>$ zH(rS+kwZblKC@2PZQgA~gb*F`JIL9XT_*oCFp@wzLUz2jjw(bPbE}L$fx3r_&mhNZ z-uKK$A;jS*l;akCua*>_K4DCWLqzifSSd-q)P@}ys0?!B*8>EESHdfJ1W2>!pNnsqHf~_8Jrb{1b~RsR03JpW@bsiOa`nGIMaNJ+iU)$LTdBu!u<|;7uT$peCquys8(t2 zKPS}r1NQq$biw8)(_*w8{F+pX083*{R}vy{m^D}w+LW5;Ln_pTYtH-2SavLC-BCkw z_D!-X$+PmMiMZr4cLtrpF{JiFX@~h`AEaiPRnm{Fu7as?{1P?H$Xa+8KXqJ7<9X4^3HCwFPc5{7 zTkohe6)Z?+eE8}}2OE{ZyPa=HGb9oourwSHIx3bH5vWq(W6sT5I<}l!q^R%=^0JG_rHkKR1A~sZ6 zc*rDAUmJRo4RZlR#B6+m^0Lh;oU#fQ}ExsAbu`+2&x(H-!?U5Tb z47wgosjx%aP&_j`zJ{G63yii)8zv*kPt{lU)8dOR@No@pUtCQqj*plo5cWk5Mx?Pm zv$nKFIw~fJ{>fb2Sd+VnZKzgXhIeJ|N9Qb9Raz=2XZFk<987&81TLN@p*Bt(-j&}O z<7i_wQr4ROLAE0E%B@jes=K`rfgON9NMEHdr!K>lPVI4KxF$CGjl)&H{bcVVdm9Mb zTa@TBJES;MwXIsP!D6*kzzU%9p?yTZn(qprP36Vrd9y-^5fgu)GXz!Va0N$zamHbm zg8P8(Pj^W~T=Y7>SDHe9vxWxlS$E*R;LW{kNPcpr`R@(xeAKks1_AlmNzR;X<8w)H z(}#&2SE(Qt7I$Vxk=^Hmzb(=W;JlA#9QLICg0Qbf)}x9d#im54E)%}_PPGi`A;epM zPpP^|t6{b<`Bch~g7V!kstN@RM-aPq%`MVhJ($+8z06}@3S6pE=L!l*7v}jvg<)M% z&ZNXm6eu4d$}U@^U$W&xLaYEpq3$cVA=EDgnQ75$kq8BW!vyShe!^y0JIKWY;d;=< zD**beTl{Dq)e!~^Ts#ZF{ROUFqN0dmy+cr}DnF}vcAI`2BS=`zQ%KSFFu^sJ;A@E^ z-UqY<N<;UsRFCnjGEzVq$@|BQ9aSrz@; zzQ7u(;W6wAO$I;K$V=F{U3zJWEc18lK?Lcz6;tEPqddz-`l33lIhhuW_>{>?v&*Iv zC^J@gGt2xTk?@A7L+Qq*LO^T|$k$~E@(m^prOo=n}cUX99hTn20=l#omt=nGQai?q7twf7G-^ItkIE&Ap0 zMw2?BYOJ+(BAxJ4C5THzsQ+w2Z!?2QhvZ!^B8q3Ps{?VhM$wM1 zP%c*x*fPs|ya?l3{jB2sgg!A_d+^SMI4{>-*ijP}FVJ;C4=)cC^&i%M4;AS%ro088hx0>3AJ$=VPmGI^UTcn*a(4;?d z0L7Aw9|Ib1Vn*W$fBhjY~a8J2TG;WHi zA~)-4371NKD!Bzj>0GO$44RiOFZoXSE?diGK@GoJsQ;z&_As}>7=ep~R@`5czR@L% zD24M1I3*J63iB3)NxYwa90>`nN-tmk!a2*Rc(u@y#X1bWho^$^tib7W;^sP~T3Swc zwD5xMVw3->e>buvfibjR&1Jo`qZQe+My0^KFsPv!(fmMr37UQUy69Fo|F&R+rZ)bU zGcgr`tr@fxoUCv&McP-Bun3;82sq%o85G56D*c~}!7$#fVqpq%DA%zw4c|kD(>oAc zgFL@7Hf99-_p$|ZsGsj2nQrs*F37`<0f<`m5yBDSg57d>42GHj$hA%5ExV`<06JJ!ZS4qA9LE^w|6D$yHkA(#%|z(7Q4{xDou#8w~L ztBqDsVQ5he3V--;Fry*|r^b&+8o5TV*`;-PKlQ8{ouMkh#oKqsyR9l?90IAOJG$Hr z9+B%E@OQjBuAx5d*k$*vdQM3Ga@6A8ox(tji~437`MPquEzTTb}cxpKK;i9 zST-4VPINa*fS#(X-4X2!;u0R0ohd#Ftetk_V?JypWG~}X@{fZuI_J*epyEw)5{mk^q>~Y@-@ya z;gnMDBr-{`zmfKdnb~xKbAv0JR00455A7qd2TL@-It;JlBCAeao);7!<m_}8^y;414VG? z8d}+5;al1f`0KmI?-G?=(=(bds~DOz@@wBzGKkEbNBhbl-`YRumr57A0v>B4`iZQM zP-?z-MG0&6 z=4K7^G)VKEzI-H2uxOy6)-Jt?*}TV>r6%Z!;+dXz?iCm)wFF}*&CTc!qBEn~G7j3Yk3z!xq9h=8NVZ8Nw0-L_+vc>9m$OQa9WJuwvMtYcn}!nxhnx41pLPsj*NTR0Va z#uAv439kXx$CouHNORaaVaRYG2|9vK2Q%2!o3P61BEg5rch z&FDk>oRj>wrW2GMBMi0|IEO&$SULiv+f``jKq=j4@!c>-KOe}lAjU{UA>>pLI};y; z#Rk<;UT(f?vZzT`5I*hfPf38#o$XH9lnfQ#hgon@r9((c*2>Emob0ioDaXrPQ?rv5i?Ti|bJt{m;kSGM zw~k1Jw@jix^sQUrz+&Q>1ma)K-o=<`7wIn799s-}UDsQEi;ckTwMCfp>liw#9$h@( z$2RL6%JO2Hk$Wt#;I14VXWU=BdiyqL6T?LC&u9PfrD{R~>6p~rv2W+=Q$1_Sze7y6 zd^p;8?TacA3CK+j4(@ppi#TJGFAMEgYEw)omKUVPc4o!hH%`D^qdRX?}0+};{ zx35n>0vk=q+(_P9+0ILem5uoHObWnH(6m8P1>5f?3UZzxT&#EZ7<5d0K5Z) zKf$aBI3L{ep0<9*WvRt-v<+GB!GyaFi?kxLp6Oir`vpK#xXTx?qDLC-3`K4~K2i@L zLkkT<5#avq3!_6-{ZR3@LoU{ijv@o8tX0r={fQ2fCozGH_{bGZky|qtdoULh4Ll0^ zRF!JIu>MpgB2Jjx8~Ar7?@GRI0_GhMbj5&uKYp)L&sA7;@|IfWs1G%f+TRWPaJ&PD zMVr8}Pf)z=E780{2nhne#l}XT%6=sB&WTnpH}NAQ+XLSA2j@vmXJNZ5e{!UdoQD1F ze8givG+=Rd0S6j?qb=H+qu99@L`cC-XT06o0#fWe6K4m~Ta(?NJPkcQz1WjL1Oqba z2q`cSu+TExM!_B;&Mx-&5H5s}U@ns(x0?N~uxRz>+FU=)Rxt{k9GgOceGqY z7R1(4L`unbIi@e4ETzLOw(kJcwZc=z3%a<}i?Hi8>G85BCcnE&(G=u|)eKqQ77Rx*P zmFe;MQ|^0}%}_8AcyiQ=xr=!cuEfDqe|ZmIUW12`Yc7kQU*_^6oN#ivD2A!ZY@$iu zW@_x?ewv|Ph#GR%pU3)!B>(G^r5V3x=t@DN6{3IKl;9p$*ab zbE{E{n@kmtq6C8!K^Wifs9aoCocv^Q2;U`p6UgykG4hy&t6@EWDC2OWLQB!0`{_Ib zEBtMJGJ_IOLd>F6b$zE5Ai!+@5G5781tG%884?jJ|al%^dzaWcU$Xkm^kj2 zkl2-HGi_H?&V+Mgk9B&Uxc7;7JHEE;eAa53NqG*4oeJ{&gwkL) zmvaeby?Qu&pv~Qc7Dfi%)WX?8t;d@$Z2&{e;z!FEG48d?h z^|E($SmEtDpF8z*^4`&92raSEPW^0#OT6928Y;fI)m?nv;bD`ZK&5WFvkt4d+~0*L z(Uak5`r&E^S#DNXAga@6mN?^%?Ju!XuCtyk?ku}#hJ^}EQAZUVpZE(HKx!Qxw**33 za=N-i9v&VXy?FW+H{*v>7ZcYu9yj&>=%Im&#o9pd#&_I2_y_;&#Dh~^^FVnZKh{r|>TWR|N6{bzLX2*t#m{~3Id=KuV{ zm8aH*?iN376jcGeufz~>7}RVXv^@n-{I|ZJZDvWw6bJ|I0QYu-E&i^2GY^9y4+Cf} z4z#^mK!o()0-2!VX`4IDOQuR1fo8N&Nr_?KLe+QZ{=e&X8C$Cz@gNzp&Iq%~;Cr%e zw$S<0)qNo|`b-Pu%2Mxt|Fd~S-J8yae@o9pG;to4hF22f^NbaP`` zMM>osph{s|%lIGj{vQ%%IHbsr6J@6!47;kC*@Zt5*qa=!rWe?&+ysturu2+G>y#GU z2wI$weH4=hu>M(7OW$hk2v1;%jg$3cL)9^KHfl$0k71RZjiEXv`$zp{D1-(>u;RZ; z4Ftvx>xl~Wd>M+e1qHR8Y=|<>634CMYdEUYv|$)8f9rbS?Tgo`0?!n`?MmBZfOctQ z`|;YUY9l**r55u)RjNADjle+87yi+41mDVvkkPeG+J1Vjp{XIU>G>Ilua=DH^B$JM zHrv(FJz`=REXXXW(RAyZf`6?NpJqQ;TPYE!Oawpu`;c3xqbY7LtYHOHo^Wx5y9|h= z75)1t+FO%s#YK*QQgu3CE!>>;>oGVjPWC~OXo5G^5y3i8q76)YxLl4}`X+AAHMj{M zqoDARbx92mGR~YJim=JW0#gJ&-)pG zHRv(=KH^=0WAH$j3<*;Uqh{JPH@ki!A@)Qq$96oueq?l6BVr-KM_5IO3n$dulAO1l z`No4-06zMha$@}U>N{YiB^~P9nZ~M~M(|&LWAn9ElEskv(AEp;c9ANiksc!uC~yrU}xC1UZ$Qj9GY3LexqM!&6{^N|;X_FF%d%7F5xwW!V9 z4|(YX?ze1G`w((*($^`^e9Yar6^?`n7m)r23Z zxDKDMZ_#UcmT12z{hlp{Te$}<7x=XN0oFkoW!M8c51ug`O@7EQO+Et% zb;=to&JRCObe+Pb4^%4$!O~G*!^uqi7^IXIzD+7$t(keuYG#LN<#`S9o-L)*)jEDW zP|Hp?c3JA{I48ANwmVQwzrU!@5^NOhW3RSVC>9rY0$mMFa@No16+<1+pqKE$jdA9b z0Y;vbJimFWo9j+(M7{sa=otl6yBWHnmTykobJpah*~Yqnz|!GG>T_CNW)#v6-|T_8 zQX7o3;6+fr1I@afGBg&tr+P3nS{nb~9j;0dvPIvp)=E8u*o?_aTN*Fzgj?gV* z;|{bk5a$o;HU%%2EGN?JAM1j>&c4Cu7>|n6ELl+Zxr!`Fk}A*j1?TEYG0UqXuGEib ze3?*bf+w9Qw{U-*Y&k7i@PxNaF?(aUOv+X8L2ei3=!VfsN$}+JzWQ|=@A53HTeO9t zaFgt-{|DePpe#QsPgsekF>~fLSSa;m+CXURm$I@N6ABkUXRoKlv@jv(!?j45tK8N- zHZ$8#1TWzcbu)&F2LYuiEq?!18n;(=hSO1*25RGkCHcq~()QNZw=n)M%v0n7N?V)R z1n=MH!yA$|eH?jt!5K)FThwk*`lwx49-CW;wODliC1VIahH05o?BG*6{}W^7lVQ{O zk=2jyGtg;Vl?tAau$l-GW;rI#40&79aFW9R#Q!l5W-K${@wYr+~(4q*!s=^i1$WUHa9{2yu}<4w&nzE^A2NR3ra3rNhv-s#DZShke077bmE!t@wrEBW^cRpc_E&dSl zEtbeCEUgw*b_xqA5u=Nov)_d0P#yfy0OUqxhV;%8YaC-5@(um25-MwmG{Ki;o0$Es zseOd9P22LhpCmBC-HALj2dmW{ScJ;O&Y^Sy|L1LBXg=-%!-o-b68l0$D~acg8_y7; zl--EM(WLW$9{2Jwr1yP`Ee7jOs_A9W4vv$(ENOcLyvr1M=LwSgW>DP(@b= zIV073W78$Th$+#^^mHZ3$UI4zQn06t3~pV^433Fb?Yz>o1I@vb<)(HTZ5B~RYQ7i! z#OKD|@mj4iT_WQoViGEobd2VRPCz3_G0x0v1z=6vmPu)+l)n{W+*b|XJncaYF~}w- zxepno;8izYTfp=eR2&S0KE$4c)xpg&L{c;uzD7Z^Md@aiL6C)SwkUhBjexS6|7q=YE2H~waO7gif6f1Ho!U%@i5w~P0 z^T8HZ*>9w@PLV#jcc*<>+Mo{N^7KCjExkSZ9C&bTl0cj*X2z59-N4#OBPlv|$p9>~rNe zYW3N$jy{Buz&zHS$iZ`7gRZgJW&E1Nr5KX;)%z%Ufmsbf*2N;#`>sTJW(OEfp4RG+ znd=+8iP?w_+S9hU?uT>9FL011_7nxGxxQ(%+=mN+jO++{gqbW_9xe%2cB$TZr?Ue) z672FnQAK(Za~|&gomzEE+NmI$iW77|7-oL5>BKLqdFjWV6z;7&h3N|YioyiNcv(U4 z#gR)Gh_!I`pC`KGL+3=&F-=uh;7l2(5%Mq&OV+}U^ngf!-PemW&@`zpxF?@m4)US0 zIZ`|{3U>n=&Op~7SP1`;F;p#zJ?bqCZsUP3(nnyTyzPN+qW*e8t4i^joTyEFh>3ne zKVyXWyGl`;inJb5fbLG=p3zooy#*d=__{tGQv#KP=FAqDAMP3hx6#_uV^v!MB5IR| zT}=~(q{6`nf_%wNDk%(oTMNl2l=%5ZLy};y-$gPevTC1jxjy~*|x zx^Xh>>|MQ}&O(J7*-^upwIQJs%jcik(FoQQ4AR7|Ua}N0C;-p80N>n1 zIe_H3^6YmQDp@o3_O9~mH3aiC1qqYKz~3jiy8Hw2`$^6oA^)Is8X5 zlU*&1MO&-Qwg;dcDH^@hYB8FE=j~8X%s{*KE_FLzm+Mj4p@v-F_{|5TP_zIQ6UQpQ zPmi7`#KND7k_}7NuC1E_YeKa|CZeZ0#+O0?m3mm*|9E`;6PLGStI1%^S%7OQj5=D_yIsPf zL1@9V@oif`o6TIipWrUUG9AD<&|s6tkeTo(O^>VA(k8C3M{tt6bIk;=13j7_5*amz z(|XIsl#x@!E+knr#d&e*M&it^fn#RzKyOc4WGztRC%6#3`;NoB36v;DTf>}WUZU{2 zDrYFn9UBJ1JAh8Qos59ijxh7wTN6p}Fp+1{c`rVAnNQluh;5*z?{XxVB&$~CD`;h9 z>OlC}j#ayvbMPb)gr`GLUH6$WhycmVkHJ!%KSO5wyP12|@on%%lo^VvUU*qg1n8L|V%!=Sht`D61iR$B#$fDe-KJn+^?Z{Wx@> z<4@lHZy-GRn^(C?3>r53!qu?AICaTkREh-J@q-<|CcKa!&S}eypU@oUs7lN1*@R%e zWsL-ay4F+f)a{T&hw74w`yf-_6MSQBt9 z<^41eU@Ky{!5=BjP8k~Z2$l>8$u|ktD3riQ?i-)}l}l$OfnA%waRuPb1?p+>6M}iNF6y#D7Q@^$eHLEQ=jct65c;OqoCAtkVkDcBn=&p5&tF zzDARNZsuOm_ZeGL+*hiCwcQYA;?Tlb4^GWStt~kH%xb0c?IG};*4&R8ww1jDJl(GT zgR_XbTv~^8en+zQB95P}D*HICT~xyNI{?x(niMAEQiB*315Z-vEGh#My@f6c%{er-uW!3;lOiEI9+5K*4RT?bRR9u+wcSF zs1o_jgNN+r;mCia?j*4c>3;Fxfs#+rUpCO!FNbQJBwO{R=eVH(dYDVL7nKnu$ZYwP z*M($mZq6;*)|;m|75v#Es8woM()$t`4jQSrqpz@>e<^w6p^|( z7DR_wtw6+ogE6>_l8e?Uf3&OST>l(>g5SZ-?b2G)9@+dL#6IHOTH-KD`7&aqQ9k9N z8fJU=aUQ&BHC0isGgvxWA$kWhcjo#%ogj*h;xxm8l~cp|qL-HdvM)~;nL78)gs6&K zwfazE(KO#nK#iSmr@tNZdja2Yq-)wA@%{fGA`$J&T&0tFDFN4X3uhr?ke9yh?n3D* z;i$}550@-GjlRZyNij*BU`IW>7)?fvgYED@6XT4%jL0-K zq^YZ)4(NUCH4f<>kAn=!QHY%wK;*t@i1zOj)GV&+3kj*1Fh}rWDrNQ0e-NxK){?)V zym_|OR<|mau{JPGH)fd0YDvQJ%`eo-^hw-ux$4@qlFrRzJmTVf8@NZNiT{C=905A++W!Lt{lCC_{?8Gj|MOq`jVblA_g@J?;Wp4V zF+dXnMSXf)NPt(MPRaiOBdi5NBg2@oENX-4vZHEbpKnpuf(UQ5_F1Gz zy>iPAO`1yL;rkK8)^Mpo83w>7D@0)n6nmXX*=xsR&9~xiN=mImkz3~iJoVH%K~;AN z(K7029zGT3v z^50+Q{})wKJX;ii$TM&&_HipFs~x}KhfzXF$6QvE&|H8R2JAsw*Tv9Cip+HS=5>By zR(h4%#XLZ8h~HNE(!?|%DZS&O2@5%&;!=Z~Iq zvdxqcxL8N`_VPvsmjiVX|G@e=Vke{G&&vyhgK;Dqf3jriTgQ9v5tVW?iofIV@!p%5 zX?T52pDXn_U631fYKZx!Fb&@8PpBW)Tyb~w{O}Km*n+%@3!?(<;F=}q1=`)UXma`m zG9lpORbIKu>wpzT{GJ`JKNlY2cFg$XIafJrZ_}TiEp)x8^Z&lRmq z)y%SUqi%ab_I1Z`lw9EBI`mAm_p%?Ov;MJE%`KR@>Qt z00e?R?bry;Ju^l{-(Yo*$Ykj-B$m)CZUKx>(`s|dOAgA&x8Psk z{XZA1_t|~dRkf9L*q9olS=mP$YQ>wyBWUOx9XtxX)$9Q~Bo-h0ho};cEsXa);S5l- z|H8c_G(55(w5bey{yzpAqV4^xV+zbJ9@H<(T?B+j#;-Y3hI<|zCEb;CJOxBOh`!Mm zRceA*7DolK)L$+&+n?Ae6v{ah0$u>yx(A} zXIC#h5DE6ze^iHg5l?pYRSai{`RXHMtGV7vKe|cbiZG7@6yL6 zO~$)=6lkUlT(~8FLZVa8i=Urv!yTkcwF$+XP#BxAkd;;#XVcKG^7tB0U%}y45>qNb zgZ$o=0eLKQ{{$FoxqnH{!#&Zf2;c`rTeKEkGUzXJ<5_8c_qeDaxz|V1gB(_Qbuvm1 zkWCcZl;G*PCrePKQJHx#C}(ZW1GA;wO)_PCOhNMH(O!kMS{$&7whEtYZ_q?4IvqZh z?_!$7PktEDCR4DoqURIz7M-?H%M=*vureuj#lZr2uI6u5(?V3kH5;XUTIKLVkuvA; zs<6|_m#Jxy^qAvv^H<*{zDFWVOa9K`(KF z_Y+Z^H63`aG^~oaI+CRbOaMzKOed`9EnvtR(~(G1@@w4a?rw;_joP3=#wvi#pvXR6 zh5gjXs5?%6?*5UOX?!`EXKaAeeQu%M&q=qh! zAPXRHL#M?%G=qyHIWIN@ z3D**-iGf^PTvN4f3Jrcq1P>Fj_5T77ZOuEw9yn6mnTkr;0IBx15@;jmO1Cfa4Ma&S)M)}wX0$eur%2sVlP*);M8{z=wLmlE})4N?vC|H(?yyHsf zDu8`LBRz#D%?TLcaq}nbi}}hLYa8xaDv`C+JA6Rk7gk?m*$Tk%8)ibUTq_BA*G@HxnlhqN?jOu#T!s2l)>cy)JiLy&YSb^Dtgo}OK=&>Bh3dROPUNKQ= zyckxb2b7tOa#i=pO2ohH)XG}S69FzK*Z@{fDk)E&NLPZ*{I&jna}F;1ehMIcJ|a}5 z93eSqn`~?A2}({1?-L&uHqOjl`1a{6=TYbp%yPj3~Y+$0au(!DP-fd@owc-S(4DCV-J zf*l-!#UmrZNyK!wzf;BV;wJF3~fl=u;PG+k3VA0iGqrnFjZZ_ zTvBykamwTUDWfZL^wj({_ybl(7+eEhsm(oZDkITAL$m`os}2~LuYo@mhk!%S_I0nN zMfWOEl7|Y^?%oz<>t}4vH6I(X{pB& zrMkvyKoO)M&C52dLIPz^TOcd{l}uxhk(qNid7@vryX8EQ=?_5eZu>F9#bxe=x`C5u zm*pl*v^sj+IqqTFT_4z(2H|Mek> zS1(2yO$eZ6YKzsN{Su8=pm7_N58!%lYin(yD$BwZ0ceBGAUVzdVw zD45SJZHDxmB-;!rkOIVoE zf~IU$@-t^a-YpsiySW2I9MET*WERUf1qkCuy;ybT6=m8DyXykaZjN@1brCt25PprS zAB@Boigm7=mmn?~P6MKuHG=I11>TUv|C>`^X=~A+rJJVGJYtEZT`u=2 ze=5Ig-q_}IlzDaNcZ~~mAEW_h!l7OY1r9E$`nLY8y*W)5fCo9Q9t5b%%@vtBG4t!= z)Yb{fl|v@LL-z&^IhH%p;o1C=WEp>qM>R!`wp|J-n027x?Hb@}|JYlMZNmK>)4>Lx zJLdp5;!uCfCWN_?`E%3Rjc(20>@U6(-&#H%(i4)Ud6Ka;BxH5oQ4qorS%C8m{g=fm zHG?|vg=vsxx}z&NM?bOQ*fh+>Hwrj zYB^8w+=oPWqQ=HnIXCp7_Mc$bD=lT`0qrHV+=i&?xXx?{t!<5UYz$hP(#P{`HS)O4 z+UdZ*l_}1%8Ng~e_#v&eVBDODZy|49*Sxkqg(X<A;9=KezE1CejrXFQ&inNDeF{+-l|*}Ut^cDf z)jRX17&ZIse9tWlLm{U;jmYe{J1(L4q4&v4eZ$s4h1mOGVRF+FHJZop1H}e8B0z?v zF&Gb2ZesWu7DAPNZZYPM84K+>apElsAMSpRQHXw)XKqKJCw;+|T3)D;xCt+Rop#xR zCfRvc>BqHBRz;-aL1Gd=uCiQUWceqlQVtRbC?1Gl*j*3iYVn*~J z|HO@2wP;z&b-h|2+*@DG$?@t-PUPndjwv=-roP74gPi{7xZ-k8%YS@Gvh|wXwd=k) zcltbe$)drUR?8f1&l_E0LthNe&Mr2rP6E;{)mb371)L5{+BFj8?EiI$J60G+6{CQg zbd9@8n^%|?WZFw1Uhe=z)xg0DqfB_m4Py{J;|{Y{qp203Dfv~IV4&YR?~p*!coF)R zagqA8O;3R&(Hk8HI3_5G^wBZJ#ePp|LQpA!>0rD}8H};)5c3LMJ{$N znaXPU%)j#$@_jX^D7ct^I1b6mc_-fJm;`u?4HLDL|tv|VH0B!kZ z#MR+4Tz`?ptSos@#(EYvuASCurcsXp$X^bjq_RDMv0cvUu7{&GnK%%r&f{1!t6cZK z_n^ur_OjaGY;=<-Y}fIR?hFd>IMHK-2itDqQ!9i`Yfe+946@dgc%XOI_{*y+VbLxu z)MHm9?PXgW<)^^V@r_&cg&5cL&BV}dZ!2&`yFRP@v8rkEUK8(w+bXKPUNgEwL)<@P z5f`r(vn0EfCd8mX%lcN!#FNJtp19a;f?}K|f9zkI?%~k=C7xe%CQ{X2>rwq5oicho3xxO%b9hobTB_? zWY@L1opB4#2HGKu2=)FQ)4JNuy8B&{UlN9R1o4NF#+JhOVxp{RX7=_co?23?RNLFz z^R|tD3CJ;GHS;XM)d`A~x)hpE{_kA=|B}G}L(0(g{yLg#h(D;Q~a>4Q>k6oHScpm0^_vnAxB3J3F^ zrv%g?TYgO;?EidS%6jkS1-hDZur*9Py+d8~{`H$F*$Q94htu>}UGTsp{eJG#s6!e{ zT&${OK(?>l1!7xtmd^{1WoIDT8$@QS_{W@8rIE&(Ulmif^Mln>7qgpaop*66M^lMy z>l|x7v{M=kUiwW!obq2Yr(dCxKK_OPQ19@(CgCyxoeT>L@!meX66#*jrIY3E==(=> zDxc=LE1a_-9kAamtA5u-KbvM9bcG1Z{skZN9k9gf`*}}r3B5kPW_|qZlCF+R-hDi0 z&zLC8U@sv<{yBqAbE$cDhl6St7ncC-9xrW+7>fu6Hx_PW*AA>k(+s~(#~ z@;dtKqP%-~hwk;|%l=`$P%&RS$m>I#<2KIJQ+w{-K~i^LyT~6*k+#R1>cW{Px2My6 zIsx64zK@T5V2R&m}K|bV)}eL*FDDf-2=~EMKw}m&*1aX)R!Fe^8>RMe-PKy$0?^*&FC-JzXDRv zU08e_r99fM=0UG~FQ>}c`+i@}OYeV#-_=U!y_S-H5*UWOY)Iwg670ylURrsJ&+)GP zC0S%CQt+$Z%WtiKw2#$mQ!lwsIA88ZhBVK`-tKolmp+X+y;{9&G`>cD@jA%864|Do zdQCfbHFgb*`*@2j)H~79E%`$T9{PL!ZyzV7hhA}WKmRGo{+qyAzW#2+Bgp*at;oZ% z(N1RoP~{$tE#T1Sr7x7N8%D<$1%5>_v70oqu_YF3agsjnV`ExyzD%nw3=;lp+x3yE ztu)$QPbXiFHq6f1etz8PR`ah?+1nDAJtxzJflT|TIjAT;K3tQ}JS|OK5}%)#S)n&f zeM#FkdJqmce0>rsQ~vUi+{c?7J-{9R6>>L7<2!e`9od37crcV7_rApB#?U<`vTmsV zgx>EBa^9W6=j$(iLFiI&i1Bm?&>$tEIj>pNwKD&Zcf|Cgoaj>L^&TgGm~?)3?n{q? zv~B^b?V-TSpSu^qscxYWtPS%hp%?Y;NpvA?bB&KZwP{9M%H8~ZZ{WRs9z@Qbf5YDo z(|NM1_(V><&RThQts2*Q2^QywktumFJQpfo_NOvGpD}NT=j^5yjy_=d9P`B3?HC;2@r zImwk~)pm6|_m~U?e=nrF-F5Lr`H7SK^MfiGAuNK*5x>z(6wwx_sTL{ z(=q{I_@={tw(fqTC#keMXm!vEaAFr9nw+-TAIr`;^4Ky9w zLh5(La*R{+&tEyne1D7Fn)8xI=ZtY78a>AU4RecmRDQIFZn@s#UjJKNlP z#%{EckZAkq%;R*p&!yjbk4%=;eeo1Y-m3Q6?bp`?@-O_YzT_Fw-CpF%pSMh!hSqmi zMAT^fEIzbf%@5^ndIfAplTy+gX})oY{=yX zO~9P{rV8J___fJ{YL~>RHSY6CPt1c_kw(I^TzQgV1bN7AA4B@}-5lMwe@qF5B1+9@ z>dWgs?En_MCa0Umcld`-63_P_41xk?6thQ6-eGJiZXAUf3p_i@C!0qa8S!+I`NSfx zQ>0c1T2>evwt^-5WqmiEyF$6oVmxCl5F66OX~`YaU7L;Qq8-~>5n!jUsc#^N*^00n zwn<;dUSlW+$46Jsw$0iL$^YbmF;gWKmnzD!Q`$L>yZn3?zIUb${MC}?GFTd< zQXqX2>_GR9t?5nVr;U~_9!Q>9#-24#thB!5$PjDc3T_&FSyg7G7r9&Opu`|W9DH=q zKM0Yo59;=1@1&tIUQH*bRjgmX(9JOw#TErL>{sWR+sz>788(Vy`!m3U)!_bg6VYe??#~%7U$s-Ct8;~BwZ@|&^NmJyDf6dK_gv}7?GM^x zrkql%tG~H3v~g{g^HF}xIA_baJlB;xIksi$&3$`DT56P`JTG9Y-8HI^vO4Hi&I7yc zyTo8dcc!91@ZK{JzV7ss5wT70Kv+-7mVxty`H1}(b>lnB!?%oGSQON&&Cr7(nNCwE zd(HG#Kj~pWGg6p`m*TFaMIu?^4x#vZHh@xbsa3?G8L5vSbrd5CYDrDD_qJ`-A|2cL z(r|PYw@?N&*IlcYj128;C5yR$Bljh6S1j3Q^FLn9-jt1ES{urg1{@ylzU5(A<_-s4 z=Drh1lyoqu!)o^ffuwl7yStNoWv0om+1`}#BmK-sD@3k2Bv=W^d&nEle7-SXqw%)W zyjNFf2ldXeE!hI@Uji1cs7flYSa7a;2umi^b`lD+<%9xX>xT^M;Ao1Nfj6TJS2Mr_ zkCfGrY+jHIF-WK(Q%5c6mMiKcK{XPkoZ?W|i=tGA;xx3+?GYB6C$vr2B)ifxy~vo^ zX=OW$&*_%TM!2BvPq*daKD^cJ2Ajl4NzcSdA#8W?4Lj^DzN-_Bw|jGai{o?K37(@V zu676tqf|O& zc92c>%J?R3g|P689Co$Z9o?b<^Yfha_Kn<~a$=A=eatZ1mdE@_E{(5VWJk$g1kt(% z@?bojJ+|_4no~Pt1Kbj~_fu;6w7yF*Bhc7O4(l6V5*TjR9ISAex9d^LM zSB??0QP);iXq@Kl}heA1tIOm}zD1y3Z3cO~n5Es#V2npMp%V%2sFQPXV2W zs}%F4o^N=bhj8k&2DV}W+zsS0L?2|#A#Svc2std&*P^7Q5P3`jA7r6E%hkDwV28+@ zv$zdAq~k^u*|Nl8Si_$89twAdN(+1}O6u*N$}wv`TdV@lm_dG4Uz>zSm4A0VT$IAn zN>(n&FkVymEUme3;(d-mn&k7y}*uSgvT`kpX$%F1thS$~Ok zvt9~bC<|fJ4YPe|z)W`R>xY=L&`sJt>?X|^%(rtGq%*Wy09BbmF4inaua-3OB{6*1 zd9q6~FJCk<`}M9HHoqC%K4s&*J&ot=bsVa^5bTql0n5smTOzu+)Jt!cX?^~Fy^@d7 zKzGOR8tEI8;TufQ<&%+dRk>$B$y<8eL~c|>3zSR*i@Fq)#Q2dN;0GLWGhkGjE^{2R zHrTqB*|^|+fT1KLB*4~_%-*uaZckT+Ig2S)Os%f=#6phx1)asx!f*@uzuRwk*YB=L zFvI-#nhtLw+2Bb`-7&+~3iT~j%-0#feX1vxg3!5TJRLzfr+rT>yHt6w?)A*Yn4NbJ z(r1S<-Sa~4D8tu-tno_lV#*HEwZJUdRvTso~P zZu#^h;u8?9A$wNIv1cW6mv?G&?7yjpzS7>@4bD9}5q{cW^+!JBb`gS$^L z8SCm$EO{}JM!Y|664%5=Zq-&DDyW?2+lVo@#dmz^m2POj@z;Vxf~z9G4ZL)h|IC|J zGBdwEt-yU)WEgG?=__xjGrf z14&k;Wk%k6RbrLGP`VQAWjSg$qO1v z`@vZ&;VHbK{E_s{>Y;N!JV$1t&q)1&WGR?^ToKQJ$xwq&Xiru)%uGRQJ^D`a=RwbS~J25`GJ-$1BhLuY`y`-xn~IjuNxZG#-s z453EF`tu4GQVl-dASgpG=TExnh?8zG>pDkA8DpWR!Ly3_vCcwuW*RDplim7m75po9 zP>si;+t#>i-PHdG<*>7C$nVI%MP&=5tX)36Ve}(bd=g_#;5TJEJARkdoh!16l&ZNj zJ@cyLc+JYZGBwJ5w&;cEDC)LmyJJuMRr>(WR zvk7+*?nIHa8l}c#+Ck?fKdNcJKMcO~pz2S8+1al;cPUEmnpBn8Jt;M3n&2kHdzLub zy1aUZ-a;E7qd)vQ6o)yCRrb3hiA|Ny@Tnj~wrlCMR$tQ`JT}_uuFkj0W_C(af6V({ zU(UKr==}cudkElS1T=ccKF{o!9xQio>(u>jq0ETP2&EM{DsHavuNU!(UBGUNU68lM7JY-?k#qGV@CD(mH_;5`Gpx^X~5X zAtpB9m`q85`J_{Is1y)ysIn(OZ`_YQpb0LQGX!%i8CS?KUqWroTbdWm=?#7ujK88{ z^X+cMzq7$$@i?3UxObcT@fYVHG;lii=n2hZ6DJ24LTse^Pq~p>g7Kt`$w5Ao{+;zw z=QU-m%Lu)L?7ZaKb+V=o?vj*8^z2PhuIfYQWef;ue3)gP3S3j(dBRn9kavwv$vVZ6 zAH`Fch`Yh3dsChPs%;bd^(*upZ>Ig_uQalY2MaiCETrM7vZUEl*HsTCcU@6Q83^Or zi%%puAg*GSU6*f{Tg=PN3s?@lYX6r(sz1J*zp=|Xxo@}0x!OIi201H=I$G;85Q=7@ zv@lt(+*{49aJPS~!KTV>zh&JMB{$mzzZdEO2-0UI;fq!H&NkXzSMk*Buv0G5mb5eVb2U5HkO}}@&n>y{iNwA1c(h=dJ(5HAv zQKl|YVJbe|@U9j2HRF@AE+&L&Mf58Znf>jyF)rtufneHs-fpcCAopdS-8w`hbGt$#8{?A8jT8& zmfFqXU+hN)W2cArvW5LRN7yriE)ia%I*~>ZiQ0Jyb@e;Xp3P3s-V^0{k_1qAV z0$Yq~>T0#n7`nO=ujvu!#$3TMof_<>dJ@l~$l!B|Q+_@&PVOW2p(m#F=BZ9(^16bw z--z_&o{|{Ylcag)|}@43+*&e}~XFR72kou9*ILlD@ztJ$~p) z=VcVmIH{!J8*XOkR9hyb;5}S6D$i~&Y=^ttGKbE-c*^e}!T(||75zult!yWPVaU+W zo|dI+ex>;1x*s4T{3Apx5f%|D|8ryR9cRMh+h33!v1zZA@?yuw)pzT*c$qx6%QWh= z+S=7JAHDn6LH`5Q3KyYNc|-CEB77Dm3lR z8#eN+b}AsJ%25K2b7rtEW*ElYQbb&D5+NOxYMhHR%8<`H`f|3wpN(%}n3r0#ef$TM z#-3oXF_@y!faad2_63Bk_o8-3>ljr#)%!^B=Q6K@WX@EEoM`2?=w!)5%sd5v6MTs404FKe8FdX%Tv%uPmXIXlWY2O*Ks@O^w8J>y^dC zi|`t|Hs0|x4PScRong_REBtkCp>4K~WP58Tvx1MX?7>GIXy4i{86nrQ)4Jq#znAQ} zSTcKB&}uY-LDKoNPo%4kgftJU5$JH&Rr?p&{iq#7#4d-i;80_F#2uMQ5z@sD(~@lW zad6}`8y#xCrFVSB+uc(ps|qp zoS||+XrMWydVZ+2oNe;bbW3o1(IT&Mhkt5TvT8T{1&9PEQXx$Jh@2zm7suB*sR(zH ztx3=CVG@mmUrAy&pgx{EPhF9_Xr66-%fYc)+USX*)hX$W%LzU zBe5a3-{pG<@`V8_d%MyQ>PNmn4?=2MW@Pixd-r6kbF5H!q1hM}5xN%(by0h|1ZOfC z)%TBfe!BFII$qG4MoqpJoiGF2YID4>4cPq|_<167Nutc=UF(&ZR^t)>44HDrQ5qfm z)ju8wsu!Ro6=we7rA>i7V6^r&2+#ETGP&fiJ+BnhWf&eIu3SFu@b$e7<&lOd=1kVN zL&bY+`-H62%1Y$Yp*!hD{GS0574KCOrYmGHW=z-s;$7f=uK%E{b4#nKkg8c+fukl8 zA4tNp(GfWbqvu$E*sN;|!Gv)gP)9k!W{fUO>-~7+;>rMYPFyR|C1mQtMoqoXa$ zZemkSE+oi^h-h;K3iO=Zgn2?aH_h(HP_DitHJlLN^*SN9xc8UkPm><}p=*;KLuNm7 z&b~!7l=vl009>leyt)m02Cu>z60=h#eK`E640 zmR)vdY#^>?8wF$3kcyAc^>Af#-+%{m=wf-_AzHH~s2ac$iqHdI_Jx`9WV22gIn{8% zCfrjWNk_qmqht$j1f0v}1?!Fo!DOW=JKx0w{ue5keitYx*|h9?cD!jbb>7;S6;Lki z-rQhQG`9&g=8I{UlUN$yR>Uc=N!!`+2@4BTkAY=aRb>^WCG1X0)&sAx!XXlpz5cgz zY1tXY-@?5`2PoB42|AUf{#;pWTE7>HsLEy668{~Y$9zgo^5pFasQ^PoniuTFU`U_V zI}0PqgIzOC!EIAd*U!66EVE7C3=G{d=ETcn#%1lNWlQ-=bj7xrYZ&C37uout4YBZ` z@qC+w(D_39q+O*VD$^!;k;Eh4w#ckcYTKkEjp-Mc0(pv3l}RMj^6M_jw|yMLom`xZ zEFuZEm_KHQG+6Ta(a-!$rp|RWmpJpi_F<|oerUJg1ewxM_>E>$=dLywd5cpt*^+^OCZm8ACSlHbx{vI$7rF{iT-#s@_+yG^Q3=f@YJv zie|^GFna|60#eWKs;}5;_wxv{g15Cso=N$|LO_}eofq{|t*PQo{oYZLBNILZCzKHl zMYa#4MqBv5I}V@p)6<*nbX~_t`O=UJIqlq$>hxTwN_4bhs<6g8TEC35iIN-$Sm4Yw z`5-|=jE|DDtO^pVISk^J32qvomb{D&d7NBg;`*q!(3Gs~IsWJh%X{*cO*chntRQh| z(QXTD!8~XlUkMfmAud0lvMxARb^SERFm_kb>bk&Ug>_%o=-^EV_MFV z#)O2>j)okF%s#he2y^4dvER#${d1QRpz9+z<`1&Le$-QQ>0pGe+^{nB2bDiYp6Vdl zZob_=_x=^;_IR;&NAoQGiVoQ&uSU&w9xW?&9b=VDs5-z>?Z!7Tz?1zOGd39IT9P5k zd`_|My-|YgiE2ik-CZVg+dtTw?QdJZf2GPyT9Wa;)(6{U$ugR zm8Y8~`6;|1zSnm9Iu-s2wP8uW#V zO19qFg}%ZLBdTXlEsANcsXeZDj=Yu^X8Bjt6XN5C=Qj}IPc^pk#ye&}Az!<5+Bv)z zf(Jm=VGCZDR*9wt>_?(pSRu4=viXxJ@oj{=R}1K9l{`DVbL2+_8;v?~3O=3RhN&c zR9`BTBYTDi2MH^z$oucm| zR;I-`8RO1iz#J(!PTq#P5f;rt8}cBE?d=*xB0|}559PW9^YR zsi>FAK9wftxz8yXO%&_g3V2CJr_@|CRj?QFB>I4R@cjeZdV(!3_vNu>HAoU$00CmT zg<7ns>0$KO5R|4jmco`*Q6QNutzy|{?PTCv`0J22SQ}5BBpuYw6!uhNtsyVjV!QSU z>_4?Wl0A2+2J)C=evGnJWrfTf_Ba?GJSht)dpg;uYb{4n-{*%g>q?g67mGpA9xpmi zm93AIU<(Z^jVd+mwFMSQR~-D4!lS=Fm0Q=j)h3xb&VV+`=*!-d(kpXYzBF6!&ae-k zxJ>?4g@#lqmR#xBgYB6;2ZEizVGuAQ8#cCzj|%#R)G-^en)(Ku$_q^(u2oIVtf6dP zi0Ctjk!Sl#DjSKDJX|_q#7W-lj*gTKku_>}x;+U6M+m70->IMRmAk#|WV1Q_cY&P* zR0R|>u9~S0Y9vvQkN04HW=+?7kZF+Gn%QE$n&Dr%U5p!_x{JMlb4YH-f2-&DyvlWnNZe&g2Z z$LuOOUJ}c{M;2>Fq6uo9>U}3<&?t3oxs9Y#C_5W}z>OS0DznMu_82d3i#~~dhvm`7 z5l9McB+b&T&-8iK2~X`(WIqL>7y?1~2z&BE+svG~py!ef)*MFjy&e524p&OLd_Gj% zAikw_(f;3E&lGRg*n4c&Ebkm8`3&l^MiYhn?WPB{5ZatQT*4CeHCmw2k%wA9 zhq3M$z4;9q{s*LU{^zd=Pl>s%oeMDUJp0Q=_4u)X`+sSJ$NrZbynx*Q%S&S}XS~OG zM%6PRGTF{9E|hf-MU}ILIb7=-hfKaUuvn(>djG4NB0kn65G60{v6F}JgFxyVA6Fqj zC6Yu|eevjEl693U`h?e^= zrG}&@{}FPCmMgzOLlap1j~er8Ru0#HB$xlY4g7ER&wulCWARfd;0DF05RukD8qk0S z7C-S~jeVK|TMz1pfa~pF(sp1T8XA=;IN$Ys3iWK%)v5hQ%fcOB*KKXuunf@7`b(<} z5G&(#wNM`W@64VL*fN zk|aie_qyu7w*fgn#uZwC?lpRMcYU!nAUr($epHtnTkNDYXx3K5r#ZtOtYBos>f+*Z z>n0w7HPFjHi?k|&%+lR+hfJWZ^Ow7Bqtnyc8v?5Wu>+=PG@6Ajg40~_K``Pa$HS~& zzkYpp`70g*2*uQY7lzti_((D1CcE}=m#9lk>en?O#aJK#{d8|Z8Sv);RfjX2g|)Tu zc%fF!9EFZ6Hx*HmLXakRCk6vfOG~p}Xi6Iy`KYa}{j;DTB}VTF(5HiyK!-RuJm*p` z|1$Wfi*xfZf*&I_Dm;Ukn@7Mr0RB?ckoWA~N027dt zBYgAbOs(rfQwok&q+e9^)9T3eykj>bYf;|61lBJI+%+fwGemp6<@|0pHgg z_HrdjdW&^*bi_{QAyG!aki#HM>P6abBs21|vjegoU%vWhi$G1p>5U63#(LvU%YZ}D zdVdn)7(M!olQa4FH-;*Vpn66TXspwEKcKE&?tWy-WB2Iab)x3tg13O_1>7Afo!RM6 z6NfJ^FFS#-i3T*VM&0S@>AQiifYBNr9hK&Vi?idX|Fw)f5KVeUGSOA6o%it>9X);i z&!1pEqT1kBESpqb9M2m?*#4s5p2Nk(j5 zbTk&~U0S*u9L!1_)kzcfjOVKc06{H#{uI!!u~8O zT5IvcS5;O0*D{`3WGuCU%UGW;f%Ko2frlw}b?uSVTJAb`7}a7W-jmWSckD^M@GT7t zHR;nLPu`YX6W(@(JoVYtrh8QF_ALUpV$CeE>r)aHxWk(a(E>?HwCN%q;Y=fq%Jk1K zX6xGhhMCP~);T21zzeZQ-Tg1KqIAS@Gz=lJqDz&f)M_f~AKqnq#sLHiUrfh8(4DSG zjQYglAG=09j{)Lz)#>-mHtwZ_#WL;r8g+f^L0=G@NnFtHdYbMPRF83^c0on9%f~dt>89ebOT#pLw$ojm zJ9qXyQfHmV6xJ0=I?<)0b8cU#MRv?~)&bhBs8V}%2_V3vnsL9_z>sA7*Dp@>5?w`s zBuIv`GO!Db!~nlEkCboTMYyhT(@k@7;C1I2SQFuVF2Trkn_ISeEyr?~t~NIv&fTmH z^d|8%Qe!vQU{pk)s4z4So_~i$_bM%&q5$mJcGNbnaJJ+3iy(Xj$Nul5FTK;~)relLfiK1m%ZDEOGmH&a+qfr( zT8H`1Ntwe9?FwInt)@$10R{ygvZL+*dMzp29LJ?Ljke8J?*c7c3XR3?Vq;$(#g7|; zpE5Y8*(Dm_aG$xr>)nDx-3^aHKfrjhv$HW?O{1=a$P~6{7=@daoHRJ(^+ z)r*2H@2Aecl)t-OB05u!?^Ls!e%;YqJ!nApf)`J^dAURiD|imlDBC(GP&iwAG~9Qp zh!X`rWWm#9%PS$X*XgpY z3ta;&=cd2o~I~aaH?o01yL0O`Xy!5T# zQbrW~@r^`dK;kSJX>@r#u-Y)gYJAyAIh}~u0B?)V&ydffN*`KYs@xAE?W9#mesZL8 z*v{u98Or&~Jayv5RES%W)*%|wYACK$PhutchBMkwD7nidBKj?=XSHS1euXrMP^{I^ zW%1DCITXb38Sh&tKU2hWDkMW=$D2nCEi112QoHu~-S=hBS6&O~YZlgo_7c_@(M^<*CgC;SvUTFZHB@VMQrW&Sdt z^l8$cnpVs3=cS&^I`tm3?e|ni#)lPL z+!tfETlr1??v%?1V5X=$QC&{GJB3sM_GMA^b~>*iNu4N{kDng2Syp~~Yf8fuAs|49 zxM2Nq%F8E0HtPKTRfZ+7M;JwIZ=QynGc`KLQr? zZn>gpT@5Nicw#OmZevV-qvLj~S6AGWo%rF+#uu=Ne-fJAkHR@DmeM0m3 z2tLF78Bx<2?(A@N1B{Qo?-HiIA9;P2=k} zA)+j1x5)}_NgiN}&kcCv1Sxcvd<7w5PoW=Q-xqMR{ko=s$?sk-6N`bI=}RHEL!Yaz z8jLT~+4dYCuDCdy2jGcm<2TI38_OGgW6Oxwk0y}i?P|FUp0cF*fp@{QITMD(SO=Ua zGpu3}?zdIglC0BV0#Sp1?g1#HM0pem@=bo72U}$hZOmn`X0`Ae_YZslM()cY45u$d zmuM%-e|83O3BTAYeo5NVpiu8X6~D?K6R^h>b1~NAv1Q}i-_{_j6 zF+;ndL=pA5!;%&3B?1Sa(E!d(N)%w-cr&{c(Mu6~(KAVj7ot5i0 zC%$5{G2Ym~uo2@kDMU%riBS`76uwcJ{7t@ek#%87dao&BCIv?e$fo^&~H&sTt4ff+i@_a^%34Rx}H|CML=Yb-lkk zvo4sY?^}3e_7349kkl?TFdA76BF4|?3aQV%b+pl3L=~Va)@P?~hnhgzm>m`C0u#qZ zkrFE0oD{Sfqq2(>0v1m$BIru@{!SRg&qE|wmPRA0p@Di8xXBip@@s!5?K@)d# zx0r~6+ex^qN5Y=lzg4F>?zLk}WP@O$si?;4n$pwoip``CRdlyYju{yuOD_X&>CLa3 zq6ZYce*bwV2kI(f(P_wV;aY++5D?)VNp%)N5Swny~)%$Qj;3J0T=R-6h~g7w^!=a=cRfB3HB z=@AYap5IEYIy^v>1c|4f1F9y5r7NGTf8mJtFo;i>iC;dq^)4Q`T`j|{lP=Yh3vPyI zI`8EyYT7Q>Sp}cW};-=i|m#WWse6Qu393ldm?liaP73wK}c+{U-aPJ^k ztQqia@WBkEz=@{dvrR?gwA2$i<%0~erk1dj)93s`N@`l)B5Nc5PL`_Ndkm4IQY0w@ zK^-6WKM(+pSKug?Xx9_Q(>zZ^Bzb6e5kXOSB}SLBWqvQ?*Nn?O4A0r+7>EgbI?U^3 zN=5E%tvuJFb7V7F!x2sZnS&MfO~iIy84jny}Ae^hP|o=)iseX3;X_~1PIgSyLY%_^`$Ag#%n z-v`i>!|+b0A5QMv`H%xxcUE;f>0;Oe9W}Z$A z?;fH4a0K9jX_@BF-hCDhI1w6GA5!%y-`UaRVfnT7j)U`bSx)wVIBFRnpR`>kY_P>K zOj*Y`kGKDZ?Vsy_Q>gj*R@&Db@d?>v&Vo1!?y6{0wHwjUIPeu8+(jz{32{J`)g_~n z`l8LPA2IBIJg(a?>R2LN-fwAt5dli@KBs^#5q|jd@lBv0-c!M!0=kdjZ<%ZWT|=$z z7%u8^SdY-JLRahHt)Fw_iq=A%FymB2p7jjlZ;ac)h7;SAzMxY=|M%SIvORNlCQHoB zZ5&&73@D&>QY_ zk)JmI$t#K$fR;#tWC3O!v@<6Vo#3i!wc}yr1sW~OZ(-QAO zm>$C9+lpvu4?^1H6!yzLvT98c;&=F{XKG>$mJ1YDwgVxGC1{JA=LuOwBN^WExAoK~ zW^|Woa*)>NAAQ=Nx#38BoQIA|`SE9XA5ywxFTNifnKIOmYF#O9lf&K9EYqCDT#{~s z@XM))!w5csq{kr#!l2JLOoSy#BN#H>oWc!)@xafD^MMZnlE8Io^d((>qZWSQ1PD_^ zx}xE_;)y1hdYiQHO^0f(;H0A&ov8s{n~?Jt+WE^*pz90V1#Uj13X{_aGUXMmN~8Rl z`KuxEeHp$Xh?|$J_28vr5;xj;Tgb-qp5~j?eXwWsRl;S0gU1C$7tCEcE~t)*^!3By z1tA1KaAbL%{UK|3Lo0Zz!6HUP(UMF0ApwLtQLF1jLm@Bc%0)$>L5VZo5C)?unFyP+ zm0CFkEE`_i~6)B0oVIdokt#I3X8^p@0MXvscD50T8^KpPk zJgXgD>T_-Jom==yrg5Scg-7qvWs8FV!)N4vAN(;f{q5dy6vBc{sP6}RtsT+*?}bgF zLf)@EqwH@zN;2)YkFK6{uzEV1zjUh4Rq);A+Eykw!5&QFQbM~KYy2ZG7J+bZ6b>^d zBpI!?Wf#};2_g|6ukhJ>UGhT*QDkQ=S}0hxbGv8QN5-|pcMaDvtu9?tdkgs#yl@N{ zO~KeZEiKyUw_gqp9NL!lrz8dqGr3n$6nnLiP+sL0R4&+llW;f^{`Sen-X8nIdrQv0 zDgbv4x_hD84{epu`_w9N13$`Xq50z5^?6EOk~`4N26&-&Z%JSdsR}ze$`Hy2J7nJJ zfA)OBs;_$9T@_n1OVj%f%I?mFiQC0=1qsJ@&W|DdUi6>(q@_I{FejRnZu*ki zFJv+VN1BKi1$##eu)tYNzHnIa=F|=NN6RBJPaw5sU-9z71e#IX37D832lvw80&{wg zuZ@5#S#e`Xuh;}vMWvY`Zfaj@VG(_Tn3OulzuLQiyRY(H$1pzS(%esyg&CVZB)#~G z^tKjXJxU#e4ke6M?#Mw5#MM#O#f@fo@>iH0ZWp?5kpijwrDCa=eq9;fGGScq_ExWD z<;c)b3lIuJAP{DkHL7CL8Ve7YU>7F4p3XdfPo?HheAJ^NfZ(^Ao64t8VH2Lulum(| zp#b617Hr0BZ*5BoBkSWktfgcwL#Np_PJJ`{G+t#r3=oo3(AYIiHdXzo=V@KfFx0WQ zM3eo8!uH_W%x{9!*Fv@at zSH8(+m=tKI@E+3JMs*t6r|tGTg4<51&oOOe9`2mFq+S~=aQ%i(MnGo^t+J4qDs`Ov!!AeSV)K1+wx-m=USwCX&- ziMDS{@&`zpIdm_gr%!!RBGRMzwT{$?DQfJAp!B!MwmMI2e}*r-*%wA+=JYjeAWo;Y zYRdZ0_;@)$?JpxEqpOv$r64c`k(J46sIg#P8GfQ$9Uy8WY~}?8mL5QsdTGg^xbbwl zLM-9y*KU)J%{B@^oz|{9R>53`lqRzVD?MA|NT8t>d~j~Nh}iQE!TB8LK~C|Bbm7#j z@4w_Z(nqg?vxgs>B5RXpfF0ZSVl)pEW@q}AR^2N{F!3tMGjYwWoRsDcaRIaMfx`T$ zpKH_6Vg*FR^!~-76+AB53DJ*|BaPf&_7QoCcPFQ09x<<&t;%y;0n?Ju(=_*=c;$L# z06H;qh=Xa?{QL^l;0uoYfmWPJTsbN&XKjfzizSZ0SlIEH))G$T$xd3)7%y#nF?E;u zNZ{G)Sgd9Je)jcR<^aR??h2NPTAkvp_5o<(y^2bB*u!&16Hd)i_jeW^T^WZtiz|@Q zQ=Hf4X-Ts{uDcM$kIQ7Y!+gL(dUo2>Jy@$7P41jEV|1=IikaUVSH99>EIw8W-6o;| zdx3(vv(Dpea5#%I>ZST4Mq=OV3CMZg9_sWXd${r4`762g0gK1o-EtaSHHnJoL@OZk z2+Y6+#3bkD2Eu6t2QlE_xpyw^&+Te`NC5_3z}>s)b4JT7!q5N0*H;QaasZUny6RaP zjSdinSvKYCRH={il(fobPxsJqTUg&p7=E4?d5>>($A;S*$w=HhDLt|Dq{e>|;iAx7 zPK7IEqq`)9WSVN1xKnevUWD2V-!i(zVUySqGc%p<5D~5GLtmNxF7#5paPa<#yxq$5 z5=;1b*60^sQLZV5{OG&Nk{SB;9DN&Qypy?vXrZ+FAos_H*-zkE6Nwn?69ER3t#n9I z;nv1$S1r=*kWu$1@@*-m-_7F8NS~r3)@hYGClwQxm$}P~LkB*|((+X3(SUXmf)$dY{1dys|3L5_W~Se;P1qG` zaR(3Kzr>lFl}lA%mOA`I!8!ayMOW=r88SqeZ2h1MJmrwL9pz{tSV#&vVT9I_f6R3B z`b663Vbi^D8gCmdlonyg18z53ITUUNUVxQpW$}h@*s~(+Jujk&z~+ z@(KG|Tp#Fa&kLJ8s~NNRD>r2kE>MR?iZBx*&$1h9{d$ra1d1Ish2KgfmT0JJpDCsW z84UgT(>|Cc4g|`{#>U3}#*zkCcO0iJ3Q0yaJzb4{;{l;|;6gVs8JVEfICrWN$^w2x z4ur2K=xF4QMsn{qp?CTrQ@5jawzVt6h7TRZ#KbssVPwouSe=B20~S?!LAG9c;c`YP z=#91Mx}3r5Akw;O?UA^X^nNwS!bJUXu;Q!%SrNNI3=<%L@u6r`xEk(^!} zYb{P^wsO7_w2>3T5dPGCf1?V&K6t7EH<>1O%^3%sH(q>udz8@lF){O3`{fn|AU+L- zzU(Vpu_eYOx?Xs;uOrTqXF~5zJao8Vn=fZ;$V;}GTy9?%U!q~JR~$_H>$gm`mWwMl zC;6T`+NL$7ep0UO7@Iu`?z$ZP5T3XDWkzYH3SV`&Zd*xPS-ZdI)XgE~u&)-tXaKn3 zZxVJSqj;i(C&;!Mmm0WW4Uz`{dv9-VaGFxCaz?R94G>kE|2~i+aufpGX$zm>(Q8VL zjEsEt^X+_LkfTV3*QcE%ky|p^T1^)SC7JB0BWQf89ojkhWNRW;A>AXnwzv0P0dQ==@tB5mEE1mI6?q zJ4JErI^B4&j%Vl2psR)Avs9b850bb69kWWCc_G@UXPSEVpuE%~bIugG?wgTV^@8;S zDpB}7f%{W?XQO}qycS4W1xPj@GerThb{V;zlsyaPu#Sz*O~Zj?;lCiq^t4$1Flt4~p|(;P5farw{K9&(ACI!n3QZ z;V_7jx3>h4SylrruGnQuf0qN$j(yL|3kIZDfMygG6{%`y02ni}0sr4w?B7jW&A|G_F1lKhL6P0BO@=l5^E+x)z4mF--win7F;NB6%2_(5ps zy?65R00!dm6v`ee2T;6-I&a*co0|hnLPcA$UW)b;s1y21Z9{C0~%E|wFjiZ zTII%sz-0J4G6sm-on2jWIUk?I%2|WxmGUTn6&1kJNJvQjRti86P+s_d{s<`L0T9k+ zI4!eX1QLV~4;^EAo&d7~z@2#E2mq!m(*!^kpd}C{G9Un0KUeHh_*cFC_3Iz{yovVS z;Q*Mqb+UZoL8S8+I_Zwn60853%Q>*?)l|bsHA~7P@$@kYNkCl;e8j5(IH5eBsvZI; z*((6KjIHHQ$a`mYWIa#cfvOsT=G%Kq+H8dic;FST*wEYtr9_wuX>WYwrO#L0^w*m3 zw6}k6bNLW}G}A{`{sja>Z=@=*1I$FTZVTRlyldqK0H!*1&zJL|;wt7``VIhbDX<{; z_px4o4QOIQW5bb`h%`9hJ%{Rsz&;EDpqD9g^={O4aeYAxdl}^{?Sa=ae}})gX8GPa zGD8nQ%fy+Y@`j#vn{=C2e9+Jc{>!DH^|zQH1L*x&<^>iZhN z7HV%WqztL>GHX=du}~G+_kVUsRTZ`$IArxIH{EBb{x@3XFE;e?M*LG!PI-nvULd7l zFuLt5;y-wI_x}Op9(i3ee(wfQ#NWp*GXH-jBIMftgF5}+WLi)xO>@{&{=2lt)LhaU ze~0St!!~g9w!1zI@^M4^-!ESCa?V}iui_CUt{$@WsQwxf1`P7=168fV;d<5vLbxVE zywY97-KgsRrj7tlbl5w$>l+~<_9W5Pkth+HXU>ZMsVP39{_H*yRjU7jJHu=&G7WM# zdlXnK|L>|+v-Z24kVnhAbKz!A6dJ{f-=)%)hSjVl=f~6*5C8K!)-&~WFy}G4^HD8@ z@Q~*d`rigqfFs;MHIv5|M0R#yvC2QC`8&g$$+iQLLiBM9IMEHjD4Fm)PL0U>o83Y6j0|W$g1qSM?Wc9lfBM1l)h_slns(aSi zhKIN6e&^Hmbh^(Z8Neru48lkX2>v5J4+?T{!?SjIsmaQ^dCls5L))Iyy1cnr$G*C8 z>G#jd2boGWv2vJ}8fs*sVE*7>a<35%X|r7J!?%w#*z{l!(0Qx#Ti;HKbZ+N^tV8a@ zi3zuyL$4gt(y}rVm_QrRBU5a9&}az;DTU- zJjBLlwS_!fw$Ks2lEA1Vze>m$dZg?^tV(wCB=(R1iZb;sNqJp3TacpwYC0WX*xwG*duv_yy(8-yssI*_PwuBTz04%FTwjYPgTH4pu|nG8ie$ z)ka{_o30O)zUk*NdOYuiXtWHuuqx)xw)<#!ItI!yD8XGm6@Gy& zM*U4V92eHO87W*rby4Oler6aC`PkFSTWR-*U(K0P5~{J!@N+Hq?I$H;C?5sSKZH?Z z%TDRobyfwlMS+3~)nMAc5~z1~#7NkK2>uh)2CvwZFup`h_P&st`1new^?b; zEerinnV)Le5`ZoACD8FtxZH{YLD`xEc*hI)ld5snVA-b)@mGtL~j*_#9VZbqjuR^Hy$^!97 z{cspy^!J30FdM;(+r1`kC`Zq8m8Y~E4p47^5<$T~L>8j-Mi!Wmp@T&ZQ>9zsx6PCx zODn|{*CUb~^ps%@toNn2Kj#{F;NYCK`ulBhese3zs4Y<(^S4297^-=tJsu~*)Z;dk zfR4%_bfa!?jNw(ILmn@---y_Hpj;yR2HSGS*wDQf(5C-rS(Fg6vJhpyd)bIs{f zzp|Z0HHEHrZ^Y3;?|_%J$C~%bLwEByLi2T}1CuQ78kh%;xu#1}0j*aCYpeE|P_$?v zA!cM2eBsn9@{|;Grdi8p7ii2)3LH1P9i+H6<{ZQJ=+s_gr+KeajrQ`KRR(NSmYMM% zso5W!gTdo)Ek_Hnuff4DM|M{G?qLAFq3d^EM#RjLpwLdrT6#JPFT5ze7f*dd=X%Wd zy#3;c03UH%>t=A=x_N1=z@qY4`RY{_LX+jCj8#0FKA-;=4&4$ zE8Ht11^Lbmru;Vg_66M&%0b$i>-MKFZ)OxXy!W3kRT91{jwulb5ar~6c6<;KH&`^7 z;Yo8uYsoi|iwY-zx3s@pjecX%a*<%=$b@pfQ=va2%a;>g~PQY1b* z-#f}B+$r&sAwN7|yna$i7Ax=FJhVULyzJ=P-GFi;>N6WPwD&ls>b&qLCEpSvNw+jQx{h(U+&>2i=N5%TgPw7m`rRshy88;(Y~(0lYn+f zV63l!E78A7^c48Cu>7>?cf|bmq+q9|B$Z*e_pxZqq*=pTDYklS5~xQg><6M&-FyB} zSVp5&h+e-EtadZEcqpk}Fkiv3BbRaHh%TlsO0~+QR}FtuGr(Ju29HICO}^K^NNOD2 zY`}IrTUtAR_lJP-q6-wPE_E|jfKP$e5D`$Z9o=3zdNXkeN4MF104yQ_S0a=gVipG}g>72imTd00ESD2m zKId93up&)O@S+OT8WB3-ppk^)|s(MR_k0uAY%{~aFw33f$3tI?|OkHBp} z$dCZ6$}G54TdzF~w`Z{wn-WoUaC9)3;m?U%r#m_nZXAsfsWQB07VObO^7XkSci233?U9ac4hAm|^bN^ar#xCfT`h)AO8)N%jxDyGx)P>Fi=)z_kf`+6ZCr@5 zhnmiPj5=0fza{-85Mcw#>h)I`#_Fv}J(dW?&Xlkv?@U=0QhkY;pmuB2IQnN|dzTgq z;_N=zs>7+zCqzy$!3hN$-_R|N&FL^)k~rE6pB!GhiXx{Si_^2-!_Cq1X^8Y+kB1sA zw_rwP!n5>9SKQOp&j!m@dK{<@dS>OT zy`v0-PFhIvVHkkV#gPvtFTe;rec@BL+pN>AOU6#7rSpCLcE*}J(H4rO2zzq8ic{7! z{ReovXP>)I&k9(S0f=i(IUTZ#OYLnfIp0kgl>D`-T{msEsGq9BXHTNfOkHGZ6Lmv- zc2ZoMyfMDfbQ1-RHpTVimQQAg!dj`m##G=6-P=R;(?Pd)*wE@YkTpNPA%gVLo|=`$ ze*blPtJkJS3iDOHd#viQnTd%!!8}K^zsEoBE|SsteQvyE{0&Few)3@g<$cL*VC&O;_ozyYbgxX+n^xLzXJV5@ZwIMttS%RJC zYJC~gRamP{t;iwm+#+)C6*=ByFCLRn-`eL9m%IF0zkL^@?7l3&i&wg&?NhwdorA|B&GsDN>_V( zX?3*!B$5{Ca1lJ0FTd4hW3 zhu@a**-^rZZ*}TYReQ@}S3aRgAJC@^JnGl!(ku`trJ#Tqg~>?ppkr)Idb(5zZg9Ob zxVIOb@(7YxBtEAd&ZaUVmQigw^R+QiU2LmNcQ(7Hyv zs=H%`>?j(YzA21`FDXyS3yuugJEB~|h^`$o5++L^Nvlv#cmdoVs&+p=;-xoJ4-z3P z3XJ5z=CM#HMRGt9J8xjvBj(fJH`bnKD{FQhq?J72k6I>JhFb!3liecx2)O-GEJR`B^e0N)Wi`&90sSDGj@HBn2l zHf?~*F_%3In=)xb=i-`jGPnfqrdH0!6PVN93K%B!*-r;&DYDW#}nE;bUqlqaBMh$ttlFXcR*0f(MVmWlOWb=m6 zZ2dC2@OSr4Cgu#VpGAWfe8Uop+6FgH7m7TxnmfYwu1wFx`d9Y*Ja;b&8Pr&r$$A^hdz?!)!v#{l!lnS`u>x!1|^LYr`z$io~CD+30NYfte^Y(N#(Nt#; zeJ0|~#VsYU`^xF#KA*M*{>)&!m?*~H&hRpMSxF2;aaw|7iS{Tl_3Cf+t&~7R3g*vh z(`5MAOh7nN+p*qxLBfM5en#{QE)e`GQbXn0V;|KPLngs6J0F7nOo zHRBE-|G|>eWMS5*&I-Q*)!h}CCJ~Ec#?GLhz1GkieF%RDA^%+Y-jhJYE#Gm z3e@*Y{Hd=w-Z%(Ho%HVh3gvJQ{4s$TY4-y8seVzi%qujU-)ZCZ3vMD;L}o|2Y!f&! z;{di?%3NII(J4_Xhxn*Pvb5Z#%lPG8`7MN`g(=oUj zLIgXzArVmYD<+2Wg0JpecCR5}X-bw!XB$(4Y}xs4-t=<1f5R01@?X8LuHS#hVfz}3 zWMt1mOM;vBy0;5cPUdBILN-#a$ttJaUWV!Kz1T*9KBnB09ujKm2vW(|8s|d=cqs7w z{e7$$iIdaQm9}5B_xJZnsj0>+*_Di{pzO%!OIYw|MuDNdxV7|Xq&X_k`naL90w;|e za@6x0p3{fY6_vvWGO^mkc-VbWN zQm?OZa$#i$_V`zVfke4zU0SUyLEi_Hun$eCWvOZo%{a*9B4N#Lp;fFxS2E+CmXyFx z%=RxQCZ3f2;=w1QnJ84qnV_mV`bLuHMVl`grl_r2(;V_}!l`+h-q(>xLgpdZ$nR4U zLfC(IKWE;wGoIZ;Ha@~xk5SnxZMR||wAnvE}$pyK|?uEWfkO7aUc^Rq68^V6LF z)jkKevYNnIhr)xEVZV%gg=`G_&*Vk}+e4m0R}yX27{!m+erE@M+{XpwWiJE(9!T~P zN=YK`uBTla2lOy}#7XDnuC0K~ypXco){6yRk;07ds7d0_)^s)QWY|(W9CgByZU2N0 z#;pOhRIZtn7KhG-fdDrohqJK;DLa4O*rFZm2`x|VpRwfEl*mFCr}^aeJnET{!y||C zD@8@8(ux;FjkqSaBfrEF1Alg}DbDE0Js;YeXa-H}%Z+1Li$8*|wJ)X#xIYu8O)76%a0EZ{Q%?To`y;q|336)`JHTi};Ep0)8 zsjSQqP?Vv|ydlo-!Wpv-ygIJQaHcNnh#)6N+=+cu`BbIPd{~+t(?Q`_Ee7)VYx0%5$R(Nqt?>gn;hg*ay<``b|Op$20{ia)l_`4^$IzHZ;|s2eJH za^!9^);0ajq1p0VCR&6AwMK_43zWgn+Gz3>1K#w=_rD;N>!4;7vShgQXw$9XeSHh_ zaY%-80*e8I6X~p=z!pc+)8*=6t45<*jXzaY2O|ljNhvAHnwk-VPAT?3)gs8gBQ&XJ zeIt{ALaLpI0*B|uiHCZCz9fx_vCRTLLXn^^f0yly{qK~Z$c6%b zVkeSfTySM^=)r?{!#yOH!!tKV+VCQ3G*^XxV|-t0$hzP-f_x(u6%i+IT&c<#va4tZ zpy)$^?Om_!g|~)H)iEzdiqOFuqZEUX8v_@y9=2TFIaZ$)Q&}JB9UlR2{R-52Qy`Yj zo_Zc5iDhtA%!|n%^H&mIXhH#Oni^rP>ACBJi*}m#u>8a%8>*Y$N~}56xCY8*P^Sw% z??B3<^^e0X#UBCR9}WM+r2oEjN0-dxv2X>|0x!Z;!B{Y;(+CILV{s2l&-HTXoNwS& zWKYe_nV_J;3qeItmrgid7PWFlQ$iq1I*Bl#nkf!gfViZSmB^bck?}66%Y(M1o=hJtzjl_ zxP-=w92!xdp8g6dxeHQ}b~dQG`4ex&p7*h4Z85Cm5W+_|J>T#J4+~*Fos+gr5DktZ zJEEaU@5MA^#=`Wm+1X{<_krELR_|HdtR&qL%Z5zVBz|p6*t|c}dj?9lH6Td7GkEIz z9H=obM`E~~?1;f;MX*$AAbo5LGFRKnG2-)a#nwcvx?rbXPoh6Hc_yR;{RT7G28Htx8eL z^}$$qNei|{$Bxk`A4P<)7dztdEgAFfY+qZ9->9Vc1|~^A5a;@Ic=)@QBLzKp8cpaq+G-=E0H0*9C9TrGq|g(w9zqN8HU zKcbge(knMCn;Hb!CC2oORqiovU%Ewp+t2w`tR~x8aZHGIO}*-GjM~dl>~c_Pctik` zFOmUs{-`|BkMeDuP7qRrhO^%%E7jNi?0;`Se{(9go_$lFkT)NTpx}Ea(D_ybUtTRY zb4r1n^kecG=&*}p?L#i8_elKE)g5_A_yo7H^@hLIU7S{@1Lr<@G*_QS0$mHAvr$+^ zG#)%dV##j7CYG@)+S%gCQFnsbZCX;5Rlw*6Ak<0s^i58kR!(77(s?cAtqD7HMRVM8 z;y3#px66P8t|yqY>DmUJb=UQZ>-%}q-qDnr-*t~WSrpts*4#KtCEAseRz-oX2D|Ni zkIXS-eARmW*lH1$#>hb{Q6991Hxt{6@G4gqUQd~@7d&#gM23RmMZ6wW9tVeqQyllu z_V|1>yykJfKr%<&L6+QAb+q>6ZOJC(NowW?BCZa@x+AJ|kykP=FWLUR5VR;^Umfj; zM_Mru+dS|bzS|-U1?I8inToNiHoX}s_=gAz!?IDau25}ZNdHztL?yI09&E~OHmyn_ zwGi$sSj>bU;uk5eT?sRMZB>JJX< zDkN6V8?&=0$#jmE?4W?OI4Oj9DUmYJpMB{vJN=geBVKX7aot%mJHHGR8Fmx(l9j;X z4f>Jgh`u|@M|Gzt`WS%5=jKjtxNS|&D+*5b^niRxAyswtoYxTKXOSO$Sylm9@K_3v z=-c@i-^hzicNz>tV>O3h`0riLHAWLF_uq`3@o1t7YBOfS9Mek@*!3oM9hYZUv}AJWI}(P{Mj7To9^MDj*temED(K<;7G-qbe83RTT0;cJDId2I^2aPAAC63 z<$w=8e6L=%B4*9J`-;u;>bUe$l~^N^BfIK=i5S8Y(Cc=V!=E*g1P?BqS-lh<}wc2~S1+9Ilr7qy>zmaXM(LhRYI?Trb-$Z8S z=Y=r6h0bp+ZY@;49KYc8CPKs8kUcqUtYv4C7XzStYngiLbJQP+wj#?>6bZ3{s z0p~F1OHs({5BVIBUiD}8art(5eo105f9z89`}g(pv|kSIWe4Eq=BD1w557=Lo34P9 z+*3s~ft7FJYQ}{f?U>_7py(}i?~(WHabcqd(DuklnacAu)n-#wR_*jJDszOlF6;p1 zfN@O{Q}Yg$+OPJNUk(lu*hdDhC!D3WmjgOHA#$CF=X=s}z+0S{)2-dgm$ZA!%wwCB z<3Ea|D4u{7aDz=C=WB4gDm z1Z1rvsGjo{TyTa#H#R8tAetVUs4j;@mjc z=2kDlmM9dO8ta+u5mi_a2K*`vaWhH<8shG?Pl@+}I{mh@FHCrBP}37_MKUu)QkoF# z<5E9Bui8B=N=pkE(D+0Nq(L>GiBWD5ueJr~VW(7CI@(uSeDUKt9m7HCsW9ih6-f7> z2m)~JE%rLiKL?^{q2or8Yf_ti-%$whAC22P0=c1>vYHUVEzBKe8$4eE7j4!z!HEUW zbo*c4&sE*PeHrtYFc6zC5|cOs0(an9=2WC*>kQ@^W>7bv4n?oqE%jf?v=IPIn5oW| zO_o$JN0xIzWUr3yQh0wN!PhF@X|EWEcI*kQ(^g@ahBGRjtWSn~2D z>{I>^f!&4$YaUC?Fa7K`o15VIL}!&oVbth~3Wxv&*^@CMV)B3;*{1q)C1mkkvLLez zx6Z-O*A2vscVUqTz{u!zyw$4kq8?1Bf6jS@-;22K{fzcmz-)V7@a>HoYQ?b&4~1fm zH)yr0aT}A76P1GOSoHCY(%yEQ;wc4o@6kYpGqW3=V9&wH;@feLSA}$RRVK)Gum@U_ z?!+A#DU=U`soVPC_M}&-?yofHE&1rAD1o*%Ix_TRM@J71j2O_wF^#r6rp)FG(+x&K zlfzQqJ)%0!oT3nPokY+fXJ1SlW(`)V_QEXwYTq8-SJzrfVzHWXK#sJ&kU3icE0+{w z&X8L3<<4Ys-0hndK7~A?KyHZ8gN@BhN-w%wH@1 zRsTeeFxl!qCZ3U?{D)Qc9+8AwUH2W$9?MQ2AE<55*o4F_01{NQ>*GL2w_q&+u4>!z_)Kwxjz+%=~%#L@| zAB*E4R*`c~h2g|fYA%Tlxz>^yDb^<1`sH%^-E%DQGM3a-g!gTFHhms^SGRG>yW~*- zR0b!>9t=cFJ9K?bucn;7FMeuunc?!1;PrSLyNQ^j)%md;rSrCF(oY4Re(G`@qKK#z zg^~-#Mw`#Yem)HoaO*TXd#nfj_p@|rh0Ehh`33nfx9Y?7Ju6@ z!WxWXcC2uru<=;2#WtO1P$ux|DCms^x1o#SC9t&!O`$ja$V_HwO|`p=pnN0vUPJ;L zW9DOzQt)|{Qa8N2%mDL5=$8w8q=Q@@G7ir;sTp#`b}L%G#f{m-3Q@6*0|QPi3OJ83 z$}^^7k9K`nXwWP7%#wt*Hl?jChm3t^h%7Bhgf~uhLhxJE=-txHrbB!s^s0rmbxCC< zrq_xsT~`4K&wwpiI&(c4YIb?{L8W%7opoVlWlR$X`0*`9?a`9V0hcifrzz6K2Qq^` z*nBkualehhRamG*2`RB4^yh^r8$S0$zy*<==y%R7A5>@O9qE~4X5Jm?QN_a7>_@Hz z@2nRFgoCVOo%c!HG}~YE^LAvvsp6!`)49|jMHn))jf-RIp2;f-oF!oAoda7|ae;03 zLJf$vEdUw~m;1$aEpA9koT9HRW(t4!;}gNjx>;Xh@X&^CmimOI2Sgl4loA)#8UBXosZG!`Of?qjMeikjD;chl zo?7SR-zHC2Gv+Ijq9X2X?J$=3WN3^Tnf;}zKCi=F!0|7Mg}S(ee*NQ)2g*MK9_4RFT8 z(M{R{|5}cQb^gT;6$-b=86tkfcicn;e@9jwUU` zR`jx}u%6XlTOrTD4(dZ4SA~(5f|E68z!@JmU!bj>tRdDV5)&g4%tA5~qdkB437h%g ze0^3n(;jEM%N-KE-dUnwM94r>W9mKlTvX@ zpYPP`f-bI74T~Z%lbPZCxMJAnY^spbmqIc+!AV}1l-ktW)n|7L6+nU-MJTCqZWcKFs|C2lWzu`22TT#!?%2IHz1m5Ms7FU0~ zaCppEh%yKqQXE;1HdwbpX7d0EctnOTg3Y@ryvHbOR2Mg1TVMEiD~?7I3PW8@-XzUo z)Zau-Ts%zR_15AngeXGy9{}g=8gAd{NYP%F0F4-g2gWvAPKT(sASZF1EoSKrt7a^5 zng*4a1GG;3BSmBx-+;lkM8`ISMs_~j@f3JQ4qTR)RA3yPcaoNlhi&+!{F4$;pXVGbIoZ@Ydbu^aLFUuoXVg3GtWkp?aHId{7DIVUJfpjbs1`!q@ z>CZV;Q>DH<#Lc}CqasEtzM|WyOm3AeeS+%H`_sSUH%oZo`lNA zAfv|7fNzo*NqDt_Nkab9n}1wlCsQ;SIPxx~lpk%`S*cdO;_)ZNcuB-ezDX!Arwjoh zi)jz}XQHC7BDmUVtnueM#5ZMSsqs;wi!>QMOODZNGXXP+h)Dxd-E{yd1nN|gM3j7Z>c?R?UVl3fUk(Xij!Kgl|yVv`O3a$W#do$VS>seWV9b(mT;6 zzB%c1qOz#A)Err**JSVa)>K~|fiWioi~3Qa-5h&zV&&xIq|xR=tzQ1?jFEt^KPZg> z$t|Gm1h_OcmzVbJL)$TU9b?7ne>l$Ch^lz303m+_T#kP! zGCV|RI7|kUo4wIP&f*Z7xT71GVKST8BNXmMQw-ZBhPXmW&01B%xcE=KY}vTzH6M{-q>e^)01QhX;+C8!H~ zLr3k%dRyW;FVD^Uc9bhh9kV3cqyMuiG7TC7GZt(>8;%qPT~9+{NU@-hw54zR@Y3le zT9i{sGu&8N(Q`(#&0$FTzS)Plz#c;)2sE8{NV9=cEcXl0F4rw^Z`*e4lEopH5~xar zs3C*?^n)I=xx#w$1fBTatkK1{=P<^44|_OD!68@FFKZ7LPAtoz<-H;tZh=4Ec;Rz@ zkQ~axqR-t?bt>+w!HWWRL>`S~9_<+HAQ9P3T_unBc3cn%YeubD4uVJpUm>+z!#}}L z2^{H77d|c-b+~+Aet%`3Q1@=}EFiVdXpj;X-0TuqH$-iMz%>KtvFXEpEf-U8cyD`1!k_qzN8R>dGAvch4{%@Xy!j+P6%v*#WWw6R4v@xIbTpl|Y(;;2YA9;aJ zO=;`C9VWwwitk58ug={E=aXJ58|b>lii!ts`xD(}1b|;!Y(R(NLAri}-W;3l-Npaj z(t})pGnJV!nl#FM*jK0$7MFZx5=;`6-zwAM1W5dp(l~6Mw5vsy23*UqMJNV63G5Nl zCU+{DQ zp2$O%5ceA#SqwJHVbBuSm@-*>gOnCr;u1{a1D&<1@Wbrox1e7C6}z1~SLFW_iDt@R zir{Db8u1%?cy+2{F~qA*|vS}>G6KQoG$1mz|GB#*@UbXp#!D62#4T_A6ESk+{FUe;o zC$apMHrUi;qgsbG+h%6dF*HOxuAVjf?yu;)P|?2Ogh@O!5fC|8g1->L;Cf%er;NjsbJlblC|cl!oh#op1SNyk*spG_QC!9M;1c@=hYA(Z zYD^+I`+ni3&ku1e`w!U9OTW*FF@4?PxhRFJ0aV^2SLh#Hy_*Qo+zwO#++3d^!LAP| z`;I5lDpx8z-DeE1fEkYzxvzcubcPx*NLAJS;rZpoEiEkmmX_r7ox8@p56V!@(d37c zJ|-KuXx(A(%EO8~)ApIeFoDggN8iqh_H^e~T2~pE8N#y4;{BcIQ};!6lV=5BLeGf( z)P`%{WGt>=OC>A8mK>Fn`DX4km{EE52z`_v4(a9xxcqonTaSk|qmNGtod2%);*lct zuPejEZ6XqewHiz~F~R+Y>vo)xP6YZFL7*XJVr^{UuJ%+;d);MXLC~gu;2=CKa)4E+ zLo?_siCeNQoe7@JIjWtYLBim`8O@uttdhdvZ^#k}x-F~Lz^8uRC!#5TwZr^wQlV7d zu+eiv8Pq$nm3xTTpFi$jbFU}Vv0z$`xUz)C_6BuaeSiOR5g)=|QWkA-agmLUEj}x2 zVh~e5dej8xH7aah1%5i6>$ZU@fmPH9EK+5hd%6la25Qt`fJ_=b#+Ntw1X;VnQ|Z$4dIP_XlcQ7|^kfZ!ok9*lxYH=uxo)Tjy%M`fhvCIIhxC+(q= z)QREd$H?C)T+;&6uv}BgAoeK^q8^=M!a})^>~^}`+Qk(VVTFlL*}gJw`I~K0D$6P9 zak+ZCbMhO2@Ke7_8{%PV@y*_Wm2ko9+EbVr6}w9GpHnaR@&Nt2*EL@WO_6-$GUr+R4uzqhJepgaN_{Ofx z_0Gf$3@mZ=d1)T{9}KwFt*L}>OQMt!dlOxeUcSEIA&zDf86m1V9)X)vC9URDp9UaB z5w}z`P0DEi1r^*8?r_q7=8GkvJbkG%Hr>!$6(1c9f9CoMNiS;q&i|zyhV!t}WxvnA ze}C1$HpTg7Q5pY88cvJbh2qB>bI;(}K~Z;LvU|s_(msre?NR^bBx(K@zW*gqXmE98 zu@Sa*PE^2MozN^QE=sgQK)(4p5S~FQKZx`ufB=>>u5*&QiM(VY;F^@SF}N3Qq4^+C zIeZz~5g2_`KSt#csF(GV?8~?YkOKy};F`Mw)?2@Or1>w%NWBn!<2PK8p~(Iie`c+mZ8C71Z?+F%}O&FggQ9IRLs zR>R1m+FTX^zg)>)SgX*d^v1OMq$%YIEf#i-@z0>9!Di7}ruwo^VchIR5ugh|Lmn2` zg%=!_w_gC>+< zp#Wb!YE&e>%>%hb6jc++8%bD-JVH=IMPO?9gM+GN&7oC@T}ctGzAH-WG0W^9 zE8uchprTNKz)8~TCJJPaWq;GYo?mOpC1vO3T7V?p2Qb8a$*`+t5-mETr*~ft8=(L6 zq483MW>Ha5)*}ns5-hSHIJ)guFi0H#EiSl-JwGlpcq%8Rh&2cYN)3t}uai)KU0!W9 z0c|V&CxsU*VuOk^RvpFfguMm>Aqhmp869UVZfg|S1LWSRT~&Mn_!Q-l48DMlK2^LD zj0H)_jUTaub_ZlQM6p?OMox3tWLRLqZ`lj>0z&12;i>K@%Ju2W9H5jz38i5lu^2dI zi1Sb*9Qfxkoljxt9Ip6UMA@UJ&nCq~hWwY6|5nvoE24)aRHCrgtp57r^%4~xscyGnefuvNn!;%U34jyt;PPfz?s3AnoIEXL0Z z-naQhRx0+0ex)w~RxjcbGElQ(<9%PQPcA5!TdCcA^Kx39`^Z9O68}mJ1kFc;$qrVc z3~nP@K*-mN-^ha?5e~%xGadK@zM8|)O(;ZT&uipuOpQ)4DBOW|5r9>C0qLg6xmy9K zgzSzruAto;wLwU3X9kmzU^{(Y?gz=D{_qVo*R{hy%n`F*I9}lOHjnF@DP7T+{e>_TQlhq8m#k25;DzAJ6^% zy5uLUu4?Id9+Q7blb70Noj>^&GfWFN{$&FVdeLb^;fJAU*H%ol z9N|!Yh==N%9x{3i^YE(#2CJp%?HkGx6`d^MP#z&YXHrc5_JB@#*^!0@ryYN>(- zV|V2`S3W+J5w8#nF7yxUBnR!{KLgH*>w0l;nyuDqH3+f94xmL&63!l~z_eso*u%{o zOCRp&$nN<&$&qk!29;L&G!%g7-nl-^*Z6@Cv%Rye_6wo5mv6|8Q0G~Kd^^LeDf}AH z=f9V=+KbtrpUaC3nsqiF36K0usFYJX0};|-hOo$BY&O61Rb(s!Qko{Xdz)XmzE`W|Z1Fv=~b&ax*n_Gm5s4KPgO03A9IdNeG zO;uGFt%>JH+0)#Qc*0K;-+PU~Dl04R?(YrjSE%Ue#j6FwtjQIlOVjdj99K`o-rh%A zW|+BSHl=PR2Dz3Ozguh$>Q&}!46~$vPNFHFBi5zTk&whFJw8z&f+gfLA&AnvH__c- zXflJR-5uTWD0n0%z&LS<`9HZAiWV*!H~5o*ZXrYmH(NvMF#5feBfIn4{ODZXGC{8gAZC<#8Lra++aDFL`3anr?UeMI`9DX}18i z@|&E_x!g;>=Y0~HG~Kg`!SZaszC)V94;AVBR+qb-4}(RAH9tqq(ui^;89qYuC&+!n z2hW@rUBdItS-pdsQ_jB5KTTpixr4WJ`iJ?1q z$zZ_KZrAwVJ#(6g*_}0Zcy~L3GAFOJG$JDdN4-+(o;j8U2d!_G;XC<-6*9YbUHRU? z?yjBHSuuq1qvA3;SRQ0uX_{@p?v?9O~{IKB=eKZjP1z zS;z!~U^E4=r`J>HL3CJ);C;#O3V5k?G%jcKQ1{cr(HOPz+}FZ7zq~NhjV47o-G0C@ zN5Qu>b)dt|-OLtRpd0@FvaZur@H7JyzQ@~a32z8}r8iUig?KMOH_qu&(Qmr{6mjO0 zdGp_GY`b1sm2T%Nl=?NCL|KOXva*vbMs`S}UShnTztZwvgGO3x6CAhVV*AsIjJ8*M zi!pIZPaPdb!D-WDG0epwJ&q-*uwCj53<)rT5UKsJ)wuog_7|aB-dFXFp^EZNSWnlF&Eb7$SFgQnUwAkxTzCL~?=~pGkOZVjn zre40iX_;|NkV$FXU{sqVkj%FoxL&wV$qk$cT_F5O0iA7Bik@iskcfTTme=$7ORJM< z7TnA9VBI~KHCE8_%=S;d+-857og4+~cnZDoP&787wG$nPTCy;#BqOidZqVRURb0f7 zme>#!N=yQ5l#C}Yb*m;C&;}Up>yqhY-EuU9R_8T|rdV$<2l@a;gQ*LTgFr1`sK{Wp zB)&+Oks!>*p*fP~NFBu>EmX)ago@KMx?WzM&e<>Bwj#6B!RXjuMs~vIyKa)G%M&JB zek)C^#VGACmDhpO^>?nO6FP8o&?EyBkZ#nk3PVAk_Km@4c2I&XqlF`7+EnicOL5%2 z0^C2%CjJ$3t6gHq0&hL_Na{WR6QHNcjeI_)gf1kkwp)!BVHanIyK%T@ATMn#l&Tub z@o7i4HlcV+{x5jer-_OlMO}OZ2NQY%b5BTwf(OCg)S~egXhQSHf~%G(o#!PDidvWU ze^`JoPSM38rWDA+*k9x<0j>M(-$y)zROyP-%7TRu^Tv8r7|{8jC1lOHA|Vo?Vx|I% z*aOLifdA?pLVu_Gnsx}`G?tz2zORBnB022;DI)pbulh~JYQCy`#R0~`|94&{>3grp zzoKAj(!l@vF#r{bi4N|?B%-pjs44}|F*ITn3zx54frU$!M*-cx7Pz{@4VVX29~nrp zt(9IjC1Rcm#{K`y9=FeC%#z883hoNC!Oq7w7(LVfv+-MTh$w1|V=uVYOMEnYII5e` zMxl76+5F(pAGid4N;i)dfP(;uPs`l8|L${f+75T%jAra8-#?}!7&hN=ui`v(fV0U+4#Gr+L&mzn%8$-@0R+A0F|kp;Mv6Cg3Ruo zvtaeu%Pe<6FIQ^x)G9MehFS6@#c&YYGoAXlgd)DW)QLiGom+D+hT;aW8w|a1OtY0* zEP*Kp0!WAXnqyHY`gF3NIomo@?k&hINHvx|g37+ctSQNf_doFz{>?=)42Fta%+rs3 zrdg)^h|o|}bT|Yl9yTqwu`2=9X<{Wc)xQIY^kv@?2}YA*CGaKKc_?5o!dB|9(Ldf& zJ&R7j5{c~~RcSH2(%#BRlO!qDrlYQperQ3f)NZyUMbe>03<2kpk^dKE?;KoN__Yhh zww;dCv2C8%=#HIqY}>Y-bc~K|Cmo|>+qUk>Z|?nOYG!WL{qoPQRGoA7e%D^_;`6Mx z#pPxugp(_)DX8_Cl{(ixgCSFDYB17}OI9Q?@a9rSB7H7uKP%Nj%^&6BLEYmVif!A` z`-4jwCgj)h-EhA-gSJE+%vaWy$n#pVbRi8 zP(FlkqVY&km<{Bb3^}AqK?R8xVL*ij!d9yh|P-mGli_NUFjqp)u>+n zCj6vu%Y?CMaCa$YwzZ9 zm;9~aDL-hb$H%B}1%343EpshM9VUV?8Z7`T8j{0u&&K_@eS>Z;bm0%k>mrenii#lND?axu@s3_jSM;+i+W6N#cBBjtm$kH{we5PQ1WDEN;dXa-HzM-A zo#3>vwx(cYjQz{l?KQg#;6YawgI1;^A6O^H5DHf(m#9Fex}Y5hjX>uV2v<9IJ~~HA zkhvY@yQ7>KKA6*uSE%!e6M6*YK-Q?4cLxogeRWzq-&%Orus?OG$@$AQ7ta8-+P1Ws zqF|ALRmkA?#{?O?Q+KxOh8lT2dGu_|ij?=W?;^Ho&VGIBX)$sZa8$bA+2#FqfgH|v z)kvcp4~u}j&He;4g7Off`1vM!CYRp-=Gzgxnh0h7$2)fT-+V&XFCrN@HYehjIQq|9 zF7L&)sqDE*E^p{k+lw6q-;0CGOI_jJ%eFMN+Mr}t#zF*?eluXiP#gn;#Y~wP-q66- zWW5?PWB$9iI3ytfEui7&M zD5#ilr&%92M&Gv|f|qEIfow$vqgo>qdTHWA$CE0S5}9$rx*~%401yQjkuD!7JeL`@ zhNy;lQqvzuSHiAgCC$W##Rb}xFQYy>lw8<)_!kC{@B5p^7V*h!uvc0&6vj&S3u=`k zkQLR5)~7EPmQF06?VNTCbiCp3)AvtEO&y(yffePNRezHnoQ+>Sw9pQj}cwxReXiGu&&=DOii^lugyJ z?Lu3JPY=H~Vg#x_EeaATUsYPhJ8X)+=Jae$lYAvyW$TUfw|~OID!X z45+~j1xJt4VE)=O7B>gwuPiN&G^pbUpZ2Exk+j=13V z_xvWV{YAqE)?)`CW5crsx8$ZQCRMIcuN!CPE2+pz#fMSA-|4MZSHu(+``@}33&0hU z?P##Hz#7R?6W=FyJ8s@6bytwn67>fI`8t2?olTmMUXX-z5<%4rSvMHT$$wkMP1}=V znI3&$N3Qp&5_o{Ggr0MP3q%Fe?J*Qd%$1E$CmWIn`t>(PbYQYkp$!XO1 zv-Nh8cXWiydbm%j9IZ+-s!TTO^aAHr(>S0v^BQzF5yuF$3!U!j*g57mGJ&W;K0L3va57pUSUUzY5&dUbWp!b`}i0sEp24o ztc5CL+HiY2z8z!(d5L(lnTcs!venSD;Sq!6vvYI64JG(URbI>e9Y>>z%R~`aL8Teeb>MLy zG)(Bt^xLp1dK=^YVU=Um4GNa?t?NeXsr~QY?+U57Tw5l2s{?D9x3%~RF^Nn(vw%O^ zfE7nudn+F(6L%Mf@xzZM*>QQFdnak=*t*?Cm%DdSgx|^aSH*b6KZZU7@R-Ss zmAthOUv<4w7m?@d7`bIjyO9?gv}SOlj}Tl~XiXjWHGa99Oc?RKhae>mMQ_@Yq;*a>Ow_y#+_^`C zK#6@~WvTz==Cl6zuI&RI+58#bEKpw3v=}ic5V){NZ*1y9YTA>UN=b)K$1M2QV&wlS@#&PipK8?hcrJrovfcxiz1*XG@Hk4@(uG11?|vh?9YjBE=?%R>x-Rx)AjtK-XQC{VanT8h4%hi z!_-%=ii=RGHqEe(BXw)UMx?Vn90FRHzqKW;TmqX6|DEV}VnuGbST{7eROr8?fT}xX z*_AuTtm~WG-p#JmHtdgJTfWvi<$!+hD>L}-r2!D|U*AG0j`~mJ_?1sE7d<}H&BwAd5Vo4}|C$aiAMwM;WFR2- zM*De)X+HNyXm(X_-SMmU{XrR~Z%?EGMkvOUBYfcr-$zy&5x|27obToI?`VFfJV4-- zXBr2G*SY0CQ9nH@-K5d4npD7MI|?4Cnz%T6a|>=Ms^CeF3x+sUR31BX(<5z@diapv zP+G)LLh#U5m?vM*)PlH%5m{G9(OyX!fIz27EV*}cGM^GR5R$G9rYf4nT}B4Le4M_r zAP0ufL{v1jFFILPJOKLQcs`Km9kh0Sw(g9O+8I_5U?rUmOGV_udAX;lh4P0v^#-z) z>+PKF?3T3XcbwYE9{Qh0h)~!&_S(kkNFhLs&D<&z4_vw+6?D7sD`zWCHZc7n2Cl$N z8it(~w)AfF?)$*Ca(oiZCCVJ}IYoy>hli)}zsQ1c_ z_1HZn^J$MU(Ffo1;`z5MYj%+}1?>jae03^bPQhWS@RF5{KnR=~)?L$Vt%t1p1&$rE zj0@o>Gqv=WQUaG}S$h&x9%Le7tM0yvqe1sM$91X%k?QrMG4kituC{!2< zIBnTowf~K!58{cxH-Pdl_-SF_#K2KXrB>Hhs{vFpY$S{(1xyo;4a{TcLULoo9- zFCV9^rEPwdQk%^5iegy9*Rc)LTR+3*7({(p^C5U6LTR z%{hl1Uh;>Pm1neo(f!9T9|4+e)Dr-8V#R`WC3UnZ{FMML--N@HseRUuaz z^UP>EmKPGN*e8)m5>!4N{;Bu+iQ1ZCK1em#1`&Bd%=I$uNKlnKl~2IGd>-od9xwXa zH$T!gFx%&BHv4t8__JYvLBR{^42s$;Y=`=%sb@?*`XkoL^zqWJ2WW=NZ zI2(^Xo8rJGX#NGWw{@>haxl>B6=^khu zaajc!ip`7s$9J+bw~E{dUumPQD+c2qq^?TbF+of%$aRi-RJ~}dD_H6O*fWo%7$_JO zBDrTnJX-=?bJqqca~X^Hmc?r9d0$;SMmZv=GfgC?P(rn!xR01w1zmKrc^7Ldy8L%x zi&T>}^UkR=H`l`p=IqZq2&~Y%jPQEK8nQq<0!1tZsZ(Gs0~Y zy5K|$WT#`q;h7iu%(1e$6d9C_BX4om`=D6%tBpCy8Em-{*%I-& ze}i_z(0r{HP=b0HGIbUKg3XgWCp_;2jT&~ZW5;`GTuRr>l%@%spAubO6|%lcSQeCw z{ru3&_hXJu7GonLe~mnPQF>$e`R+B5zHjP{-3f740muHWW{I2JHG@&EPy!oju&BK| z9at4?VjWosu=b#VtZT&e{8(Z`tV_(rN%dT}-%nm%ERNxotO)g=H0eWC4jc`B(xe}# zdw{Ze{N77fglEXy!c<-_!=(vI8*kEvc!Ip@zx^lkqzOu1k}BeP;kvLbg40j%^u?^IM7#% zSg%M+#y8$B@7kD=n8TLm)j#&;&ur2%)+6WER^I3g9+$+eznO4XaY;*~SFf$)AD``spcTumXjt*xpA38m+0BORjS^|7U+0VG~j?dPJxRPAd z=1_TVKWwt^1JxSw$a5Y81B!=`+MdCzJYD(5uxj!OZL;&D1E!$J0;dzq6wizoMU2Yv)FlAV4ySyjMPEGctn3DV2P*s%h2Ul+ye4nw2nb8;4wo@E}jGD1Q8Cn-arKW_(%45eF)osC;+wE+bL$=f89Pc9h ziRHr>sTzvg2Q151rA2pEM;~~%bNNW2t~QPB>E=o(`P>yu0EML!TfLQk&wq9thJy6l zh)riu9OS*TWlhv69@SSYfxu;!wU_?y^s+?iCbnyE5Y`Ae|7Or4Y;~d5^3#nqUkz%= zo6!C}UH6MJQ4able^me}EL%T)!%3a__fk_O5#-K>S%G6uLc*u?oD4t$VNaBLs=Q4v z>dIR`LaSq0PIpqf&%zk8j~k({ljk)cJ&8egkdvq@_q1;N==Sku&oR@@LQr2m02BG< zj-4mVA?~hAm&ea)5`zJ4#-b!Kv8>+^s>Vo)DIr;FDzp>TEB6kd0u1d~QGlDYc&Pd$ zEl=8>)Jj%0I}Dj1zBX1)%uFb=ISy_eYp>Uv?T(^`wa!oLhVC~xfQik;wW>Y<%o3ho zlH+z;fblYB{NScR^(L{+Vxu)!gGe{@bcfjfHkNJ;lTY?NG}PVR`V4#_N6auFIf+@) zX&3jJg$u--EiNObe>%u(#~u<#zlJJk7^HPMS#|S6i|7X^2`*r)_ZTE3M$C1Q%YGV= z_sZ|mp(btgG8i=8Z+1PbFH{jf4FD0wa1YzKAQ*?I(?oYVI)^l7{Gbthn<{DvFzC|( zmS9}2+c&#}_hT9QTF-237`y!c{?8PD+{V~#7;8KfS#i~o-J(oiAf65kA|$qce@1Uw z;I)0cTzV)70yw~doE)}CW}4VEk25!koPKEPf`S_ut49Mx=2cvt7lO;`0*0GpuR}yt zjv1e*7V%_{S@`<>X5bvaQzL6+x(#&_%ELXaIwrIXi9vx^BY(GPslxEQOo`;%klX#1 z53ler@w=!vj?&ff%AD-d)}Hn9lF{Hgi!B1Ij64>h_IOY}1PW86Ox$?CJGQVe=e#j+ zJlAA+sXO&0gi^pNP+1B&1y1_!KSv>fq23VGa%pm4+$7A6YHf%Yye#ivwHU|Bd6CsI ze6;Dg12GC%nE8%e=Q3fC#km>9U3QLO+l1g$*S?JtY|UEA?0!wWIvJ9`JWtL&62&&# za>{iYQ{-@q&0r8S=(i11W5D|Pc#aj)j~W42o~{MrI82}+YHvUv`bf05Jj@aQ`d%d4 zoCyHw;Fm1(J+#m9u#Hf>6Jxs1mP%N9G$M%G<%bpH)yV0DhS z$yj}5*2+9OirM-*LFy|{33oDK?zGZ0vSZitGJi*sMeaO1rY){ZouB>z z0tQeJ)zMvg)|IC6A0L_cPHjvz_EgSrwz*JANw6h>G+JI*`a2rAdCvBuKiZRbPUtS4 z46VGHiv5dA!Vf?NXVY~Hfbzrm(oc?`wPD10WwIF5hKc%RH>1^w*CgP{ ztU6&w)VZP8RiIY=HI-xG7I%TtMm@k83EN3bmh9#rTJp>kjtnLiHs~@Hj#4rl{zX|k zBl{$ zQA1e?$;~Xy+fonw4#b;pfxx0nrvjtF!i@tZK{vI<3{E8%%bBK}hf{bNmxHNd;(k7x zOe`ciR(mwLB$$L0_zDD?3fhdOTrDlTlMpQYxEz6xBlIcqOHGlwX9I|osVueFmEbn>{459_0#H{_iDY_Rv=G*!mrR;@dk#D*;r`?_~>{ z+ufhfJTwGYbWuR$UxqeAz13kbRnB&;JbY24hW%l`hN2ZDI>orAX5Y1u?e(VMGo__} z!a~J&`LZoi?>;lP8x~+D%Sf)KM%9WW|5T~cd0(2XP{=()$kJ;)juUZhM87knWiA)z zM1rxw=^p3+l1nA@t)Lg9eO4GuQ6vaVSVF>()%F*=c@j##kYD^ZjD#ebX(v<_L^%QJ znd9z_n4&6XgGa+pM2YWUDXM5uKkx7$xiNYUiTcn%)hxySC{3R>n2#e>LQMk+~JT?S}R@lb9T)MZ0A-u<1MG*lo0c6oGb4Y2k z+Pp;eBMSPEdTwl>ujvjb)yx`J{qE1i9pteo{_t2ZmT$fd8pa?ERbDPp($01L+dSXs z&K@Ls$d9Cvpx*xB*vxo7qh?92R;qK?907+8N}0}V2@3EN97+ohx8%HfI*(nmrsxM{ z`VpK^>}X2Vs7p$sc5bQWfHl6O&#rFfKarhq)ZhJ7IR)$#hOS(rc)V?F9{)Vh5B4f! zIU!plV*h1D-CE_)Sxi%K0i+ZtXt(D>*`eUE0wHB)hq+O|o*7uGKV+85jiNO9&J#^2 zHxgYg7M5Gbi%0Og#aYboG2YOCtW9qAXodpo8-@JmrVs34ID~8y97Fr#CDZs6*<+IN zeK!T9*)nPMiw}=fD^|jwu_iD`feNoi`Jbf>&EOwjHI4sgxAXs7=J-Eqo3h%q~o(8{zRB!jX&8m=DZ{1M|?n!^p1&p}n`?+J~g^qDx%h3?yJ- ziERZB9nX=dygbiQ*MBGpF@YNIt7Du?OsXl%-0I63-@A?i%hJXW8WB`3{Vg=Ulb$-% zH~crV=os3xd_!C#L;{wSrSL4C@NA4Fx!=_8;4UH>_kQb7wx6sI%oR~DcF4~-It1Rb zyhkhQ%g2MTl5|MdH;@O9jimLf_7)-FI$6SIvgP!k34 z3RJ}@_m0g5{)k#i_54~WM0~|@aEJMR0ukAK%0#It6(*QEl@YG)_TDfh1?=ytd?ePVIyD5H4%doWx|O-&&J}vt3=|ed?J|GWesFmvwKG0p_AkV zRSNJRKOH{b%Uh>I2IC7?b;m*T+Y$>-&kKj@_v^VeR${d19`km=b-;TBwEN8k{0{+s zOuzpMC+EI*Jab$;sek8oX0*HH%rQ3mgt<`BRe}9$^GVq}l>65#`W3`eZ*|OQt$_&8Gztt#_l&3nG`w_M#jrsLNPT%nMBK>5GWv>jt#&A&*RC> zqeYT1iMCD*nFLb`S55=|%_16*-w$xWWV)DBMcQ(tN=$M@blvPuIJPrvy%kbmJ?Gur zul4oCTt82>)6&D&_+N7YYFWibEWe>>4xC8Z6!gXWy$|@a36Z)dQ|v`EbQ2;8zjJg* z>7IxP&qHBra1olBH%I1>-JiWbTl3u)N@}X@=Lx~0-bmn_u_Q9h_t`BC!|3WGx+X2Ggf&8<0lXM{DMp{~W@)?I`7>tdF48Svg1QMy~rl_P8&&JbmfY4BkL0*NV ziaQTO&4R-1u9vKoEKJVMB_-pMko{v`+YvF+e+DU8aY`WO2hvSRDAKgcKHr)=2rHBd ztYfO)Xk8`wEEWGN3W+ZQt zfq(qX+3I?6Ao^1bMLV+#bQ6$?NOtVAExuHiO>BcXs^gWB{3Mfv%lAc4JhlgaSeMgp3SLacard&~x)>=4p0 zNgyM=_OH}Eqpt}x{oEg$8WoF1b(9HP$oUc&dyejPXCzEcL5QoW%9m-QveEcOCcK`n z*mnNA#%|on;AT>ososT|&YK>gDJIKF7f@h8j?YjOLCh=uFpZmsDs^vA)gPT>m%Y8m%7(vO=)0_JrQya`?^lhfgp9fw=7R zJ=1SsHktUQrOl}q|KvmZd1B6O3vEjyQzoI1fqY>30x*xFZr>gjFgwN9zIhgIiy#iKlg|8+Ha|0x{pXUV z*fSwyMwM;fyek>wsIS29?RZneiw20wP9*ijIXN!o_4%x3;CYp}3O2?Nx<}fwT<@1` z`!zdNxA{6~?IXp}-0s>;l6_VTW z(wxk{GbcJEl{HY+o~f{k*bVzXW%aHw&5UfqfRm!aYm`6y>?3`-ADppWH97Z|L$X< zkNwf3BFHwg?hv)|-svYY!rCJlD>znLhpBx#f~V_tBKdZAK=kj;9{OGm=|HD5fpO#A z!_QJHlKt0r18!>Zl(iTu}#&A=_?qG7--TR&y z9ffc=$Z0O|=(KY0phD2| zMFmjC?zLK*9qgpqkbn}Vmy4%i^1 zAo}1X{djMLOk6TyUQA|9l#0vO!CS0r3R2$svWkwd(Qu#yjP%N~p?U5o39+=|Ud(I` zW3_bH9^7#+W>`kFQ-G21{Q^7;jcv`rgQfd20)TtG^M$9n&7K<`9V0Ix*_HEVEToF> zKDqI2@;CU+51&UuIz7HXhs1#L7nm2VrH9p5ceCt3W6?M}{WP*{j&W}y)0im1X4Xc} z6;2gk2+%bf^K19p>5X-nI>DzDrhmE7SS)Z5GF-~L0zkl8t%!5M)<~^ zZy!j_n|;K_Xt*&e_c|%T!{}tlX&LV0lMU>t`;xtTGq|*4JKRV7AkRR+0Z{<5WMaA| zK2rWDXLw~So;#ykRhzZf#_daSD31$xfRgiT7AxiP`^|1l3AZLSbtoq^ybeb%KXCfEtin61`pnafazXOpzWL`nKG+IB)#!s2R*C9eZL zvFjsXW}|T@4hP(BWC7w?0CEwaAhepSdM_VYeLuWX=(SvIpq2KQo?zUy)kF+rABV!v z;}er3nEgpF+|9@;GAL3Xw~4)S^xmGo>$Y&^t{xt$c%+mNo>&@~+XclhZypf)I-!b7 zQOf$gUag+_Tu8o|`Z8iqWSqfaGWHWnmU>$A^55EgE18x8j!I$E%mYmrk#lj>UnFU2 z)?`wphxA_mk+Xa(-xe9;t>t!IyEyW?OS|@S_cvW#^rN0z_P-Ti7Lhz6#2VcR3N^m) zwysb;hyZBpJ}{edz1eu^N2sD1I^Y?rcA-y+NcJ)kXDQx7@w!4;{J7?V#*6sT>ITJO zjc2iJ@w@5`O$InLD4#+|KQFkd3QHPZMM`5B65f?HI=jT;@x{UF3wGFd7z+%hI&>K= z|5cI@Ak}+4-#8*;3N^@(jgQ9V#UR2Pfep2sgy4m*+B&T+yY?@QG3K3&3D|rbQN6uh zax$-aA#w-P7(v0ajz%)7Jl-<@a-o0K)Ov z#*UInhb=0-V-IuqCyPE^zSlcsEpZ7HM<*Pocf7xlJh*y1Uu4Ti-8{w4*9LM9KVlqB zaL~bGjX&W!jN&BH;k<+P>9PvELSh&rpx%u+A+_V)Ad^|d%x&QIZnmeV>IsgulMTM@ zL2JYzn!kdHk%NbaQ#Kd~&TeBrPnC$0PyOs!w5{yJCGZEu?Hm;g81%#9g}Qb6Rb91v z+~3YjUYwA*DS8>xZTEOu|8z*KJAp0jY<`c2fX8@2#JO=rsq5AlT$R}PchsKw%R*5B zEtLL3xf*bqqE81^EHaR2hK(_VJeFjHZWQgy=QDlSsvU1gRboY=_x6D8{+ijngIuQG z!jru=3S~Q_?R3eQ&Rsx3mL@fEuFp2We*_q0bL61?_z*|JPMJGMH=j0#IJ~3KezC=W zz9=d)rUVPz#gmd7PS+f`>y>q=7hYxlSW{qiLoe<4(6#xviPo-I@9Eq$H#+Xu1LBy? zl$xd|2p9Q#_&KXg2C#(_mE?cc1((lyw7rl%{j%8^TmGD!p4&8A2zV_7=jn&n^m(jW zbDR=4#z!ze-0UYL_Kq&meFHLLEQBgDzBL4``rL}!{N#>Q6*6jM{mg-WKC+Cx-m&!= zWOU}BYl5rxyc57mF)>nLOZ>T)$8s+Cyl81~6uw%Tw(f6M=i)zga<&H)nlGXhf3xLx z!9|I75g@#0@`EPMetr@-`>S_}0AqJpdBE9sU{ix~DFkcsgtQh#$-sFNbmdVdLoK_gz>Eu+ zLloUmhEtX`55+q+7Z~5(m?N07J!(EeUlw4j~sQO94e=R z+bVE31GnZ6M97!4by8&WMdEe=$FhdWt%!VREjHbNY4=>xFm4}-3<$eGmyVjdrDp10#_eeX4;j_ZL(u`O6KgePM zodR0p@^ooMS#Pm7RAUneRao-xDI^7i&_-AUDnNR9;p%^AdM-{6GSkO%0-cNhIjQUr zp!#2c=3kuuZzRJ1QHuWmk8Bosr}kH$*SEDojKfg_lY-}=%@{}r@L1k;eL)etV!q&_ zN%@2$=f2-&+hIvRj#SsnDS337|3y(6;Dto!<;j(c%&wwFn*9eLP6b?Cg!sz_IZF*8 zJ6aSZ+<7>Vqz8amo)f#;dLIdF7lQR(DftgcPeu9*$$fGu42w9Z&YrBOW^q&vmgERu=iNDXdH7E2S`g&Q6$ znloE_N0724u?7hC1TVh%DXuXLJd_F+CJ_F?ddv)lLQZhBd-RWo2b{z!t+vQiiOUm; z+jKgDgz8IR>_CB;v*A^$(_VJmBIPTF?f*?Rs@0r4#(5d9h*QP}68I1i%J~?Wf`noH zc0xy(P*x?CvX}(WyS%RjRY~{?{qK z!MV?S%Jyh1V_(GP&qu+lqCu7oYu@LDPk`5@t6t%(1%(n}!S0r4$J5``8vZAI^^_7t zri-Fj?i_Z|h*U+~BT7eD43Kg(@;&$1RNrSD%gu_zQijBV-!iR-gTBTl;fVx+L3k(m zmrIs>&QpaQ{A{wZJKt9d1x)E}Io z?4Lnh;orSG&!!nnTvAX&pXWJtV;^Ty5WSof@OU6kJPTq&`D|SHUqGBO7w!60Y_DhV zW3SF0-}qkY8#~&Y2{~<69=rao~KpxIqXl`Sn%BFce=cr z$VElx4&t(n3H@Jqj%J?A?s=IXy&z=g!^fxAWOe!^?pWZkMq^Ng!!rE^RXYiobE9Ll z-z-O^8UBputF!oJ#&zddpVCs(W)AmJ%#F~{Qkp42-adE(re*|Icvp{kSNcO=50q-D zLwD-v>JI1*>ll5qhr8Q@&@!3->3mtptUqEJBM`vhwg4F!qsNPNHVzInq|m94(O={) zxMgUFkhM0^iR+}&PQ*#ItMX3aVmlA9DEOt!{{Z;wIwUV0>DqC&;U6gHb0bqzhNdN% z@)&u!y8#^Czm zx$5I|r#$ljkXX(r0wvs<$pS99*aaAzY%ch0ZQUo0x1O&8?Gyqk9p&`OinN{{F-KYIa^NjXx1qSRAw-1MW_tj&Amg%Pg;lsk zS59Ich9dI_gvv&shWkYg5K`mj-YmtEVlkACgNa3gSojr(c85a&%Y0e-Ro?vyW&d~N zx=JlF1_1SSKB;;zj$S%Wm2ng@9(r`GopHiRO+r56*8M28DZLoa@hNUzm7^0C8PqNv zgEoI`@TU`@OcYuWU&|ZX&p^})3XvYJND5fre53A6QSjg;bTdcG_`tJ*k{?g^Pf&q= zvN4_U2JB&i-vX8VrA;qyFtTDLJqxp;Dg{m4}rr58aFM za-hEAg*t`-AQz)XF*X((O!zfex)Aok4V3(C+7l<=|DItNe{Do9(Jn2|CvZ_bWFyVw z;u}znQk)ht; zRU7!7(UAVQ;kGip)?&5M>o$^XJ?%&cEDbC=;S_SauJL+~OVd3F7gL6*a{Ugy3n!8O zBPi#8L6~C-RBs$_rRW_Lbvoi#IzeA_{JsjeFZ`Q7uBmPBJ?*@sT(yB-3V6aPW+Ycc z!Pd1~%U*&^X?Z!%p^TirrX9?%8X@J;$2S%mE#tMv!d)iH_BB<7jh$pVW#gZVYmEW7$Bb_8;Ecy+ZhC}zCf}XBK#0$=wpP$Z`XPFYO0USaiXzlSJWZ)r7Q20CR_Gsk(%Uj(*gfx z&K`3%iCNLeNTMJDnP(24-J;kZ$HzNeCHg#09Vht@jR>Bn8awW)6dcWRz}t+TF5l1= zC(O)-9Gk9+*Z!}i^rY@7B7sivkY0P)H@up91j=euk}6;|GwRK4~Cgzb-2%! zJ)e}MA3JX2e^N07q3no?1&G6y%#Ggc|7Em2kTdbamC<%7R}LH;sg9i)`Z*8^jkew! z93h<(fICkY)ZXUQ)F4b=5kR_V7~$Z>RpK`XHaYrN^9~idtt(c-DbLTH_CSf39iGZ> zA>4E2*Ttt7d;XhrxpemB>&9CmHmh%~$fCp2f^}d39!<(bA8;Nmqf#~HBk~h$pchVu(aHi%_dl5v8_i8#z+1+!piyw z@2mhr5`;o5pj-=JHIe9rDU2F%PmRcV&12-SXoSj$v2iZ^L6A3!qXqobA`~p}9wb2k z{AU%-udi8<^?v>T-?*~c7H8rLwvG7=(^O{H@+ zyqV8``I?7@NR|$~0Bz3I$Ufh**dX(|`6$Q2JmpdEP6l|_mVba6K)u_rB@UsjK2jFM z99J_I3?3YmecBjfC=ykNv+8>f2ZSe1>o`pv&acami0o82<0oz z_>9LiD`vp2vtqJYIv~dP0-1Ufa1V5qKOAd4XlJatkPr3>*CD0|ww_Bo(mWQuiq$aV z-g^mtz>o}F!op%%6z`BEp^~9e-ievxlxrU4{g|P*8SmmR?EzJUgG8WTF2FG7U^5eF zI}zos6Kv5pkO)I=m}zMyysS%4@?nz16oI++1gdI=g*tKuJuNC}Qc9^XH9(cji7gY` zbCS<0eQw5DK+(Pj*l?gpS>iyqE}jW8MT&C32sCFBVt^S<6YMQ*DrBrTl$Oua9n-n%xdjPI3&O$PCAqd6p> ztK4_G>^H}p_4%poIYmBONLQcRR4)?&V=jTXST*2lU>6Ax2Qs42Ef=dH_4mh;laiAW zJ-yCX8rj&{mDJUT#*%3nTZku4#3HqXWkQ0IGDBd~!XpOsoej-b$=OvA)^V)WJOjb%VcThIlm8`jnhGIA^ zh{ri)PEM!v1iy8^N!cL^0SXBS-OYhQa@`zc>yGV6kJL>1A#t7X^A{h<(ZbT}I8s5$ z>JdficzkI1&zc~X^twGHfx6#W$KcB?Ilh5ZpN`n{@gCCg`oP_^LjZi(=jZ22&DsEe zf6y;NR+tzmFq8XNr6p-&!vH)wZ2sTBuFsfxefB<_PPpE%8vA_d;E3D`^C+6Yj!Fm0 zsoa2mB+bZC+ANWEHsYN8CImhkbl1w%Y9iVYTR3>)v_7F#19@V%cwJ6k_I{WHQX$AY1c{TZqio(Xh<>Kqm#oC zErqMTIlcVHu0*S?2QQLJ)fU&i1+ePj+8s zaUsx*r7e+bMggB2Il8vyXBBW1n_*+jbs-)c9QMfzj?X?YA2wWSi9j`Cn(bxEJBJw7 zy3x0RoU^229!2+SA^u~;=>MV1)1Jr2FNrP!!z?US)8hB`=5=#>JNzk$ z9C|yX76n6eT&`)ZZa2^5`oXYavpF#LSrXr@v=udnWjT<~V}1#k$_H9uS#31BSvlN8 zDBBqIDga?p`p-t3e~<}Yvh~_q-{kAYXwvZ}`j4S1T=F>tA=T#6QCYuVuhg0@)V@`B zI#n-^$nd&M|8f>`=WmQGPUNhQvuek0uLuaH^_Ha{=`m_f)Deh2)d))8YuE;Ck33ZI!MGXET`KOPev_ z>pb;k&w{@7?%#0rPtPv4TRGet}BEp7^s%%NKN~Q!0 zje&}fx_)9?ih*j8d%r4x#~VD$*e9(;=XAf-nPB<9{4XrP#$24g5y5&({O4;w2y)jA z<_QHbR`}1dXjVGhS?THN`JT1{Q(Hofokfnn)0X@i^~?9S89vF3p!a0>7X|m_?dAY$ z8um=Pez0wbJ8~8tW`4dLi|bm03hLBrt-7#4ugNS7sA-Al+h#&UMCAK;+FkR0T;HwM zKFS&8qUlD!(kKv4AI$_E6SII@HpNsFBY#g$Ri>MvsPw92F;l-|K%wpB!6;RK<=giA_@vGL zH2UlEk-D!HWwVtZ2HHVD}Fg!7(?OT^zzB%>X);q*V%vFlB;vG%Vv(^7p zWeiSUcgp7L`{xX58f>IGBeS|KXXR#3rBf?CR&J^^(xlwkN19^L^sX%SVt( z;U{%@MIjSjq3fpUKbxw7`1IaRH4D7YFLNIeuWyg3rmk+-yo!s1qd!+H2c#jNoSY1y zG9)C2Jb@gFh)DNrk*@ZyBnt0|43mufP(WK$9|H;Zz{fvDGi`rK`T&>w2cA(+_wCouiW@5b=p(1d0k`P2ghU~ z;4x*?DGc=`&{t`kd6!Lxrub7lSPMrFb*MEp{o&NKB=ege1T)oIXz9UXE1-Oq>oEVdqdp`~+lT9)uZ(L&8RnN%OZ1sErwS zk+^;>$X-G^;ZUY~!ht$(2y^c1=MGuY6_4PLMn6dSlOHu(Bp(;c>u0B(eI-CENlO2l zc8|vL*Du3~40Z$rgs+)`zbq|>uYVd}2bXd9P%D3|S*9n65;)fYqW9cqM1PYjgG9s- z@sAx$WOCc@KmY+mxQ9=02^x+AI2tj^klTeq^i(j5~R-cC;0 z`{NJ0YZ{6X&EA~QTDxZ&bI+Q>I9hWOIZI|#^_2k>uG+DTv*78xPtSjNxV?+ViVaSckn4)PwQ#{s>H327>~+TWzM6t*r^vZG%!nRAQw@CPBXl@u-iBM1s|Z z5Dn@fUk~)v)%q|sM&p#to_`J*gr|?pTeJo5PVCFIOautKjOE7CKd>fgyn;{n> zvSQ@e2^c6k9-|v0s?#a|d18`;#~78WNwTj#H8vg*qR4S1Ley#A9-RbDC2aS}=OA3) z>C=ddUNjoEY1DV~GR8J3aD~vDPWlCJfv}Kl8pPr`0QYT`{;y+p^oCEZoT4lDX4Zt{>@+IAh>jH=0WsG|{W~KaE#-5~VwLH(k|OM? zlGh{9DqPJU!x1$m46MuG;1A*7lTC(1#?-^U-Q`KTE19HE(=}ss3d^WVQZ_~=A`*mh z%GK+SBu6B&zQAW%q0J0gcM7Vw=_ zz&;a&!e?=-`&3GjKfD35&}i9D`LmzmXr?muO;8<}hZw%^1BS0hwQ+^W+uT} zpK_rm5;qvMk?EAI%GDn!hLLMq0mf3!@E~W81nMpft$#-OxcpP=tE_@LiI}K3ASIv6 zj(}~dfn~5BmpFQvoM1q%Y#4WV`YB*;tk)-U?SRM4w!(c34@z%>FJXGI2lfi2cs)Bt z5P9-O&A^UyygmeDBbd5DnoA5YI5EEZoE(}ZvMSn?%!aeSor&$3k{2iQKd^Nc?2$8a zP2cd_9ve*(U)QIW*@dL~hX@`fP$2p52UUxh|B~JfX8HoCm0rrP_m6xEZ9WK4$*O|B znPo3kHiTE1$aZhiK~H^SLxnk35Ri`ORmsMM-xVxT!Se&SVH?%@zj@|BRKgB|^D zW_`|uTrat`8wHhDe5%TX^Yl;6bNRw{{c%Xvq;4GR<0jgDiEPSu@>S(A z1|89OTa#*b)YtE-mzU(urzJA)z0)qX@y$lfWmD1hrHzyOy>0!LETjk8HlFV|#_N(G z&-jOIG6g;r%?H90=Jm4R{T*9x!wYQiX~Q6xkK?y?i6dZ(s=AQ^DXV&>V<}U<eldN52XELHp7-6h@lhN;Tnj-0XeS{y`>~uA|B-aDBsl?rc^wcHkvQOgGgVJ`R zvzyE(Ut>MQ~L#vLH4{(MJz({poE^YecdydRYze8Iqg1bMe{FSGl<5;7&F z3qg0*&WM5!{?pm0aseUJoD{BE_vfGVsp$zQ{Gq(6?XQyETRUe37#*Af_XS)dqHawX zWGW2f3{fJ}K;tk4tj;D(*hy)d?!?;#1%muYG(50A7;3%82jU4yQ9JQGe+QsZJmt79 z)&+VSw6T)~!|{VZJ9ZP-Wk#WM)LpIaT2z6JO9LY##y5vE|D=FzWA#$SVm=-GbFISCIFc4g zFmzV_cO#v*_l-b1cV@a45T2=C?*)0w>vN)W>oIMbkhV})pK`yW{3*U)$1QQ$-`#Ywf*iTwD{in)7-9*SQC zqT${d>PbqIteS$LwRN%OW8kLzh(Ol!jjD6=VR?C!8T&gp00d`%rsIpQt^$x* z=|8Y@ zIsJylR8-4USlB$w@%`!O$n%vUUHBpJiH~X6q~D^7&4V)%_X4N_ z@4Evr!R{vj{s(~+SG~#r3K9|$ARYi9R9sd@v=shRx|lurOu3jPI2eW_7idC>FuL3N zTdZ$4k!QIw+1WX6IViISqL=BHU{ZH={W_L5G|bEo9MXxs&pTMBjJ>?zDtqgQfqMqC zNuOW&S6)Y%zFz^lv8^YNVqEOIbMmeWwtb5VgZejFJImbS!cbAuuCF`a#~u9&YJ_=P zSR7mWF-2fwInfyeKLGaID1!IvR4req`V}KeWg|+Z5LMVVDIg@%uRh}J*%>%veyQ*2 zR(NxTj5O{YZfgyKuWx4EL*+ln)C2*cjMu7W!Y|v9Gky3)}-IE?eeEFCS+o4f9r!2 zcFR8H(jH(S^8T94EzWr*?N0ExLo6Pc*$vXypwLNlLZyfdSxZG?TPhaFzQf5r%s%uh zK?lg&=_$al>Iy;ux8j8%InF;hXO$=973brP5nf17Nx(9WH-u57 zhF(3_10jEN5D2|UApd?=c_GmjcP^7(1jcG@2(zqP>eHYZ%^TEwr?G9pTjZfH+B(!pRNusdPr|BD4^^b3dh#9~_7nEY_+te_* z$ZNR@fq7)vB%;mrNo@GhH7(T#P1?wf*HIZb2*&OZ4mrYwkY>6%<3_WU?L*sI7-eg; zrsL!&vf1B|jupM!k=u(7kg=N(#lR(4NFMjvEFPJ#oxhZNyd(u%{QJ7HIE?V$I*^s;#MhH>`hKZ)`tRFF5GX;nYa8y4K-a?|ii#udniY?qy=?{v}cO4fVbGI9V7t=7#D-G=-G~DPa;15j(U3C^79Lmu7x(2u6^LhMee`JRYQs z{V2=g7$P|i(M*~LApwn$mX$vFS@!nfJhosI^EZx-4%(E7mS z&sLy+^D|dnJ9{%5k!5S(=^}^II8zuTx<}HJ_}Q9npGV#!dEdd#U`f5JBsv82Nm&{7 zZ?@&A>|j{+Ky~y+4eAs15NtVgh zt4h~|k)|sZ2>yhnz@9aJ?0a@&SsL;3d`5h7V{IINA(CWmTKOn4eiYJr&d*UFoU-pi zlD9;;6okh8O?Sy2ON9JTcrJY}MCc+RzZC$zY|as{PDRptxB~WmAVC9YqOHZ?GBXa1 zQ;6}C(2nc~G+#1k6Wn3co+qDed)cdHPh&9XRP&g7Dt?hUmDv|d0s;lu%^V!TeuLY~ z%eAr{mrCCnWlh(ee2`i$)$(J~+6Kz0=3u1pXt?vwYcAV$=ZcGZZ;bVtGq3oact7@X z_f$FNcH#bXy64-AIoR8q^{h8I>&62L56&l!*XJyqyu9BqZ_f%I+n@I!zuwo^G&jOKpQ#h( zh!Vnb^ISxF{Gi#1sVDcR+j=|&-f*x#;%Yi6paRvs@4_i6D$={!9pS%Qw%=L}4g!}T z5nCdig|2c6ar{(@VPHx&izERyEJbcqgquv!Rtq2iru9nV;_+KWETAl_`TpCJ4BcopjR<-yG~dL-M`JNrloYT$ogZa}%T33}cvJ98DdlnpRV#3l?8oAB1on z5uI|V;H@uXx-$u!UD*$YNqoR<3ZY)4{HgCDrkZf-zEB?bHK$?h))j$)8M48n? zwr~BVN`>KvT{GL?bCFG6G#E~I%v#zB6pyBeJD#MF&`FAbpPS1qzp&Xye5dlz;s>Mx zQ89dgjZTD4oD@|L;Dge+?fiJ`ch7<1N0bdsL2RkuuMcn_j;}r7KZ}fF@F|BkeEkww z*r@HuCty2m8I-m|i1Qv~!6lT)#9g=C5t7b4NAr6kXBhG(n_*-aq}eU}IHdUJWw+o6 z0?`muG7`ptVAJmXi{8i&_5;N8b)isxRaNZcqZ?2TIhC0o(o@7e-o<4NBLDNdCnD3E z;1D{Lvc7*2>xbWnyYu;T8Vnh}-^p9|)e2Agt%9-1DOF44(52U2Tx2&-_~W;Vs;hHB zr_-ara`~=i=X2>^k?O+TFH9g^I5MxX&%FkIEOPOHx4#_MikP!9Ud_umQMdPAlG=}M26(~q)4)4E9HM5fV5n&R zuF4rj&U3QB9<54mXilhp;JPfXkN^}5o1G#DExn4kJ(+M$ zL>*kxn*Sj}_@Expc13!>PR^RceAAEgYgl#UpXo^qhm)*u};aq_U&iizG ze-4gtqVFb1iIBIO`7G3p5vVq&!DjpqG~;4ugOh(W6ge$%KP z@hi}*;{I`gwc~wCw_yFTO!JJ-Z^g!Yr8{Fp6 z*tz+?-T!~rC6G1ESL@@O@ixswn%Mc=dTj+`p&Dn?2k2KB-bLL9T1$im`Cs3D2u0xw z{;EPq%$ylpK~x`}9uAY;;I~xQb4|Mf+{DDn;K>krJiqLRxmX;$+ zOC)wK^ytT(t1xw#j=c4Y-7Sa6j6-fK-+pNrni&KTM2m6pR73JIg?*g1sZ&9ch0f+xVty^7zb8=|~pPcF@G#hoOr&Eowko5FO@y^f5tFUorLI$9xdz;)ZA8oP@O_pvUhqb@;{c58z zJ4=?-%tp*AOEY`YadP^}Hnu_Kwe2W>ydu&+cy|8xrjdK>*hqCw$LmQJI_pJ^C$$&2ej(#}R<>9}pDb4)m*Y3^Szvz6GH8y>j5iL(M#W(?^ z$0u=mtioyxDq({qAptPl)i$7h0w=vc3&rV;X2UDwsbT(jR)sYVcdKR=+vtE}QAX$}&r9h={k3@)FRus?D5&vf9`3Se($yc2U08 zV7fN85A-^g!u`O+3q8hL7n4PrzH$4otv989!QG2iuOff(xFKD5Lt!lyH z+-N=2x1LXIKC^qei5%i2qc+PTzpy!e>Wrvcs5w=3O#M;A!Oi`PPMWT8Z2#b|PZ))6 zor+-KO=HKusxG(-Yx&gqYeM+jiSkF$k8KJce15tNA>Z0)4%I>SbI>JLY6m&qRbwp=L&pJ2!)w0h>tTyq0a9Zd| z=aXTX8s?VW-sT;o+IX!N8(VYdaY2Q*$C)>SLt4hMy3BdYibSO=SAQuhKC)YKV@Ztc z$p=Y)@W=CCEnU&{-J%jY-1%il-_5aJ(+Ow=8-7lCPT4kFxj6cu#`^kOzV*&67)`_< ztVZ*hg4?@eRYAnW1p>7ts!jvHg{lkJRD!!$UH+d0DuN+X98sUK6To|JZFsO&90yQf-B{L0B5RDMv{ z?BDUQrb-=%yn`ccEIX6k1p?(^n7(6)E0f>DbJlE>agw7!$`k*hgBYO#6%9iDM%L>! zu-l+7E;#OUPp*DqjpE?^@k0+CZ(-rbMWdhzDb#eSc(h*r*cv6&u}3dIGNpJgDF1E1=Gbw>s?Hf(#+0P4xzmr0WZ#? zn(N-yp5MC$GmLD}z+6bB2Ij(eylUXrF?A2~90 zVvlO|^Uj|Q0Y=Sv0m4KJ#jQB_utfH_uIJ&gkjX&9J76I#(`bz>ge|)1=(~DbZ4e@2 z!jE`m9s&>JZSLcFt-$GJCwfV5NBFV|oFBiFTdt#%+c$*fXO_i4jhM5;>rqP<1I`2d z*nko=t?nh6b=Ivmd415Jz0c;j(*T*0NkA^;Ke{04`wp=jj2i68?I(QjrItG$gAe(u zy9Z-$VNr4U!_Si>H7%r65y?shv829jq|i7`eLZ0-C%p%DTQN~WfOvHCmjPK{DM(AY z$Q@_&H3Ri1Xq(*VlflDv4wZ0Rcsx?MR|&300OCkk^$zOChLo84_3BX?*1TPe=j*J@ zZEjSO8+EK{uVaMe*KwNSv3PlC;GUE3_mqux){o2-j&`PoHb$QKl&^wVtFJpV?p@on zQeX!`$gWy`O}1(_N#uXcRr7G0VcmikdQ(sP_zuuE!9pU?Mn z)pJ5cD_78nDH0MY^$s-0I-osT$JPt#;WKhR z<;49?rd9?0DI#4k^@iRb=W=4|{se1ON?nel`tTTU-Bf&(t=CN{T z+F&fz*W`}sBitYu2-)J?Bpa-qS2#XD>(!x!Cmf;doS682iF^KpoAN6F%D+)`8ssX5 zDOP5!r0J5O6YKq$X|X%&0*Z)|N?2x2iqv}4Z66`?W!aG&(qI4`>J%x@y`PwB2(mPd zQXR|q2)M)MUKX`>`f@`i#@Pv#R(fZUqb6)Hh0$mW(7(iMU0bmysbHPsOuA6_EO?r{ zCE;kb8L68glExX{==?Qy$vtN7^;CecM!~+NIVI>tKfUdM;b}6fGJ7~nO{DegLn}-s z(IUxLMZrB2!N;8$*@;@#w=G4&oel)%%7b1cc0H&;_3Pp>J5O!u+djyaD-xK$IunD< ze5u@1o4+be;J5^@@ht4wk3BUP9tY8)oK0ATT(xAz9;_}=zQNj+Rq{UPE>0>;f;z&#V{!HfwOi+t<*ZUr#Pg_QZ-7a_8~ix2SJ7 zx*u4DPAqL19{Q0lucWCxtsz}E+S93j4XJl#wt1fNuKLX^HJ+rP6qQsu4!3Gm8Ka&m z=_DWE3xp7F4}`K_V@yo!c;jnSM5iBr1%DpFdvcfJG~+LcO>_@LMpv1x(JfvVCnW5| z;P8#+ydtvOV7ku%fy+*bCnH1wgAGjwVl)CPA9$$FN|^>4lLNzL#7lJ z$^8O8a2nNllEVqwsX|y8Mj)hXpq|`cu(05mPr4Me#vaCEp{R6P1%|rITt@`1Ltg>l>Jk> z&gLQP$VG7D%k5GFS$(X3MO&8wv3nE+$#04|r;Bc21^fY;#6N)CH{cW47MdLy&r03> zX0o0^TA2}5t!lj;5!BuOJp7aq%fyJ-{wF3LV&@?=#01}%0$o8V)s~#{h0v$wn2EzV zUQRIOIdz0B#25;{GNMKiP6qlS#KVh<%lop>$hnVHR8%Vpg?K-CdvoG(ViZemsc0>s85l3aE2K_O^R~`f(@mIMD_9%x=;O&a#a?*ExRC8I9 zF2Kav9CcD;&-=MFNRq#2nQpr~FX#rmD-}T1X;_Geu8p@F*d2&x3S_lkAbQ5HMv*pK zYaNUtalp}=a8<2O@ZTkrCY(|fS)k-MoGauEg$vq)7PltmSGI{ts5Ae9JCb>DXIMQ zug7PU{0yTA>X-axxKf@UvUYQ9mb*-~-y{w2> z|bdqhZQ z8>Eo^brWCe{L&B*{?4Rvdl))KJvk$LWr<@S9slUs?6zH}5uMMZ+2 z0hhWYO4ZBHBt;&4H&Y766*Bf>6M%*n23|Y7T=&kco%TzKOeU#Jio|8yM5m%YG72IN zBI+K>>Q@W1xNtOvc`Y5SHdy(gb))sXKMR%apmQTUZbp23YkqY+wU*Isls{NSMnQS8 z@italWfa28>Ie;c?)1qzng0FX{wAn;r;mAgQyHiB^?Fxm zj@Lq%cphINK5q)S9PCA(i~O+cF9S~5xUwGXs&2(-R_PL%!`AVBhVz;_Ehs&eKYiGh zmgdJtE{h90`eU^Mb;_OMgpFaQt>U2GIu32_2ZxaSWOk+PdY z)LR(CjgEoA?}>XjC?&vAIxGkHuu9`J9$xamSjxIW{%M*N+ zW(3u~^(Qb8HYGm%IEl0@u8Ct~RWdfi{(QeD6OgVuzBAF|aaiF)6GU|6v+X$j9qy=S zGIZRu&FS53I$q-i*zS4rpNvb~w*e9Z@H0BXfDP>e@*Nz0O7y9+dgiZ;CUL^{Hx{GRTE;cK4j7&u_1oFJ_S2sYeZq=1pe7-$} zZ1)dlyx7j1DLk&*k!&g|^^JCm%iR4gGZlblGx;;HadGOEksW?jOM#Z4T}V{}8PUoj zGD;=3RG_zyj|mjyF%WN_Huf;)L4`Y<>)nkSP3#E0N5lJ!2F7Y)Hco=z`ir0sD{-4 zQl$S!JDA~3^A5c0zeH+55H;?52|J*H|35eQrB6)nP!leN`aOQ!82VEP0KT%^=nOr{DcUxM>5o_vbJ#58v{2IKwCv*<`{is2Y*pCH zVW$kxa_|O#I(*`NCpU2@r&(>q*hE7=@};zqhNK8$wMD-g7s@?g`l}9s-B0U2@u?55ihw4RX`g$N|p<` z@MQC?qrB${3n-8NgOovw;bAB&4av#HwcCdV13vm6VY8?j&ML+oOmpK{)h0;ut2dZ> zmAr&*{i3t^5Q0d4*+Y)K8R2NAAvC@vW$6pDXz=4Dt$H4Nxl#x{>ifXxKEU5V;c3P0 zjENNPFSG|$c$KH*3*EDGl_ifRgtzWWx99>-GVGl_>(qY?l=y%^AzN9WmB~aB zJLJ|+H%vR>>(#Uf5rBvR(taWuhz+hcpo;bol3GnSxa_~gf78PD&P_iMrlIorhrT;{ zA3&8_M0YTXAuco^WCs*MQSKzO$58t!FlH)W4SdAe_-QfWWv(-zp5f$xN zkVw6(HSuU`2;}l5g1N_s>ykJxPiL);Pw6^u#=aQ|wj@~S;uOx==r09%vKv5JsNHrL z?0&_HK|)0ly^_du@e~SHxP$norSkUt%SR9G^wnD?o7QXU$d@ovuLkI`ZZ2h^`$eUc zPs~V1t2unr3NUs~Cl((_O;=Br6|Fm$UWgSerObb42wQmtxU3^a{;MlAy|%km1KC)I zvv9a0JVimYNnQiv2R>XUT9vLieLN{vZFh_EtWW=-<3o{I9L`D&Ky7 zT{IrjupCOqepqAYa>v?4&U=FN{o%g*&gJUF@I$pSEa6gb@h0NAThU+*IvnBF z_|VzqMpWLkbFl3_WAcVZ({9w>>jGMnh9=K~OL}I=&+g__vm#7;kYBASkK72*wa>No8Aq z8a=hhbv!z|_v}B}cGKQ2zF|LI>KjDq106kTxd|DsmGIw%c&!232R=Fj6FO5;c=K6X z+E04b>hE(*fNuy;??)kyh7rd*wG}41)){B-2yu)wtIBe_egPlD5D_;3BWsh}{8ho3 z?U%pS5Fanl>wft$rEGSLT-L+J6es{Y4 zPzX8vcCht4mS*~8zBaJ+_giE|i{{X`Mg%pFsV`l^FfgwJ{YhEgF(uE}8;;83U8{QF zbjl>_H*eYy{W_Z$?T={f05S%hy-`=RYXJXRUqU(F?YV6wEK2R{=?p$6qWDpp>UsAZ zb@sY~$TTCkT~=S>dY(T+*tny^25m_Q?sPF*f}CD+wppCDDs5ckZ&<-UxJJl3e5<`x zoSM;J`!M&z!kOO78(Y5&K{R^3t;LTuO2g~U{E6vx7>xu7kfT6nixDujf|gE9ULJ4W zn*(7;JYuG&r#DV4#d5!eP6-Q>;9`yz$s?A2K`gcIffy)+hg_Pkp+n;EW&;%(8-9iZ zoz^usKIY>W2@HBw(~7|0n^|2=%^>AN)g-%~DY&RQ$DaQ9G-g(z!ir!rntNYDrw87r z-8Fp4!_BtGasd1}p|3?|s60D0xgz|X&lDP=Z&SK4wAqF}r-&4a7dV{Dg?434EUf?o z_tIWr9E&fLiVLt|6c~A%BAh=#uB&CP${K9>Kz7A$EG2HTpiP%ie@9uQ4V*RO!kO})z zsVVe*O$iVy1mJSQVdK2Jr5+v~4GauyR1YzA9}srxrh#Jx=aitC7AxxY_ys1Ow_yXW zcnq!)bffuZ`gjjjiGza-(z^=z^Sd3p40?l;X${h2WQ94A#JXG?w~(c7#vmT&k=``H zIQnbXFTR$2%%ui72f_m-dkNUS1(24@ivA#uNIL}kD)oMryxI(f!+PbtG-0n*2kPdp zrCE(O;N7Ki01ICPD7U4|QY8T0EYRpng$m2!e5zFfm_s|ED#L)-%$CIrRR6A91kUOf z0&-wju2(CD9Ru^$7qpt zvPPHFMID)6U~kZjiQjHs4b>-7cV1EHyjt)`kj85AlgxR|6Yw zgj~1PX>=bJZ?w1ylOt}C7u_%?C$+gxu)ofP^%fYYzBtr7Y>heOA(^TSBQT=-K(_Bm zjs*`Svqm$oDSg%{!jV6iPnTb2;=}GRaE?)R<>|yai`n8xQObmi&D1{uvd_IVhF#lO z^*T#D1Z)P}mC*}Zy&i7~14E`-GpcS_f3&ba;^?a={luXs`g$SdF~{bz>Bs$x*92{j zTcGEh70J~MUE_j3!J^*w6j#_f{Vf$XRQ9`C#XNrD~DGOCw-TSE;_tNgp# zZ?wA4bC|@h{YwoND&RUctP2>R;=d2fZO%h)8~KjGX1s;JT{7ndSnl-Oc&(TP+P!@U z_C^d>yQqer+z58&v<9^6M?*$&EvovV%f${DUzzm&eRM&?$f7|nNvd^q5)jau9i=6wRwn$NiKwBm-HnzQrUZFT2a z1|^2t%ity@^(~k>viO40+|5kwop0i+_TcU*T0xHscPEb0mqnP z?}!-fz#~e)dvSFO8lC41%gxo$=DuX=)p(}*s&Eka1R;UjYQ!G(fTlXuwiN-MN)|27jCoLy)PeIeW5ymT_l&Vymxz$-t#v`sWLN7$%&UF)B z0k*{5494OWx7%Lb{Nx7kxt=VPVl~PXJhM(%=U$c9uPk!L>s?xIA6A@`*W1qWxPO4j zSbC1{b0+&7ezM!uC$Yzx9hUz3lpR>W%UQFV&wE>E^y9`kkqxRc<0$lQw%Vo}+3T*E zbWXsN2E?{fn6&vmm>`*t*l;2_s53J&wRLq-kGKVB;G)qg^ad!h9M~)j$t4)!&8XoN zP~j!|N|0&^f~D66`2_SCYLO}o8Wdq?7~@T&&oS$t@$aUq4ZlO4eENdDf#^JGcTJi$ zcf9AqB0`JzE^W7)hz%3>(_@ixbmZ{;bsre30>-h<SQOKtXL)-rhlOV~PTmOEj4<_g7O(wj(RM=t7{_nf zsWa`K8J>bPNYOiS8Cl|^o9xt-Cx?K7y8%}%(`7T1M(`~D-cY}Osko>pyRk7v!2Nc7 zVPOC;!;^48q_Tx2XUx9yn?Pt{zCG_J_S6f?1@E2)V^k>{f6}FaMmyuLj1DDQf!Jns z4fEGiU>dz1a^1c|v6HI{HvCOo*d#zShV%AQSI~}G#(s6fIe2B?0vSOD(M`c>BjpK& z?Izad@?6L}t-Z|-{%5(f>yPimS7Cz<22M;VczEo`3_G#)Z;5I2;dHeczba&bryBxv z&->=m0%sCe8x5e(mTSvcSuxV9mK!Zp8+TV|C8M#3Kz>9?mJqoyP$ckQC8*56UMYV= z1c$M%fT>^dA37kTU=GB*t+dGq-DS+#jHAPp9UpkK;ZlAm!=P=H`L=w=WYd(+ttGDIrV8a$NU=Ed&U&O%z+sD; zSz7)oD~p_-{wggaQ?(#r3)(wi#S;BWA^3+k_FjVklQ&3|Y~C?$wCUvDkTJ0uqFScf zR(zSeRaxzM9Etty9%=Suu|Frqx1_Onh-t6$XejvvcY+H2eHBx7lKYyc{wvCr6BUKT z!oqs*c%tA7$?5M?p!@(w!TPnQ1l6A&<3hS`J)5;O?K9Cl5val7fspB8)=KMCk@Pr^ zB3rMD@0^=rKL_<>HgNd{W$u!y8S0NCPXBLJmb0WY`vD{7_=1RY12}-25sj&Gg#+}d z^eUzAo+D5Q*p-$G)k=g^#F*q0OlTAv)-m@!aufhTmmQ4fj+--oGB|_b%*kO^elx$kbHL4J3M6`9+em7SI z6V4BlpL%b*VapPUmh?-TDDm#3FrUX)7){>wXlrqK^FQo4eFkERmJy{Ir7ds9*Kglg z9S^6KMXy zA_KCbQN()*S_mkd{!?;hzf{nFr}HQyKfF6+{12|fEh&}~u*zrQfX5d@B zb%3{(GJ7lNwgiLwny0t_^4&LE&!89fPH*-V?CF<{!RIWe2vj_I{OBjW%emr zsgk=7_k_SM|Mxu}ndATK@DQKMJ1n&8pR56<9F2;EVZqLxUanS@t)|4t6p@*c+~%p5 zn%r?fr74SnNe~9YnK|xsFhUkmGZXZ%qTz1f`x_7<-&xewS$L3t5MTdbrVZIvyE8nb zAX3SFwnvC@@T9{)3k;b zI_`0}J1AHf(PU1nEanjNR5e2DFJICdehMx&`|nGXj+~H<6hr7g6X`pE{PZXGkEX!s z%N>}R3W=UVyyJmgR6^9R7gfje=G(t+uN13uI<_<>qh0$y_6h{o^;7ZT@%6HkdG}YU z?rQhZj|z~lZ7TX8`pn(HqFTE^LRaxTd2!4P6_hAM+z;bO7AHL!lTz2fJ`nIr_0BhOD`yTHlTX+4RF zu#Qh&#Y^T1Noip{f4FIuXWHs27!cR>7UF(CSPTv=-)GdDAB6o`xkHWC%|f=^>XqcO zW2=t7t-2}IaKudRx+D=CxXiyQPA~!%4Nky^@DJAYX@FsDjoXa{r}eTFH{ov6Q8~c` zE9P$u@ftsL1UNVpC`guEtWX!n&Fk;}J&JaZ!d;BNOR%bGKuq`K8H@+hPG95pkVK!H zEHt#$`nd;cuB+S1qCfRf_Cc>va8Em_>(>U!J>M1+MR=}%CLVH*#pC(Z-G zO!|tAsxzJN-_G<$Lhw`feQr+L-WbZT8)s@mi=xo8=>)Eq{TKraZ%pm3C)zp_o$ivH z2NaKT04l>pg2RRb%yo^8jRChUPOHTpz?v8!X&KZi_3l^5fqodUi5NXZcsTz>blp7v z9F!7`9!SXu1E@Kp0)>!srG}r{H?0h*Ia95skc_Kz3ENAwh(wW56Si_Dj{)^XL>A3< z#tD(i*%oj=>sN-SS((_b$?Lw1^pBksQV^2$*hQV16&5o^H+sK7B@Um*&1OnFcU#M! zj)Nna8Js-{1Sl6)t!FMZy2e4&@I9<+K5_33P2X@EBvO6N{`@ps>14|2n8C%mfG{4!@twD~Cg~zjGwgg+rD)*>+;b$@ z{P3N{K*jMJZs7?4nn@JDd=b&qBmfeM5B{ASXO?{>XcCnA%VNLUtlut9vtN!*c`CAxZFRmB94B_;Iagi*j+e2s4HvCTR7OfcVk zinQwD4I-J#q!cTaK<6L6$b%;$Qf{bagACRVd{&pGW8SD1$=zG1PilhXQDekN(aD5Y z;gc=WYswFv&g6``i@N2Ck&u^QRUOUn>9!7>w%d+K`Lwg$Q^&r{1gZKfEsALz2@GY6 zM$W{^mjDx z3?!(F5-|_LzzHEe`%fGct5oRTMBdiv7icLvpn-Xfp$!2|ZWnDlf;u(27NKCcKvZ6q zh!glPAs^fiEcu6L*IpUNT9*1U4fVTx2}@7Y8j-S_!-?CYm0i#U7s6>~=N_&$sD6*QptDeZT_X+%RGSm3=<@d@Snf74Xh_REyCzTNW_1ad>W z7`@o+ii&7}GXJ8fIaF&trB-bOS6p07I|%z){N3W^8^Eiraj<1KQ!Kv$c#8a$cX|!U zASk$0O>ZF2r3I$`OTYbFQ(V*~-nNlxtl&NSSY1ZD|LK<3A#b4)Z=nxd{N(^iyj&s< zgBu2ohJ#-$TNpLW=drcFM`v}Yu!pv00!z-PI~jRkPL-o37CUHewM3;$%iyv9tFkly zhjM-6xFrc0dzNF1Ff_%8X>5_L>|5lNWh_Z{F)3S?vBV%tLPI$xgjAC(N47E6!ZZzX zY=g11kQos&#`kv4_xlHYpI`3Zp6B(v?&rR)&wYLF>-}h~Omw+imu3B-pzKM%r%+P; zcgG{`N09R;*xt@8lsbWphq8THL^%m?_)gn?6w8wrz6bUaeG3EmzrR8OEo7!>m@fG! ze?IbZ-z=eoalY7Oid{I=ZbezL#yc?|Hy@5YC1FJ$_4A8sz^uSXf)U!dYkGmQIy7a? zyE7q;?etJ-{3P8K-I61tqWChKc1kLaRu3&RO#4DO25Dzw&KZ~g^9NOR7)z=x|vRQS#?&5G~QIuDG+YxH}yp&sKogAV6mkB7L;?!Cn6pJ}Q zBU5?YKU0K^(=+dbNdGT|_%y&}lT&!pxsovOVRC;gcs{}zK=;Q@&G zguYa#l);bhiz`$kzwfEOTup3;M?i}k(^Gbeo9hXc#w_O5;;RC6dSkESsyJOc*K3y| z7I7S@Xp{6fx{lrew4}Q`3}P$pDu(JusNbn@Dw2Xjk<*1k+gSPB0^7zleIC*J?aT<* zOAbagizod2cz(RJy5{XMu~Uoy;Il&+H_GshO-Sxu2Gw{C@?r1#pq*D4g#RAFJDr}$ zo{{lYI$4voCLjEBnOO&*rXrA^`96)Va3yJQ0vdk+@8nDA3J_kTWsh&fx5tk zVUAWW2{#57ajd0y4^Tv-)j2b1KDFZlrm0i@!p;J*S-Y}VhBxns|J*p(JIVoSou=YQ zq7X7sNH?WA&8LomBJbmb^R zHLzzBv(|2DZ>jc?iWha#qn&}YZMq{O7rY8)2ytiX-n@)Ul{-uFoxoZalA>s9+Zb`V zxI(l{+na0Rb1r*Wt_{isq%ENPs3Xxz`}BbHXazt+9tSi-PGqSq zFipmr!xbMPf;l9@n_o5a5duKPmMinNwsFq6vx-3cAKhwt94|r6;36-R?Y(de$rsY% ztf3(-xrxq1i=7qb=6U8rm)VO^^PxJ{t7#qc#F?Y7m9wk*MdlaCCPBIor^p14lE8Dm z@6+VMq4jyHDX1F;)|AB3Ru}h+Use}y=k6YW@UYn+OhM9;ffWugev^&CK7iTUJRJi5 z)|YCy)HTvc?`zS*VvNeSI?he|ooJ0}>?PF*px!-CJmoB!O;VxySJHe{-Ws;2{#KLGFGs^Lt3^p3 z{cVf0ui0g|Zv;hBgmHaL-dB?e7FNHrDq?nKJUxtMQ5Nr<4~nbsybQC~#aCdW-L+!9 zoxF$4-|%6&c~cSoZ!za_OCL5tH@m5_t$Q~tM&`1+qxCI6-pHuA(7=ksZic9b+jnW+ zUK102_(BEk#6$eWbnsreZjN|~u9&s93pO_VAdkU3+ohW(4Va~N)VW-Hw1j=zk-i#{ ziO#L8ur9^&0Jv`thpp_CO(4ys7Y1F}l+?*oNx*Tx9nA;^6|+C7x)eed)Qb zQ>8fFZ)7l$>Ev8guDmF(gS-0>kjwPwHn%&A2N>S0AX`2sxskahz^#Vx8bH+D#66oNTty3F z*{XLIo^Iw2GD0UWam4k>UNK|w`&XYut2U-=-UXQ_CHEJep zc9YGz*oMjvU+d)#hBW*5(%lu3xkF2g67uz^Ui;yE1|n-T^%taae~J`hrIwg~HuXJU zW>HM-gXOUoOT@xhh-%i#->r{L;_mx!R4Ww>%U#HPnQCy7I=iYmyE6SgdsUb9=67q; ze~26s1|TN=i`MrY$Rpd`zxEYxX`+8gf|HZ@H;3tbaCKFap22__mi`Z88!U~5-$(Q&L+WG4}?=|4# z=>1RI2tm~Ul8a@}U+%^SqFtv)i=?SbS12e@ZObtfU>T5gpu(YW8A0e9%vBq04dKJV zy(cBv#E0e`_Kp*^H(i;@sAa=HXCwkq!|E$>FQQE**Takb~;Vt#yMg6{^{{@q4o0EuhGv zDn3EK4MRNI7`dm^!kGt@H8anxjw+~H%}|z7jPiKBI{oZHf-|>M`xieh_182ohA@H_Kla(_`?bpq S%mjrEToz`wrZ0?9N&f+EhEt3H literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530004950623.png b/README.assets/image-20220530004950623.png new file mode 100644 index 0000000000000000000000000000000000000000..549533f13c34b98b297a413a83f6826d14257b30 GIT binary patch literal 54492 zcmb5Wb8zNCx9=Nc!ijC$ww+8gv29IkTTg6FGO=yjdg6&~`()mI_C9s%RNcDwzf`B| z*IK>$+iQLLiBM9IMEHjD4Fm)PL0U>o83Y6j0|W$g1qSM?Wc9lfBM1l)h_slns(aSi zhKIN6e&^Hmbh^(Z8Neru48lkX2>v5J4+?T{!?SjIsmaQ^dCls5L))Iyy1cnr$G*C8 z>G#jd2boGWv2vJ}8fs*sVE*7>a<35%X|r7J!?%w#*z{l!(0Qx#Ti;HKbZ+N^tV8a@ zi3zuyL$4gt(y}rVm_QrRBU5a9&}az;DTU- zJjBLlwS_!fw$Ks2lEA1Vze>m$dZg?^tV(wCB=(R1iZb;sNqJp3TacpwYC0WX*xwG*duv_yy(8-yssI*_PwuBTz04%FTwjYPgTH4pu|nG8ie$ z)ka{_o30O)zUk*NdOYuiXtWHuuqx)xw)<#!ItI!yD8XGm6@Gy& zM*U4V92eHO87W*rby4Oler6aC`PkFSTWR-*U(K0P5~{J!@N+Hq?I$H;C?5sSKZH?Z z%TDRobyfwlMS+3~)nMAc5~z1~#7NkK2>uh)2CvwZFup`h_P&st`1new^?b; zEerinnV)Le5`ZoACD8FtxZH{YLD`xEc*hI)ld5snVA-b)@mGtL~j*_#9VZbqjuR^Hy$^!97 z{cspy^!J30FdM;(+r1`kC`Zq8m8Y~E4p47^5<$T~L>8j-Mi!Wmp@T&ZQ>9zsx6PCx zODn|{*CUb~^ps%@toNn2Kj#{F;NYCK`ulBhese3zs4Y<(^S4297^-=tJsu~*)Z;dk zfR4%_bfa!?jNw(ILmn@---y_Hpj;yR2HSGS*wDQf(5C-rS(Fg6vJhpyd)bIs{f zzp|Z0HHEHrZ^Y3;?|_%J$C~%bLwEByLi2T}1CuQ78kh%;xu#1}0j*aCYpeE|P_$?v zA!cM2eBsn9@{|;Grdi8p7ii2)3LH1P9i+H6<{ZQJ=+s_gr+KeajrQ`KRR(NSmYMM% zso5W!gTdo)Ek_Hnuff4DM|M{G?qLAFq3d^EM#RjLpwLdrT6#JPFT5ze7f*dd=X%Wd zy#3;c03UH%>t=A=x_N1=z@qY4`RY{_LX+jCj8#0FKA-;=4&4$ zE8Ht11^Lbmru;Vg_66M&%0b$i>-MKFZ)OxXy!W3kRT91{jwulb5ar~6c6<;KH&`^7 z;Yo8uYsoi|iwY-zx3s@pjecX%a*<%=$b@pfQ=va2%a;>g~PQY1b* z-#f}B+$r&sAwN7|yna$i7Ax=FJhVULyzJ=P-GFi;>N6WPwD&ls>b&qLCEpSvNw+jQx{h(U+&>2i=N5%TgPw7m`rRshy88;(Y~(0lYn+f zV63l!E78A7^c48Cu>7>?cf|bmq+q9|B$Z*e_pxZqq*=pTDYklS5~xQg><6M&-FyB} zSVp5&h+e-EtadZEcqpk}Fkiv3BbRaHh%TlsO0~+QR}FtuGr(Ju29HICO}^K^NNOD2 zY`}IrTUtAR_lJP-q6-wPE_E|jfKP$e5D`$Z9o=3zdNXkeN4MF104yQ_S0a=gVipG}g>72imTd00ESD2m zKId93up&)O@S+OT8WB3-ppk^)|s(MR_k0uAY%{~aFw33f$3tI?|OkHBp} z$dCZ6$}G54TdzF~w`Z{wn-WoUaC9)3;m?U%r#m_nZXAsfsWQB07VObO^7XkSci233?U9ac4hAm|^bN^ar#xCfT`h)AO8)N%jxDyGx)P>Fi=)z_kf`+6ZCr@5 zhnmiPj5=0fza{-85Mcw#>h)I`#_Fv}J(dW?&Xlkv?@U=0QhkY;pmuB2IQnN|dzTgq z;_N=zs>7+zCqzy$!3hN$-_R|N&FL^)k~rE6pB!GhiXx{Si_^2-!_Cq1X^8Y+kB1sA zw_rwP!n5>9SKQOp&j!m@dK{<@dS>OT zy`v0-PFhIvVHkkV#gPvtFTe;rec@BL+pN>AOU6#7rSpCLcE*}J(H4rO2zzq8ic{7! z{ReovXP>)I&k9(S0f=i(IUTZ#OYLnfIp0kgl>D`-T{msEsGq9BXHTNfOkHGZ6Lmv- zc2ZoMyfMDfbQ1-RHpTVimQQAg!dj`m##G=6-P=R;(?Pd)*wE@YkTpNPA%gVLo|=`$ ze*blPtJkJS3iDOHd#viQnTd%!!8}K^zsEoBE|SsteQvyE{0&Few)3@g<$cL*VC&O;_ozyYbgxX+n^xLzXJV5@ZwIMttS%RJC zYJC~gRamP{t;iwm+#+)C6*=ByFCLRn-`eL9m%IF0zkL^@?7l3&i&wg&?NhwdorA|B&GsDN>_V( zX?3*!B$5{Ca1lJ0FTd4hW3 zhu@a**-^rZZ*}TYReQ@}S3aRgAJC@^JnGl!(ku`trJ#Tqg~>?ppkr)Idb(5zZg9Ob zxVIOb@(7YxBtEAd&ZaUVmQigw^R+QiU2LmNcQ(7Hyv zs=H%`>?j(YzA21`FDXyS3yuugJEB~|h^`$o5++L^Nvlv#cmdoVs&+p=;-xoJ4-z3P z3XJ5z=CM#HMRGt9J8xjvBj(fJH`bnKD{FQhq?J72k6I>JhFb!3liecx2)O-GEJR`B^e0N)Wi`&90sSDGj@HBn2l zHf?~*F_%3In=)xb=i-`jGPnfqrdH0!6PVN93K%B!*-r;&DYDW#}nE;bUqlqaBMh$ttlFXcR*0f(MVmWlOWb=m6 zZ2dC2@OSr4Cgu#VpGAWfe8Uop+6FgH7m7TxnmfYwu1wFx`d9Y*Ja;b&8Pr&r$$A^hdz?!)!v#{l!lnS`u>x!1|^LYr`z$io~CD+30NYfte^Y(N#(Nt#; zeJ0|~#VsYU`^xF#KA*M*{>)&!m?*~H&hRpMSxF2;aaw|7iS{Tl_3Cf+t&~7R3g*vh z(`5MAOh7nN+p*qxLBfM5en#{QE)e`GQbXn0V;|KPLngs6J0F7nOo zHRBE-|G|>eWMS5*&I-Q*)!h}CCJ~Ec#?GLhz1GkieF%RDA^%+Y-jhJYE#Gm z3e@*Y{Hd=w-Z%(Ho%HVh3gvJQ{4s$TY4-y8seVzi%qujU-)ZCZ3vMD;L}o|2Y!f&! z;{di?%3NII(J4_Xhxn*Pvb5Z#%lPG8`7MN`g(=oUj zLIgXzArVmYD<+2Wg0JpecCR5}X-bw!XB$(4Y}xs4-t=<1f5R01@?X8LuHS#hVfz}3 zWMt1mOM;vBy0;5cPUdBILN-#a$ttJaUWV!Kz1T*9KBnB09ujKm2vW(|8s|d=cqs7w z{e7$$iIdaQm9}5B_xJZnsj0>+*_Di{pzO%!OIYw|MuDNdxV7|Xq&X_k`naL90w;|e za@6x0p3{fY6_vvWGO^mkc-VbWN zQm?OZa$#i$_V`zVfke4zU0SUyLEi_Hun$eCWvOZo%{a*9B4N#Lp;fFxS2E+CmXyFx z%=RxQCZ3f2;=w1QnJ84qnV_mV`bLuHMVl`grl_r2(;V_}!l`+h-q(>xLgpdZ$nR4U zLfC(IKWE;wGoIZ;Ha@~xk5SnxZMR||wAnvE}$pyK|?uEWfkO7aUc^Rq68^V6LF z)jkKevYNnIhr)xEVZV%gg=`G_&*Vk}+e4m0R}yX27{!m+erE@M+{XpwWiJE(9!T~P zN=YK`uBTla2lOy}#7XDnuC0K~ypXco){6yRk;07ds7d0_)^s)QWY|(W9CgByZU2N0 z#;pOhRIZtn7KhG-fdDrohqJK;DLa4O*rFZm2`x|VpRwfEl*mFCr}^aeJnET{!y||C zD@8@8(ux;FjkqSaBfrEF1Alg}DbDE0Js;YeXa-H}%Z+1Li$8*|wJ)X#xIYu8O)76%a0EZ{Q%?To`y;q|336)`JHTi};Ep0)8 zsjSQqP?Vv|ydlo-!Wpv-ygIJQaHcNnh#)6N+=+cu`BbIPd{~+t(?Q`_Ee7)VYx0%5$R(Nqt?>gn;hg*ay<``b|Op$20{ia)l_`4^$IzHZ;|s2eJH za^!9^);0ajq1p0VCR&6AwMK_43zWgn+Gz3>1K#w=_rD;N>!4;7vShgQXw$9XeSHh_ zaY%-80*e8I6X~p=z!pc+)8*=6t45<*jXzaY2O|ljNhvAHnwk-VPAT?3)gs8gBQ&XJ zeIt{ALaLpI0*B|uiHCZCz9fx_vCRTLLXn^^f0yly{qK~Z$c6%b zVkeSfTySM^=)r?{!#yOH!!tKV+VCQ3G*^XxV|-t0$hzP-f_x(u6%i+IT&c<#va4tZ zpy)$^?Om_!g|~)H)iEzdiqOFuqZEUX8v_@y9=2TFIaZ$)Q&}JB9UlR2{R-52Qy`Yj zo_Zc5iDhtA%!|n%^H&mIXhH#Oni^rP>ACBJi*}m#u>8a%8>*Y$N~}56xCY8*P^Sw% z??B3<^^e0X#UBCR9}WM+r2oEjN0-dxv2X>|0x!Z;!B{Y;(+CILV{s2l&-HTXoNwS& zWKYe_nV_J;3qeItmrgid7PWFlQ$iq1I*Bl#nkf!gfViZSmB^bck?}66%Y(M1o=hJtzjl_ zxP-=w92!xdp8g6dxeHQ}b~dQG`4ex&p7*h4Z85Cm5W+_|J>T#J4+~*Fos+gr5DktZ zJEEaU@5MA^#=`Wm+1X{<_krELR_|HdtR&qL%Z5zVBz|p6*t|c}dj?9lH6Td7GkEIz z9H=obM`E~~?1;f;MX*$AAbo5LGFRKnG2-)a#nwcvx?rbXPoh6Hc_yR;{RT7G28Htx8eL z^}$$qNei|{$Bxk`A4P<)7dztdEgAFfY+qZ9->9Vc1|~^A5a;@Ic=)@QBLzKp8cpaq+G-=E0H0*9C9TrGq|g(w9zqN8HU zKcbge(knMCn;Hb!CC2oORqiovU%Ewp+t2w`tR~x8aZHGIO}*-GjM~dl>~c_Pctik` zFOmUs{-`|BkMeDuP7qRrhO^%%E7jNi?0;`Se{(9go_$lFkT)NTpx}Ea(D_ybUtTRY zb4r1n^kecG=&*}p?L#i8_elKE)g5_A_yo7H^@hLIU7S{@1Lr<@G*_QS0$mHAvr$+^ zG#)%dV##j7CYG@)+S%gCQFnsbZCX;5Rlw*6Ak<0s^i58kR!(77(s?cAtqD7HMRVM8 z;y3#px66P8t|yqY>DmUJb=UQZ>-%}q-qDnr-*t~WSrpts*4#KtCEAseRz-oX2D|Ni zkIXS-eARmW*lH1$#>hb{Q6991Hxt{6@G4gqUQd~@7d&#gM23RmMZ6wW9tVeqQyllu z_V|1>yykJfKr%<&L6+QAb+q>6ZOJC(NowW?BCZa@x+AJ|kykP=FWLUR5VR;^Umfj; zM_Mru+dS|bzS|-U1?I8inToNiHoX}s_=gAz!?IDau25}ZNdHztL?yI09&E~OHmyn_ zwGi$sSj>bU;uk5eT?sRMZB>JJX< zDkN6V8?&=0$#jmE?4W?OI4Oj9DUmYJpMB{vJN=geBVKX7aot%mJHHGR8Fmx(l9j;X z4f>Jgh`u|@M|Gzt`WS%5=jKjtxNS|&D+*5b^niRxAyswtoYxTKXOSO$Sylm9@K_3v z=-c@i-^hzicNz>tV>O3h`0riLHAWLF_uq`3@o1t7YBOfS9Mek@*!3oM9hYZUv}AJWI}(P{Mj7To9^MDj*temED(K<;7G-qbe83RTT0;cJDId2I^2aPAAC63 z<$w=8e6L=%B4*9J`-;u;>bUe$l~^N^BfIK=i5S8Y(Cc=V!=E*g1P?BqS-lh<}wc2~S1+9Ilr7qy>zmaXM(LhRYI?Trb-$Z8S z=Y=r6h0bp+ZY@;49KYc8CPKs8kUcqUtYv4C7XzStYngiLbJQP+wj#?>6bZ3{s z0p~F1OHs({5BVIBUiD}8art(5eo105f9z89`}g(pv|kSIWe4Eq=BD1w557=Lo34P9 z+*3s~ft7FJYQ}{f?U>_7py(}i?~(WHabcqd(DuklnacAu)n-#wR_*jJDszOlF6;p1 zfN@O{Q}Yg$+OPJNUk(lu*hdDhC!D3WmjgOHA#$CF=X=s}z+0S{)2-dgm$ZA!%wwCB z<3Ea|D4u{7aDz=C=WB4gDm z1Z1rvsGjo{TyTa#H#R8tAetVUs4j;@mjc z=2kDlmM9dO8ta+u5mi_a2K*`vaWhH<8shG?Pl@+}I{mh@FHCrBP}37_MKUu)QkoF# z<5E9Bui8B=N=pkE(D+0Nq(L>GiBWD5ueJr~VW(7CI@(uSeDUKt9m7HCsW9ih6-f7> z2m)~JE%rLiKL?^{q2or8Yf_ti-%$whAC22P0=c1>vYHUVEzBKe8$4eE7j4!z!HEUW zbo*c4&sE*PeHrtYFc6zC5|cOs0(an9=2WC*>kQ@^W>7bv4n?oqE%jf?v=IPIn5oW| zO_o$JN0xIzWUr3yQh0wN!PhF@X|EWEcI*kQ(^g@ahBGRjtWSn~2D z>{I>^f!&4$YaUC?Fa7K`o15VIL}!&oVbth~3Wxv&*^@CMV)B3;*{1q)C1mkkvLLez zx6Z-O*A2vscVUqTz{u!zyw$4kq8?1Bf6jS@-;22K{fzcmz-)V7@a>HoYQ?b&4~1fm zH)yr0aT}A76P1GOSoHCY(%yEQ;wc4o@6kYpGqW3=V9&wH;@feLSA}$RRVK)Gum@U_ z?!+A#DU=U`soVPC_M}&-?yofHE&1rAD1o*%Ix_TRM@J71j2O_wF^#r6rp)FG(+x&K zlfzQqJ)%0!oT3nPokY+fXJ1SlW(`)V_QEXwYTq8-SJzrfVzHWXK#sJ&kU3icE0+{w z&X8L3<<4Ys-0hndK7~A?KyHZ8gN@BhN-w%wH@1 zRsTeeFxl!qCZ3U?{D)Qc9+8AwUH2W$9?MQ2AE<55*o4F_01{NQ>*GL2w_q&+u4>!z_)Kwxjz+%=~%#L@| zAB*E4R*`c~h2g|fYA%Tlxz>^yDb^<1`sH%^-E%DQGM3a-g!gTFHhms^SGRG>yW~*- zR0b!>9t=cFJ9K?bucn;7FMeuunc?!1;PrSLyNQ^j)%md;rSrCF(oY4Re(G`@qKK#z zg^~-#Mw`#Yem)HoaO*TXd#nfj_p@|rh0Ehh`33nfx9Y?7Ju6@ z!WxWXcC2uru<=;2#WtO1P$ux|DCms^x1o#SC9t&!O`$ja$V_HwO|`p=pnN0vUPJ;L zW9DOzQt)|{Qa8N2%mDL5=$8w8q=Q@@G7ir;sTp#`b}L%G#f{m-3Q@6*0|QPi3OJ83 z$}^^7k9K`nXwWP7%#wt*Hl?jChm3t^h%7Bhgf~uhLhxJE=-txHrbB!s^s0rmbxCC< zrq_xsT~`4K&wwpiI&(c4YIb?{L8W%7opoVlWlR$X`0*`9?a`9V0hcifrzz6K2Qq^` z*nBkualehhRamG*2`RB4^yh^r8$S0$zy*<==y%R7A5>@O9qE~4X5Jm?QN_a7>_@Hz z@2nRFgoCVOo%c!HG}~YE^LAvvsp6!`)49|jMHn))jf-RIp2;f-oF!oAoda7|ae;03 zLJf$vEdUw~m;1$aEpA9koT9HRW(t4!;}gNjx>;Xh@X&^CmimOI2Sgl4loA)#8UBXosZG!`Of?qjMeikjD;chl zo?7SR-zHC2Gv+Ijq9X2X?J$=3WN3^Tnf;}zKCi=F!0|7Mg}S(ee*NQ)2g*MK9_4RFT8 z(M{R{|5}cQb^gT;6$-b=86tkfcicn;e@9jwUU` zR`jx}u%6XlTOrTD4(dZ4SA~(5f|E68z!@JmU!bj>tRdDV5)&g4%tA5~qdkB437h%g ze0^3n(;jEM%N-KE-dUnwM94r>W9mKlTvX@ zpYPP`f-bI74T~Z%lbPZCxMJAnY^spbmqIc+!AV}1l-ktW)n|7L6+nU-MJTCqZWcKFs|C2lWzu`22TT#!?%2IHz1m5Ms7FU0~ zaCppEh%yKqQXE;1HdwbpX7d0EctnOTg3Y@ryvHbOR2Mg1TVMEiD~?7I3PW8@-XzUo z)Zau-Ts%zR_15AngeXGy9{}g=8gAd{NYP%F0F4-g2gWvAPKT(sASZF1EoSKrt7a^5 zng*4a1GG;3BSmBx-+;lkM8`ISMs_~j@f3JQ4qTR)RA3yPcaoNlhi&+!{F4$;pXVGbIoZ@Ydbu^aLFUuoXVg3GtWkp?aHId{7DIVUJfpjbs1`!q@ z>CZV;Q>DH<#Lc}CqasEtzM|WyOm3AeeS+%H`_sSUH%oZo`lNA zAfv|7fNzo*NqDt_Nkab9n}1wlCsQ;SIPxx~lpk%`S*cdO;_)ZNcuB-ezDX!Arwjoh zi)jz}XQHC7BDmUVtnueM#5ZMSsqs;wi!>QMOODZNGXXP+h)Dxd-E{yd1nN|gM3j7Z>c?R?UVl3fUk(Xij!Kgl|yVv`O3a$W#do$VS>seWV9b(mT;6 zzB%c1qOz#A)Err**JSVa)>K~|fiWioi~3Qa-5h&zV&&xIq|xR=tzQ1?jFEt^KPZg> z$t|Gm1h_OcmzVbJL)$TU9b?7ne>l$Ch^lz303m+_T#kP! zGCV|RI7|kUo4wIP&f*Z7xT71GVKST8BNXmMQw-ZBhPXmW&01B%xcE=KY}vTzH6M{-q>e^)01QhX;+C8!H~ zLr3k%dRyW;FVD^Uc9bhh9kV3cqyMuiG7TC7GZt(>8;%qPT~9+{NU@-hw54zR@Y3le zT9i{sGu&8N(Q`(#&0$FTzS)Plz#c;)2sE8{NV9=cEcXl0F4rw^Z`*e4lEopH5~xar zs3C*?^n)I=xx#w$1fBTatkK1{=P<^44|_OD!68@FFKZ7LPAtoz<-H;tZh=4Ec;Rz@ zkQ~axqR-t?bt>+w!HWWRL>`S~9_<+HAQ9P3T_unBc3cn%YeubD4uVJpUm>+z!#}}L z2^{H77d|c-b+~+Aet%`3Q1@=}EFiVdXpj;X-0TuqH$-iMz%>KtvFXEpEf-U8cyD`1!k_qzN8R>dGAvch4{%@Xy!j+P6%v*#WWw6R4v@xIbTpl|Y(;;2YA9;aJ zO=;`C9VWwwitk58ug={E=aXJ58|b>lii!ts`xD(}1b|;!Y(R(NLAri}-W;3l-Npaj z(t})pGnJV!nl#FM*jK0$7MFZx5=;`6-zwAM1W5dp(l~6Mw5vsy23*UqMJNV63G5Nl zCU+{DQ zp2$O%5ceA#SqwJHVbBuSm@-*>gOnCr;u1{a1D&<1@Wbrox1e7C6}z1~SLFW_iDt@R zir{Db8u1%?cy+2{F~qA*|vS}>G6KQoG$1mz|GB#*@UbXp#!D62#4T_A6ESk+{FUe;o zC$apMHrUi;qgsbG+h%6dF*HOxuAVjf?yu;)P|?2Ogh@O!5fC|8g1->L;Cf%er;NjsbJlblC|cl!oh#op1SNyk*spG_QC!9M;1c@=hYA(Z zYD^+I`+ni3&ku1e`w!U9OTW*FF@4?PxhRFJ0aV^2SLh#Hy_*Qo+zwO#++3d^!LAP| z`;I5lDpx8z-DeE1fEkYzxvzcubcPx*NLAJS;rZpoEiEkmmX_r7ox8@p56V!@(d37c zJ|-KuXx(A(%EO8~)ApIeFoDggN8iqh_H^e~T2~pE8N#y4;{BcIQ};!6lV=5BLeGf( z)P`%{WGt>=OC>A8mK>Fn`DX4km{EE52z`_v4(a9xxcqonTaSk|qmNGtod2%);*lct zuPejEZ6XqewHiz~F~R+Y>vo)xP6YZFL7*XJVr^{UuJ%+;d);MXLC~gu;2=CKa)4E+ zLo?_siCeNQoe7@JIjWtYLBim`8O@uttdhdvZ^#k}x-F~Lz^8uRC!#5TwZr^wQlV7d zu+eiv8Pq$nm3xTTpFi$jbFU}Vv0z$`xUz)C_6BuaeSiOR5g)=|QWkA-agmLUEj}x2 zVh~e5dej8xH7aah1%5i6>$ZU@fmPH9EK+5hd%6la25Qt`fJ_=b#+Ntw1X;VnQ|Z$4dIP_XlcQ7|^kfZ!ok9*lxYH=uxo)Tjy%M`fhvCIIhxC+(q= z)QREd$H?C)T+;&6uv}BgAoeK^q8^=M!a})^>~^}`+Qk(VVTFlL*}gJw`I~K0D$6P9 zak+ZCbMhO2@Ke7_8{%PV@y*_Wm2ko9+EbVr6}w9GpHnaR@&Nt2*EL@WO_6-$GUr+R4uzqhJepgaN_{Ofx z_0Gf$3@mZ=d1)T{9}KwFt*L}>OQMt!dlOxeUcSEIA&zDf86m1V9)X)vC9URDp9UaB z5w}z`P0DEi1r^*8?r_q7=8GkvJbkG%Hr>!$6(1c9f9CoMNiS;q&i|zyhV!t}WxvnA ze}C1$HpTg7Q5pY88cvJbh2qB>bI;(}K~Z;LvU|s_(msre?NR^bBx(K@zW*gqXmE98 zu@Sa*PE^2MozN^QE=sgQK)(4p5S~FQKZx`ufB=>>u5*&QiM(VY;F^@SF}N3Qq4^+C zIeZz~5g2_`KSt#csF(GV?8~?YkOKy};F`Mw)?2@Or1>w%NWBn!<2PK8p~(Iie`c+mZ8C71Z?+F%}O&FggQ9IRLs zR>R1m+FTX^zg)>)SgX*d^v1OMq$%YIEf#i-@z0>9!Di7}ruwo^VchIR5ugh|Lmn2` zg%=!_w_gC>+< zp#Wb!YE&e>%>%hb6jc++8%bD-JVH=IMPO?9gM+GN&7oC@T}ctGzAH-WG0W^9 zE8uchprTNKz)8~TCJJPaWq;GYo?mOpC1vO3T7V?p2Qb8a$*`+t5-mETr*~ft8=(L6 zq483MW>Ha5)*}ns5-hSHIJ)guFi0H#EiSl-JwGlpcq%8Rh&2cYN)3t}uai)KU0!W9 z0c|V&CxsU*VuOk^RvpFfguMm>Aqhmp869UVZfg|S1LWSRT~&Mn_!Q-l48DMlK2^LD zj0H)_jUTaub_ZlQM6p?OMox3tWLRLqZ`lj>0z&12;i>K@%Ju2W9H5jz38i5lu^2dI zi1Sb*9Qfxkoljxt9Ip6UMA@UJ&nCq~hWwY6|5nvoE24)aRHCrgtp57r^%4~xscyGnefuvNn!;%U34jyt;PPfz?s3AnoIEXL0Z z-naQhRx0+0ex)w~RxjcbGElQ(<9%PQPcA5!TdCcA^Kx39`^Z9O68}mJ1kFc;$qrVc z3~nP@K*-mN-^ha?5e~%xGadK@zM8|)O(;ZT&uipuOpQ)4DBOW|5r9>C0qLg6xmy9K zgzSzruAto;wLwU3X9kmzU^{(Y?gz=D{_qVo*R{hy%n`F*I9}lOHjnF@DP7T+{e>_TQlhq8m#k25;DzAJ6^% zy5uLUu4?Id9+Q7blb70Noj>^&GfWFN{$&FVdeLb^;fJAU*H%ol z9N|!Yh==N%9x{3i^YE(#2CJp%?HkGx6`d^MP#z&YXHrc5_JB@#*^!0@ryYN>(- zV|V2`S3W+J5w8#nF7yxUBnR!{KLgH*>w0l;nyuDqH3+f94xmL&63!l~z_eso*u%{o zOCRp&$nN<&$&qk!29;L&G!%g7-nl-^*Z6@Cv%Rye_6wo5mv6|8Q0G~Kd^^LeDf}AH z=f9V=+KbtrpUaC3nsqiF36K0usFYJX0};|-hOo$BY&O61Rb(s!Qko{Xdz)XmzE`W|Z1Fv=~b&ax*n_Gm5s4KPgO03A9IdNeG zO;uGFt%>JH+0)#Qc*0K;-+PU~Dl04R?(YrjSE%Ue#j6FwtjQIlOVjdj99K`o-rh%A zW|+BSHl=PR2Dz3Ozguh$>Q&}!46~$vPNFHFBi5zTk&whFJw8z&f+gfLA&AnvH__c- zXflJR-5uTWD0n0%z&LS<`9HZAiWV*!H~5o*ZXrYmH(NvMF#5feBfIn4{ODZXGC{8gAZC<#8Lra++aDFL`3anr?UeMI`9DX}18i z@|&E_x!g;>=Y0~HG~Kg`!SZaszC)V94;AVBR+qb-4}(RAH9tqq(ui^;89qYuC&+!n z2hW@rUBdItS-pdsQ_jB5KTTpixr4WJ`iJ?1q z$zZ_KZrAwVJ#(6g*_}0Zcy~L3GAFOJG$JDdN4-+(o;j8U2d!_G;XC<-6*9YbUHRU? z?yjBHSuuq1qvA3;SRQ0uX_{@p?v?9O~{IKB=eKZjP1z zS;z!~U^E4=r`J>HL3CJ);C;#O3V5k?G%jcKQ1{cr(HOPz+}FZ7zq~NhjV47o-G0C@ zN5Qu>b)dt|-OLtRpd0@FvaZur@H7JyzQ@~a32z8}r8iUig?KMOH_qu&(Qmr{6mjO0 zdGp_GY`b1sm2T%Nl=?NCL|KOXva*vbMs`S}UShnTztZwvgGO3x6CAhVV*AsIjJ8*M zi!pIZPaPdb!D-WDG0epwJ&q-*uwCj53<)rT5UKsJ)wuog_7|aB-dFXFp^EZNSWnlF&Eb7$SFgQnUwAkxTzCL~?=~pGkOZVjn zre40iX_;|NkV$FXU{sqVkj%FoxL&wV$qk$cT_F5O0iA7Bik@iskcfTTme=$7ORJM< z7TnA9VBI~KHCE8_%=S;d+-857og4+~cnZDoP&787wG$nPTCy;#BqOidZqVRURb0f7 zme>#!N=yQ5l#C}Yb*m;C&;}Up>yqhY-EuU9R_8T|rdV$<2l@a;gQ*LTgFr1`sK{Wp zB)&+Oks!>*p*fP~NFBu>EmX)ago@KMx?WzM&e<>Bwj#6B!RXjuMs~vIyKa)G%M&JB zek)C^#VGACmDhpO^>?nO6FP8o&?EyBkZ#nk3PVAk_Km@4c2I&XqlF`7+EnicOL5%2 z0^C2%CjJ$3t6gHq0&hL_Na{WR6QHNcjeI_)gf1kkwp)!BVHanIyK%T@ATMn#l&Tub z@o7i4HlcV+{x5jer-_OlMO}OZ2NQY%b5BTwf(OCg)S~egXhQSHf~%G(o#!PDidvWU ze^`JoPSM38rWDA+*k9x<0j>M(-$y)zROyP-%7TRu^Tv8r7|{8jC1lOHA|Vo?Vx|I% z*aOLifdA?pLVu_Gnsx}`G?tz2zORBnB022;DI)pbulh~JYQCy`#R0~`|94&{>3grp zzoKAj(!l@vF#r{bi4N|?B%-pjs44}|F*ITn3zx54frU$!M*-cx7Pz{@4VVX29~nrp zt(9IjC1Rcm#{K`y9=FeC%#z883hoNC!Oq7w7(LVfv+-MTh$w1|V=uVYOMEnYII5e` zMxl76+5F(pAGid4N;i)dfP(;uPs`l8|L${f+75T%jAra8-#?}!7&hN=ui`v(fV0U+4#Gr+L&mzn%8$-@0R+A0F|kp;Mv6Cg3Ruo zvtaeu%Pe<6FIQ^x)G9MehFS6@#c&YYGoAXlgd)DW)QLiGom+D+hT;aW8w|a1OtY0* zEP*Kp0!WAXnqyHY`gF3NIomo@?k&hINHvx|g37+ctSQNf_doFz{>?=)42Fta%+rs3 zrdg)^h|o|}bT|Yl9yTqwu`2=9X<{Wc)xQIY^kv@?2}YA*CGaKKc_?5o!dB|9(Ldf& zJ&R7j5{c~~RcSH2(%#BRlO!qDrlYQperQ3f)NZyUMbe>03<2kpk^dKE?;KoN__Yhh zww;dCv2C8%=#HIqY}>Y-bc~K|Cmo|>+qUk>Z|?nOYG!WL{qoPQRGoA7e%D^_;`6Mx z#pPxugp(_)DX8_Cl{(ixgCSFDYB17}OI9Q?@a9rSB7H7uKP%Nj%^&6BLEYmVif!A` z`-4jwCgj)h-EhA-gSJE+%vaWy$n#pVbRi8 zP(FlkqVY&km<{Bb3^}AqK?R8xVL*ij!d9yh|P-mGli_NUFjqp)u>+n zCj6vu%Y?CMaCa$YwzZ9 zm;9~aDL-hb$H%B}1%343EpshM9VUV?8Z7`T8j{0u&&K_@eS>Z;bm0%k>mrenii#lND?axu@s3_jSM;+i+W6N#cBBjtm$kH{we5PQ1WDEN;dXa-HzM-A zo#3>vwx(cYjQz{l?KQg#;6YawgI1;^A6O^H5DHf(m#9Fex}Y5hjX>uV2v<9IJ~~HA zkhvY@yQ7>KKA6*uSE%!e6M6*YK-Q?4cLxogeRWzq-&%Orus?OG$@$AQ7ta8-+P1Ws zqF|ALRmkA?#{?O?Q+KxOh8lT2dGu_|ij?=W?;^Ho&VGIBX)$sZa8$bA+2#FqfgH|v z)kvcp4~u}j&He;4g7Off`1vM!CYRp-=Gzgxnh0h7$2)fT-+V&XFCrN@HYehjIQq|9 zF7L&)sqDE*E^p{k+lw6q-;0CGOI_jJ%eFMN+Mr}t#zF*?eluXiP#gn;#Y~wP-q66- zWW5?PWB$9iI3ytfEui7&M zD5#ilr&%92M&Gv|f|qEIfow$vqgo>qdTHWA$CE0S5}9$rx*~%401yQjkuD!7JeL`@ zhNy;lQqvzuSHiAgCC$W##Rb}xFQYy>lw8<)_!kC{@B5p^7V*h!uvc0&6vj&S3u=`k zkQLR5)~7EPmQF06?VNTCbiCp3)AvtEO&y(yffePNRezHnoQ+>Sw9pQj}cwxReXiGu&&=DOii^lugyJ z?Lu3JPY=H~Vg#x_EeaATUsYPhJ8X)+=Jae$lYAvyW$TUfw|~OID!X z45+~j1xJt4VE)=O7B>gwuPiN&G^pbUpZ2Exk+j=13V z_xvWV{YAqE)?)`CW5crsx8$ZQCRMIcuN!CPE2+pz#fMSA-|4MZSHu(+``@}33&0hU z?P##Hz#7R?6W=FyJ8s@6bytwn67>fI`8t2?olTmMUXX-z5<%4rSvMHT$$wkMP1}=V znI3&$N3Qp&5_o{Ggr0MP3q%Fe?J*Qd%$1E$CmWIn`t>(PbYQYkp$!XO1 zv-Nh8cXWiydbm%j9IZ+-s!TTO^aAHr(>S0v^BQzF5yuF$3!U!j*g57mGJ&W;K0L3va57pUSUUzY5&dUbWp!b`}i0sEp24o ztc5CL+HiY2z8z!(d5L(lnTcs!venSD;Sq!6vvYI64JG(URbI>e9Y>>z%R~`aL8Teeb>MLy zG)(Bt^xLp1dK=^YVU=Um4GNa?t?NeXsr~QY?+U57Tw5l2s{?D9x3%~RF^Nn(vw%O^ zfE7nudn+F(6L%Mf@xzZM*>QQFdnak=*t*?Cm%DdSgx|^aSH*b6KZZU7@R-Ss zmAthOUv<4w7m?@d7`bIjyO9?gv}SOlj}Tl~XiXjWHGa99Oc?RKhae>mMQ_@Yq;*a>Ow_y#+_^`C zK#6@~WvTz==Cl6zuI&RI+58#bEKpw3v=}ic5V){NZ*1y9YTA>UN=b)K$1M2QV&wlS@#&PipK8?hcrJrovfcxiz1*XG@Hk4@(uG11?|vh?9YjBE=?%R>x-Rx)AjtK-XQC{VanT8h4%hi z!_-%=ii=RGHqEe(BXw)UMx?Vn90FRHzqKW;TmqX6|DEV}VnuGbST{7eROr8?fT}xX z*_AuTtm~WG-p#JmHtdgJTfWvi<$!+hD>L}-r2!D|U*AG0j`~mJ_?1sE7d<}H&BwAd5Vo4}|C$aiAMwM;WFR2- zM*De)X+HNyXm(X_-SMmU{XrR~Z%?EGMkvOUBYfcr-$zy&5x|27obToI?`VFfJV4-- zXBr2G*SY0CQ9nH@-K5d4npD7MI|?4Cnz%T6a|>=Ms^CeF3x+sUR31BX(<5z@diapv zP+G)LLh#U5m?vM*)PlH%5m{G9(OyX!fIz27EV*}cGM^GR5R$G9rYf4nT}B4Le4M_r zAP0ufL{v1jFFILPJOKLQcs`Km9kh0Sw(g9O+8I_5U?rUmOGV_udAX;lh4P0v^#-z) z>+PKF?3T3XcbwYE9{Qh0h)~!&_S(kkNFhLs&D<&z4_vw+6?D7sD`zWCHZc7n2Cl$N z8it(~w)AfF?)$*Ca(oiZCCVJ}IYoy>hli)}zsQ1c_ z_1HZn^J$MU(Ffo1;`z5MYj%+}1?>jae03^bPQhWS@RF5{KnR=~)?L$Vt%t1p1&$rE zj0@o>Gqv=WQUaG}S$h&x9%Le7tM0yvqe1sM$91X%k?QrMG4kituC{!2< zIBnTowf~K!58{cxH-Pdl_-SF_#K2KXrB>Hhs{vFpY$S{(1xyo;4a{TcLULoo9- zFCV9^rEPwdQk%^5iegy9*Rc)LTR+3*7({(p^C5U6LTR z%{hl1Uh;>Pm1neo(f!9T9|4+e)Dr-8V#R`WC3UnZ{FMML--N@HseRUuaz z^UP>EmKPGN*e8)m5>!4N{;Bu+iQ1ZCK1em#1`&Bd%=I$uNKlnKl~2IGd>-od9xwXa zH$T!gFx%&BHv4t8__JYvLBR{^42s$;Y=`=%sb@?*`XkoL^zqWJ2WW=NZ zI2(^Xo8rJGX#NGWw{@>haxl>B6=^khu zaajc!ip`7s$9J+bw~E{dUumPQD+c2qq^?TbF+of%$aRi-RJ~}dD_H6O*fWo%7$_JO zBDrTnJX-=?bJqqca~X^Hmc?r9d0$;SMmZv=GfgC?P(rn!xR01w1zmKrc^7Ldy8L%x zi&T>}^UkR=H`l`p=IqZq2&~Y%jPQEK8nQq<0!1tZsZ(Gs0~Y zy5K|$WT#`q;h7iu%(1e$6d9C_BX4om`=D6%tBpCy8Em-{*%I-& ze}i_z(0r{HP=b0HGIbUKg3XgWCp_;2jT&~ZW5;`GTuRr>l%@%spAubO6|%lcSQeCw z{ru3&_hXJu7GonLe~mnPQF>$e`R+B5zHjP{-3f740muHWW{I2JHG@&EPy!oju&BK| z9at4?VjWosu=b#VtZT&e{8(Z`tV_(rN%dT}-%nm%ERNxotO)g=H0eWC4jc`B(xe}# zdw{Ze{N77fglEXy!c<-_!=(vI8*kEvc!Ip@zx^lkqzOu1k}BeP;kvLbg40j%^u?^IM7#% zSg%M+#y8$B@7kD=n8TLm)j#&;&ur2%)+6WER^I3g9+$+eznO4XaY;*~SFf$)AD``spcTumXjt*xpA38m+0BORjS^|7U+0VG~j?dPJxRPAd z=1_TVKWwt^1JxSw$a5Y81B!=`+MdCzJYD(5uxj!OZL;&D1E!$J0;dzq6wizoMU2Yv)FlAV4ySyjMPEGctn3DV2P*s%h2Ul+ye4nw2nb8;4wo@E}jGD1Q8Cn-arKW_(%45eF)osC;+wE+bL$=f89Pc9h ziRHr>sTzvg2Q151rA2pEM;~~%bNNW2t~QPB>E=o(`P>yu0EML!TfLQk&wq9thJy6l zh)riu9OS*TWlhv69@SSYfxu;!wU_?y^s+?iCbnyE5Y`Ae|7Or4Y;~d5^3#nqUkz%= zo6!C}UH6MJQ4able^me}EL%T)!%3a__fk_O5#-K>S%G6uLc*u?oD4t$VNaBLs=Q4v z>dIR`LaSq0PIpqf&%zk8j~k({ljk)cJ&8egkdvq@_q1;N==Sku&oR@@LQr2m02BG< zj-4mVA?~hAm&ea)5`zJ4#-b!Kv8>+^s>Vo)DIr;FDzp>TEB6kd0u1d~QGlDYc&Pd$ zEl=8>)Jj%0I}Dj1zBX1)%uFb=ISy_eYp>Uv?T(^`wa!oLhVC~xfQik;wW>Y<%o3ho zlH+z;fblYB{NScR^(L{+Vxu)!gGe{@bcfjfHkNJ;lTY?NG}PVR`V4#_N6auFIf+@) zX&3jJg$u--EiNObe>%u(#~u<#zlJJk7^HPMS#|S6i|7X^2`*r)_ZTE3M$C1Q%YGV= z_sZ|mp(btgG8i=8Z+1PbFH{jf4FD0wa1YzKAQ*?I(?oYVI)^l7{Gbthn<{DvFzC|( zmS9}2+c&#}_hT9QTF-237`y!c{?8PD+{V~#7;8KfS#i~o-J(oiAf65kA|$qce@1Uw z;I)0cTzV)70yw~doE)}CW}4VEk25!koPKEPf`S_ut49Mx=2cvt7lO;`0*0GpuR}yt zjv1e*7V%_{S@`<>X5bvaQzL6+x(#&_%ELXaIwrIXi9vx^BY(GPslxEQOo`;%klX#1 z53ler@w=!vj?&ff%AD-d)}Hn9lF{Hgi!B1Ij64>h_IOY}1PW86Ox$?CJGQVe=e#j+ zJlAA+sXO&0gi^pNP+1B&1y1_!KSv>fq23VGa%pm4+$7A6YHf%Yye#ivwHU|Bd6CsI ze6;Dg12GC%nE8%e=Q3fC#km>9U3QLO+l1g$*S?JtY|UEA?0!wWIvJ9`JWtL&62&&# za>{iYQ{-@q&0r8S=(i11W5D|Pc#aj)j~W42o~{MrI82}+YHvUv`bf05Jj@aQ`d%d4 zoCyHw;Fm1(J+#m9u#Hf>6Jxs1mP%N9G$M%G<%bpH)yV0DhS z$yj}5*2+9OirM-*LFy|{33oDK?zGZ0vSZitGJi*sMeaO1rY){ZouB>z z0tQeJ)zMvg)|IC6A0L_cPHjvz_EgSrwz*JANw6h>G+JI*`a2rAdCvBuKiZRbPUtS4 z46VGHiv5dA!Vf?NXVY~Hfbzrm(oc?`wPD10WwIF5hKc%RH>1^w*CgP{ ztU6&w)VZP8RiIY=HI-xG7I%TtMm@k83EN3bmh9#rTJp>kjtnLiHs~@Hj#4rl{zX|k zBl{$ zQA1e?$;~Xy+fonw4#b;pfxx0nrvjtF!i@tZK{vI<3{E8%%bBK}hf{bNmxHNd;(k7x zOe`ciR(mwLB$$L0_zDD?3fhdOTrDlTlMpQYxEz6xBlIcqOHGlwX9I|osVueFmEbn>{459_0#H{_iDY_Rv=G*!mrR;@dk#D*;r`?_~>{ z+ufhfJTwGYbWuR$UxqeAz13kbRnB&;JbY24hW%l`hN2ZDI>orAX5Y1u?e(VMGo__} z!a~J&`LZoi?>;lP8x~+D%Sf)KM%9WW|5T~cd0(2XP{=()$kJ;)juUZhM87knWiA)z zM1rxw=^p3+l1nA@t)Lg9eO4GuQ6vaVSVF>()%F*=c@j##kYD^ZjD#ebX(v<_L^%QJ znd9z_n4&6XgGa+pM2YWUDXM5uKkx7$xiNYUiTcn%)hxySC{3R>n2#e>LQMk+~JT?S}R@lb9T)MZ0A-u<1MG*lo0c6oGb4Y2k z+Pp;eBMSPEdTwl>ujvjb)yx`J{qE1i9pteo{_t2ZmT$fd8pa?ERbDPp($01L+dSXs z&K@Ls$d9Cvpx*xB*vxo7qh?92R;qK?907+8N}0}V2@3EN97+ohx8%HfI*(nmrsxM{ z`VpK^>}X2Vs7p$sc5bQWfHl6O&#rFfKarhq)ZhJ7IR)$#hOS(rc)V?F9{)Vh5B4f! zIU!plV*h1D-CE_)Sxi%K0i+ZtXt(D>*`eUE0wHB)hq+O|o*7uGKV+85jiNO9&J#^2 zHxgYg7M5Gbi%0Og#aYboG2YOCtW9qAXodpo8-@JmrVs34ID~8y97Fr#CDZs6*<+IN zeK!T9*)nPMiw}=fD^|jwu_iD`feNoi`Jbf>&EOwjHI4sgxAXs7=J-Eqo3h%q~o(8{zRB!jX&8m=DZ{1M|?n!^p1&p}n`?+J~g^qDx%h3?yJ- ziERZB9nX=dygbiQ*MBGpF@YNIt7Du?OsXl%-0I63-@A?i%hJXW8WB`3{Vg=Ulb$-% zH~crV=os3xd_!C#L;{wSrSL4C@NA4Fx!=_8;4UH>_kQb7wx6sI%oR~DcF4~-It1Rb zyhkhQ%g2MTl5|MdH;@O9jimLf_7)-FI$6SIvgP!k34 z3RJ}@_m0g5{)k#i_54~WM0~|@aEJMR0ukAK%0#It6(*QEl@YG)_TDfh1?=ytd?ePVIyD5H4%doWx|O-&&J}vt3=|ed?J|GWesFmvwKG0p_AkV zRSNJRKOH{b%Uh>I2IC7?b;m*T+Y$>-&kKj@_v^VeR${d19`km=b-;TBwEN8k{0{+s zOuzpMC+EI*Jab$;sek8oX0*HH%rQ3mgt<`BRe}9$^GVq}l>65#`W3`eZ*|OQt$_&8Gztt#_l&3nG`w_M#jrsLNPT%nMBK>5GWv>jt#&A&*RC> zqeYT1iMCD*nFLb`S55=|%_16*-w$xWWV)DBMcQ(tN=$M@blvPuIJPrvy%kbmJ?Gur zul4oCTt82>)6&D&_+N7YYFWibEWe>>4xC8Z6!gXWy$|@a36Z)dQ|v`EbQ2;8zjJg* z>7IxP&qHBra1olBH%I1>-JiWbTl3u)N@}X@=Lx~0-bmn_u_Q9h_t`BC!|3WGx+X2Ggf&8<0lXM{DMp{~W@)?I`7>tdF48Svg1QMy~rl_P8&&JbmfY4BkL0*NV ziaQTO&4R-1u9vKoEKJVMB_-pMko{v`+YvF+e+DU8aY`WO2hvSRDAKgcKHr)=2rHBd ztYfO)Xk8`wEEWGN3W+ZQt zfq(qX+3I?6Ao^1bMLV+#bQ6$?NOtVAExuHiO>BcXs^gWB{3Mfv%lAc4JhlgaSeMgp3SLacard&~x)>=4p0 zNgyM=_OH}Eqpt}x{oEg$8WoF1b(9HP$oUc&dyejPXCzEcL5QoW%9m-QveEcOCcK`n z*mnNA#%|on;AT>ososT|&YK>gDJIKF7f@h8j?YjOLCh=uFpZmsDs^vA)gPT>m%Y8m%7(vO=)0_JrQya`?^lhfgp9fw=7R zJ=1SsHktUQrOl}q|KvmZd1B6O3vEjyQzoI1fqY>30x*xFZr>gjFgwN9zIhgIiy#iKlg|8+Ha|0x{pXUV z*fSwyMwM;fyek>wsIS29?RZneiw20wP9*ijIXN!o_4%x3;CYp}3O2?Nx<}fwT<@1` z`!zdNxA{6~?IXp}-0s>;l6_VTW z(wxk{GbcJEl{HY+o~f{k*bVzXW%aHw&5UfqfRm!aYm`6y>?3`-ADppWH97Z|L$X< zkNwf3BFHwg?hv)|-svYY!rCJlD>znLhpBx#f~V_tBKdZAK=kj;9{OGm=|HD5fpO#A z!_QJHlKt0r18!>Zl(iTu}#&A=_?qG7--TR&y z9ffc=$Z0O|=(KY0phD2| zMFmjC?zLK*9qgpqkbn}Vmy4%i^1 zAo}1X{djMLOk6TyUQA|9l#0vO!CS0r3R2$svWkwd(Qu#yjP%N~p?U5o39+=|Ud(I` zW3_bH9^7#+W>`kFQ-G21{Q^7;jcv`rgQfd20)TtG^M$9n&7K<`9V0Ix*_HEVEToF> zKDqI2@;CU+51&UuIz7HXhs1#L7nm2VrH9p5ceCt3W6?M}{WP*{j&W}y)0im1X4Xc} z6;2gk2+%bf^K19p>5X-nI>DzDrhmE7SS)Z5GF-~L0zkl8t%!5M)<~^ zZy!j_n|;K_Xt*&e_c|%T!{}tlX&LV0lMU>t`;xtTGq|*4JKRV7AkRR+0Z{<5WMaA| zK2rWDXLw~So;#ykRhzZf#_daSD31$xfRgiT7AxiP`^|1l3AZLSbtoq^ybeb%KXCfEtin61`pnafazXOpzWL`nKG+IB)#!s2R*C9eZL zvFjsXW}|T@4hP(BWC7w?0CEwaAhepSdM_VYeLuWX=(SvIpq2KQo?zUy)kF+rABV!v z;}er3nEgpF+|9@;GAL3Xw~4)S^xmGo>$Y&^t{xt$c%+mNo>&@~+XclhZypf)I-!b7 zQOf$gUag+_Tu8o|`Z8iqWSqfaGWHWnmU>$A^55EgE18x8j!I$E%mYmrk#lj>UnFU2 z)?`wphxA_mk+Xa(-xe9;t>t!IyEyW?OS|@S_cvW#^rN0z_P-Ti7Lhz6#2VcR3N^m) zwysb;hyZBpJ}{edz1eu^N2sD1I^Y?rcA-y+NcJ)kXDQx7@w!4;{J7?V#*6sT>ITJO zjc2iJ@w@5`O$InLD4#+|KQFkd3QHPZMM`5B65f?HI=jT;@x{UF3wGFd7z+%hI&>K= z|5cI@Ak}+4-#8*;3N^@(jgQ9V#UR2Pfep2sgy4m*+B&T+yY?@QG3K3&3D|rbQN6uh zax$-aA#w-P7(v0ajz%)7Jl-<@a-o0K)Ov z#*UInhb=0-V-IuqCyPE^zSlcsEpZ7HM<*Pocf7xlJh*y1Uu4Ti-8{w4*9LM9KVlqB zaL~bGjX&W!jN&BH;k<+P>9PvELSh&rpx%u+A+_V)Ad^|d%x&QIZnmeV>IsgulMTM@ zL2JYzn!kdHk%NbaQ#Kd~&TeBrPnC$0PyOs!w5{yJCGZEu?Hm;g81%#9g}Qb6Rb91v z+~3YjUYwA*DS8>xZTEOu|8z*KJAp0jY<`c2fX8@2#JO=rsq5AlT$R}PchsKw%R*5B zEtLL3xf*bqqE81^EHaR2hK(_VJeFjHZWQgy=QDlSsvU1gRboY=_x6D8{+ijngIuQG z!jru=3S~Q_?R3eQ&Rsx3mL@fEuFp2We*_q0bL61?_z*|JPMJGMH=j0#IJ~3KezC=W zz9=d)rUVPz#gmd7PS+f`>y>q=7hYxlSW{qiLoe<4(6#xviPo-I@9Eq$H#+Xu1LBy? zl$xd|2p9Q#_&KXg2C#(_mE?cc1((lyw7rl%{j%8^TmGD!p4&8A2zV_7=jn&n^m(jW zbDR=4#z!ze-0UYL_Kq&meFHLLEQBgDzBL4``rL}!{N#>Q6*6jM{mg-WKC+Cx-m&!= zWOU}BYl5rxyc57mF)>nLOZ>T)$8s+Cyl81~6uw%Tw(f6M=i)zga<&H)nlGXhf3xLx z!9|I75g@#0@`EPMetr@-`>S_}0AqJpdBE9sU{ix~DFkcsgtQh#$-sFNbmdVdLoK_gz>Eu+ zLloUmhEtX`55+q+7Z~5(m?N07J!(EeUlw4j~sQO94e=R z+bVE31GnZ6M97!4by8&WMdEe=$FhdWt%!VREjHbNY4=>xFm4}-3<$eGmyVjdrDp10#_eeX4;j_ZL(u`O6KgePM zodR0p@^ooMS#Pm7RAUneRao-xDI^7i&_-AUDnNR9;p%^AdM-{6GSkO%0-cNhIjQUr zp!#2c=3kuuZzRJ1QHuWmk8Bosr}kH$*SEDojKfg_lY-}=%@{}r@L1k;eL)etV!q&_ zN%@2$=f2-&+hIvRj#SsnDS337|3y(6;Dto!<;j(c%&wwFn*9eLP6b?Cg!sz_IZF*8 zJ6aSZ+<7>Vqz8amo)f#;dLIdF7lQR(DftgcPeu9*$$fGu42w9Z&YrBOW^q&vmgERu=iNDXdH7E2S`g&Q6$ znloE_N0724u?7hC1TVh%DXuXLJd_F+CJ_F?ddv)lLQZhBd-RWo2b{z!t+vQiiOUm; z+jKgDgz8IR>_CB;v*A^$(_VJmBIPTF?f*?Rs@0r4#(5d9h*QP}68I1i%J~?Wf`noH zc0xy(P*x?CvX}(WyS%RjRY~{?{qK z!MV?S%Jyh1V_(GP&qu+lqCu7oYu@LDPk`5@t6t%(1%(n}!S0r4$J5``8vZAI^^_7t zri-Fj?i_Z|h*U+~BT7eD43Kg(@;&$1RNrSD%gu_zQijBV-!iR-gTBTl;fVx+L3k(m zmrIs>&QpaQ{A{wZJKt9d1x)E}Io z?4Lnh;orSG&!!nnTvAX&pXWJtV;^Ty5WSof@OU6kJPTq&`D|SHUqGBO7w!60Y_DhV zW3SF0-}qkY8#~&Y2{~<69=rao~KpxIqXl`Sn%BFce=cr z$VElx4&t(n3H@Jqj%J?A?s=IXy&z=g!^fxAWOe!^?pWZkMq^Ng!!rE^RXYiobE9Ll z-z-O^8UBputF!oJ#&zddpVCs(W)AmJ%#F~{Qkp42-adE(re*|Icvp{kSNcO=50q-D zLwD-v>JI1*>ll5qhr8Q@&@!3->3mtptUqEJBM`vhwg4F!qsNPNHVzInq|m94(O={) zxMgUFkhM0^iR+}&PQ*#ItMX3aVmlA9DEOt!{{Z;wIwUV0>DqC&;U6gHb0bqzhNdN% z@)&u!y8#^Czm zx$5I|r#$ljkXX(r0wvs<$pS99*aaAzY%ch0ZQUo0x1O&8?Gyqk9p&`OinN{{F-KYIa^NjXx1qSRAw-1MW_tj&Amg%Pg;lsk zS59Ich9dI_gvv&shWkYg5K`mj-YmtEVlkACgNa3gSojr(c85a&%Y0e-Ro?vyW&d~N zx=JlF1_1SSKB;;zj$S%Wm2ng@9(r`GopHiRO+r56*8M28DZLoa@hNUzm7^0C8PqNv zgEoI`@TU`@OcYuWU&|ZX&p^})3XvYJND5fre53A6QSjg;bTdcG_`tJ*k{?g^Pf&q= zvN4_U2JB&i-vX8VrA;qyFtTDLJqxp;Dg{m4}rr58aFM za-hEAg*t`-AQz)XF*X((O!zfex)Aok4V3(C+7l<=|DItNe{Do9(Jn2|CvZ_bWFyVw z;u}znQk)ht; zRU7!7(UAVQ;kGip)?&5M>o$^XJ?%&cEDbC=;S_SauJL+~OVd3F7gL6*a{Ugy3n!8O zBPi#8L6~C-RBs$_rRW_Lbvoi#IzeA_{JsjeFZ`Q7uBmPBJ?*@sT(yB-3V6aPW+Ycc z!Pd1~%U*&^X?Z!%p^TirrX9?%8X@J;$2S%mE#tMv!d)iH_BB<7jh$pVW#gZVYmEW7$Bb_8;Ecy+ZhC}zCf}XBK#0$=wpP$Z`XPFYO0USaiXzlSJWZ)r7Q20CR_Gsk(%Uj(*gfx z&K`3%iCNLeNTMJDnP(24-J;kZ$HzNeCHg#09Vht@jR>Bn8awW)6dcWRz}t+TF5l1= zC(O)-9Gk9+*Z!}i^rY@7B7sivkY0P)H@up91j=euk}6;|GwRK4~Cgzb-2%! zJ)e}MA3JX2e^N07q3no?1&G6y%#Ggc|7Em2kTdbamC<%7R}LH;sg9i)`Z*8^jkew! z93h<(fICkY)ZXUQ)F4b=5kR_V7~$Z>RpK`XHaYrN^9~idtt(c-DbLTH_CSf39iGZ> zA>4E2*Ttt7d;XhrxpemB>&9CmHmh%~$fCp2f^}d39!<(bA8;Nmqf#~HBk~h$pchVu(aHi%_dl5v8_i8#z+1+!piyw z@2mhr5`;o5pj-=JHIe9rDU2F%PmRcV&12-SXoSj$v2iZ^L6A3!qXqobA`~p}9wb2k z{AU%-udi8<^?v>T-?*~c7H8rLwvG7=(^O{H@+ zyqV8``I?7@NR|$~0Bz3I$Ufh**dX(|`6$Q2JmpdEP6l|_mVba6K)u_rB@UsjK2jFM z99J_I3?3YmecBjfC=ykNv+8>f2ZSe1>o`pv&acami0o82<0oz z_>9LiD`vp2vtqJYIv~dP0-1Ufa1V5qKOAd4XlJatkPr3>*CD0|ww_Bo(mWQuiq$aV z-g^mtz>o}F!op%%6z`BEp^~9e-ievxlxrU4{g|P*8SmmR?EzJUgG8WTF2FG7U^5eF zI}zos6Kv5pkO)I=m}zMyysS%4@?nz16oI++1gdI=g*tKuJuNC}Qc9^XH9(cji7gY` zbCS<0eQw5DK+(Pj*l?gpS>iyqE}jW8MT&C32sCFBVt^S<6YMQ*DrBrTl$Oua9n-n%xdjPI3&O$PCAqd6p> ztK4_G>^H}p_4%poIYmBONLQcRR4)?&V=jTXST*2lU>6Ax2Qs42Ef=dH_4mh;laiAW zJ-yCX8rj&{mDJUT#*%3nTZku4#3HqXWkQ0IGDBd~!XpOsoej-b$=OvA)^V)WJOjb%VcThIlm8`jnhGIA^ zh{ri)PEM!v1iy8^N!cL^0SXBS-OYhQa@`zc>yGV6kJL>1A#t7X^A{h<(ZbT}I8s5$ z>JdficzkI1&zc~X^twGHfx6#W$KcB?Ilh5ZpN`n{@gCCg`oP_^LjZi(=jZ22&DsEe zf6y;NR+tzmFq8XNr6p-&!vH)wZ2sTBuFsfxefB<_PPpE%8vA_d;E3D`^C+6Yj!Fm0 zsoa2mB+bZC+ANWEHsYN8CImhkbl1w%Y9iVYTR3>)v_7F#19@V%cwJ6k_I{WHQX$AY1c{TZqio(Xh<>Kqm#oC zErqMTIlcVHu0*S?2QQLJ)fU&i1+ePj+8s zaUsx*r7e+bMggB2Il8vyXBBW1n_*+jbs-)c9QMfzj?X?YA2wWSi9j`Cn(bxEJBJw7 zy3x0RoU^229!2+SA^u~;=>MV1)1Jr2FNrP!!z?US)8hB`=5=#>JNzk$ z9C|yX76n6eT&`)ZZa2^5`oXYavpF#LSrXr@v=udnWjT<~V}1#k$_H9uS#31BSvlN8 zDBBqIDga?p`p-t3e~<}Yvh~_q-{kAYXwvZ}`j4S1T=F>tA=T#6QCYuVuhg0@)V@`B zI#n-^$nd&M|8f>`=WmQGPUNhQvuek0uLuaH^_Ha{=`m_f)Deh2)d))8YuE;Ck33ZI!MGXET`KOPev_ z>pb;k&w{@7?%#0rPtPv4TRGet}BEp7^s%%NKN~Q!0 zje&}fx_)9?ih*j8d%r4x#~VD$*e9(;=XAf-nPB<9{4XrP#$24g5y5&({O4;w2y)jA z<_QHbR`}1dXjVGhS?THN`JT1{Q(Hofokfnn)0X@i^~?9S89vF3p!a0>7X|m_?dAY$ z8um=Pez0wbJ8~8tW`4dLi|bm03hLBrt-7#4ugNS7sA-Al+h#&UMCAK;+FkR0T;HwM zKFS&8qUlD!(kKv4AI$_E6SII@HpNsFBY#g$Ri>MvsPw92F;l-|K%wpB!6;RK<=giA_@vGL zH2UlEk-D!HWwVtZ2HHVD}Fg!7(?OT^zzB%>X);q*V%vFlB;vG%Vv(^7p zWeiSUcgp7L`{xX58f>IGBeS|KXXR#3rBf?CR&J^^(xlwkN19^L^sX%SVt( z;U{%@MIjSjq3fpUKbxw7`1IaRH4D7YFLNIeuWyg3rmk+-yo!s1qd!+H2c#jNoSY1y zG9)C2Jb@gFh)DNrk*@ZyBnt0|43mufP(WK$9|H;Zz{fvDGi`rK`T&>w2cA(+_wCouiW@5b=p(1d0k`P2ghU~ z;4x*?DGc=`&{t`kd6!Lxrub7lSPMrFb*MEp{o&NKB=ege1T)oIXz9UXE1-Oq>oEVdqdp`~+lT9)uZ(L&8RnN%OZ1sErwS zk+^;>$X-G^;ZUY~!ht$(2y^c1=MGuY6_4PLMn6dSlOHu(Bp(;c>u0B(eI-CENlO2l zc8|vL*Du3~40Z$rgs+)`zbq|>uYVd}2bXd9P%D3|S*9n65;)fYqW9cqM1PYjgG9s- z@sAx$WOCc@KmY+mxQ9=02^x+AI2tj^klTeq^i(j5~R-cC;0 z`{NJ0YZ{6X&EA~QTDxZ&bI+Q>I9hWOIZI|#^_2k>uG+DTv*78xPtSjNxV?+ViVaSckn4)PwQ#{s>H327>~+TWzM6t*r^vZG%!nRAQw@CPBXl@u-iBM1s|Z z5Dn@fUk~)v)%q|sM&p#to_`J*gr|?pTeJo5PVCFIOautKjOE7CKd>fgyn;{n> zvSQ@e2^c6k9-|v0s?#a|d18`;#~78WNwTj#H8vg*qR4S1Ley#A9-RbDC2aS}=OA3) z>C=ddUNjoEY1DV~GR8J3aD~vDPWlCJfv}Kl8pPr`0QYT`{;y+p^oCEZoT4lDX4Zt{>@+IAh>jH=0WsG|{W~KaE#-5~VwLH(k|OM? zlGh{9DqPJU!x1$m46MuG;1A*7lTC(1#?-^U-Q`KTE19HE(=}ss3d^WVQZ_~=A`*mh z%GK+SBu6B&zQAW%q0J0gcM7Vw=_ zz&;a&!e?=-`&3GjKfD35&}i9D`LmzmXr?muO;8<}hZw%^1BS0hwQ+^W+uT} zpK_rm5;qvMk?EAI%GDn!hLLMq0mf3!@E~W81nMpft$#-OxcpP=tE_@LiI}K3ASIv6 zj(}~dfn~5BmpFQvoM1q%Y#4WV`YB*;tk)-U?SRM4w!(c34@z%>FJXGI2lfi2cs)Bt z5P9-O&A^UyygmeDBbd5DnoA5YI5EEZoE(}ZvMSn?%!aeSor&$3k{2iQKd^Nc?2$8a zP2cd_9ve*(U)QIW*@dL~hX@`fP$2p52UUxh|B~JfX8HoCm0rrP_m6xEZ9WK4$*O|B znPo3kHiTE1$aZhiK~H^SLxnk35Ri`ORmsMM-xVxT!Se&SVH?%@zj@|BRKgB|^D zW_`|uTrat`8wHhDe5%TX^Yl;6bNRw{{c%Xvq;4GR<0jgDiEPSu@>S(A z1|89OTa#*b)YtE-mzU(urzJA)z0)qX@y$lfWmD1hrHzyOy>0!LETjk8HlFV|#_N(G z&-jOIG6g;r%?H90=Jm4R{T*9x!wYQiX~Q6xkK?y?i6dZ(s=AQ^DXV&>V<}U<eldN52XELHp7-6h@lhN;Tnj-0XeS{y`>~uA|B-aDBsl?rc^wcHkvQOgGgVJ`R zvzyE(Ut>MQ~L#vLH4{(MJz({poE^YecdydRYze8Iqg1bMe{FSGl<5;7&F z3qg0*&WM5!{?pm0aseUJoD{BE_vfGVsp$zQ{Gq(6?XQyETRUe37#*Af_XS)dqHawX zWGW2f3{fJ}K;tk4tj;D(*hy)d?!?;#1%muYG(50A7;3%82jU4yQ9JQGe+QsZJmt79 z)&+VSw6T)~!|{VZJ9ZP-Wk#WM)LpIaT2z6JO9LY##y5vE|D=FzWA#$SVm=-GbFISCIFc4g zFmzV_cO#v*_l-b1cV@a45T2=C?*)0w>vN)W>oIMbkhV})pK`yW{3*U)$1QQ$-`#Ywf*iTwD{in)7-9*SQC zqT${d>PbqIteS$LwRN%OW8kLzh(Ol!jjD6=VR?C!8T&gp00d`%rsIpQt^$x* z=|8Y@ zIsJylR8-4USlB$w@%`!O$n%vUUHBpJiH~X6q~D^7&4V)%_X4N_ z@4Evr!R{vj{s(~+SG~#r3K9|$ARYi9R9sd@v=shRx|lurOu3jPI2eW_7idC>FuL3N zTdZ$4k!QIw+1WX6IViISqL=BHU{ZH={W_L5G|bEo9MXxs&pTMBjJ>?zDtqgQfqMqC zNuOW&S6)Y%zFz^lv8^YNVqEOIbMmeWwtb5VgZejFJImbS!cbAuuCF`a#~u9&YJ_=P zSR7mWF-2fwInfyeKLGaID1!IvR4req`V}KeWg|+Z5LMVVDIg@%uRh}J*%>%veyQ*2 zR(NxTj5O{YZfgyKuWx4EL*+ln)C2*cjMu7W!Y|v9Gky3)}-IE?eeEFCS+o4f9r!2 zcFR8H(jH(S^8T94EzWr*?N0ExLo6Pc*$vXypwLNlLZyfdSxZG?TPhaFzQf5r%s%uh zK?lg&=_$al>Iy;ux8j8%InF;hXO$=973brP5nf17Nx(9WH-u57 zhF(3_10jEN5D2|UApd?=c_GmjcP^7(1jcG@2(zqP>eHYZ%^TEwr?G9pTjZfH+B(!pRNusdPr|BD4^^b3dh#9~_7nEY_+te_* z$ZNR@fq7)vB%;mrNo@GhH7(T#P1?wf*HIZb2*&OZ4mrYwkY>6%<3_WU?L*sI7-eg; zrsL!&vf1B|jupM!k=u(7kg=N(#lR(4NFMjvEFPJ#oxhZNyd(u%{QJ7HIE?V$I*^s;#MhH>`hKZ)`tRFF5GX;nYa8y4K-a?|ii#udniY?qy=?{v}cO4fVbGI9V7t=7#D-G=-G~DPa;15j(U3C^79Lmu7x(2u6^LhMee`JRYQs z{V2=g7$P|i(M*~LApwn$mX$vFS@!nfJhosI^EZx-4%(E7mS z&sLy+^D|dnJ9{%5k!5S(=^}^II8zuTx<}HJ_}Q9npGV#!dEdd#U`f5JBsv82Nm&{7 zZ?@&A>|j{+Ky~y+4eAs15NtVgh zt4h~|k)|sZ2>yhnz@9aJ?0a@&SsL;3d`5h7V{IINA(CWmTKOn4eiYJr&d*UFoU-pi zlD9;;6okh8O?Sy2ON9JTcrJY}MCc+RzZC$zY|as{PDRptxB~WmAVC9YqOHZ?GBXa1 zQ;6}C(2nc~G+#1k6Wn3co+qDed)cdHPh&9XRP&g7Dt?hUmDv|d0s;lu%^V!TeuLY~ z%eAr{mrCCnWlh(ee2`i$)$(J~+6Kz0=3u1pXt?vwYcAV$=ZcGZZ;bVtGq3oact7@X z_f$FNcH#bXy64-AIoR8q^{h8I>&62L56&l!*XJyqyu9BqZ_f%I+n@I!zuwo^G&jOKpQ#h( zh!Vnb^ISxF{Gi#1sVDcR+j=|&-f*x#;%Yi6paRvs@4_i6D$={!9pS%Qw%=L}4g!}T z5nCdig|2c6ar{(@VPHx&izERyEJbcqgquv!Rtq2iru9nV;_+KWETAl_`TpCJ4BcopjR<-yG~dL-M`JNrloYT$ogZa}%T33}cvJ98DdlnpRV#3l?8oAB1on z5uI|V;H@uXx-$u!UD*$YNqoR<3ZY)4{HgCDrkZf-zEB?bHK$?h))j$)8M48n? zwr~BVN`>KvT{GL?bCFG6G#E~I%v#zB6pyBeJD#MF&`FAbpPS1qzp&Xye5dlz;s>Mx zQ89dgjZTD4oD@|L;Dge+?fiJ`ch7<1N0bdsL2RkuuMcn_j;}r7KZ}fF@F|BkeEkww z*r@HuCty2m8I-m|i1Qv~!6lT)#9g=C5t7b4NAr6kXBhG(n_*-aq}eU}IHdUJWw+o6 z0?`muG7`ptVAJmXi{8i&_5;N8b)isxRaNZcqZ?2TIhC0o(o@7e-o<4NBLDNdCnD3E z;1D{Lvc7*2>xbWnyYu;T8Vnh}-^p9|)e2Agt%9-1DOF44(52U2Tx2&-_~W;Vs;hHB zr_-ara`~=i=X2>^k?O+TFH9g^I5MxX&%FkIEOPOHx4#_MikP!9Ud_umQMdPAlG=}M26(~q)4)4E9HM5fV5n&R zuF4rj&U3QB9<54mXilhp;JPfXkN^}5o1G#DExn4kJ(+M$ zL>*kxn*Sj}_@Expc13!>PR^RceAAEgYgl#UpXo^qhm)*u};aq_U&iizG ze-4gtqVFb1iIBIO`7G3p5vVq&!DjpqG~;4ugOh(W6ge$%KP z@hi}*;{I`gwc~wCw_yFTO!JJ-Z^g!Yr8{Fp6 z*tz+?-T!~rC6G1ESL@@O@ixswn%Mc=dTj+`p&Dn?2k2KB-bLL9T1$im`Cs3D2u0xw z{;EPq%$ylpK~x`}9uAY;;I~xQb4|Mf+{DDn;K>krJiqLRxmX;$+ zOC)wK^ytT(t1xw#j=c4Y-7Sa6j6-fK-+pNrni&KTM2m6pR73JIg?*g1sZ&9ch0f+xVty^7zb8=|~pPcF@G#hoOr&Eowko5FO@y^f5tFUorLI$9xdz;)ZA8oP@O_pvUhqb@;{c58z zJ4=?-%tp*AOEY`YadP^}Hnu_Kwe2W>ydu&+cy|8xrjdK>*hqCw$LmQJI_pJ^C$$&2ej(#}R<>9}pDb4)m*Y3^Szvz6GH8y>j5iL(M#W(?^ z$0u=mtioyxDq({qAptPl)i$7h0w=vc3&rV;X2UDwsbT(jR)sYVcdKR=+vtE}QAX$}&r9h={k3@)FRus?D5&vf9`3Se($yc2U08 zV7fN85A-^g!u`O+3q8hL7n4PrzH$4otv989!QG2iuOff(xFKD5Lt!lyH z+-N=2x1LXIKC^qei5%i2qc+PTzpy!e>Wrvcs5w=3O#M;A!Oi`PPMWT8Z2#b|PZ))6 zor+-KO=HKusxG(-Yx&gqYeM+jiSkF$k8KJce15tNA>Z0)4%I>SbI>JLY6m&qRbwp=L&pJ2!)w0h>tTyq0a9Zd| z=aXTX8s?VW-sT;o+IX!N8(VYdaY2Q*$C)>SLt4hMy3BdYibSO=SAQuhKC)YKV@Ztc z$p=Y)@W=CCEnU&{-J%jY-1%il-_5aJ(+Ow=8-7lCPT4kFxj6cu#`^kOzV*&67)`_< ztVZ*hg4?@eRYAnW1p>7ts!jvHg{lkJRD!!$UH+d0DuN+X98sUK6To|JZFsO&90yQf-B{L0B5RDMv{ z?BDUQrb-=%yn`ccEIX6k1p?(^n7(6)E0f>DbJlE>agw7!$`k*hgBYO#6%9iDM%L>! zu-l+7E;#OUPp*DqjpE?^@k0+CZ(-rbMWdhzDb#eSc(h*r*cv6&u}3dIGNpJgDF1E1=Gbw>s?Hf(#+0P4xzmr0WZ#? zn(N-yp5MC$GmLD}z+6bB2Ij(eylUXrF?A2~90 zVvlO|^Uj|Q0Y=Sv0m4KJ#jQB_utfH_uIJ&gkjX&9J76I#(`bz>ge|)1=(~DbZ4e@2 z!jE`m9s&>JZSLcFt-$GJCwfV5NBFV|oFBiFTdt#%+c$*fXO_i4jhM5;>rqP<1I`2d z*nko=t?nh6b=Ivmd415Jz0c;j(*T*0NkA^;Ke{04`wp=jj2i68?I(QjrItG$gAe(u zy9Z-$VNr4U!_Si>H7%r65y?shv829jq|i7`eLZ0-C%p%DTQN~WfOvHCmjPK{DM(AY z$Q@_&H3Ri1Xq(*VlflDv4wZ0Rcsx?MR|&300OCkk^$zOChLo84_3BX?*1TPe=j*J@ zZEjSO8+EK{uVaMe*KwNSv3PlC;GUE3_mqux){o2-j&`PoHb$QKl&^wVtFJpV?p@on zQeX!`$gWy`O}1(_N#uXcRr7G0VcmikdQ(sP_zuuE!9pU?Mn z)pJ5cD_78nDH0MY^$s-0I-osT$JPt#;WKhR z<;49?rd9?0DI#4k^@iRb=W=4|{se1ON?nel`tTTU-Bf&(t=CN{T z+F&fz*W`}sBitYu2-)J?Bpa-qS2#XD>(!x!Cmf;doS682iF^KpoAN6F%D+)`8ssX5 zDOP5!r0J5O6YKq$X|X%&0*Z)|N?2x2iqv}4Z66`?W!aG&(qI4`>J%x@y`PwB2(mPd zQXR|q2)M)MUKX`>`f@`i#@Pv#R(fZUqb6)Hh0$mW(7(iMU0bmysbHPsOuA6_EO?r{ zCE;kb8L68glExX{==?Qy$vtN7^;CecM!~+NIVI>tKfUdM;b}6fGJ7~nO{DegLn}-s z(IUxLMZrB2!N;8$*@;@#w=G4&oel)%%7b1cc0H&;_3Pp>J5O!u+djyaD-xK$IunD< ze5u@1o4+be;J5^@@ht4wk3BUP9tY8)oK0ATT(xAz9;_}=zQNj+Rq{UPE>0>;f;z&#V{!HfwOi+t<*ZUr#Pg_QZ-7a_8~ix2SJ7 zx*u4DPAqL19{Q0lucWCxtsz}E+S93j4XJl#wt1fNuKLX^HJ+rP6qQsu4!3Gm8Ka&m z=_DWE3xp7F4}`K_V@yo!c;jnSM5iBr1%DpFdvcfJG~+LcO>_@LMpv1x(JfvVCnW5| z;P8#+ydtvOV7ku%fy+*bCnH1wgAGjwVl)CPA9$$FN|^>4lLNzL#7lJ z$^8O8a2nNllEVqwsX|y8Mj)hXpq|`cu(05mPr4Me#vaCEp{R6P1%|rITt@`1Ltg>l>Jk> z&gLQP$VG7D%k5GFS$(X3MO&8wv3nE+$#04|r;Bc21^fY;#6N)CH{cW47MdLy&r03> zX0o0^TA2}5t!lj;5!BuOJp7aq%fyJ-{wF3LV&@?=#01}%0$o8V)s~#{h0v$wn2EzV zUQRIOIdz0B#25;{GNMKiP6qlS#KVh<%lop>$hnVHR8%Vpg?K-CdvoG(ViZemsc0>s85l3aE2K_O^R~`f(@mIMD_9%x=;O&a#a?*ExRC8I9 zF2Kav9CcD;&-=MFNRq#2nQpr~FX#rmD-}T1X;_Geu8p@F*d2&x3S_lkAbQ5HMv*pK zYaNUtalp}=a8<2O@ZTkrCY(|fS)k-MoGauEg$vq)7PltmSGI{ts5Ae9JCb>DXIMQ zug7PU{0yTA>X-axxKf@UvUYQ9mb*-~-y{w2> z|bdqhZQ z8>Eo^brWCe{L&B*{?4Rvdl))KJvk$LWr<@S9slUs?6zH}5uMMZ+2 z0hhWYO4ZBHBt;&4H&Y766*Bf>6M%*n23|Y7T=&kco%TzKOeU#Jio|8yM5m%YG72IN zBI+K>>Q@W1xNtOvc`Y5SHdy(gb))sXKMR%apmQTUZbp23YkqY+wU*Isls{NSMnQS8 z@italWfa28>Ie;c?)1qzng0FX{wAn;r;mAgQyHiB^?Fxm zj@Lq%cphINK5q)S9PCA(i~O+cF9S~5xUwGXs&2(-R_PL%!`AVBhVz;_Ehs&eKYiGh zmgdJtE{h90`eU^Mb;_OMgpFaQt>U2GIu32_2ZxaSWOk+PdY z)LR(CjgEoA?}>XjC?&vAIxGkHuu9`J9$xamSjxIW{%M*N+ zW(3u~^(Qb8HYGm%IEl0@u8Ct~RWdfi{(QeD6OgVuzBAF|aaiF)6GU|6v+X$j9qy=S zGIZRu&FS53I$q-i*zS4rpNvb~w*e9Z@H0BXfDP>e@*Nz0O7y9+dgiZ;CUL^{Hx{GRTE;cK4j7&u_1oFJ_S2sYeZq=1pe7-$} zZ1)dlyx7j1DLk&*k!&g|^^JCm%iR4gGZlblGx;;HadGOEksW?jOM#Z4T}V{}8PUoj zGD;=3RG_zyj|mjyF%WN_Huf;)L4`Y<>)nkSP3#E0N5lJ!2F7Y)Hco=z`ir0sD{-4 zQl$S!JDA~3^A5c0zeH+55H;?52|J*H|35eQrB6)nP!leN`aOQ!82VEP0KT%^=nOr{DcUxM>5o_vbJ#58v{2IKwCv*<`{is2Y*pCH zVW$kxa_|O#I(*`NCpU2@r&(>q*hE7=@};zqhNK8$wMD-g7s@?g`l}9s-B0U2@u?55ihw4RX`g$N|p<` z@MQC?qrB${3n-8NgOovw;bAB&4av#HwcCdV13vm6VY8?j&ML+oOmpK{)h0;ut2dZ> zmAr&*{i3t^5Q0d4*+Y)K8R2NAAvC@vW$6pDXz=4Dt$H4Nxl#x{>ifXxKEU5V;c3P0 zjENNPFSG|$c$KH*3*EDGl_ifRgtzWWx99>-GVGl_>(qY?l=y%^AzN9WmB~aB zJLJ|+H%vR>>(#Uf5rBvR(taWuhz+hcpo;bol3GnSxa_~gf78PD&P_iMrlIorhrT;{ zA3&8_M0YTXAuco^WCs*MQSKzO$58t!FlH)W4SdAe_-QfWWv(-zp5f$xN zkVw6(HSuU`2;}l5g1N_s>ykJxPiL);Pw6^u#=aQ|wj@~S;uOx==r09%vKv5JsNHrL z?0&_HK|)0ly^_du@e~SHxP$norSkUt%SR9G^wnD?o7QXU$d@ovuLkI`ZZ2h^`$eUc zPs~V1t2unr3NUs~Cl((_O;=Br6|Fm$UWgSerObb42wQmtxU3^a{;MlAy|%km1KC)I zvv9a0JVimYNnQiv2R>XUT9vLieLN{vZFh_EtWW=-<3o{I9L`D&Ky7 zT{IrjupCOqepqAYa>v?4&U=FN{o%g*&gJUF@I$pSEa6gb@h0NAThU+*IvnBF z_|VzqMpWLkbFl3_WAcVZ({9w>>jGMnh9=K~OL}I=&+g__vm#7;kYBASkK72*wa>No8Aq z8a=hhbv!z|_v}B}cGKQ2zF|LI>KjDq106kTxd|DsmGIw%c&!232R=Fj6FO5;c=K6X z+E04b>hE(*fNuy;??)kyh7rd*wG}41)){B-2yu)wtIBe_egPlD5D_;3BWsh}{8ho3 z?U%pS5Fanl>wft$rEGSLT-L+J6es{Y4 zPzX8vcCht4mS*~8zBaJ+_giE|i{{X`Mg%pFsV`l^FfgwJ{YhEgF(uE}8;;83U8{QF zbjl>_H*eYy{W_Z$?T={f05S%hy-`=RYXJXRUqU(F?YV6wEK2R{=?p$6qWDpp>UsAZ zb@sY~$TTCkT~=S>dY(T+*tny^25m_Q?sPF*f}CD+wppCDDs5ckZ&<-UxJJl3e5<`x zoSM;J`!M&z!kOO78(Y5&K{R^3t;LTuO2g~U{E6vx7>xu7kfT6nixDujf|gE9ULJ4W zn*(7;JYuG&r#DV4#d5!eP6-Q>;9`yz$s?A2K`gcIffy)+hg_Pkp+n;EW&;%(8-9iZ zoz^usKIY>W2@HBw(~7|0n^|2=%^>AN)g-%~DY&RQ$DaQ9G-g(z!ir!rntNYDrw87r z-8Fp4!_BtGasd1}p|3?|s60D0xgz|X&lDP=Z&SK4wAqF}r-&4a7dV{Dg?434EUf?o z_tIWr9E&fLiVLt|6c~A%BAh=#uB&CP${K9>Kz7A$EG2HTpiP%ie@9uQ4V*RO!kO})z zsVVe*O$iVy1mJSQVdK2Jr5+v~4GauyR1YzA9}srxrh#Jx=aitC7AxxY_ys1Ow_yXW zcnq!)bffuZ`gjjjiGza-(z^=z^Sd3p40?l;X${h2WQ94A#JXG?w~(c7#vmT&k=``H zIQnbXFTR$2%%ui72f_m-dkNUS1(24@ivA#uNIL}kD)oMryxI(f!+PbtG-0n*2kPdp zrCE(O;N7Ki01ICPD7U4|QY8T0EYRpng$m2!e5zFfm_s|ED#L)-%$CIrRR6A91kUOf z0&-wju2(CD9Ru^$7qpt zvPPHFMID)6U~kZjiQjHs4b>-7cV1EHyjt)`kj85AlgxR|6Yw zgj~1PX>=bJZ?w1ylOt}C7u_%?C$+gxu)ofP^%fYYzBtr7Y>heOA(^TSBQT=-K(_Bm zjs*`Svqm$oDSg%{!jV6iPnTb2;=}GRaE?)R<>|yai`n8xQObmi&D1{uvd_IVhF#lO z^*T#D1Z)P}mC*}Zy&i7~14E`-GpcS_f3&ba;^?a={luXs`g$SdF~{bz>Bs$x*92{j zTcGEh70J~MUE_j3!J^*w6j#_f{Vf$XRQ9`C#XNrD~DGOCw-TSE;_tNgp# zZ?wA4bC|@h{YwoND&RUctP2>R;=d2fZO%h)8~KjGX1s;JT{7ndSnl-Oc&(TP+P!@U z_C^d>yQqer+z58&v<9^6M?*$&EvovV%f${DUzzm&eRM&?$f7|nNvd^q5)jau9i=6wRwn$NiKwBm-HnzQrUZFT2a z1|^2t%ity@^(~k>viO40+|5kwop0i+_TcU*T0xHscPEb0mqnP z?}!-fz#~e)dvSFO8lC41%gxo$=DuX=)p(}*s&Eka1R;UjYQ!G(fTlXuwiN-MN)|27jCoLy)PeIeW5ymT_l&Vymxz$-t#v`sWLN7$%&UF)B z0k*{5494OWx7%Lb{Nx7kxt=VPVl~PXJhM(%=U$c9uPk!L>s?xIA6A@`*W1qWxPO4j zSbC1{b0+&7ezM!uC$Yzx9hUz3lpR>W%UQFV&wE>E^y9`kkqxRc<0$lQw%Vo}+3T*E zbWXsN2E?{fn6&vmm>`*t*l;2_s53J&wRLq-kGKVB;G)qg^ad!h9M~)j$t4)!&8XoN zP~j!|N|0&^f~D66`2_SCYLO}o8Wdq?7~@T&&oS$t@$aUq4ZlO4eENdDf#^JGcTJi$ zcf9AqB0`JzE^W7)hz%3>(_@ixbmZ{;bsre30>-h<SQOKtXL)-rhlOV~PTmOEj4<_g7O(wj(RM=t7{_nf zsWa`K8J>bPNYOiS8Cl|^o9xt-Cx?K7y8%}%(`7T1M(`~D-cY}Osko>pyRk7v!2Nc7 zVPOC;!;^48q_Tx2XUx9yn?Pt{zCG_J_S6f?1@E2)V^k>{f6}FaMmyuLj1DDQf!Jns z4fEGiU>dz1a^1c|v6HI{HvCOo*d#zShV%AQSI~}G#(s6fIe2B?0vSOD(M`c>BjpK& z?Izad@?6L}t-Z|-{%5(f>yPimS7Cz<22M;VczEo`3_G#)Z;5I2;dHeczba&bryBxv z&->=m0%sCe8x5e(mTSvcSuxV9mK!Zp8+TV|C8M#3Kz>9?mJqoyP$ckQC8*56UMYV= z1c$M%fT>^dA37kTU=GB*t+dGq-DS+#jHAPp9UpkK;ZlAm!=P=H`L=w=WYd(+ttGDIrV8a$NU=Ed&U&O%z+sD; zSz7)oD~p_-{wggaQ?(#r3)(wi#S;BWA^3+k_FjVklQ&3|Y~C?$wCUvDkTJ0uqFScf zR(zSeRaxzM9Etty9%=Suu|Frqx1_Onh-t6$XejvvcY+H2eHBx7lKYyc{wvCr6BUKT z!oqs*c%tA7$?5M?p!@(w!TPnQ1l6A&<3hS`J)5;O?K9Cl5val7fspB8)=KMCk@Pr^ zB3rMD@0^=rKL_<>HgNd{W$u!y8S0NCPXBLJmb0WY`vD{7_=1RY12}-25sj&Gg#+}d z^eUzAo+D5Q*p-$G)k=g^#F*q0OlTAv)-m@!aufhTmmQ4fj+--oGB|_b%*kO^elx$kbHL4J3M6`9+em7SI z6V4BlpL%b*VapPUmh?-TDDm#3FrUX)7){>wXlrqK^FQo4eFkERmJy{Ir7ds9*Kglg z9S^6KMXy zA_KCbQN()*S_mkd{!?;hzf{nFr}HQyKfF6+{12|fEh&}~u*zrQfX5d@B zb%3{(GJ7lNwgiLwny0t_^4&LE&!89fPH*-V?CF<{!RIWe2vj_I{OBjW%emr zsgk=7_k_SM|Mxu}ndATK@DQKMJ1n&8pR56<9F2;EVZqLxUanS@t)|4t6p@*c+~%p5 zn%r?fr74SnNe~9YnK|xsFhUkmGZXZ%qTz1f`x_7<-&xewS$L3t5MTdbrVZIvyE8nb zAX3SFwnvC@@T9{)3k;b zI_`0}J1AHf(PU1nEanjNR5e2DFJICdehMx&`|nGXj+~H<6hr7g6X`pE{PZXGkEX!s z%N>}R3W=UVyyJmgR6^9R7gfje=G(t+uN13uI<_<>qh0$y_6h{o^;7ZT@%6HkdG}YU z?rQhZj|z~lZ7TX8`pn(HqFTE^LRaxTd2!4P6_hAM+z;bO7AHL!lTz2fJ`nIr_0BhOD`yTHlTX+4RF zu#Qh&#Y^T1Noip{f4FIuXWHs27!cR>7UF(CSPTv=-)GdDAB6o`xkHWC%|f=^>XqcO zW2=t7t-2}IaKudRx+D=CxXiyQPA~!%4Nky^@DJAYX@FsDjoXa{r}eTFH{ov6Q8~c` zE9P$u@ftsL1UNVpC`guEtWX!n&Fk;}J&JaZ!d;BNOR%bGKuq`K8H@+hPG95pkVK!H zEHt#$`nd;cuB+S1qCfRf_Cc>va8Em_>(>U!J>M1+MR=}%CLVH*#pC(Z-G zO!|tAsxzJN-_G<$Lhw`feQr+L-WbZT8)s@mi=xo8=>)Eq{TKraZ%pm3C)zp_o$ivH z2NaKT04l>pg2RRb%yo^8jRChUPOHTpz?v8!X&KZi_3l^5fqodUi5NXZcsTz>blp7v z9F!7`9!SXu1E@Kp0)>!srG}r{H?0h*Ia95skc_Kz3ENAwh(wW56Si_Dj{)^XL>A3< z#tD(i*%oj=>sN-SS((_b$?Lw1^pBksQV^2$*hQV16&5o^H+sK7B@Um*&1OnFcU#M! zj)Nna8Js-{1Sl6)t!FMZy2e4&@I9<+K5_33P2X@EBvO6N{`@ps>14|2n8C%mfG{4!@twD~Cg~zjGwgg+rD)*>+;b$@ z{P3N{K*jMJZs7?4nn@JDd=b&qBmfeM5B{ASXO?{>XcCnA%VNLUtlut9vtN!*c`CAxZFRmB94B_;Iagi*j+e2s4HvCTR7OfcVk zinQwD4I-J#q!cTaK<6L6$b%;$Qf{bagACRVd{&pGW8SD1$=zG1PilhXQDekN(aD5Y z;gc=WYswFv&g6``i@N2Ck&u^QRUOUn>9!7>w%d+K`Lwg$Q^&r{1gZKfEsALz2@GY6 zM$W{^mjDx z3?!(F5-|_LzzHEe`%fGct5oRTMBdiv7icLvpn-Xfp$!2|ZWnDlf;u(27NKCcKvZ6q zh!glPAs^fiEcu6L*IpUNT9*1U4fVTx2}@7Y8j-S_!-?CYm0i#U7s6>~=N_&$sD6*QptDeZT_X+%RGSm3=<@d@Snf74Xh_REyCzTNW_1ad>W z7`@o+ii&7}GXJ8fIaF&trB-bOS6p07I|%z){N3W^8^Eiraj<1KQ!Kv$c#8a$cX|!U zASk$0O>ZF2r3I$`OTYbFQ(V*~-nNlxtl&NSSY1ZD|LK<3A#b4)Z=nxd{N(^iyj&s< zgBu2ohJ#-$TNpLW=drcFM`v}Yu!pv00!z-PI~jRkPL-o37CUHewM3;$%iyv9tFkly zhjM-6xFrc0dzNF1Ff_%8X>5_L>|5lNWh_Z{F)3S?vBV%tLPI$xgjAC(N47E6!ZZzX zY=g11kQos&#`kv4_xlHYpI`3Zp6B(v?&rR)&wYLF>-}h~Omw+imu3B-pzKM%r%+P; zcgG{`N09R;*xt@8lsbWphq8THL^%m?_)gn?6w8wrz6bUaeG3EmzrR8OEo7!>m@fG! ze?IbZ-z=eoalY7Oid{I=ZbezL#yc?|Hy@5YC1FJ$_4A8sz^uSXf)U!dYkGmQIy7a? zyE7q;?etJ-{3P8K-I61tqWChKc1kLaRu3&RO#4DO25Dzw&KZ~g^9NOR7)z=x|vRQS#?&5G~QIuDG+YxH}yp&sKogAV6mkB7L;?!Cn6pJ}Q zBU5?YKU0K^(=+dbNdGT|_%y&}lT&!pxsovOVRC;gcs{}zK=;Q@&G zguYa#l);bhiz`$kzwfEOTup3;M?i}k(^Gbeo9hXc#w_O5;;RC6dSkESsyJOc*K3y| z7I7S@Xp{6fx{lrew4}Q`3}P$pDu(JusNbn@Dw2Xjk<*1k+gSPB0^7zleIC*J?aT<* zOAbagizod2cz(RJy5{XMu~Uoy;Il&+H_GshO-Sxu2Gw{C@?r1#pq*D4g#RAFJDr}$ zo{{lYI$4voCLjEBnOO&*rXrA^`96)Va3yJQ0vdk+@8nDA3J_kTWsh&fx5tk zVUAWW2{#57ajd0y4^Tv-)j2b1KDFZlrm0i@!p;J*S-Y}VhBxns|J*p(JIVoSou=YQ zq7X7sNH?WA&8LomBJbmb^R zHLzzBv(|2DZ>jc?iWha#qn&}YZMq{O7rY8)2ytiX-n@)Ul{-uFoxoZalA>s9+Zb`V zxI(l{+na0Rb1r*Wt_{isq%ENPs3Xxz`}BbHXazt+9tSi-PGqSq zFipmr!xbMPf;l9@n_o5a5duKPmMinNwsFq6vx-3cAKhwt94|r6;36-R?Y(de$rsY% ztf3(-xrxq1i=7qb=6U8rm)VO^^PxJ{t7#qc#F?Y7m9wk*MdlaCCPBIor^p14lE8Dm z@6+VMq4jyHDX1F;)|AB3Ru}h+Use}y=k6YW@UYn+OhM9;ffWugev^&CK7iTUJRJi5 z)|YCy)HTvc?`zS*VvNeSI?he|ooJ0}>?PF*px!-CJmoB!O;VxySJHe{-Ws;2{#KLGFGs^Lt3^p3 z{cVf0ui0g|Zv;hBgmHaL-dB?e7FNHrDq?nKJUxtMQ5Nr<4~nbsybQC~#aCdW-L+!9 zoxF$4-|%6&c~cSoZ!za_OCL5tH@m5_t$Q~tM&`1+qxCI6-pHuA(7=ksZic9b+jnW+ zUK102_(BEk#6$eWbnsreZjN|~u9&s93pO_VAdkU3+ohW(4Va~N)VW-Hw1j=zk-i#{ ziO#L8ur9^&0Jv`thpp_CO(4ys7Y1F}l+?*oNx*Tx9nA;^6|+C7x)eed)Qb zQ>8fFZ)7l$>Ev8guDmF(gS-0>kjwPwHn%&A2N>S0AX`2sxskahz^#Vx8bH+D#66oNTty3F z*{XLIo^Iw2GD0UWam4k>UNK|w`&XYut2U-=-UXQ_CHEJep zc9YGz*oMjvU+d)#hBW*5(%lu3xkF2g67uz^Ui;yE1|n-T^%taae~J`hrIwg~HuXJU zW>HM-gXOUoOT@xhh-%i#->r{L;_mx!R4Ww>%U#HPnQCy7I=iYmyE6SgdsUb9=67q; ze~26s1|TN=i`MrY$Rpd`zxEYxX`+8gf|HZ@H;3tbaCKFap22__mi`Z88!U~5-$(Q&L+WG4}?=|4# z=>1RI2tm~Ul8a@}U+%^SqFtv)i=?SbS12e@ZObtfU>T5gpu(YW8A0e9%vBq04dKJV zy(cBv#E0e`_Kp*^H(i;@sAa=HXCwkq!|E$>FQQE**Takb~;Vt#yMg6{^{{@q4o0EuhGv zDn3EK4MRNI7`dm^!kGt@H8anxjw+~H%}|z7jPiKBI{oZHf-|>M`xieh_182ohA@H_Kla(_`?bpq S%mjrEToz`wrZ0?9N&f+EhEt3H literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530005217981.png b/README.assets/image-20220530005217981.png new file mode 100644 index 0000000000000000000000000000000000000000..1aa9b084c3b7e1ad42f5386e2a53b350bfc631fc GIT binary patch literal 41473 zcmb@tV|1lK(>5AoqKR$W=EOE9nb@{%+jcUsZS2^#Z9Dlg&-1?L$NAPezs`@n*6zN$ ztGlkM#;UF>OkP$D?g!QnARr((32|XXARyrD?_UiR#CMJAJ$pD15CM>c@GoW8%<~Nw zSDb~;>zgaftKS!8RqoB{5&OaIClLB`++ZMn9fX9?fdWV^B!ujNB=bL^NCKzZ837nI zaCG)p0Fh)vsbo@(&gv#vx35@Owq*b~$RuyhQ7@pr-eEG0m%E$OXi~CQS6=8R*sq^~ z3E`I+lfDE{{sd4%vS7BqzAHJP!+_}iRge=R_JDua?2wRvwESz587K^d{-0j4P}|=P z{B4ntfVKX~krgEJh54@OlMw%3A(&k!u$eSmTwKRzXT(@h-g6p=-wnYKdty|5eE7@C zkdTq@WK2Z<^%e%=|2<=hk}@V@Y<$R`h5Bz6KMnpn0@MFJLZshU$gq8&ErS5Vv=|AF zK(wfQB1Jlqh?3Dg7hHh0P)W1CGs(8h_;YbR&G)Q5Bf@|_S!Y>LeRRm<(L|!bpq@Q$ zo?MXO;0VM5O6@UZq6o|sBFUf&v`O>T8HV;l|D!!l9MrZBu}1W4iw6uuB@8Yi3u>e& zbFDS8XeVkxZ@2=z9>Z}g4H=6}LF=HLk2;UVKge*>zB?hSsL1CNX2L_eL}tYL`0DzE z2D(BH15cwUtB?|v2l`XB0pphCBi)wkI(p5m{KK>BpzCK(V^yOkj|n>WZ~e5#v3g80 z35@RK!jFc__0d&!^nRme1~S@Uk}*AJxaJw1?(lBjY0(jx5+y#mi2Z6(IUQOVrC)ft zB}Eb0c>LjIAB^*eJ`#A%Kr zoLaUMuDA104fF>u%AvEkC7yi{|w9u_7@v#iGr zrLoieVFVKLyrAhnyzua=tBY_MQY$m<=lU~sE{Ufc5{>Sz^q*cucy6XWPyL``-9}$B z-DjRS_`e+9M7f~Y>5gjOG)G$9xeQ7U6J7^FXBFDB557G87n$*mU$0SaV-nF>eQ*FI!PKlGx9R9%j5W?0-kuy5K2bt|UB!M(fskfUc ze|Ov5lxr@E;f+zEZw-Ti={g*U0SMqeWGvq83*lzoOczCt-|zBn8a!C)AH3r#TQWHS za_9g#OeyvL-KTFpcZw$&61NI^~H%%8O z5802D@a=c`&IF4AIlA6!Dc6Vf9>3Z(!m(Do)~(A=6CFWn-PrnZNdE!*GD_2>rbDp7YnM7Zq^l3b=H z`7NYKS^o`O+!Si@f^^V6BfO}H+ed#3W%gh!0qn4x&g2Yp!ZgmPw|!t~?-m?X zf2OKLsMeV}KwjS3&jKM&Z>$Qxt)jaQo9`EE6cx6+o2uUsjvZFz&i;|r#=?*mI@ow) zjOpIqi`FPIZ2kUP9~|z|G?$|ys{o4uve2+#eYmG~xYzCkQBBt0%G-Fp(h=*^@e1#-CAqtMQb55q|JS;z z(0s&#=K=6Wa@d$8sPFpWbc?*S97Rk$VhsW>0Cd1&2a2PW3 zY!7Hb61*rk+8gqaCx_$TcYC3FaiJ~HHv_-2nHi>{9|FfPHOjq1R(-!Sd!_42)hJ>d zSd~52bkM(7t*DjQkEz>f#F9IA$G0wNZ3}-Gvx+;(Hvjx&I#aAZNZbWOil+8WwIwZz{aL%i;068y$5v}0L@I+v zTtsf0ihL}1Ra99V{hIF8PyiY~OglwJI>UPZ>#qR&!&$kh>4sjkmf}kr zzl_+1{yO5<6)=MDA&KLuHmORm>yfSon9_g3?hC4|vb!K6db9aYeSl(!17GvsL6js^b!{Yufuea2XVZ@ma8sE<;tch6sVLyxn zHn(_#3ZZqKV;Z3u2AC`mEQ>!hdFQjScj@ET;c097pD|U zi=G&&4YH-b20YvC-WMwHFovl2{IoXEabWkreyf?4bkJcs>93cNi^46N3Mo(6n5WeQ ztjcuWqyCxvXqG0!W2gy{+w@La`AQwD|CE-z%oYga6IXLUe~9v0HZ3ZmPivU9oSmgP zZqN9u(UpZpp#QYXk`~&WQFDMmKKP^9lzYPC^lzDUu@8ll&7(Ne?3{RQ$TY~?vKF{# zI#iIm=_QCn3300{lZFHxk306_GRcq8b=OKVLAZ>+TWdYpRiNQ}6J*rHS@DL*zjNaz z&dkl8LZCp6#b`zb6Nc{`XSy8N8y8qvT(~vfHdSZE)@)5mkSv^WZL8W$mlY>AJ1-pd zMC0Qr)8fVA$NWiG#e7^KbLLG4R?N+=pl2?=XriAxr=GsuSJ0eNizIK7SilP#(%gBtbb zTw5|VdKivnPkywsvkZD`2YEf*gQnW`h(pg)8!BUrElh4dLCkKq!%0k8n>PIyk?8Zs zrq?m$riSW>wGa~glB2cTf!O%46v@K#%ie|FnZM7?>sp3-k}If>k1pAuF(jL>E%xUr zCy#Bvb}^4LuZi4`xmJD7C%(mzz};qzHqPPfVyNtQrPSwyqn0;iZ0#>q)y~E=mBt&b z_iETt(i8qo`=x1l)F4w1K^7$7kwBWU;hE!-KS$}sz*MX9=xt@k2tEaQ=F=-8)$vgy z3I6nif&SpU+nCHzcIA*zKJ(&E+$i``bB)z8ez74n#8H_Iz>W~uSV++wis1lfhP$*N zmS&NYr(f#|^QorW$g15pG*j6u(uC7!-Pff+z^CxnbzhzNxcHwWh1U1WYeJ(-!s z%&x5odsy;(m_!|A7Ul&EMiVq28;CYr71aF^nY1kKG{R`Q7nHpHrT9P+i6izomvQ1U zUt2IGWF~{FQj#+^j+lnh4#b0@BzJIs({0qaBA4?;!B-GWwz_e1pT(Q)@DzjpPo^of zK}K^;CvGB+sm2W~eOE_#k{^<{1#;uzhT@XGVmT5JbJJWTX=Kge6On|q50SDy*%@i1^h zty>Pc4J`p#EnLk*@9|7AHADw5Zkw*Ikgg_m$*InGDVsN7wG?%RMz8VmulA_R3P!ER z>!Qdd6pYoyq@;nCG1`i+jSR~(RrR+Dyuls942kN4~1 z#kg&1=*i~rtxL-7{n*;Dy=9*M6KvJ{oQ#&8-Ak{K5~KoQU0f2XZYb^;ZL>6=?lOJC zPDxgTY?8X$2DN3^-%v0!Zi~%7eMZ4sABl*Bi(s(!6-V&?>lK;oQNKS-E@^B`OVBHKeKVRGU94)Mz{bg~V{;SmTP`Sq8MTo2*9*)#~^QXzXn`Z=bPoix8`F3;c$~YZMBgoY*W=3(;WI48ZG^wd1?tLsMO3GE6Ah_5f)nakuGCkB*i*q1R zk^VuG@gX{kmpZj2>o9x&SpB?Zh3(4D=BL2yDGXtr>ap}y(|pfX_0h|mdATC9wTj;I zJoq%yjzOf1T=O`mz!S3Mb4gtL>6HE15+QQsGmxY-H8^w>>|}_^R-u>03vJ;|R|K6i z6_-$$@6h^sm7rj0w+zeW?}oplev9X_9xplDkFJ<~-Y5G5vw;4vs^}>1sijsN-Bu=S zv}n~2yt+8g*tg7SrEn`(&(bEJbTXKaG8qgg3*M8GWF;B-^sJCIvzJoo((ut0S@!I6 z@1AJvOrxFwmvtfPD7N!QPJ$1gnn{_~ZBWPaN-JB&{Z+sW&`Z7dRP|KoPiRMiMz5ZD zde1QB+%#01$~NzyduU4&DZBws_a^?QN>70`Ip zMAJYSxexlaSrdDJlFx3CAb+pZl*5X_9m5t!z*zAhD5!9wWVS_HF!$v<;+BMk@lf5$ z`dxW>>pge(ZnkFjuFDghYJ!Wtmc~25uMt*^^lg2c_z_d>QeQt zz??5LR$?1m8CZcK>+2`IHZRudsD}81dWQj7WR)P9vt?aHc~879c~V@yb&bE$)ZV_M zSuPA(AY3j1-Pn6mOV_93)GK`4f6j6YPVx~AE_dXr+4s(uBoo7rW_*5C4X~Iy@;f~qL_@$#SYrCT|dtY-P9KMBBdBnqPYW5cA zV@M9+Wj3xme1$O1`Ao(T>nRucHTyiGw-ra}jjL13ETFz$j2an!yx?o8Ws6od1*9j9 zJx^Hq=ud>=Gdw1jhaEFB($zW)w)5{bY`3$_^nRK#rl;-Mo2#RYYLE}{@AN!?!%U0LMKgF{~@GZUApu6_Pxmm zpvT^}_M4{zl6^kXDsPlhZwI`1{!B~lWqP!DZT|Ko<8C#;bzH36yU5uRT`H=+J-Z1? zG&@^vGAB&=tjaF2?go2lH5P3RakvRkV+4+-7R40Bq=NuQ)(@m~`c^uYy{CzJS_ngEt+ZCyOJ%GCf8Y<=crMkof1@yZt!K5;;bn82 zycUE@5yS3L+E|M%0QzVP{6^Mo<>Y$AzF>UlJ*;pHB=JUNz`#k@DSk0V)b=40u0jWhe17JndsTBd(6dH z|IU`cx%l+bZK<+|id>9)Fb8|_+H_k_JriEz5|h%9F*%Z&q{geGI6Do@y<*gD2Pee3 z6z0=vR7aJVLT_cBFm;Aw2M&u@4$;K@y@)5I)8(PUMAmy5d>K1CzAjf7uc(E>2fF-L z(nx+>g7C4u{lqJ+zS48$IyePUHMr^3&WKfG4DaC^|EXIuhTmafF};?@fCJ~<@DpHeDEM?9SbN2lLQ9nZkjE^=y03ASNayF?;I+^I2fe_-W1Jt%6Dcj0hh+n04xUzTR#5PdT@kqnjs}|zu;&D@=NA@Zez=*bRVaKbS?pn z7zrj{iK^V`;ba6gJ%wlUOpUtgU;@Za4WZA4ATcM$$*E3js!0CHM$b4D2+!_oP#VMF zV}jIa$%+00U079}PyJKhx4%&t+qB|$zm0L#dj&VwYRKd{!AS~&-D4<9o%F-GYP_8~ zG6w&GSTLkM?1S>vk6M#CQ#wz55;scKU1q7_wN>d?v2u;ZD-dHG7BefL21zy=1_R6- zF*^-lOf%krKVHBEKJrq!0}PL7?V;lW73N`}^YhvOm zF=n@OOGXSF)Wh~*GAa=C#X`V;6j%jb9br9dz^n3!3UHmVGQgI_aoDm41~@vPt+|}q zA#_f!3T=+e(K;yf+RU+vh8#g?T9hJeJ$6UNY-{Dp3rz?>diezXs1AAGiGnkX6_O7J zJOSM{HT6nGtoVz7XYdRAun7MdoU2$_oY=JPNegY&Wnv%Vy3X%MObP=Ms}eC@ z{~Of8d$VuSVyaKR@yP)81`S@8_OuOyVVy1F)@D)K@hgAlH&wQKl2JQRX=?(<+dUK0 zh3{ab20G_x`w^ORwHBbxC8ge27e|RMbMiR9ke;(72VEF`N#W+coTf4?_fT3NfGOnm z!ZgE|kE@y5UW)HELLxbKd+mg~t}>_89)4kgR#WP3Ds%`2D1rZJ;1ZAY18#C|8wwrX z4XCj`ybOXK+!^6U8(CKjT}PnS0gsSW+y@MaF?Vh-J_AiIat=h4+t`GMF9uTQ@Y9M6 z77bbU6&g|{pUD?FggR=RQNy)Dx5hXj-r7Wc*ZmZm(0!cw7(}=)i{ z<`A##v1wYnT5$m}zXxQy&(tv3U!=?qD6ihqo~5ep;zHdDKOF8(#&hCS_ucRFUi|=Z<$-DjwsC zlyDM^karoU<&~QNht$5bYf>Ht_aWzc^qu1GQA|-OK^jK_ru0c-c7kAkT}fJfW7O&- zUK=*|N>IRcN)`-f=%R{*lMoH2D#DGOaZfmkj(DB}pEs$1&p-qma(tq!s5va7ENH3d zy(n_+Mx`)nQZcQ=N{b%y*`o_K>ZGo*Grn%G{!^Tyws#K+TaB9+N;YqtB0h)5V~z=o z1hf#GpP!dw)BW7^g@JUF*R|K7;VuuI{Wx3$oWOmq*$dOOsF(vktJJ1}&X#o(m!Roy zP?fa+4$Yytb&CO1=s8PzV%o{zwIADqS(gVLj=EQ6)rR)ZH%@tCeZq;LCY|EG&;=qP zy-=k;ev?Rx&plhxM69cJ5|UZS@SJ{rIdj@-aU(&` zEv$g2M-~qY_aXM}K-E5;>ej0z$GxofD_abrg z67cqHvHUs1&GURV^q0d4>+dE#%=X&})Kk-}M!nv#9ZRge=fHtmtq5it0;3+wadaz) zd6~b@7F$_UV@(10wV|F%BI4vz+-xVLn+~&wki5OTTLGBI?-jMyDBV{>#i%Stcww`- zj!Z>IzUIrE@bfK^gWcBmm&qY@?^9*PT`kulJaawf9cG@m%Y)z@|_!zzGUL8lQ9GK z%;Chh!}_^@_D(OzvBSy)Vd6E6z=x!tE=!a^*EW)3+e#muBws%cFx zgOgg;YW0It!2-)DwVvSc3l_q}XZzXW{Hz z+uWG)`3Th*iDiC)?^h;Bao^gO2RahDQbz2Wh)BDvF|}C+XITnH0zF=k7W;E&I$=3l zkR_aEED(XKUldl9xR{s^p`3VnM!;kNXhTTzyny-URZBe|HadcfCe?8^j5o~zZ0OTz z_JoiyATd?)6$%;ludV{YtbjwkboGeujB&rN6!}^$suznONtqvED2`>Wb+zAfEM6yk zPxOqs@XK{Q=Gg~1HWrmzHBpQL`k~$ez9#)OyA^|}*!9~-X_=&t5B@@u=7_UM97|eu zHeMSf%d97!fMC)=p0y*KGO9$pJS*w~0sbddVPM`XD^pLh*Z<}M;CW98x!)LGcDa%~ zek5%&$9L?4C%P=jZxo4*j1dfe5UPBto@V67*87NkhYQ8!LH?MrjgWyZ2FJWS<*V|+ zM;|1u$qt%fRd{gJg-%f(p4<88UHD2LOWD){OJht7O1C^C0X97-m1wy_@8@u1Vd|V?|mzh&P$2?lx=4Ud;KuZa~LoUnro7C@*Pf`?K+g@ER?rg-!-S3re zBA~#l)YK;z75k0dQ+uq+iKeN#HW)=G+N*+G)@_GG)-6YhbUepdaOc`H(w|+Nmdoy( zX3*C9dols&2r`7b)rKbyUt`7MjFf8Yy-zT8!_L-&g@Mpw$_#<>0Upb9x&4UK1{`@q zzmyG01-Aq+R9JsC1WnSJo=g&Rqe^2;OJSA%2nP|*748#8Jz#i{jFH6;>F3Ql!+(dH z3oePH6bTI!a)f~U4yvRgG+y?m%$(%9vJ|wVD{eIhu;LC%$E@j)7X+@IEjM>YFI1vm z_rGJr^T^-57_=aVEnthUH>dmoWlB@!MI#j^!O;_dK*yrUskz?auWjm%)$7h4TW11) z>>9taS(85dbg+$_zvgqcUY>kq<;{F4Pcs~1UVc^6G+ki~8KQf|Z6Z%`nD`)#thd&C z>vLQ8T)=}J-R4>AXVQrEUgs#zTN@Uz?XHK)-a2$=o z5`Hy9z^GXsUnX9dAI3^vHBW!*zo*_#g1}bh{lnB$dYg2Qgg>M<5=xS!z*CiO?S>mc z#YKSS7iFQbC#^@o9+BUoE}e`7$ZAZTXm74H)1-HFLENkh1J^hhFdmHiY+WP1DwM*! zoJQdcF zK~66w5)&GpfvUs7edqpuFHG#`hqPu8TyX_lxTj=;-?=&s`O&M^Hd6^t1k=oVLBIwx zg%7=)OtUd~%shfVo*8-!3ZhMYVQeJcJXfGuf{UO8I`4U0LE~w|@a90AlC`Zp)}4M3 zbuf~h>u}}u03|B%IJ1AuQt>^v;O_slbd7Jne1m-IZcSs0z%~%&M3zjRnVB89bSIea z6F7)iciPNxwbLW@h<-UoDCRy`=a`>d;JM34(Etsg)z3A1z~OU!(RuH`7Aj6|9Z6Le z_AZQ`fBFOnS>$?rMYGJzX-|zlh2OMDFN0D)Z*P5V-=v&UzK*FcKRI|W3n0P74rr>H<;Hj=vaThrh=Suy% zHm8oZj9%=IWUmHz6kSQI-qHX(3hRRI?tsHZgDJPAQ%*~(i(KnnIITE{%a5nePjA6W zJ@cYFOg^UILOIAsq1+2&9Vv`2#GF!F0*O6LuT^vN-)yz^UhL0r)2g(41&K)Gt$g-! zrPesrIEr;7vy$l7<704+&LVm)tWKT37SUsj6tQwx6N5+n9Df{?R2jLPiKTfmKXX32C_LTNuQNP)A6{DSaPXzmb4bHc89)nxBEq8H~eZ&IWMQ*uV9uEpFd+kGV~+_?X+;)L!U~xT^5Oqbb*}& z;)Vac#Kq@b5^N=7UHs(^0j_f=?U*GSvUEmDM+e`%6|=R4kSMS5K!qNpEZ) z0Exou3$CVxSLD-@gGq{~*yZTf*qfK=pN3v@7KD)MaMd{O*$2C!pl`fBd|#)fPfAT@ z0(`V_C$#DLYNeg=M)TDmd5l7yrskQmyDPe^@-nzMoWc~xbMU*Wo`%$EMDj9|69FL? z5+oeXWEK4V(tFtxn^Co7TB5Fwc0fL*VS+TYe zbBLI|_RNg|;UUP4DTMjP`VS8SC3aG7T| zLA1!yIP*A}plp*lh7HNX!}Fe>!@So(DgD07WCnRswIXPApi0$r)qgWQaqbO29{k}( zsn_@5vpp+li?4StF^kQ}wJZM4;zeyhnL~IcF^NJOdp14p$|;Dv^i9;`O@)z ziU0EH@GH}|Si(`{F4gffDAQxnbXJOIscRVM1qQNfB z)ro0nt`rv~Kx&3L|4iro{fpOs9u=U zS$S=nSci(vLAQJmUqQB{}%N;3Q$~B8>`#e z?2+55$v-^My=bs6Lx^?UPU|}{QN4SdRcn3QWe*eaA7B~(qcTA93IRH#pd+l38}9_O zRA)LVs+yrT&GA-G?`5ftxzZZ6?s=i8{oaq@_9wZ9OMm)=WEQ4rZWFi9W}JxA0eo|s zd)>t^LFb)Da;QXXn((9|^8NC`(#sK3>hd`joDu$5M)!1T((sjX#r2^P=T_OXGLj?; zM@VCfE_vO7xVhU*1a1h4-JFPh-5Ww9c&ZxWuTVVAw+tss4@*o`7p*~}W<++v%u>{ThH^>+%DtzZ;$VQFWHZ4IA$rIbFeA#_ykzq%=on4xnkCh``)KXQTiC= z+7`FGo;JEUZ36p`_83EIX!qx zvXv%7&p9%E3+D_Xa-g@^G99NAanSQ61|!73mm#HwmIe@RITxvT~N>a`r} z$NA3o0K;uY{F?2EP5<5`(VJ&2#a*0bSXnIzOj!IJnfK2iz3;-vNx&Mco?xf%f{eS_ z55~-8LAtE0tkenP^-Cc+%w!Vif|<|}mgfQzuTEaDxAtM##OZwR)pqxjW9WiY>HXrt z{88ZixZ&-V<}!jjqP#pz9CiI!acSQ9I`x2r<@GMGOk-+eiIBmg{-e8{J5&bGT`+(g zwnVl;&DhZHvTfPm2Mrb7b7JMemAVSTO16>fQ?_yF)7Qg^vMDk4&gDvIS4uQ zA@8#@(tJKxgLt5-AHXlunhYFs6lt+?zdP=7!%gfwYEN-EqR7T6DWB~{nLjEL_sGg1oAX?}Y~~h~eBo z*OIu>!Um2P!e(Ve>KS10o;cE_W`_*r4%KvbKx@;064FreAq9_Ss3`&xVTzUZ8FiC| zw(sK-`TgTs`DPU#bA<3uG&uLsqDaQ9NZ1JBOIG~mbo=7tB>|yx944o>!6ogCr9bLG zf*TYPQ4ZsBURD@A`S4o@5B3YmetwZ|X_4XxI^e{n%uhwfC3B{xoU1e7y6WE>-$y%! z1CHXdkGTd0e}RmIuEYtv4pZ)vuG-=nZ!4SB=tj$sQV#~wXw=oQ=*&I03e$==JUgpfkB@V^Qh@15w+@d{-{|^q*og;{`V6EM77~xME;Ttl^8rwFC*=SO;F_O?z>KMo8WND@*3mn-p0lz zN!*m)%h|xj1ovK&((xr1a=?7%hAIEEc0^z8T&g4BM0%V-Zyw=cDxH_a&{#n^IogE+ zu3#d1Bh8nZ#y~=fkdPP6A}73RNOm&Ggkk)EXr`clx1oUD4T3+R!yXVhYBZn9R9A05 zVw(|nZiW&)LCQ-B!A)=y+!Qs2y>4u)8zW~jKhKhxjvT|Dl<9vTaB6OTY5PM;jL|AF zs%D>%j}B2s6u330KaGtrC37cXiY}3Fmk!!aAGNR};OeQ6%0jQ#}Qp6#siZ zMLbxs`Yv-F1>Kh=|3BrD1fB)kgixdE9tf7+xhcHl*$J>$iGqZDt-87cCSq$iM zcHnaTK0Oy*xru=k?q~;NSv}#l42%H0fDutkcZlF@1~fUE%Xuw(DN%<*QYB2ZqdtSV zom;XUnaR9D9?++qTTd`W1`M7_GyE@3D=VuCov)SE#n#r={Udz6jiKsaPEM?JDG}r2 z&Q=i_iR^rd1dKsA4vrz>7%s3 z>3t%ePu1uOP(xqspnWNd{oWul85-Rla1J@kVeu@%nBDDR^>U81_tnD^Hx`E6&ga`= z{I4@5U!OBE-UC+68;@{@$HP3?z1%yM*viT(qAGm>{9t~;WpL4Bl#(bS(Yn*vjOnx# z@oBO8y*racbeu;SbpF>lv+YrhHr+i2KAHj#gf7#-L0b12?X9=@t{q};{p4Rsk*T<{ zS~rB}I;raS`1yaQTf@IEsx;MJH3tkZ+Z+t3lC39cAuWcMT$BCP&99`drt1tTOZe`A zCS{K{V}|DYL4y*N(t*N5(G#c#urOTh5pz|So_ ztn_ujhk%ycsiS9cGY-vyEU`p&J~+{6Ji{m48u@!w&a*bumyim}vohxm2WelDQdtPs zAkDOj)2GYYi$cq~@IVBBXMJM7+kx)zi@_n@LmoecL^Hf?hAtfRSu-2FlA+yyErufD zK_UJq#n3mXIql9Pr~*5_!X@|_j%Q4EvppS1%!Zbs;e!H0fEz8z!Xc2`o#Q7*9Ri%N z5WI1~p(`%++-6!9iFBN2K@k4EJ*`@{;2c(8)Ycd{DS}18qv>0%Y5fgJIi6==`dafN}pGORXk$c2Ui~rX?_zd0>9|UMbKYIhRqw} z;*#WY=^@~7*-9W2M#9-Cvo;rnQAB!ABgx6=;7rCD`4C9Hc?Rz}#SA&k9UfQO_UVkLR3^Np1gOc$AZY zJS*69W!*nK%&e`w{SPl=z~O&682>}Y`2V1L{Qtrk`ClP)i8B-Q|6;Bfa;(F+cjA>V zyylEY{A>Ka1Rc^ZTrgAp-Vy@04G{nw(tndgPVo<{uM~>#+eR?k|4YdKLw|wihVZ6g zks(HcM}oaagopnb6&QN}RrZg1;#hj@gyr5DXc*a>5F0jl_)Zm%_D$^w{7R6e@C^y@ z?#uIb90r4Yz5ZsN{J19!0Ufr7l7SAu5~)^W#3K17uK18ZWb_mN57EYV4`Dl9)Wrlj z>&;o086vJg!O@+Wt{$;`EcBPnfT6Aa{MmFGtnM^&*zkGjsqox@xy`o%{ zU1JSS-wyB zwcYdrGq<%BzkSeGql6p_I^Qg}jH;{{ZZa`}BwqnshB@~J72J*$_Cm_-@o;vadZOGVZcR!a$`uNPSG(;5PTNSGMWupnEUBeGb+ zwA8dLm_$MxX}B)D_~fN*m;Ja0M@$mWl#iW_RG`5F{S0l!z6^#i}!gE1)==2l1(16gM!O{iMaW5;d z-FJLdhQL!BN@32D5JgJF6>i(KRBtFvykOwC1K+qCUDc>8NwD+xyW z0GR|qUS8?!G_j%B+K(-n4`%MB8=%30|TuLCl><) zZMK}W7%|Ph|FwZLNc}Xcyb6noXtZc733hyO{wULoI0gxBDOOoAd}9x*p^9Kav>v>> z4`?MY??y7nwKCbm>t{fle;e-~zF0sMF7MPAvdd`gS3jSYS8HW1RNF11$l z&!|z1qF&$VLLsF_IdrSI=~!0WbOqj52v-*W3eXk(J}~hi1%ZDq`)uPl53Hqt0^$b* z3JQu5C0bTi#sH>SbIeK<_cLl@f&|biew!ZWD^Bu$g24gnlxM-kV2a}e_C&I$(u}+| zD{dt~I8-)75dtMf1eUMM9S!nd=9&;3@{jM+0D%zy-v9C#v}NncUwkjO7{7iJmH_WKqYF39u=%AS|)1-+2 zPH}D{CgRuM8V@N~cKy_74ey@kyl7DGcSm zEpLm=JT)fKO+^;W_uxKw{=b}d$A-V1`TOe1^LfnW=>v5^*+8X#tmxFb zSd?5Q$(dRlgbHh*PKbls*BIZ>NJE4qC4FmZaPIXi>iu|eW#3;#zLhcfa`j4Z^}aTy zVV@s>E(k>^`)gIHWiJ5s5t8Cg5NC77X&2Z!o$Rl2c=95fph%1^i%d<0fP+QgPK5{u zPTv4AQp3$Sg$BQLep42wgR0^jM}`1{zmZH+r)2o!(kEz6=W&4Nx#`OvUwIl?8t;7K z|BNB?;|4@eJJr`>Bm*M>$tn%m5({imk&?_ zrK9UbwmZU+sJRNu`)O_)uKKXzd_pQf$HQ`{N8Aq(UH zo)|N|;*bK-`d3K85GAcYr0pL*y2Fy3dYm+5diMUS^qT^OC{4PnFaYHr$WBEeJ_j+M z?G+WUV|8Rt2fIJLAQ5Vg1khHw)YpF!;xQ5W7@j`$1pO3*x&eVHD$U5sw|->aj8Pty zJO1uJ@K^l5V}VQf{&R;C0%+TRE{Wo(7{1)F$T7(Cvd%H+iMB+Un;3A_YO15RYmkOD z#>8+Amc+^oB{n7t$orNZIyc(@(vdnPPgBUKuwTDtI7^ITzgMacU-ZMY8mcS8=w%rg zbZp)*6Kuw{2(0CMGK_Fa2)31&n0y1*JF@xCcn58%s-d^BGKK48x+`FyM$5@zn6Lsp zeRe2W8~vsiIRi@Hod{+5mEdiQaL#?js8EaZi2!-LA0)_#`GlbFM9+NLX9?7=vD98e zc04?CITf}4(WjCUvSra%Z9oD)&xb|I#wJ~zLtwbUHjC$XN?ZHO?-Z&7SkR@1X)a&m zctUSOUY`~>$QXP{` z%S*$hpT$%`>XhPeWb6c2OLRaTZKghAB^(Ri>JmnN1EE#ko#Sm7s2SUG25fjXFuzTgmNEMk!iT z_B6&U@)hd=ZM$Jzgpm0FasN`O7bO=;yfO5Rndx>wcx!XVV1T25sj=aRaJZ)|=Ccj- z!fxYOX78gwJeLQ(IGV`g(nkilwr|3{{?=uF(Z|h}V^?6RG^?B!YH- zQqt40PS4JA?(R+|dc5$9w8DcxBr#pH1t}2@+Ds`>%gv&6Mr{(QXgM<)h-0opuBwhU zah*EOnz|2gdPc2xc5=LP@ZXoREW^e07F%hk?q_Y`8-RXubDTi7JV|?16UNK;6Xh#xR|{GorBi8DS+#*;TJ@3BYXfI0(y7AZ!L&=2n0^ULl;k=7TM`35^c5G#)7 z_LjV8=Ktmbti4;Vaqt$1VJvfw;+45w{^tLW+ZxRRS2Y5jyc+0Kl2Y*Gvj=;qC;E~C z&ZsO4P>wOkR+q#wnlMZg*=Cyf8=*O{GKr$Ec5uC>fc%$#-C>gJ$73!}lyVLL0ilh+ z7|Uy*lJ6TyAmHd93282GzCgt|8lB+c=oKQsOa9xRI7FnmdU&UZQ^w*ZjBBkjE-$S? zUikWw0d_y`?;jO2s7k7+0)aVX5gYh^HyG#MG(ZDSBqFUhgk|q-}G5J0ZT!~%Q?I1PTs>yTkNHCkB zF>H0WtQW0M4Zn62q^U!X4i!c@e@_={K^AFw`jllYTk3LNP`fakRv%5iLG(`a7iYXo z9OB_!LW=8$pw-{bdbm0s?OD28!iqXO>}S*4zliw^(6c`=u<=P+|Ab$u)_b{y`ddc+ zl+*w8IP0JuHzs2j`p-oo3}>0I)oDb(V^654sQ-t#w+^c7>$U}vAi)U`TmlIY+}(l( zf=loOm*DR19)i0CcXxL^NO0GKyC0-C`F;0xbyt7y-utRvRsR816o<`Pd#|eFKL3`F%;tWrqbCtV_dFitavA1yp0eoKDN_lR zM`$#$xH{0X^Fy!lRVk3B9c-^|JPSNASe~K^Z^x<8$aRk}xFTp*xsY)L6n_L_V9RGp z;svky ziufYq;|-X&PAEqclHqSS`Fbv?bs?RB#;M&&;2+XCzeXisiiCgOBgY>bO_HR&iQf8!r%fX#MfAq%iH~=PP`q$ReiM0)EvHl zI@s9ocf0lejlgD2tVt+s-;>`33BUU_xK-V@#)X!`X=U`-eKUzon$|#Kw zULJn!LQj{dAZug~WucacWue?Dq^Xb{QJmO(iSu45f^o;??^zO}IN|iP+de!rR8a!9 zy1VPak{h3!a~_d3r&=2LfPpwZGb7ISrt^ls2Ar*eDUwh$T+2|atTOb;4K3bO2d>Nc zE4Ns2@z%EMW--r~1C=at3&5UK!%?tf53AKLjS=G<@0(;`~mO@JF>U`Y!!j%Se7BGLQ zTq#dSF>@%(S+8E@7{B<7DTBm%l&h8%P%;t7n&oFJ&87eRa z;Z(ZwKhiIQ!F~_T@ba_o`xgKctn~9Qbg)7C1@%u5ezW%Scs~BWAWY^*PFok6Qg&Hp zIRQ>t=8RqkBwBW7F5uYF!NQJD^@;7<$G-!T?*0R-WhNeo&g|Y0Q;;Un$dHGV z&1Zo1vHrChN2d^eouM8)EJlSjk(luflLmz93>%n5@DwN(R_h}I?^?7}Kw&|!jftG# zps2se08~3-TNL=76N( znlJQ@E?@+4zQpfTs|{P?XjN`U+J~Bn#@kB? zu6)2KWL2k-tXFT&v~ah1a_8&vPh-VD)?=?NNSKjMF+rX3MO=%3+VzhGaU!wrS7uPk6<{76c1nLcC zP~u=Xcj=!1k2ORHhrM0J31W_Dg$Qa*24~QIu#9Oe+7P}0_;HadmGM`Y+V7j2UvN+M zxPrhHn1CzD5alHIakD0Jx1%MczF>qbX)E|+2=%ri9k%>X#|5^O3-zp+NTHgH*@L2I zjMF6qqe=^?U%MYpOXtA45Xq+Ln}{GtGnH1mtmsQN%YeLMz64x zlli_eA>y;Du)D?YPy7j>@|+KNQ0zS>Agj9-iSq6Ab({MGuwqhp)t{h&9(ffTM&8+{ zRI}APVvgw7J+|*A0LC z)S1#~d&VJfQ;QlN&f9?@_pl>=+eN=8qNF@_Q<(4ZbQ$7M`lXN>v^cWYvL=6aSq_gN zp#-Zcd{dX%+@HnDs87DLWQ}7cjI^)LpVD`FCLe2W@Y#_HR%r`q|3PnEX#A7fax;FF zPG>AAp>ku1o2>^+6gF)4cHa->kS`1tSwz$gVa~qamZ8ZL|0s;Wv?J5Qnp1VD5|b9H zA_X=rhiGnQME$wOKYj*ry+_Rc(2MB#sekT%Ilkv+w+nB`^feH8D?- z2(xWGrPsXOjA|R}tb&Tx!7rR~{MzD)9}kBuE_uL`dQQ2M+X4T1L`N28ry&S$u{x#9 zuQpZvtE7q{MzFprNLOLr>Qu$&a1LXogG{@XUTa=nobN3ZL4kSdFt?pf7%G#vk-0x? zl!ftD{`ZaKMKXh{s*5LzEt@%Jm})GH*udJCt^ddwl-C=gZOE=(wC{|w#41}S;+s$cY*=qa=Q0tWd^ApP z(*^%7=?4Wx9@aPzQ;RW{CNwhHSFx!s_zf{8+4)d6U|})lijsfgNHH`wKjaq7u=jRL zmtaT$xD>rbj^*X$SLYu7^bwobyL(5u94fNfDu}SwspKXeH727%o2FPW$&ysg+k6YZ z2>0;YGn!98m66--4Nb{ApM8Xxh4XeC+&2(ZbyMK`$`%_Qoo-Ge4^GxXal9l0aNaX< z1oA9(`;dqBR|qi zo$I5^k`uJM0$T=C@p{f;gugku*z-QBh5QGmiaLu+lrP#ZY3Wx@FQ0-teQJor1~@NBb@HE~4q~zz_Q{Mq~8j8fQ%C zR^HjLD9a$L@<$HU=Vfj4*YtUtlWucW2h1D-9Pktp)Rrp)#1_U1%*DwwqF8aYD)uFJ zsP#*=DIWaXyDq*SQA^!dX+IsIcBXjBg$x(@m#pp3lS+KcQf{B>+eZ<~S`$cw(mLi} z;7|e)~FG9w-A@M}3y zs|ftdGP4WxOQ)Me=h3Z)?Zx6wM9Bnb=tuyk2ZT(uR6XC%a*(y588X! z(0;hC`)+Gj67D_Q6Gz&dYL~zf%?8V4#|(B~!#aE#!@ZqZCi#x?b&c00zFwFKN@uEO zUn@TR=Ik_Kr5oZ!@X458@5}ezeNKj4f+U}pAf*fBF&2w?b#?KPk!U=;yo1JpAKwzk z79%ENASH7}I@vd>nbJ2zm3v6T(!rukK^>90(L0lg)2V=#df{mNpv^mEM~ypst-vRb zpNt%V-V;WjD&hlKzn;Yxm;Kh`-O}>rAuwXp9}WGg=q=`LV22RKSR+Z=6m{hN1&1{O z=pJCVSn%4pVh!n=jXHN>83~$_EOpb*;jxtd64Bqv+~2-RY);a;j23GtLRe7d9Ac?9 zM(P-SdtdMCVT3UnbkdBfSe5X(hSzP=a+|61PwYL-Vgd(7Was}mpnQ{Ic^w}Yr>j2o z>~Zan%LNAmy|AzlEKYvg7Idxk|KKZ4K%Fe8B|>;0ntT%#rNye?&veX3FSi{dzZ&Zs z!v6*fDH)~!{IwoW-k<*=yVxUleftkT7Ry^XJ;U)cD#!*2Uz%6Aswlnap1Ch@e=y=k zUqkoJG%K~-%o`N3bgv-bM*1h#d_-_&!Y0Qn@>*~^JD1wnj+-KheWAc2<(lmOPUSzC zy8jtQmT8P0Rx&NM33WMdv;iPtnUc^)gjKtVwyvIj7WQ~Uow?UEW=0s1@oC{AfB#Lc zDV#HNMwZ%V{p8N@QKU6`F#fsqeH}|13#KX_80fS(oSPh-dt=>-yO{_) zv7Rj%+76G^emm{hgIJ@*^e!cW+$BYCGtyEI>29cw3$_Jxe$Y2!Wt*RA=zN{)Eg}qh z%x&cfbaJDQbbCG`hZ?Igq?rYIHpeJNV+>UBd-`8E*~W@KsNhfp2Z4>aYH|suxxzw~ zapFM9GJ^VEXHbujD0$}v4thPk|>-qqR${zl<_H8B_)lzp(pL)hPtV)-HZ zRxJboepX-Px5S3++~Vv~G}l)jd$sjM7MHDmw`|Nno%IR^rNY)*1+{1{mO{0+aW`IG*@5Co*hU#1JTB6IhfeE2A-J71bywCSf0(w+UKIIZWNmDF!obCNIucT;G^CltnJztb*h$7lz2- zLia2!?|Q&o4VOnP;5=0G+efFys|?*?-0dI(e?J}yNC$+V9=i&aAW)1>F20ZT5sNp@Wtt#9E%)|n zoXia^PyH7`p3?zORoL?{We1!=HD(9ou)YV3_ z(hnnlsQ@TWIZN|II)$%o;4m$2(xM#rv;Cbt@uZS-LJlH znq^GVTSuIu*4U&HTt1L(!ur|YaM&5@<5woavB}SKCD<8tza`WOADKf$AUQDj4=hY< z)K4lwtr0etMh{-92CoY+^>n23UncsQe-{*86k}Czv)Zf+x;dZICByKAOR$;FCV{^X zMKK^yn6yuk#bO&37X0kQckJurRMu0Hr~mJxD#IdEWRp{^;8?JBmw* zv9*yQq#}JN!&e8mHjbf0|(QsR8Aqrs8Iq{DZY?vwI` z^!%?Gn$ zvu|sB=3c=-`^v4*GQPFpL+{OqM1OZ!A=%-1P7j;??$F!8_I~OGy!A8hm7MWKX)#D} zr1aKVG&MKB-hv=%67+u@pIZE4QIy(LgaN$zq%hLRKQv8C=K6veela>@ zoOf_{tapbhO!c89>bycEof{rE3B-iEiVr&3!6!aLq|Em3u6xxC5H=sr;=WveW`y;C zcYG(!f1&U%3GsI=&&Q`)QEDeW?e1sdOg&@<(cn@$j?*zQ{@gG_y+NBth-0~ z4XTiuj`bh=N*{iZ#y<6N#{|$iG8N6*fLr}CwdQIfuMAPcK}lk6fW&jaGG@^p)w$Ar z$Pa~$7PE5g<$gXrdm7``%*}N7Ec+6wroyl7Z4Ly}hY7#eCQn;E8J9hs^$p4)=~v=S zPfsf=EB_ocu+~DDrC)}XqZC%A6yB=B@0-F`9ujXvBQVp0FJp!xedO~PhgBZa8ri>j zrf6=zIC0-Z7x<3&FLXQrQ(^kef#gdcL>;nybJ~^>IH4XjSM^2xu`gE{_U+qRWKd>f zU5dJ&N@{CWoC)=5{`a+vzC6?E+>%SJ>(x^dfy*#Nnr{JsIXn|B{h`sllW=9AjC5tN zT<{qns7tAdB$+RWy*hIf=(8CxdSyqzwW`nT?YCo$cZ2k++xNjfxmY945QsWgd(y(- zx4#4+{>C)D7mePRX{FUAmOH3=i!2G`2Owq9=S znn2q%Gin72lQe9N*HZ0TXO$~K!neWga@)^GAQqEZh4f%nUgy_z4EYRbm1?}kC6ihX zhB%AR2{cCOwV~DVGni>}at)>*a9b*WHBEmq8jW~U8|Cs@j~zMDiKE36Z{|uQOOMha z+Rn5f{LK%)VAN=QaP>wu8GKY_7!*^+1*6u`#>~*-#!QVSmFQObokrO-5i&whOC5e?@5Ns2c<<=X-S0-j=6a*n_5RwJEiK5`F zFVou^2^vK-+nM|b!)z5Wx_rf{*(x#?!{p?Z;N3j(7ot>>cfHGGicKxK*do%=VD zLi!(+F`YMG#Ei1!gAG_*Mi@!>DiW4XEv?}d+GJX){zYjk>^gvQU9K7$8mi^aWP=zzf?*NRs`STmEZ2V+eR#*he3gDaxwWtW ze}2X!`_9i);`7&OB^ANGIeGrZGf!z+>1Oq&E9)s7pZ)I-7`v z<- zSW^Avsar-`Ojxb|k22xDhU%|iK#>Q906i3rLaKLbO{KsaWveYsE9x>psc4B+Veae0 zVm{o10#By1&J{X#tXt#xlmQRS6j8yoLCwYGu6iZI)|+-)2Z2wqkO>Ee8SQ9~Dk&HP z6@Lx46X2aQv?hYI_IM*V*IitPsDK+I9Q^Cwi~5#b5RHVlDTM#R{>;LBFATxzMH)Z| z2ng{Xi2$oK8ND@1l>xN_3)HI36t6RlP_{i}_;GGMVu+`&`WJQR!6mkPep- zDZWPSw{ln2kf86I$A^pDR@3e~D*T4et&4bb^+{KdjUH0c^+P)>QS$y>!_7!0TOCru zW0LGMKd|5t-Vkvnq)&4`)s;1*hbTEmsnM0AvPk2HM%UcCitxh2&5xmvK-uisF4i<1 z^p32Z6A&K0tpNRU{*5m|L5d1AWg>XV=SELOBp5{d^rWOU7yJ9Vk%N0u0;E)L=4so^ ze4dlicqXD+y`IGytUNv0L?elZy0y3ZM~re!kFF#OyiWWZq#@<<-aa)_c}7KoJ-Xs9oRbh@#Y#6TD1}IJ7D$`tKHwqT!n-PlDO;mKN2=`jl20P znA7ogj%?H4YC2Xrfn?E8BdgEGENap?gYry%f}0m!vIv=}6d#CyR3kPrTrA5eUw|UX zki&#L&DSXcFFnV?7i9sN>eFxY4<{`<%ZInZ=m;bpscqFDrEBxlz4W}NGBM0cf#^K|{h!&~)3PHYmzVFUOriR&#{w4C-X5_7ITzS1^|m3O98b$={Jbbqcdfpoia zG{_u2I^$Th0|Lqf*)-!^?OR~gDkfi}EIDZKrC|Jr7vOL5L@4?ZHx~s+YCS*95|py{ z#XukX?7)=?)k~Y0=XvVTd+-*`b2tmI7HM=1usqrdRKT%uyS7AzWr;T3q%7AoJ?oN`a{tF zW%`s7fF4cU8es<9$dSNoqbPITbxgZN4l8!Xf+>GdjK15Pi-P|`I{i|+C&?)8*j9KhD%-2SX;wr4 zrcobQyC7Z4KQw;R~g(xe>BI9P-5IHV=9hsMt100z=T&3ddw}d@V`KyipZy zR#e?8_*Dpy-G%!2WpG^u>nUCkX=4J!QRYx@=Ps3#S8i*tl1@X)ZbMH0wSV?V`yos` zNJ@V15S~2Ih;>>8y6YX8ps1^kciGC@GIMGQ5@e{4Z&YgOLIIJgGv~JEjTm5rIf&Di1|wx|9enNyOn85q2HUUim{|2y857$@iWQS3*_^%77WN$25oO z4r*3o6Y|s}w*jxOufKJnj?ywor^Ve+*2N*^6RDf+;Zb86<|A&3WdZ5W@RlnIKH~a* z!_QR}!@mj5!fyEf2xaV6cE%y7GE8Cs_3b3lUzeJogrlXa?H*s>p}1moad4Bjt`M7O z2TN{9E0FAuwH$8QbzJb-HWJO7zg?``J3glTc|u`sN|Y}oXT?}sXuDq|jOV?H9kl`* z6p}Gs3%Fn|-rus_no!By`yk9~tn`GtR43tb3+vu|B|&YEsQ1`cWDqchm+TlssX7}5 z+d|YB@2+VZ_xCyNrj?u=4EW8wu6q6iV#>WKE;Ib zD*`;BpE?C;(_Uv^zq&s$atRvv#_W7v>8KLv8TDlGgBC`(VdhI-5B7B(7AfYVkl^!$ zyTL!$0mzGodE4nNs~95|e1HgVJnJKD+>GR%t8(GLyCfTIkm>M-g*a9_Dp5huqx3XB z@o`2eq78WreE~8nWc2_6VU7#3)t38N<(V@Uf0apVle^^!xe zjAR+ z*e3o|20D4<{etdriNYQ%~9V%0G zPdM<2r2LHi&u;$;5t)*vY(G{4HWy=*se;Wjb1e2x$PhJsAWGVVRx_R7wFFKkA4^l( zUB26RNjuKxFF5;c=2~1>4@lb*@@^52Mg<;&ZtOr5kO5c28jzW8XSgj(4y;LcSE@-4 z68u8w8w;)8rQC9|q#y3gpi4s$H-QtfMIBYT(i3^@^+?gr-T1!tq!5>iTq#j#Xw z+CtM*88W=iD%n+1r&9UUz}fHJoHJb59w|Cp9211vFUjKXs`Em6syezb)&<-c!pLMd?jAtnV$Y>Y1lAvh zw+oEQE=c*m;nj9|B7RA-^nM){{v))wx+o1A2LP%0t^YGp9%z!KmhFf^#5%$ z`Y-gCWLt`a{7H>X?29cs;G4QuzPBP;8#vn|ASBB02iS|INF+o8i_bb>tqUY3ly^;F_OpEJLn!6*; zwgQ%sb zoN~oXbLdweVwN}bF(L)fTTSo4vk#i|Guv3M%MRbd8_HKoY-6Y*V!j0l-J_S4xrBN? ze!r_XQNn!s={##coMzPLsHTHb1X}&on=RJ`pSVT7OdnmM92!4zMCnj>ode=96+=ev zd7n4kFF+(at70z=KldP=b@=%9qM=OqWBsKqaqNNg$XLd?B11B`SV%7B%JD*w-}pS* z3-X;~=@GW=I)R?(t}n=W^aOmqASZaYGT$)!>>II1)NOw@&iFL2T;K29T}pV{-2`Y6 z%c{tz`i2O#aPc;1tZN)P^U8F1Iju41hC zul>`9&ef-g>*MAO->XBfS&gQC(iyja$-uSt%$|ctJD?01k=#z9S+xCrl6Cp=FLgx$ z*RyR&O>qKey{K&BWb&**eWB3TM?;G4WfVUMm(a$(*-#pnCW?rViJCOT?To=1NKA!8 z4;FqS0>-le_rCzRN=E-atlsYOb^|i@WYKVt;Syev>XlYH&i}U#2!tj13 zGsl|6x8)|4`%sV;LzX@_xWfA!U{)_O#y=8?K>T3c&m5@_BlBnWtD*|Nzc~~u5#ZA5 zacVIJ&Amv&3DN%pYt1u^a@Jq7KkrPr;o`N7`Ju0SQbW`@CnruHcT(Lin_O_Nu5N`gaZ0KAfh#?gsDm9nytNc82u;avN)WucEKQkxv z-LR+U3qkM}`kAEd3zGNyTtqiP+M5sRjuw_7jyf)S&U(d50?(Xvw_k!sS(nU#ve@!s*?UV5rA zTWHR1=9>AuPKt>iv#AV|t~!IMZi4kZvfGU>qxB8JTmbu^zcvF|MFc9BuLYg?m#@}8 z`6lO(Sfz3#2}bQpoR3NQ-&E1hPmbUsKEo1+8Bfed zQyTf7^{1#e6ouv4!(pN(K9oTQoEWdBUyce@5F6mP=Dz2~L&-j%O7Hb}9~A{O4}9eZ z`VMe;*holHc1_jubm?GX3$i44&jF42UVv3re?EO=Qwg6~K4f;z%z%&_QGok))2F&x z>bT~+MW{!GGPJ~T*kUo?O*Z_R|HAMg$uf1n_9dtei5KoRTVLAIz3pZS$Fe+WVn~wS z*#&=oFU&{cwc?oH@-qws1_a48pkf!?NIfggO_@xil0d7Xp*U?r7i*@wOAyHDZ`Q*c z@#BZ)+c%MvvbE~K^A;xBj0O7~G|BR$<>l6aVrm#LE}MnKNnwUSU8Z(7%)1HdI(F%n)|6@E8YUJN zVMi0fBx%7{DWB`BOkDn5Q0r`v-(?rEh=T&%$De#ff4!L6UjH8FX5rNVCEPhOd1qVW=3=>c!TsPNnB#83H`vZv-o;d-7h z{Ue)PVzFkv#`<_9o*98zv{heyKa0iv-*sELc!bNKT^|ziCzwc!9Kuf2Zv=9L(8H`dhFr+37h-mD%d{ljqaX zqRU#Pr+E5oKX$|gX#I-Rixjwg57%JWbAka{%<2VI+u8QJoz{~#V?6mWeYmRtu?kBjl64LsE!LG~YurkfO z;YQN6X)&?d92%b>WF5wB&&3w`;Fw6KrPdE~dwu7o!eUtf?QJ$&X*wkJG%WguX*LgH zAV->DNW#yQe*D$JzSSE{_fho`w?+tsKL$*q5n##;GF#-TQz5WuMk~v)CThlB8xr}5 zu1%X8b3hY|>mHrc_gbZ7V@S?D89C+G9}?4I=fw5qr)c!&T}h6wb=G4`Uun*u!y49- zZ_biA8L|%i`;~=!I%O6I@6BuA*bm)qO<9cT-;tone)H$b+Lci3V$xe*V2PF=MsC#BXic9&>}ZC<~Wd~dVff* z%S18|=d*2_)7WQZTrP>#yuD{aGsF+lhuQ6ISUc7|T7W(LlABmt;S-%gVqj%N5_d)x zf_0ogMx;5`+;&fr-smal#$mOt<3t;WCxjL8w48X?YEBpkcg1j=?y(zZb9rf>KkG(K zC6Whre7d-2e>k2n0jApU|{rGs@BIr7vy>WGQ@86M}}Mq0>3jz!(sm}4sy3prVYJw^fk zWH{`7nhe%1kBKzhXZZ9HPQ8A{wTBrdV>Ztq-t>VA<4dt?b`%qnY)cb_#(bwLhg(ql z{&878O`M)Jp4Q@KN1%uDAC;fxaT8Er^!mq`(QEpY+tEjcqcBFWlHe2G zuvys-*7rL^FUYD9*74Cg?`;3woJ_sVY#{2xy2Qy=>9FhVA!-zhZ3EY+9T2;0Sn~K_ zW@{!{E&J;zCDwS#4%T>bksJcxW5mpp;R%ptrzrD(wvJP~`!B7p+H||s*(%L}q6v?Y z{CwLZRLa{^hZ(el*nrSAVwLeE?n+--wmnjnTv*6ew=48=s2c*cnn--;+uU4r0eNEMu|Z(2 zx%k(~Xn+rpBv)b$seej-;WfaZ!!fx747!H29iMb>R=$hTaLj`(Y{|negv)7KF}{ZK z^)_0J1VT~4Nvhn1UD%vrY0dAPR~0sgfLz&UvEqPvfR_TT2(&l&+rU8A(}cqr%lKP4J>#9c<9@RqF0>-^GHhQ} zFis(n^N;UC=a!hOus{`Moc^nPqMmaGQ%ugXzu+jmHr7tXF2Ub24~Oh@5Ahu%Ap?2( z%7Kx0+F}T(ov)W3u*?@1$IAK|OCqmhHX3iX-c)^kDB-9Q~J~K zbR}$Fb3^@7cA{IaiXzIp8E!W+`yMYn_TlHsFl%9>`~EM={hX^2jYb%`;nP2yC)o%U z{ls+<3n;yWru>33cu=Spr(`)G^K7Ph*wSjB{W3O8NTbIW#pOExVF8xwRL7fB`yUJ$ zO~0c93%rbGc5#5MD@^rxQ*zL>b>RYt0iNv{D=XjJ1N{6^0t|8HIhlkkcx1I{g5lNT zUrQ0wYfQ;ENFiiwh`o83-v=42=Y}#y@pmq^-)k2U3J6ynOTW$7I;Qao-bkl%rn^L2 zIolg=;6;K6_3bCf{Ga&%4In1g*-Yt5i|Ua_*i6KwN&)}95emzp&k7o~~v2N)+M z$_9rN&7R(@wkLaMWgWG|xE(hom|3>O(1JV>2ECz+;)|+RhE=Ven7%Tt@5*zM$b57-i_6*qx1TqEjG^!A7z3x@?h_f#0#swC{{2pJqU_rI(Q#9l+eu4M z@$;taiu253VWdeBa*WRJ%`G{9`*E4Ev>B;%m*&+(P{BpcD}oYoT(Rz_1M z*8_S^pcyx0!Tala=hf%dC=Wg-T_Wm7$Pvm;Mynr6lr`9+dktG>s{Zb>-93YG^?|D! zv~0LaQS!Wvs&zT>z0zju)e(>qkO~VV z7?Q{INS_GUyV#9R|U;)d;@WAI%NHF-Tz?-X=WjEdQAwr?KHT5JcccNmFR12 zubBY2&4Za9mu+9IqID(8Y=quay8=>)AJ4aL;jz?5g zyEKDs7nDq7b*`u_fovgDstmj*EKUYfvA^tH4&Tml9;X)XAw`l74ins* zpD(HxN^{HfUnekF?s%W<8CoOm6ysnTSpCKqJK z?O%(sywVd(*6a@7K@rX(<6&6$CRL64c_IA%NAupk#wVFgI(HwYz;&;WV`48ky@m9i zO|CB9$jLWRPqt7CR4l6#qbq#+@bK`T#0%n-Q|O(Plk{Kq3Xa~#o0AcJ!9*I~A_oWu zJxb}ul>(rE`@f&2X5=I62~+*EyDpR~G61|l4f@pIJ&qHYm34=uJY9ns z+GCV$3JiOr1}NX=L{=ZsgC`CWw)Fk~6NjPIlZU;Qtd=B#a(%_j#N@9svbi7@8o(Ez z7p+$rY??fm7h<74R~Mj&)cabPZ)*73&9hTb8zM3jX~4}lJw`lC^nTHe_PgtB#8R6j zCxX$&-+Gc^a}AYUpsog)n-VPoAbKn5k^Ac^q_KwS;Og{&%SGsGaz#cchGK1VUgPPz zr5i2t^Ak}oBu?!uVah_gnIizaz)+drrh)N)UQf&%U{z!TtHCbLWqt<*gPAk(e{=CE zC~NJ2b6+a11unm4i1U5OH*x8h(e_oTMZ>Vd0@l;O>uP-uMg-^}ppQWP1ap4mP)_sp z*+^Nd`Kl8hlQ)l122gjx1A8(qQ1@g?NYVQ#eW4*@tkL1m2*1(yza$sHKgEI9xj2j} zgEvhYfKfGY)kXLMB`1o`xet9dQc7cyR_K}}&fcq!vq$DBh?CDr1d3N5i)gedN$%k| zTflC7ZmX*rL3g{Bne6 z#(mqUPNu>9F$z(mCG_pzRcC0qKw-UD$20Uo(cnnt0a1I!!U4Nf;K?oq}SG8gO75qXg7kBi&$yiU+IoA?}A7 zSonT6L0`-uFt(CoHTJZ`9HrOwJquHF-26(S*&IN%!kgfdxK)iXh^;XpjLJ6sHO6%q ze4B3`YM?^j*1;5FpX!bIAvzo@EZ|h`(e*`3Ek^_@ta7oPNrvpK&5>ooGC!h&Y=G)5 zHe$Yj{FXt?hORTVSjR4c%S|q6NB3}kxof8D>hiO=)lcJG9aCOJ-E8LRBp1xI6Jtr` zrkkBq8Ea18?~P~r9WvuTsJ0~c)lnC$7p7;w%r?{k=ph3@{FXt@4T887?wxvnx zrOFBmg!ZpU_H4x4g*jn$Ce%c^IS(r##p6+5y2p(1mTN<(sN)J0qO%K|qZ3Uti#dR% z>cV}EF=_QydNKKHKSv{l*uQegIzS3*UZj!OpcpjkS%*RJ#g;AigQs9?YwIl%!fSk_ zVVWu{9q$GE)Fx#N)C#(bT~_PFmVh$*(~q(Oov^nL#3SkxU5lRAH(CT7h`ih^aJVs0 zgNa=gEJTxFo0-J~>j?-9-dA{%`!}jj2FU1qio-?M@Z|ZP+ApWMYE2B;ZVkV)5XsP4pT;efgH@G5kYnurpX2o}T}w|=9g0bUuq_Njfi z+%Z#gP=Q_7Zr?y?C)O#g^(Pc?V?a%LN|SqJk$y}9pG7;RN-h_EgZ{gv((Jt@aukY+ ziwjFi-UCI?^Ka|4UE$NEUlmHd8U$BK8&q+bJ{x>!`WKdSU3VDQM}4nZr1tX(fAwA{ z^Z~bQeJKuH>8$rt;tAx|cx?PmdF(^eCCix0)SJmRjJ`u!7nM=f2JlQu<29~|KOZq# z?q0+74+gJkKE-#|1i02ShZ!~}oE}7DZ4pi_cHG)i?T&w=!Om~krIQ<=-OF&5;qdO> zUe-_IUN(B7#m;;Yrc8bHT<*0o7+>PX7MRQnlMf=p+U)Aw{FeiL2`4}3uSbX=srSn;D#qQWV1%#>pNq+Ai zk@l@;+Y5qLbZ=H*TJW9+7FYI#XXiEz5dQSZRMrWoSh#pv4gKqN$|p&MzC9+#tETNIP;QUxA!R>5$wXI*A$P5^xEJa|y2U*D#nlDHO9pJ?9mB!|<~ZY#R#ZQ} z*Kje@Xk8-m`Zm6wDCB2@77Y3&n()NXZT2 zC%)etAiq(tMJ-Yua0~agy={v30+`Uo8fhy$lXTrN2at7U84KnHix|+qXto=ma z1G12HrAP%&>V0eOAPXOsi$8i@{u^cEok`bkgp->6TTJ*z_2O>;;J+3=G7jW;5ZbDi z>9_FCa0ldwkQ|F*_u-EDAZ%JLcQT`je&Z9MlWv;Jnm>lpg9fi2 zw=$hS`V5ywFk$JgRv9il&eG>JfGWJK*9e#Cp6;KkY)k_(C0Qp{1fAdwl)$y{sc#I_WK8S zqZOmOnTqV6XR_4TSR(JMvfq72vDhtJiF8>|8=vjn-t=;}D1IxQOAvzGT^S2Jr*<}x z94PA)bX9SWoF1(`Sn;0gbxPQJjwYZvr~~2O-d$leuZyC;T9bf7KTH7`?fqzhQt8lnPP?6=fYbIzw&eUm*%XY+IHW=T2fz?#=M(N&@%BObhUC z0LWrWB;IKON(Tp+MLa}>+Kn>M>w{roLX2@;wq2}!V^HtxCA4P%r)qVa^tMoR?Dovi z#5#qu26rjG)%Q>qim7xkdcTHRkY8eLxEBVW1oDOd%D)$sU4U$LBciZxaM8G@fybOz z9^ljP=!@ZLhXX(tyZYKKAU1eFmn z?yL|vBd~*dN?(4KYTNTdmWbA+QA55!`izo?x+N~#e}jCw!cFu+h8hEn%?c~*3u2Bh z#^x)`1033U0qZ=Gd4YLC-_K_tlc^)naVH`Ffz7+ROfcP*xM z{&vs?iV+|e*wjXidb)!gtSv9MPQA|P= zOeT$p?^|b?+uN(*J1OIGPqB;FM&Nt!s+pR;?Wy&6>8=xL5Bl5~nXjpVtwDs2E=z-f z7u0y@D=QIaXoghV#Gn)CV5WTkmvKu!xpTlP!nreJX>THwGxc(*w)e4=hbWN2?VkV# zek~>bXw?~LrV`;BT|Vb3bAbU?)#s9L_Y0@rGVZ}{@gbwW+I!Ffb&^~{AH&Q7HCa>9 zOBxV>sy|!(%=yU$^)Qp=MeNOCHT1gI)f`#*T8ZP%LIV28Yf!+ie#0C#nEz6|umza3 z*}%`}f*g%DC~N-{l6!`yf%!KmCx|ENU~eB+aq)$zF!Gnqmoz+z;~uS4`mx_uizHq z4lV+L5bZVU!ybEg;RkF|H}%Ef;oqL-j1;)CGJTJd@O}Y4I9KfIX+kpqOo;;$;#5P;ASb6j=s%MX>kn#THZR7`Jx|DcOV#JNeWR+^ZwOBolka_&UyuybH z<1Ozd8|kyUbk2dbHZKc6V4Q_}AmTz*-IYJZv$!S0ou1nTj>pNfR}76rKYwlQBDzeDe`_L5F&frveu?Ej;*i=P`rlXXZTSIC)5Q=7VF6Y`bEtAuAW&Q5n5OO_3u)`;O-b?z%nV!!)nMC7N4qDjm$q{|@P1*EKYwmZY z_ngcQH^vX%OiB0Dpps5ZK8HlU+sk{*QS7)*u-(BmAr^mAsgG_}bC>56ZBB8#j&7{4 zc@Sh!QIWv)wzyE1<-Em9U(9NDv%L@dt|l>2SyAt9S`hOIIPeLKJXXd$ooTfL13;(g zW|jx3F%Wlr_bx)%am;nx)O-JQ_2{lZCo?DNRA^$fHd$HZXgF}5uYt7fGrm~7XLZik z3T_%ik6*jrkX!M$A6zCGYpmv1bdpC5QG7s#@u1U}^1td+ze(4^ zYf>H{8z0HYcN!8Uh-&F(KA-$K_hNHKas!zf5nw!dxgOvTrncsKSzkTK{R+~UkUd+O z02vJ0)~sm8L9TLJDw1J=mxcLQ9V4%T5Ow>h2?B}2xhDyrslc=gc{TI!>*>Siq1Z<2 zdHx97b^2CMF9~S9gy182q=58ou+GEaWp_gs0mH0ndPL1r3SgrccH8GYxgoYGtM;2B zr!!Tm7RS-4AF9TVcb0mMJ|d7ienelDYw&v_g-Tavb|>0~#{GjNub#bQx+|+zfHMwK z92?*h*|9Q2FzGd;pKYOLQ%}d}K`nRQcU47aP2%04f0K5dER)#uQ3=0%xtpZ@8)ljWam=};&hbmmDaM%IMK$P;OtpZ0w2ce)^?+{iNu$q( z0!dlSaUBemU7#2K(j5zX*`h)OKn3-JYZ^pE%@#!x^-7UL+m~!|HY9?dHpD|fiG#Fl z01RZVHYIXELMyrU5*!8^o=Y@L_xhH+R8G!tx{9M7u2!NJtJ3CDm`I1)aF!Bkhns&p zokkuYb%AVvA~>}M|9m6_*TJz3msy3`!Om`@01A{pn#}fO6_%vwW*5~6$O+BJb@W+w zIjB^73A&7=H#w}xt@4ORhzm0oC-F0l+;vkXg*X({ToUM+)@9+R)M|A^`r(=L%3|&0IlOv<1rfJY|mo(j6U5vaU^=2J)*awv#qZQUS z;w<+x979nQ-mo+MX+JQ063}pJMdeNO%*g=Eqs4K~18|-(-GGg2NZ!jd_1gRH&U}ZF zF7Rr2>-8=c@O-C`$jO5V36KjGP+9kP9B3IeMG#2_X_vMvalQL=9^Z&)hf}_Pf|RyNQD4V4O7nd_E}-PBt3j6yOj)u z{_d(n8oDo*^|QERZv^*l$tfg9X|F#ik);+iZUe#)l;Usz+_e_y58%+K4t1`1^D@a$ zb=QPP)p}Q*$KF>`QtBmgdXT&kVL`T$Qt0vB>yDZTNqiwr7-!M9Y0eni9PH;hKYFg@ z2+wi#PI0g9nMeT3p&+A}%5>+O*^lBk~|i+x5n z+xKGVp8_ue39D284LY3LxLBLnN2ZER(a}CXswICXipfPvYZI^en#C2y-=W{v|MM>D zAM9hc%b&+o*}1A7G0FrP_F5V%(jYqAonEiyELpDObq)`saEl$La1^h!)e^4_m4N{O zptog=F&xNw=F93MBB;bK6J)jOmc`UB++M{`K-{VcaI}V;vITjnznR~(@DJE^+Ocsv z;9rl3Nds>nYDVH1_H(jbrxS+u$o9JTs3m;cu%$7-yjb6$Rs68j+WFgj&-%aEQ@!N8 zRmY;YN)i&`PC#HC8SaneiHYRM(b=F~f@=d^nHrrnrmqij)1pXtpW9xXE{T?b=Q@Zh z<_GR^xugaC_KVtB{8J9B0TtNNqLJ0sq$@8nPd^DRN`|;*yZbwV4d)@q1la>{hjvI$ zSK2TD>|*HCsY2H?Zoj-XHGvlPUxa813JG+$cHg-#8m{#KISHkxZ1+v6MFh$Ja+(;N z4Y8s*-W0Q@sGyn7SN`NWUG8u1oGoe8$$pU4U>`i_19$DXBSCLW9zK}dYElBUE1cbQ+QOEWBvHIoDhvXU(Jabq2$YyeG?{*m=-Ug2 zLD0o#p@20o2p;gt*qKWBs`uSO$&Xi$R;#&yPSWO7d{FdNRPST_8 zJ1O3`R1g@P5%zwuI$U{zv<&yL@;-mB=AHlX#rW~90E%Z)*CyA+d#eS?^Q!EiA^8v5 zx@V`SVqtPbgtbC=-dqr5d-Lo&N6UHKRCvl8Y^^83y6dW#DCq_&aK65R?6Y}a zwkj2^4_0_%9>c+*a#ZJu)*>F&k=ZZH`j~dFpK0-1kHPvfHJ(%}AD^^}3VvTdKT1l8 z$hoHmdWiuS*kWQJ*_QRZ_GPwdki<=1DY9A?)>qjK?NTu#myJ-Mhsdt6Ae}ql5_G)m z9DRk;axNml$>kp(W)GcTaXoDG@lDlW!C#m5810#BO>P#?Y|@v214WL$uED{Z&26LJ zzzFl2vOHdbs|^G59z%(H?F6J_|1c6!lf$OIJbv ziRSy4tcP1!75qt~xqRI0iUK#+AO9pTTa3$wvdWyFBTiGPouV^jg@hx-vzt#ftI>dYI!WqHdjY!g4zho#IA49iihfGF9!$5^>Nnq zCh;K`-WpHn4_&twmmMJO-+n@p-P_;T<~UNRVqz19Jz+MAT97n*-D79uOR1rja8`W9 zHCP^Tm;g((9(*`1u$E+X(s+=Dj=vM@<=)5I03Bnw9Iza*-5sk!l7UuwSu z=&>VzojpYt{!xtmW`dy80(Qc5kgo-CO!M&*Eg7=2w6+f28Ws^qhvA4MIvc7gJF!++ zV=fp(KdpOSbn$P!*iEk;oSZPjq5+;SW`{Ug{YP>!J=nhhj_P7)AZ5~;Q38$+VW5Eb zNnh8OylV!k{}?EkNj?USdEeXT;8@fh-T7VpXO{L+?E2)8zqZ2vy+QmhfrEeUQYPWk zb_|Rgv5ysGb*>A!|HPvHfA9V~+W~V}&ZpOCrJJ!9zemAW2J!DMLU&&%XcgKf%1;DYshNgMjz~AuT4X>Yj1B z=Haad%DlV+wmiqJo_dLJiimuAM*9Hy5fd9jtgK>m26;a9ShnFTqQYnSYHm<)29$cl zsivb-RIw&j_9GU$C>YsA^4x2mw^Xl*$1~W@1GkBb zqQllovR|J?K9Rg1Lc)!YkB>#v=IAm}{<{9_<~Dk-1-r4b8m8P#rL+FO|5U)}O`Q1g z-*lg@q`$GIkF$z0{PSG*LqPWrv`-(t>9PKs5h-;TX_Ys^KiA13P*(q(Z=*>G{Vy#P zTyfw(HIn%P+3-&(4shhZvHnxjPb7@~A7=kK@1uzMq5XFY-VelPkTNMTTe8oULP|D^W9ZEIDl9k|Kd!!-pP@_s zTTFA<;o%1|szVf;Zp(Dh1X~hyClUz?7;zSZqf?*U|20zsHID=@o`gsbWr}!Fm{~Wn zSNUtg8Lv$eoCdE~Hub-4=u_+a&CP;m3`wYmf~KT%gknd5Q8H+k8ZzTbXl4Q*X52EZ z^|~1UZ~H4rp&?xme=~npm6T^v#hO|UvB+E;qgWienbC05$=hFA+iL{;}rr#fxWNRfcp!4A;*fBHHiSCa)d4rkGem%m4ex0Q%A*KG&ooFun# zt6H|-E;DdWH6(Y4Zu9^2l!Vcj-|EbWzQR6?c%}0JSgv_i0>9?eZIXr;$0<@Gq^ZL| zWJ6bjGt@A%M&4@-?1UA+Cy-))LBTst(@44M|7m$`UP&ui(~wN3OTOA+lL~iZe!G4OlY9!9-PY`j`$9mLqSe$Tq6e6}AXPD)xpIX`gJV;Wpglc^=D~iu_oTvjB^KKSZ zbtc&{z=(QdEwLn@EC+zvo02${htjhoJ;TBgEOVks{kF1TwDItYZJJ{Ee9&+i5s-KG zTJB(xG?0-Fb9@yrBhPrhI#LF*)rRhTWg29bZR;=jpo3prZWFwE6aoB>%H^3z@%LmC z+`{M&n{u}bdg?iBIAkd{EJibli zCb&wVuPIAsIDBrZFF(@APHEdCU3Ni1x#N+-_pXKNaUGJ%W5#h97|~yecz@-^m31e_ z?{$#(Vvz@H??^dQ`0ca6X$^0&?f==W7n}IEk0B>du z596sBS&&iH)zowYGl{~-Ht>VYx*%RYi5V^1G^0jmS_y;B=o|mFK$g}*w6!awmWOno zFa0%kp~?Mdx#xM2H%KFqT+dB_=L*?4$glJ|2gx9cxmCaWWaH6~|83N^ec>$s@J>3P zdIZy_VdwUt`5CUWsW$r1dN4kIS$t=u>!8ixRnVHOj+!W4R{bZ4w!HxEFOw63ke6%y z`XItL3EC9T!WW+N{PYVMO{tBA8Y?0Q2c!R2E>4R!7K4fe2jh3HNsn#nm9j55kR!-5 z&DB{WeDJC61yE{p(d+GL27<5rRW|fR1K2p%CIV`vz-xoGXOD_2X>|eCNQ{L#Omh9kvC7i86Cm*K_!+WnU(P!63GY&{vZL8yA4yioAsi7M{o0RSU%@%`-7Nc;eBsGn214Dy-3M`<+8Ge)|1cC)2|W)RYHb z4`lwffZp^pVMy^Tp(uQ11fPgWF?jsv+6j|iDGBDaH0J0w^RN`X@K1^X+VYXzBN-kA z1cKU7Sw0E`& zjDKR!VC>+Zh=KoM`PkCi4U?&YVJC$tBv~x3_G^mIiVJ;nV+?!SM|>jf=<{zkZ!b{| zpaR{xRrrbqRlAa$;ctPb%I8{*36JPbQsFQ?khdch?GNYpHdPkC>(IG(nm;5AWZFD| zfF2Gz4tHE1CZE9~*+tPEO}tYxeetJ@!iISYo2T}cH`s? zer#2p^+{)g-p=m+#pDD#`?b64d%DR-t{+J->@y{Ye%kVi1npuo#_o`hE`iu5}R95Y?utHQc$Y_1^;znT~I#wAu6=V=j9 zNQ^KzL2FFQ8)*UYjxJz*yauVN#%SEmwY8}F+s6!Dw;wxmgw7Har~-D3bmw{#yRuX) zoL?p-{C3(7Y?^kr&K1H^A9iKU#(cJ+f*=XOe`sudC*Ot2e+|rzuH;cssRL`$IpNu~qSyG!{ zqya7gWt?>t?V(YE2rNfO1iZ0`uaHmMz}SMAbi)&2&UU9?%R`#*2W#E0**X)EftJlb zz%QSL#d83y(5BvyB~xbf5{H%RJ>agcp0YC6+LrRLLch+XN0bUIYOO9k6h>` zd~O%rFL;r-vXctRDvkafRDTGeUgmDkR)pQwBR}-0FGqC_Rw6wwoyqO~(T5dKQ>$;o zAgCK)>*x#>VCwus%$4j=O(SIhQQdDysG`u8Br@&87CLbvDEOavf!Ep!eXb6C4qlqOZG0432%xtDU#NYjFoF}Jr*&5iLk3+;e{rKN43 zB;*S7zd+V`d`aspKQjuGcpgKfe2}0W1bygH>@tU4nHOh{9UKqfv018%b6e=>Ugo;5 zy%9n>`|%aZGBKEE)i*96>-ph$RW`Rm*b@&~rPBkmii;pu0OG98+S2a4*EYO6Yewix zX9$%&li63Zn8vhw_xseFhLuabRlH=eb}r%Z@KP6aCBAB{LPIu%KgJ_Ot8Gs+ma1P1Vev|;D)zp2pvs)f zjp@b&`kk1q7h7%~cIP>-Wl0eH{(x7q`b25p{y@pcJ3W+H6N8wHTUX?t)XGa6^h?{b zIlhr>Mf2wL!lO+v@gX;LEEQAExf%98HsBN~7%r1e#a~b)GI(hPhmzeDlFgjKaH@HB zW&=SoG9B2^y0X~dgj5CIa(mhOPTzuV#=^$}AH3Z?Gc9zcL$@>& zKTtobIlUua(T52`%dM{=Vy6zrW``5rR+rQf99?UAAZ(_P`DeV};i2um&TLL%q(iCi zV8X~uo&G|BALjD0CxvYw#-KIi=ye6wOnwJ`D1$S&L>x|Yyr@&mZ3dfFaZkqh928DH zoHZJ86v`c0QQs&LtJoaU5-8N{_63;ewFI7SBgo8_aaeEB?*JI^)TU~)i-6(vGC??jjC_6^o7k@|AoiEBPVLcfTu0}u(Zn9ydpB@Ov3K@ zy6bY25S`lbV*8SAW4oL9tnf-V6&@y}zDYT+qz@yKf{HHlfy6&3w@-!J1UHav9UyMM zBK-*d%9%X4DVsis-3fL%&ocOfV?rUR|3(J%KD&Q$IiYnW%2b$g$EJbSfRf!^ePQCi zdn}*_TJB%Ab!~PJ8Wh%aAShI&XZ?nD(%{OJh%`LrSashJ@II=Wk>=2;);e2cP#>d& zhJoJoF(;45yRTpaCAKMw zl8EGd>YljguHRSSf8N!eU#OqnLE02Jz@9mv3l1tclt@BJ?i%*J-KX`O`}_*GgWGiI z+j%pNFU^(ipn1Ajp-xXZbEMG>%>TJ8;$`wfpEY!x&e)MP1#?n|u|dFQcjL~K$mTm#>9y_&A>q4IowioWt#M?t*`0 z+VW`8i|hJ68vwiko*CX0F1VN3!G#uS@N*eDQYyV{qC9{FC@_xSr}K2xVVt!Kf zatPA{5zB6R?2HjooX9ZEXZ?y<%z3!s!x=CHOG)rb=cML0du z+Ff^GYFZ}DkIE>JapLvUT1;LYoaTA_*0pyk_YEF}MG;bF*+@DbJJuVdQ|Ilq> zlc%mm43}$iA{F@@I%@fn=HR8>cZ{rby?z8dtSh)%?PW|Ez{7L`s;OOkj>-a1fiN z#nT~uP|$E?SC?UNGLIr5S&yP)ONR?YpE%w56Kvn4qJ89Y|D8n~{crz51N$R1rRa7s z18L!jQBN#oD}NX1XWo#)X9q}O6r64s8Orlgp9A9-BK=l4)W~mGXiwyxAYB_ZcaA6SjdEDzu#KW4<4rxNaDt}H3#2aEd$sN4XUJG=2~`8W1&&ub zj4`E7j1?T^V^Nr_H6_&|SdG4qUPuIWA$_IKVOyWvS~vLBl%Rxnj07k+qHmq+xJJ~- zpxYC6(cblE!IJm4M93j8v8LI1+_EU->7p$bz1c^MkNr0NxV8fptiP@BN=q{{r&~&n zg}`H25w3j5Cx($YwwkA$<;c*VCDdG;UsX|Djam2O;!XQ4H54Nx=*@0YeO6bVNLI#! zrV?be3sKVreioMK+D!e|R`-QWrSON9Ii4IAAEpI|%m)^NOqhLJv1r@cAsev#J9||L zEceBnAiDU3Y?pYgf{DY`xO+XOZZVS!a)*ix&%9>LgGT-Hu5pDXlGNry zx!+u28;dQbdr+50txK$~SuJhQhW#0N?=H3#sl_&0uFb-`<9Pg!Qq7L>IqSSMu<$7< z+qm_-qQ+B1v9Q^FVI&KOQ!!WE(3NqyLFKIQ47?v%vsp_PoytA> z#>?1=`%)oULa#Gw@YWfgqY%L%Jk6;+48Q`c3EZv3#JHHJrS>8{*F-uW%*W)Ff_yJ5w;DdYpYWB zMa1U*nK&94-~Bfta1cM^Oa5GnD7zx>*n?eiBaM!e#m4gEhzyQacKJ;lKoZ%kNoICa z5;FfQS8S`AE=3lRpPPF$*q#eX4+RzR(BeSnR{!t4pDqZa|Hp93FJYdB<*85hvHCEj z%aMg1-6{N5mb!4s9KYwugkLyJ2`VoNd(%YMZ@t5m*Zr2atg8x3I^&~6br#oJ6UOpo zr{m+P6{8(2?)l1f3B|oC(IsCcT~M=4h{q}SRm zs#l1)-Gpo%jO4QVa$A-NG}WZ%<~d%5bG8IJZ08NMnq2VH%WV5_%i!F}4nsfgek)*` za*WYy(>LFvb6ut~kF_Z-@;!jj-&l_XfUw|e(WKq<`kEj}Q2Zyf8;LE+aMU58TPfmq z^Ot{SJ7^ahRe$oLL(8n&3dR!V6$ zJb!36_kFwqUO0no9>*dt3UeDH@ATjPL$A3Bm@cPeVX;OGOf`p@y;yK!bh-wnZF8iN z*s`Jz_BmdD$3)W6xY@=@(MSlHt4r>%w=vSeObM?vax4tg^!l-mP~H_%1QKo3`6PE% z(56C$;b>T+S)(VQ0|EcHI1z64=eL-NVy+?vTdVJcX%-+MWInRgOXBQFW5g7(*oBk? zfYj!yytWqTa12fVRz&r1UO`h7UF>u6+TFa=v`+wqP}BNc~flb)fbQ-&K;6 zYqcRkU=EM);%sN_ZMFMpsD!!y*V6HqLPOpqnG0iw#sG{3ddl&%2|3C2g6)dDa_}RU zhxo!2voX6?4V5XX+p~EJ7fHN>lA>FV+MZ>u+rov%^@fJh%BnOohOip$CrUX^0wu2R zGmFMyHxSW3=TIa27rR3l=pM&IdDn}*!p0T8MLoPw(=vwcM%d&c2A8ZnIdyjQhb$fc zG2<`}Wz7LS!v(96CX>~w2Muo!DpY$+3Hm;cHk5l+;Te2+@YSZIQZJHo2ftm28-f^MrU-xwSBdB*yjqi5(fin#L*O5rwrtcJkIw$TP3vDlVd?$~XzftZ;B)e@KVV@OiIsSwql#diY zpsd*O@}kZ%9|ox!n`}!(wf*V)ThH!OlU72+iFCk8pjPehnw?ex>DQw)a4ZbYnCd2s zDNri{&(93tpOA9UTt$%SvJ8`xo1%XT)G}yHZnPt#XsX)mF3R4|=?~<#rTmiK zGfhFSSGybWF&)ELD%%@9`+4bx-xJ8OTPOiNoWHL>I2}x6Tr%SU?ysd+qMjkz%I)hmj=JWS5sUka`bb+X(2u0{uv!%jZiLQDrZ zVKBT`a@61%KAK-~By~>r>k%29`{l`KY9Y0zpu0GRDIWUQouMc`VYfLF*Crv0?;_ys z6%#|HS_%{f(_y*5Z_t$K@jd-0SGO}LwcB@SXiPa-;Yn{XRlcBL{*L?v5qW`ByiOFo z>WEO{+BK-+SS-9U)fWfp<~S4S=4OJwjc7<&jBsf8Z{41zLTq6buc>;llHAT$MJWFt zl_$wNdLD^VLvlAc9T|skMzXYD*qVNvrrbw=x@Vu9R+JH!`J^0{8k;TVSpO5aCaq%2 z;9_e>S{jhj$F0k$n67QMU&mJO?*f;8u1dn=*Zvsf)j z5uX$<=^I2?rv%ya(5hp>>zTmo2H!GsEv4YFMJ~oYDLj5hR-d9Qe*i2kdGJarw&fT0 zN=_DnP>k68O2WnzT`q?0U?!x|z0o&yjb88U0k>#UlOJiK-5L4ks+Ya-7X5o+ESm#A zt}9GaEXe=j}(VVcXF_xvY>o#e_X@%3yNT!6VCx)v%TZ5OiC0Stmkw<>f zqGGEKQ!_!M(T&E??F%=3C-SoPv8Bby?yHqNISXC-=`Dux#FSJA{u>j(+ZD5nkLvpy zir-*z5p^>?_Bv7Py4>1?#^X(wPk;e|{zxy7(cIU8e%_2rFb_`SE2D=8E_o{fba*b3 zP83w(o+z-}N_)j6VOJL3{2ThQZeMpDBcR3IONF405jWbx%dG2UTQlzK0(@4+MvM4cdeK+DT4UO@#lu z&^~!r?Ob(9GwbqLS>hlu8t0u;&0nP|$?W76QjhE*76&$a-zF`1Yz+c$R@_9%Uq_u@ z?$%||GO@vdJxh?FQiUj}R}yJ82j2~t*sMDctfZu;06KnLp~?PD$3hSc+51e`#UicnS}Suc_1VV- zN{_r}-}wu%Ojw-4)tHtpfGKv7jL*G_L(2Tpc!JB2l`m9YmV$#L$s!$YrpVnj4b01n zU$(fGGTsN9#7ssNSx=Wq^`9Dt8nO=<2O2tTR&#&v%XnKf zni#Nf_?&r&qYL+`bNe(B7Vc zJV_dz|D~AQwD~8zu_4)o`I6v?-XTFsE!?q4&42B0+&*`yp_=@xrz#DJ!3(6_NddZ_Mz z4`hRr>`YI=-blI&&|%%`}c0zi=h1BZDL?szPnZCHo_{r_vT%>!u zaA=PiO}EWRpYhlLHa!_mC3$%xqOXCEWtEM!=a1@lu=qst@KgI=sQREf;}ZG3Pr>b; z<&N+H6NHq0`MAt zU?9LeTUdESXPN?X+wQrys_#jwej74thSYBSnA82mRF7ZvM%WWO5RP2Ru_no_8(mqJ z9VFgK@egzkQ7BvQ%XNP&`xn(5~2H&YVCmBht zR)l_dLplqHiJgd>{fo1`ZCqRl3kuH}q82I(DqbPdupTEDR59o%O=u-VNhJah>S&Ps z4nMOa=|ub!3-A}s1HDwmo_KzcI}x3EV!_d+#sN5IRg(X2#8kv)NZ&iw@$|u})Ovn$ z%HyH7D2JM|d|za20C8-9z&nT)YRmC`_suTwXNYZ*Htn1&*TrNOT@mBi6u2TO{l6|! zom84*UI$|#Cw2X)Nn5yb$CKm`4lE`kiV`iPXRIbQMAHBxJjP zh1e`7w+YAh#E^O32df9F73z<(4661tCcq?kEBQBu?6^lZ>P!QnT@SNpm z61ef>4<1Y84=cr*&+u*dPjH36Z$0%q^t2IRYDXv23_Vz4wKW5~6MD&NOId=6k|*(}L1GveM3g$-M-+eYp9wIc4lorQuESd`+JJdL7)kR^@d}%yO_&$$Mqy2YR3bi>Pw+lqpmS298j0N_(QO@sXC1g};f#b#B z&gx`dMXxTXFo_k)KZ`DjSe(U>wa}Qk?_C5lVJ-apDG~h>F-fi~B&stzsa5cpqF)Tm z?RVq*jitMNuhYe~uWn<1n7SMDG7ulGD8%b*ylGt}JXTorL{VI)oZI07c#>@9!t**Z zKwVFCru#U#`|lC~G0`}Iu7@^Gha14}ZHFadVS>taU2{4?Vbje1z29Pe+cPT&sy@Y_ zs}DcK93AJ#Ye%;a9-D)Ey2re)$2qsX(52i;cdbb3rz*V!ex3v5m&&Sc?qbc_~ zu*q}vMmRrV8`VE2;*m~oNXU7>PFRNzJykCtfTlN^^GEU zira?KxXSmC4~NuZs~9lY6)&yPv3T39-i?4X*O%YS2Pq6GoCdp&1-*=hScN%MsQBl* z##s2MG$-#YqQRR^yle{g6Z$0J_=BtS&8rm6ZZ|Fag^P|7`K74(EVJnG=(yu$uZczW ztvhoUxA&K)h=tf>1gdxEC&K~MogTY7X6EifXp*NkfrkL29vl`Nn`X4UYCI&wv2IHX ztIzgD=|2i{jQhUTY(<0)WHBe38btlpjKEm~)hAt;NzRd1K6VGJ);GsM(KQErHiZnp z`g5QGXDyMd+gOKX58y*$Gb_tHbf>}+Qi6VXF@o}Eh7tMD^WWuF3zL9y^Jwq@#CAz< zR^5*E1+8Z%(vVz;+PHh$c{8HXkYA$}LOVq9Pjnk_uw)S0%nQS{2)&Ky&&mhGDF}c z>M(VjUxe1^gvf>dT;vUU9n&OYdd(UVT9_y1twe5^_FX8kSO}A*LCU)3?htCK0jUa{>DLE)D7jXkQkfLy{;PHG@!IzG&$9r^XEhfB27UQe0mRBIVkH=aUrH$R39G> zlR$P^A2Rp5!C8owBUe(J%~%x++|s?L^ogOHmsYUTvYQS}nFOE%WLS)fT5 zjA~x>*^Wg;4%i`1ZLB#(-QiSLEiq?LDTw}pGQ!aL1qL&>3g(XoCrBZ=UpY5TqTvmt za?m0NuLX&te7?R%ttB^Z!eL>XL}?ccJk;c)oC|K+h+ZHjqEC!0Rxue!lTuwrdYQRb zD`!D2KfpVvVLTn^W?8(*>jJoY9)+uT;HGV$Msi2xI;6QMzBYI8wqkt{2w`$p$15~i z)_~h~x<{X$SU+;u!Nn274anS%3tJ3=~=S zyv%c<;UK0Z@(^6Oa^9Vd6R34F15ozsi~&=<%ZIv9YDimm>`EGM$X@raXbOI8X?IuY z%&Hh{oTFmp`!x?g+pa!<<-e%4iS&Z48!eJg`*Ra0~I^_7$!U zsFV?z>W77YfbhI@wcATIRk)GRVUo*N`aX`gv;xX6uK@X6nnrvhbEBSx6&xZ?^}UqvBcR2nx<__jfiujIuB~E0Q_MW z@1AZ+T+kr?w)O;%*3+hC(2(Niy>FDnh^H_Sb36t5+Sqjo#RRtD&|&T}ShtQS4sN>1 zW}1y1_jH||_%?t|^sV0{e)xQq)3{X~!tEpMhVHOiS3?}_7erazCvLZ@=IjD#9gqFk zgGKl9`2B0ED7T=84d6yE`-Dc3x%KYD-5mehB~TOPVb~me&^7dG&>D=dGBG1@4v%cN z0aP%!W#xMQsD5#&xb^{81*>K^)W6kD%YWd^#^99{<;`Z)FzrU`>A{fDIa@30IB3WF z=tR2wMT^YAC!Ko=FS_QzF3a7OXGVMea+Jz%a5;0X9^!5h0}Id)=9iHy5?k{#z~1fv z8*p*3t`@EQ6&GJU``gW(6+F87b&u!e15m>+z_wDO_BB!C@ikhbcEx)8vKH_Bt%(Om zAtkg~rTHY4FZIsfv;7BnRYmk*-k|RE2viSx`p*J zH3Z5MWS|lr7PWcUuLe$P~Cx;pbomMki7(7k%`Kfyp3 zc~!P_ADXJK%dZ(na0`7*rfc?OjeN8HhI+$D244@w)hm|9^*O==n(nXG%vqPfGstn~ zp>Ag5~{yd&)XOcx<+fRq^3%oz(VQB0E_guf`YtGb0?&D*Qs9vW+c#KtTIpqH1Qb znarb>3CEVMiP0qyr|xUT(I2O8*urjH!R^qmVC|7bX5|ej!Llm3o0%Guhvzw4g%_@9 z`IW)roFhi0o3*)U)+!$kKfDrvfzbV5XopeU{JLkEK9GLr+R4J~&{)m2G&j!C7l7isFDGI0EgqHgM*IHiZwBQH~hzup;*+&RmWT~ zB)ulHv76a_;^S~6W=1i4)zkRJ@(3=Ur_GY5I*@~@L+-f`Rzfz7x8_^yg2?xKam&JpgEU$OT{eL!)- z5oM5E_eihsO1~WUPGMSi!gj;JKXRs1y_0Y{JFWRP=v9KR>{rLO{hjp^K70mGSPAnu z%DmE9&;6T*}|fUb?aREn6YNpAfrt4yHrYCy|}fr`XxNY)Nr@(s+1 z|K=N$dAG!W*$>;?CRTLf&eujOy32$kn(@qhQMo2m!4fcbqH*~kz~v+p6?}huwi#hG zjYBA@fK&wwwEd;cmDN5=MBhI^aqrWPw|&a=QOD^^zo*rzWkkmX@k39o_$uqn#4rPq2n^jY z`l;p$OlSPK9&2QcdB=6d3C97BB;+(!6iMX;#K~KI5WE6C+)d{nK(^XC+zuLZ=3J+N zE^Fvg)J}VA3!2PurYwyhXru{J+yTwxqNr#Fd4gv3HFHlldv&aGL3>J>jXEP+PQ;H5 zR^K;@BM0u=cyp>`GSKXNkr~!NYZS{3O*+2PynlLWjL>>>lWr|v9!N?v?A7hlUb-;M zQ3rDlbg_T^H9i>dKnWPy$u<~cC_!p(DvPa5slgb}5HY%)^xNepTX!>9hb>^6K3cs+ zXv}V1$HsD!k%vx?`gk~#f$@#DSgy_Eu_ckcP=9n6|9poSOCgWFBsm#*k(yqXoUUJV zG{l4?px=Z|I{eD78m!(ao=%h9!$-VDe4f#hP@|Xdx+@nIy~tIr8FbeW0g(l*19a%3 zHI()Kd|%?6-5DPEG4mAMFWf3|3_Qx-cH#ZYiGk!T#oKZ})259A$D&hlO>S)XYQ5`Y z@@Y~M+BC?6fnyT7@E^rlj1+Bf5T~edCNTl6>%fwa;~1tG3y^ppM@-*tWms~!2b5c1 zTxDUcOG>o{qu+LHjUfWXuFWURmNRG~96n6B{6LnyLLW+Vgmq&aCiM*K>ArTm;+UI0 zBvknNJ86xHD~JAxf5yHeG#%}v1Zc5ymVH{}ag5U%Pg+l0W;6JU<#H}vi<>Q7#0RjlvHGX=ZC$AUI+c78qAP&fix=Hae{5U!2v!&?)y@`N^Y2Fm?GGXlA0N)NLl^- zS@Zh`99vw-G5=Vr)10O2SZesS`$_ToiioKmDLVL~0^0OMit?#AIKCCv+vU`QM{2Bg zX{^H%5@ARCsQ7SSA=);lus%j48QF-8(vP0U$<7FzVFT~uusGj2I_k$QB~zRr`($Bl zRg^a~QqR-ms1hMUzVTJLPQ<{O-Yh&kH)k&;OHSmG5z)utTf&&p9fK21ujnVUCO>HuYHG@Z=@P}JR1;P#}~Tj!K(t3Eo%Vu}?jx$m>uMb18#nhhO5I@px9 z-+b2KE(Z4nC(fxBSBEvKk3+wZfxbX-X~aS0>{CFmr%bq;E<=#V2(VqAw3H@Jhj3^cesl9>#kuy`1IMixntpD39Uj`3urn?i?t4&Ol*F zWacyEB));?m3aAzHV2%eYCZ?drAYOB2OYS?D)Oh6a2Wt2EompEWUlCSv1hm>+6~ku z(b9Uy-n}F|N!p96d7kIGzhniE!&V9A-Tl7ME~ok@`}+FRfrE?Y>7`afUR3r96t$Bt zxs3s6>IWN_@rSz|J0qfg^;hkxk+WWC8(i95_r}&!|ohclEFU9d=)DP&8li10{P@Y zg6Llp(!oT5#Q}Tl4NSl12>Vv>cg2bmbZQy;xFO9Ucg!%E?X&@&J1jwuZ<{|JR0*ac z^NClaGx>tEN|^^RV9}lOCb(r$8m3m(W9c@F&r z)GM+j$#fr$fpSkj`YyS}Vx|~}WcE=iz59jz%e08XYg|7&8I zX=;Pxnme20yVQKg&Y^u(;o~9iyi3p&$b|jwL8|3Idfj=z=c-;kUy@;6me&NQ$XRxgqqP1LE_NbDpPWBHJe*Z z!hOl*%roq@!3)qD?Xi&RGyHC(nEQ@xaEuCyq60?p6;JSfwL1sPrtB0l->l=loUM0f zFRyPg0rbXKfMArMpGA+loI)^DN^k*?v8dwG9EOf1#1J;J%uE#2POU+*7%>@^ON&*P-*}x*ex&=1T*L~>!t~yceSVak2t>@e$Cjq`+cAH6j67?1 z5fewCy9F^AZwH#1CS+Ctij??E5`aEssrLNWdh3VRlh~nT*2{9MkA9uw*kOcyDT%RN z%y9ZycQ`RW#_?pVSaFbkQ?rP*h%DwU7oWj^+P!#}SZLtBt=!E_p67P3q;kKBVUefT z(4x0IPN}c{waMlO@dJ-3Kbe2uY0BDmk~v_tZ#EYui@LeThT`i4QLMXzKKj-TW@OqCKC6z9LDJNbC{VErDF5kLi)2H|D5#--ZsvaKy=EEUi zHA52Ouc5*6G+|=*S9P3V!sc21ZUVi{^B=y|2X2xVgKIkUB7Z$Ujd2o zud6%1?!0!~mI!Gth+4F!D?U(nOHq{0_ohB8p$M!iP%Dd5J0b>m=eo^7SXlFMcC1c8eF|j8 zs~u0mn3^vJfnS~S?o5VTB7_g|ysqtR9xryjo?bmnm9|=h7VknUnH#u@vGh?ehf?r?Re?## zI)8{+G@QIQPsQOnt#T>>wwUM6Z4(qI9t1q_l}cY5yeT}5C{W&Jcilx0fe$WL{s?$% zWRY8Lsl3G#JsZ3Uy*XXSVaaUlo+Mbc0FoJd9plcwS9BydxPotak=H^lKrx`ACBX|#}#ycLMP;s z3$E;`I=^cE(8Y_l@GB%AKr=tdLZnZWx|Y*gvTBur#p%y7zOxyvsn%kgiMYd9fuYOk8^=lfZE4YXWsG~aPrPA=klWJB+P^LiQ zCDk}rapu}PlJ0f7T2ru$bzHzJLloE1P84)+8t`?OUSmKyUYqis zi~Z1hsxD)$Om_b!rNHkZjXq;)X(h`RKjT^WR(+Q*YNda17{4b~(pKMeQLZYO#|4yj z9K9~ep3Qz^@+<6mSq`@!7kr+7#`1sW+YG)tn=_gjIPKROm5<;h=Pr*ILAIzD76(T;x! z%szU4yU+kpb-lIA58NGAN@g$MA1EC4mHbT5QQV7MxXrtTPnx0iS+fAZ5>7IWf4mXx)emcX1=-=CRl~j+Q?JK z(^%D1gEcvUF!Qgs;k?(GU6b}NTQ_N;oFzP&>a88pp&?b?mBmkLO$OTi7V5=DRmfeV zXEiqZCNuVjCmVc)#x0bY&n5aqOvfQ?xn9%SEfs4nuw;A~Y8S7;4eq7I7E^PTJ~Ubl z6pvMJfxZ`SV7}L)?D3J~Q&rxz9A_C#{f1KI7Ee&qQlE?9K^NHE^L!lL(UVF7+{xu=2%3IPvK!3X5)=NTNs`g@jJ-|G% ztUb3V>RZ0H7Vn+F>t-ZP2W!_ra$nWG&%L!LBUgE)*94t`pB#{ASgN7a`LsAng13Hl zr7UO89J0dn_^>rQ(8Z6St&*Ls6e0e?ctca6!hPqN4FUo(VH9@{A%2CwP|w3xIB}T; zlMbL-^Au4EnsI#1@b1dRZ%dhuuS(H)MCZ)~Z9g=w(B-it6If%LLM@VFYonB8gkStH@ zv04Eo0kC()RA}l_mTUL@&!DFbu%-f$pL7+)N$JG6mC>b!X>d<%=7&wjVq8%>y;*R;vGrMCpi0RpaP*2NS{SLzfn#Hz_WW#{K9%C^=5ZNdyb zue`T1UZ58PKxI|uVsY0Eoi=M4Xw%+T^;ub|ze?|Hlu=>+ZmE|R;G_?D&SN@p4yM{O zW4|Dr7HCVKt*&qOzt>Z2od5j<4uDThk~I&8aV>DM+HTHz7)f>!iNkc|5b#jS(Nr>- zXc=7UIJ&|poNm%{at7Pz3Ki_jW3I>A)PyN_kn!P0W z5eCk~pow-4+mfTqld8RBlrl+SL2i;j3AQ0 zDA(`=>f{}tz{yC6OXSMbEOpIIsQ_k=4%#r?1T5*RCOU$hH`WBg@EhFZW%ld!o}Jd8 zf8ZI9w;rssdD`CbypDJAl^q~T$F`cC9AI1@u-B<$=<`f~1SR9+{vUg99n@y?{*6)> zpwuW1r4)B}XiI_O7TiklK%hvFAgKW@6e#XcoDif)a7bHRg9V2ahu|6@5Z=(|`+Mie z{LXvk%$$GDd1f-1J9l=kz4o)0?!CKr{pN8ik>lyQtuQ8ZP<{rwA`+Q1N~<16)vhmW zmgK}R5a|tT%;s8K%)pkO*QjYQ6&G+!&sA`$(*V&kk<+D<93GnP~UeV z>`XIjF76=;c7PTu07IkB4PK#da?buVB_-R!JKHAlf*;-t1)B(F1fL)cq-sy4yUC>D@*mm<54q(e$h&p{vBOO`3fQ!fEPEO=XV%DjO~<8ONYW^v$~*+Q%_+P4EOLTNbWydpZf%}L zRaqgl=(x#>^<)dZ+;l`CGHAn1@2KZd#F6c#iIVYF9n#ZF-mQ}QN>YA8oOyzV)AgJ~dN9{kKa zkCWwo!Xv}@X3)r=0LQp|+RClns>-bLEYQS&zd^fJ1a`PHEZM{}E^Kr7N}_y2l`B`@+~VO|Du`6J5hv)Zl??{LcL>K1i?HqmyLha9CKPUBV%E(*LP_HS*^tz&my`7@LSa9 z{hBt?&7LPBnuZ3fzLVR5GY#I@oX#{T<-##!puG^5YaWD2WR9P-A37tkf4%2g<7tqY@pPRx z3*YL7Hh`pl?xm0-zG{QP_3=<$ifK3@J@H8#-B`OJqmz2I+7M~7-=b}!OvV7fDMNSO z_ke6m7Zq?rgt~Dzc5y8LbN2O)s5Ee^Y3^WTx=DrAKweCwU>K4Sv{r)TLnKx`RN+Ry zy@FQ?VX;ozGECFB6~vF+0@NR#&$S~^5}CP98z_WgoE>HuN9fMEf5VFdJ>8(e_xuvc zlqO%ee74#=${Fi7H3q6^h+E610^srh9;gBn>C8eu-ID6ZmMN6yVBbIsu&YUlI5)~N zb}L~K&Swec#UytR7l%4E3)sYV+hQ!&yk4XfKEa&B2xrR#d5uHaqUQ7U(S6u{absH# z{E>dTJdD)!)aV?`&T^7(DUoyIu&U%d=qJNPNbTKpDh|QY7}huK)}Q>wPW}Wfh)xv( zk2!f$33&vRJw(L)kIUI8)2ih;Y1uWiII0S+cz9t=^iYv1BR-x$aI!=vWPDytAZ#a~CmN$j z@g&YK9ZyBmj#4ma*E2^I+*u62<7*r1q3u}%({!@k)$=vW6@KJ_o~$URO4Y(-73 zVSh(UK1a4igoMOs7Eg(u3M(AJXd?nOn=H*Gg&N{2f_-)Y0ECwr`oz)LE{qCGND3i5*x8v*uDZ9hMn`MVUl(AMC-*U>42y171h zrmH!W&yM)<2R{4L0<6rsb{%=6w)N|yc1-`ko-Po@c#vlr+c5L#`q-1Eoaj7^k9l^? zUNW~@xBOdLv~YRC#&wdPVr6m41p(*L@P>x(_u5l4(v)%2x%z(H?FlE3iVg+%$t53Ytolc3LRkBSZRG(b96mbgmoMU084J-biz-sS*t8tg6Eta6cd(2t`7&&1jcg z^@6$6lMkj{%Yor8RTuMOZ>fArBNSfq;!rba{j9v$D@kcRuR-WJ`9+1T=fPH73oQu0 zqYB!IV@K9E^^1T9(Kmc=1p(-ib8rN9`u}uL9g|pEFXQzNmfgflu z2+UZk59#oX#UNE}CEevtBIK2NKK&*_J zMa9V-e75zZJaN#{S2f1LWh1MoVD)Sr=6W4sMp{z+J=yO$`a}{v&3Vk#jaxI312)FF zfw~0flR`Voyt!;Bh!ES-l28@OBP*+0X}&{xHRT|4`BxJhWJ zt7im=OqBmhZ0a$K&~J{K4Y8$llN|Zkbymm@fLjtH9;^X zUc6ebmwG#iW82}J51$<(AW=358ab~( zJC0LCREIZ+9*_0Dq1G8U092uwQT(vY2>50MY_qrPpnUg?)i==im;Fu4B}mWc$ie=|3dfM0iD8r2b0XI1a8VMgiKDHu)=~E?+KAy_p~r` z_o&N>`w>~n=tnmj3O9YxSbJjHwU&O{r6b<9ia4U23+vO-oo!;F-!G0(dnf&pBUamV zO>R11n+cY`765cuiFI^QJS6GAfP;6!|%Z}pj6nRtLt2u6v&m&9}nPIOQC5Y@*(Tmx1R9 z)6UMH#oIdJ8PK9Ov^q%!s9jL$=?CmgrA+CC29(tqu+dGr%r}YsBN8rp!B!n^v?BfI zIvbe1YhZ8LALJ3Lu3sHnD9h(2f)kWnssG`(nzP-p-<$bxf}U;1!yWr%fs^WJj!wRHBu84?^4Ps~|>Oj{i`1_6WA>a(e@Gnl5d|omw9p$`rjV zaJ!(c{10_8s$1gld_1$P59a*4jk{3IT>ekBe+&EvsGl>~OJ+;>rb2X~KL&%%{EK51bF;w1 z+d($eZ3YyIgJPsu)!Zkjy($RD#lP=B9U>Z%5fz{h$$CwH$KZd0`3~gKg#$*+b1+7_ z9tiv;Wm=%kQD6WE9SDq6f<8`&XaqIS7BgOGEXiw9%COdA#^0iD|F~L`OLzYoe3GmG zm{*d!B>#x^Gm?LV<)VQ2^IYBWs-c=vBG0P1(PpF5*i7foYjs?4s=EPDct|-j!bBrZ z)fOId!P=ikj|*Hs1O;7N+&eC2YzwX_fv>JQ#&s_iGj;_N15FJrEsPkHq+@x{#K>q2 zYjwd^&9(odtXyC;b-RMpH%&&ocs{?KRRteXkMOe(nJ~R?DpM}4TxJAlv`7F=hPJ*j zl}#1p<>lo}=!OBf8t2{G-G;};3fkI~lGvcumx<(m2yT7(o^HyqGM=4(aIn?Dp>lG{ zeg}@IegD1bmOsX@(PDIJDm6Yn{$W^atY-eAL4~MV7GA(QRdy3NC4j-jp_WBOMRS9Kg5X)>VDm+HNg|-!8K`dD880p81wrR@ zY3!3xbr+RIEL!>Hvd}e3HFPz>oJU_Yfz!cV%p2{&!fe`^7p%dMU+Mo;Jf^c_ufh93 zikzIh+TUQ~Odjhxs#Va@1l- z4Q1toGe%pv8IcmT-(bPtib82KhjC9BNNQSUCIm*cZJ9PRgrYV!B4w{B5l+IU^&%)|fb`J>M@Ptv?a&%GVBJQ0e_1 z{ArC?H`E>gUh8^>4;PM+5|*m4`y=b=upNK(V50*UpwC4q8Ie6QV!(R;77=sG+ds57`xXMYh@&67?Ax`x zS7-n?ltmE-WzUy5DBZ-9WU_ULHG*Dbno3z*Kv$h0%~gP-@a`N%KX^?U&y}2RI^3de z5Ir0RG*C9po+FF>D6;S97X4s!SZ$Vwwv zrrpsVF&fo&ANYqv&=V7dCL7ZX_t;NMdWnYO1#?id6)z7@fe}xMZzFCodjk#BpM7f- zG2cubDK)^AS#wVxa*p7CY%_t=!_`KGh$@ULmv3F*qiJ=bgPZk5n;0QJ+svPKJku zJkaMvB>|NxSMjJ3dlTJq)#ie`%aiG?9x>xpxiuh8MpD<6p%SH7^P_wS+PwbU;XCz6sc-Hcc?)j^KRzV3${!j$8;9x!d{ukJ)@3nuWqF&3buOt z=|pwF0Wjd;`H#;bV(J_)^0yan>Hgbzq-rC_hUlr1)b0LLYwQKW1OyLxt1&57AdB*I z0(xFFNK%yoq8rY0>~c%}pI(zF7QX4#=w_p#Dso`ETdX=;HH7-2>^t7rPMfNY@osh1 zzYg|)>o+g{C;7i}tp64uBJh7F0{IuHe}Vc}v;NPK`M-Mc{~f&;GnFOA1}w+v{-t@k zoe2zXHj^XL=O0!__2D&z_~29rhZrOce)p`7OHGt!_J{Liw5{3JaXL1x+{{>L{l|+D zlhS3F0as@QOF78&FphMYSP`IKT)S%!kZWZkl=dSl9u91c;W72$ZU^7(ltjwbC*XS}_*0Kge>MRt?>>}`ASoPFtP2R9YMp+Wf8i%v!`{n0zQaX%H* z`BRqcd`rJO)v#5_8c>?6&vEs1@1#3l2>~eKmw%+nHQ|;JNQhyTV{c z2e=3Np2><7!Nmq3RStB$4TrMkp5O9dp#NG6pjYlygs=oX^VN-EN3E?=71pg8G8tsZ z7YbLedw2$j2aM0%6P?=ExlH16F^wb^#EvO01aQDja3xZ=IZ8`_wMDvuMJIL?xn{9> z{Dr9kA~C!$PE#E%5&ty)Z9wTmeFJ?f9Ie)lxxU)9I5-$>z@KVph@jW4aeIXed|j$L zXsWE;s||?CV++b=4sR&sYJCF)=x-j3pvCl(B#Xn?wXnG!gMG@3dR*%qT(H<*Z6&7hjnwu5!SzqNnWiLQth!IkKW||HN0L zcNvlMV_iGt`WAz>(^ym6y@6!aFybS@G((>PwYI6~!X!og!41QfnJhd0ua2j`zm^Ac zDrOhjsTGP^63+FvoF;cQV7lPa2Oi8pbjibwP6;OnY)JT)>Z0W0QkamLUeu@BHqLJ1 zn-cbR?=PM5uix1(H0FNr?xDS?ylly+as{{LP!RxH4LO-a*DNKD7()?7 z<)oxieq{xpA5|K;0Q9!7qo%{BEuY%jLUmEZj78=4~Fetfdc7X$Jc%X#KOKv>`LudE>S~Bb@!vmpM>f|QZ9M<;(<}+xTu9DL}YbAX8h>F zmw7HW9LKnq@0rGG%g)y~XVU0&pg~23A**mn_JeyHj4Rqsd!kwzmq@O@B&u-y9xEl{ zEule4Io~s|Q-3T5SgU3N{HmJyMdo^4ZID?@>>dpQ`J;SddIF_7wIy1XI(N)DkXtPB)%9@@>H4`p<>ur z`X<8vxG>&Kv5~~k_oM_sKa^x>mrHoASSJ;0b`T5k)fw-!hMcv;az${CiZ1pn>#HJG znyM0i8z>&Hx|u`vD*J5KLRAWv+2h>I(X3slO-m1+M`x`VZ*eeuUz4}ftur; zdXSxCPDEwM0$1+Ll0j~Xf7EWJ-BOr|wkm#;$w1l2-GIOy>!7ndbHfw&TexdHZ|aTa z_$u786yaP@H&fpGb#<__LJI7t5^w#=#iGlnYxG4ZMM7K}3U0<*2N~Px=RzlRU`1=kDRS0ITLfKY>|yHVN!7Co^9;@W<2O|<~Ae)gRtP2FHRbG0NH3s z{mQ0X*aI8@>xUcDYR1M%dH|NCO+@ax7!V)xQbRT5{SKoidhDjrV?|0(9X0FH)s@x2 z+=-YAOK_QJ+^SN!9d%t9`BhiXAnST~v>rE?_xdEnJkRPyQYAl!u`3+oEH3Kj7@Z0J0EQl_y55KaGoQkIsH4y{{LJ}Y+JSt!f zCa8i3B48hj^bw_hfU0a0G{mdv$1V6(lT|UuzFY`MtWPiM^ zxa{dDlE12M5*avqHsPq68zVoAVtWK8m??Q9ikd!yix)dMp|hVEp(i!8^8VFxoGOUu zuWvLD36`TQ(hsm^0r%FXips%yK{l$gw~D2JPThC%EAh?9np0G+jybjI86+B>HY+cG-Kpd%tI5Y%xsj|;PE__2=vd7O<(7i9?)v~`WtdTls9ry`(}s> zeU2wPj6HOVTTRrxfTeQBWABpP+xI`ZMmoBPi7J7 zCrB@OBeJlu)i5y7ptSMPh&ggcg1t#R^~8kIB$j_Z?zn3fV2^NQX5-0c&}4rVV!#5*NAYJna5J` zwcd!PJmmRMf~|_s(_>J*XwB9)IgbKx+QB#Upsvz@ zLKh3(8Y7ZRoi%rpbB_KrLuxE{!x4d%#Rz)v`1CXug)Dhtmrx!aJ^Z+Pb2Ng{l)TJ| zjQ@U=bt^h2e9F)LU=3t5u1i}}t=QeQX+HcRFK?6-doT<>Aea$VCYG=&NGU|q`;ZpRt)`0%zHWH<5u#%! zlWD_OYJ$iMbygAewa^?-Ej0mz=Hncpcs}yu2-@GH1oUchx0oJ4**^{BsjrRVsCZpy zHkDbgl)NC37mEd``8-cb;tZ$qa>}XK>WgaVN-7f4ftgi;|2#v^a8Oo$O9F73^taSx zZsNo_AAv_`g-HIG6K7vucN<3!PIzEaXCy=m6VAIi8?lMIXEoP1>$N^g>#B}78b$OiR2C zN(1-cQft)F1K%TN8)+xRix}Vv(B8$jHc}eEFMjU4TItA!(_rWEDrW2AX81tj6B9rU zU@$tTrn0X%+yFVF6yK|>Fs2(|WoE4m%}QV=*Pkxm-HUj`D=q4Y_PaVRp3{p_(rwm9 z+O|-JiE<1(@Sh9*ChIJdr2%V|cn#2!&=G2L5Xs5$IdjS6)juskEhS1}FpQ z{BqLfu;JUXH!v%6F#6)42u>1;;RSMNyiyxV=9WrMchFtC5d(zSK3}}%m^H19Pu%* zMa7lt)p=T}6AiE)vUu^X13(C!>EPsVnR8rfk*mO#vROC>3Hz-$e>g>**m zt9ZC!hv}N4!F*a{Hr?*`u@RD?)Dc-Q#)B^1PP3#MCpUxfq+5+Nj=K1c#YJ;B;^66* zs?nuaNiiA@XC%a=jRI6?KfgLOb)D;Kbk8bqO1G+?DKA#PFD{j>n5_n4h_+0Rvn;T* zXIrD25`PLJh?%T8VRswieB$|GMegJJy+|75H|prd5uys3;ub+Zha2CXe2J~YZRqte z88$5yTJ*pwMRE-z!eJXTmB|Vtv@w;$aB>Zlomy_#lxo{4VyJa}nHL$t-T5O&JAdMS zzKA6!@J*B6xKZR`PBMBvH6|sgKX$rkwT+MArfH}%KBfN3&y6qNufOYk9b_w7$r0zH zSi7F(URzi<@uJROL@=YX@Tr2PT1B$Ip`DxNyriBc-i3iNqN^k!msGyr(9)#8#~I#r z#t=&F);h1#dIRV58h2;oEwGTPg0@!*sL>W{M7e&jUKtt)h^&q)hC#qhgG|2?O5MTUl5qR+YH~doy`eA*+D_fI%O-;BhG$ol{ ztttm1Svs}g)_5`~D0!p)A=U)`TI`22p`kBT7ABk>JRwh@kxh*L9W*bcD_>fXlw62L zLpy%hPW@@x*#y0oEaB5sv89Z^ty{%|kkkbkj4P_4jf{8&^@5iFrEcAdjn5drk>=%?z!7rak8{3xJZ!~ zYb0DyTHzc;?#u$!*A7XcjMOS%uE+^e*OyMFhb8N00*11f^zA!htttyxczYvJjz#^C z^Zm3tePSS!C`V6-$pf$+nz#VIvbeXNUy7umeFvvXGWPJEv6o4Jg05GfS&VfI@yS!y zGF2Q(Yjyw2o(YF6Dv=lzcLqO)<*uzHaha1^-jnk6I|t;p zBI3fZGSa;+RJhY-@ACde{>*UgF>A40UX6q-yW$fd%~a+m;=%51HeqvL*fb&{U}hl0 z!g{XJw2`18;jZQKE=wQ1<>kHPVhf81BE7{*0cqIIfbZh6eXJ~0H{TshDYm$T3=b83 zI*b-Cu5eWc+Hqx{F3_a;ot@in^?h8gp=j=d)?)&C8fpcpr>M3R8Xk8(v>g{>FlL>M zVpZmzj02~(z%PM{XjA)YHmH%!ZX_<;H|!9T z&~(hf&r|%v2(AN18_9TmqGAk4yaJ<3G7=P^^ic7Mhc-u+tp3C~vngOUN~kpj{B z{p%XnKc2vx+CGZF1fF2QtCcTam0IuFuG5ubSQ{euWZXfBuG25p!y^W;G?^a%fUoL~ zA68d+X18z7A4?TuX}i@#3%m7~B2hYYsZENe)c1ogS@mb@xekPDG8B+!>E);3<{U>r z>-}443x5c{K(s#aMr3&`9kZ-t+i)!(R?hV7DSHMqmH)JLh~C1)Dwo*Xl|hD23#7(< z6+dx7n8}t!;`=79WziXHatG%vbX$uN*PgS?(L)p;Xz_#& z(^}OSxx4Qjn4#q_s~}UEz9ZM*zYOy%`Pt?t|LnlY(jH@oY^~0|Z{-#XyKjT}-fYqO zMWt$eruP>H`mR(KolUb$ZGlXa4qSM|=1wD|S6ya(!fc}DABXavqx<#f3;hzTn&9-VWg0(%Zw!erK{oZhvXlyicL(jKnF|67q`GqdxSoxzwHs zHkIR0z9+Mnjt8uQ#Xz>Q2tCr&MP-hN_@q9$HgS3Kjf}eYa}Mg*WBVg4l;I}|)4epg z`T8W2-DeJ-k6RXoM$U2dhBcN&fz(}A%JBWmM_u_$+0r*(Yg@h9J2>son)wZ2?)3XO z+!_eY9^K?;ne_URIXc(BOn9dyAD<;J(Jp7frPmQzUZQQ&op&1sc$I0!W;ymu5RuMH zH!BkstrlJK?)$V$`_3`{2Yl0)tj~}}&4+1HFz$qIK`96)Y4)o@L~*14*Eqy=gz%l` zxgmMfbTn^rzDc1_#J!PaNrJ)M$3yu}=}ndgWr`!T40WHb!em(1M)f-LJJR*PA&zac zoP(!2`i-BXbInWj(ww4=k?EQKJ+DDYSob&+`FGA=E`tVJZ`aPcwe99>>1AYOn>Y=G z4qaW9VWqv=yhdD3LY77|az=|@eAH`^+!ZVsnu>U9NdMe5?zookVHjEDQb(mzs>DEc zjmsx@Nv(LfkAWXsn@L5k-wV*SxvlWEC?zZUy}&yc&=&;ues^&~M$OOuqnp|D_DGDO z#Zl3*+Jih*b(f^?v6@kgl@23V9zMmd&Pm@BHPg=ZmIG4)t&>nlIHl2mcUiep#mMVHE)cJ&R?sd(+IJm|SEw z*R*psp=9sG&y-DcwCni}2$N^=nJ`YJ;LwM;aK-H2)p9yV(k`BMde^7 z<07AgoeHGF$k;e@ND^#iKz*@5==U}@!J%%G`+i5uRec^2-yj}2w9YhE^ewM@ZG$ub^Nyg=dF(>e~DZr z177?UeP5t}_2NSHPqOi%X>_bvqv-ch@AsY6AKaN0*#b6-EVxvn`%vHGbE@BI1=vQ| z-w`W06!5%uI-QX`I|9o6%cJKlA~gtULG|^bVZ5Oqb=~DUDv6=jUS9Dx7=8ZWC1}kZ zaTut4iWul`XU&<3PO&kl=j*c1Xfex0dG+=LDgV7BtRl3;0PgnZ=cUa?oW<_(DbC8K zPIqEMj6!z*?v_uxbjhLiQx(Gt-|EUNJTED?n-0GEe)Lb1af@4zHGY(jv*6P1vCLM$ zmLGA2t?PD&Cu?y@Nx40Wcx)e;${?kkw%VYnHZ|lyhh@aF$k$4CXOM@$(E6i_MQkP-wFtQ0UOzy~qbRa+N`%5UEA;Sq=v+D*Nn*LE8wO-fr#jDK)csr`H&@tq;HO?}Xo= z&|xBQ;CfQI3*hU}KYB9vn^KYnDn8Unc1N{0{boN$Q+?T-RAkLy_C7IPeG|lMD)+NK zFWxv=wlA|*uu9o{4$H`RG#vQb8yTXLy_$Nx*VceybGD2>@IAkr$Jco{gX+)6cZ^qM zwfOh$)oo4pGNdTi_KyUZ1M$9dYLVN2GHHV4>r!a`_dM&VPdN^p9D08)<$jx$l2zj! z@k_(>RpYL30A%CQ!6Gf_v8JIh$cv@{>kFxL0@ETMr9J+zPaE!%vC^<8*4aN6a+H#B z3Z4-b{yjX7VRW`$3zn|2|CaU4KLYya&385HTBVBVT;)&!{qI6LYzeou%&$-$P;QV5Tqc08n^<&Mr(+k4?bOYs?^QP>Tx(^0>gQ|^0P zAv?Ch+yoA$4VUWmN{g!%HF;nw1iLhyfFr;B7}al-^g_-fUEZvT0w4TTW%(k0jU z&z^)o@Zaj$w)fqZ5B#7-=wsSTNV+_AG~bX7j)i&uYlaw?U9uh!a58+Qymln+R( zx7@p8{zs6oZ7AQyB(r^0tKxkWSiV*Me6VzT6Wpv$!h`IX6PN4LI-TbiGz49$c56Rl znjMut4x1t`r9bv}N?cs|wS2V8M7~3c#B(>CZ)!M8ouxVZeyxWt%I}EB6YlxhGc7qq zy3T(*=HG=QW!2mcxEnnEQ-^u~($U#$8cVH;(4EFBpJFj5S0i~wjIN1Ixyj2PtewBN zti=lwj>MsnD56aJIR6M@56o&uo)DR9Uc0l?(v81V9l)W$@n9%0ByS2slyUcZ$iLm!>IpI(I(|OuT$C8l( zK8gX!_G-UyS`=Zn-N*eDGd7J?xjqdL}dsFpO8-_)By2xB)sS3~}iPvjID znM7potB zVPx|vy907FAbS^LXA-^th-g=%`P96@QMt>E^DT!s0m-s7(=gO_e4MKIVh3Kgy(-YL{-O9i~d3MVi0WROa~V zYTfQPgED72RdGq?6OtP1$v$PJIG+iOua|G`t=@RERz+#|k!G_FN+sO0yI9(zt1;cy z%XCZ=xOTjY^$QUKWR73Ix1b*({>>4c=U!sgQ6o=ynLjPx64P zc6ze!ovm>AQ5^WX@7&Y$cVK8<{YWoQ|D(a5Wvkw4f7o$Q*mb^*&TCsi4OKyn`(B%{ zjMIt^#Cy5aTHU1nS>?T_AnreRc@*wNv#+^3IHXm6y8Bx%Mzl@IYlyCeipKk6;MUz6 z>3zDGoy#cscs6R2+%kIYz+IJy^wWEqp7}KC)K;TuvKFUZS8{NaG~HCx$u$uan2PW@ z(=~tB4!h2WYF`)j9$tQBzJH14kC<3Vses`11hM?d+T*(Fy$9!e8$8IP$9_!C6@xNF zDc2mF9ggcR6(g~jTX}yeY=?ff3AsSZ?)OaneEdogXsq>@SWm-}6rKpmyRvmf_E*vS zS317OKQ*r_=o*}}YC8LKX-V_cDG*0`>C)W;HjX=SV|sYEJSqJVT5!B31G`M|3*Um4 z6$u`tdpvy=QyZ!GP@Jzn4D8S^&Kz5uJ|WdAws79Q@<)OKdSbbk58d5e?WO6!bW~|( zcv%OhxI)>H+gg!3aOhgbc5N#y{7g^`b0#Nu$`AdB^!0eJ%I34iqb?@%`)y`R$wz*- z2I1FFf@cjIYcFjexXjCQvi4*_jQ@7S zN7Fy!rO@#6tsT^^U#UNced`u9wvDU7t8<6gX%b>I^^bW{tA-@D28sEx6PTIKp>iF4 z15XrR?~Ef~qwEQs_$E9>tv&9cb=QJKm$WJi zf>Wh>k3yvpHE0YWE%NOscbMt5XUTJ~g5EIR6ccjC^Y2MR4?Xe?aspTRk0!)3{$!jU zX1v901%5Ma(`v+2f9krKYu3>-b7S1&Xn9P+%o+#BfUe}*}gO}~lh+mH1BMv=Ow z!Y7tr(Qt&8U&0ac&((3G1WUpIN~1hRR^}wgb*KK^zU8>|6_j0mryJQKe}cx>Zp4-5 zcE)wZb}a|=uf4tX*S-BodrS;ii@f$(X%Va==RKD5BgKRP@GYxF-Bc=l+}`|Xf9f7u8$`UbLstnrb|nQznS zup46vltsycIi)^b8nY)60$1ZHA{W%dM#~>b5@wOmZy^-CLz2fgBmD_6r#R#R?^0;? z*Pb2$VSOtJ3IzIkql8pDXP4`nS)~!z@y@}YxK|B?ZhF^Q!;vUm!bmLVX!AYyP+PJ^b_PD=sc~&2=;tORX zBAqj%@iXA++A@_q7eDD3=r-k@nKM%LDR=hj%4MI~Ncpxc8340rLHT(QrO@%^e7Wwl zKY2Jz`+%!|g6#RC_;ENtWoAW(8n?!vDduz8a!0(~*jd=t0t^)x&M#jPlCR|FNkwHe zb1KHgT|dXtyf`12lGJo`RNit8c+a@$Jo zD5+8Ar2YJT{<#cFqJImVG>x%aiJ;gi@t*E1iQ1GjXm9!?sZna}-t6Ut*&~Z2{5t=o zHcqy<{|;^4PGgRfX8?sl#} zclFq6&Y0tllD>q0Q6Q*wvmc!9EyonJr=%lTJ`@7Fc-dON+jRx>|#n?l~> zD`MsyLp?OPp5o_ejHNwF&+#=W?%dnk9Rs4Xtbc>USz~;ftKL0b?d5Z*o^+!}=4!r) z$zhT}9wZqvLNoiON6Gir06 z<-GLY<*<(f5H}vH)a}kmG)*WFlWIt}Z~^NoZ;tq9qmqM*v^5D^{EPM6`JrM_adG4O z>;XC}5Ged26BHn(m5G1TO8g!1qZ{Wt7sdnXc_DzINzEFQxV>L5Z( zOj(I6_go~!-z?-0ZyuPAW^#fbIC$HeVU-#Tqx{nh;&4TGD{pWV&rwA1_a z{B2S;6#n^3w%oLfI#&#vdQfKx`R5z^_d(tEg7Fw0H793hw!R_d!n1huDM%PJX6;Hkg) z1FxV%ZX(*Nv~IoE!1V2(tP)pZHvn9UcdwFN|ET8o%s%{ZDv)ui`dK|y8syCLi>tOu!&`QiMs}ITuZiz>6r#CG6@eW+ zs}ppa`qNUO<#u%R1P%D|d+cfIO4-h4ntJ5nDr1HkKAt)d^*lJ?v^J;p+l3yas5|oq*Bw&X!wnO6PsMxXvXQTKHfFz-bE|6JOSOO zOoomJex4HnCvH89=Gt$+2q}H^qH;6$j+Q!FAwLF*{s|iewat;;gccSFX#|~5Ul$#Z6cTiDx zQ&8`ZBuWb?7t4QFPXDbP1mlf~efNzGz6Zv_d36=c4GikYt~;t)KlrK_yQJp`J-jP!AQ9;Be&l=mRMZ2T z4`OLAIwszP@PLyWFXw)7Yir-LndI*2;~UykCVQuD^*Iy9Tg3gG3p?l{=CChh({|gY zo;%g(Gxa|0RgnTQP4Zlk+N3hocxQaks78LrSKH3vM-mc-`Qo4dh;+SH$kFtDBNxD0-r_0ksjbq98vUkiP_1hlF7>2zmI zDd1$|5d!!U;{RD4kXtt>yL?#iHBupcBv<}}lu%Vseq(2ScsRt!0rqTeIs z?g76k7u=@}tGrDkW*ZuN!jOy*JM(!4AIZ|cG6A}?UaHI3_e`6akCLNuVmN|vcFZh< z;$D{Tm=N8#-YXvH5-U9$|LH8sfBfN9-g6os-Z@?;fW;`E0lv>*1VKq}`co z39gin;BPoz%-ge(4oj72=m1t|m3(9G$)OH^GI1dJNVCW7)F$lvH?~c{>VhuW?^}7Q z%x=ieIW_(P3RU&Ru!U^HbH0~X`X(6frJdaG_F$KQWc_+fbr%N#Oj4EyktHF7t6dYC zlwm~i*k?PuLNh#U;7E4aWbyWcYp)uyTgMMq*Kg9f`n9i~GYpuSSkM0C*&yFqi0{o- zZ()~o+rJtqE80CK?JZ>S`Tg|`ixdc6YNpnYlqEdDXEum6f+;aqsP^OP7Zsx~D_(Uk zYcG8?NEvQn+dZD5$-k!DqLWrjb*CaZ`ORE}Uro~>yTw?$cf_!fd8Zzur*Un+5lNlX z{>i0{o#}=Er!VW+z(Yph4*_v4>mj8s9uLp|QQlic#kEB3q6uyx3GNUQELhXH2X_e& z+%>qndvFWx1P$&^2M+`ZH15zyaMwo8%HI1wcihK2#ywA`-g;51sG2obRn704HD?pz zx6IbVBL#VJJ(6$=SebUro^1N=kfq!5g7Lb}i(>ngv9ME$!}(OSHU*W;)n6~55|Zbf z-|3VbZj|Fr+mDT)(m9icfuZv-f%G5&O28N6|C5C$2ErxW??r%Xg}Hdq#RkU&f0BnxebItjuyC!aKMy4@{Zqrxo^S5 z8pJ!gO)5#GE!3BAex)sL;s?Nge5Yf;Sac$~hf3yzAp^B<%Wb+mvp_;mx|J1Q4REJ+ zTma1|YIj6j949(Y$>au2T08nYJtx`9obycsb_4K1Sy2!7TKi$f0GG zwGL}&mFbilGtA$xn&TWUZe*?w4NQNLvlmV(sK=69_~k1+&cIvDz*O~j)bKbiEgOqD zw?*0%$h6_Z=;AzxeYl1Vpgjt?YpuCTS+7&HQXg7uQd~6iTqZuHk-G3PtEbG??#{fC z?Z;E5)nEbZ8yL3MW}odA597;yZL%|>&!!awkN)|bxgwis&MzS#B=hKj33gR?W{cS( zFv&dIbh2QA;!FM3&C_P>5l^4Mh?m8cU+K#>`7l=~1o2w0HGMw(RaTmDwd%ln>eUgL2n+Uucrse zq*;TAd{mT&ic@Gn4USfMhjsapKFh?h=KRQCL9yCcShmc?3u63%jJ2jtg-VCm%$VI7NbU5lixm@VGV!85b*fwfbF_-3YdTNe4;6p%q=)yHk{{Sf z%+B8xs=SJ}F&k7KY0?iCIsBPyprr>KNZMqp=JWi-%$!Xv6L;M{53=22in}iD|F&-~ zlVYHqd@e%tA&Vw^NOd?@TYOKg$3n(p@@x2HVNU=RQ^I)oCYYI|GN471mU0|=bd_d} zHDMVI(vnZ&KR@vx6XT#7-X1co-xLdYrb1lD@WopYC6yy3o(fH-1QCtLm9YjoPKk?y zWMZ?_Ixqpl?6}B=ktv3M$QdH%*AnIx-O6Hr{UM$j%Roqs`<;AfA?(Xuw-isuRME;I z)OOH?$b7FOi4rGly{sl$DTX;31~uW=NjUq7v}jjx-qR(eg-wM9#(R$|f4tCr$C2v5 zScMt!rGRC04or?RGwKJ;;&@ErLX(17APO1T z^={Lw<_esiaX#MVcgf-r^k|33N+Q~vdc!3Qq>)FKPr-06wt_`1GgnT9YS7S?&7RBWESktK18Q6!&0cSh$LHg3f3nR z@eS?2rBT`C2%V7gEMOE#=0x5HHklt}S>jWLkxk8)Vz zSY6i;w>Wn7gSD+c(2ao; zW6=1l3A4(NOe02;JFt01UTue!;cfqMZ*ysXT?iLHB(Z*AN(S|}j=Mm9Kcb2}RZzYZ z{i#mBMQACmmr?l~FW`zK#_uPUbdun{E5c-%HbpRMn}J3SJ?wMA0sPH zSycd*pf>YN3L)>~#(5SNw=yvUSmk{J05oT6Zf#DyFK2wQz-Y~}M^5rhH5$Jcx<2u3 zSsT_j;YkuhTM671=7w`PeXC~jNhyzhg~S_l6%Y}DP*%UsEiGacG?5^*o;NmZ9Hm~b z=)47DJrewpZ(@6QyFnAZg;4O^@e%~j<^K@{9D{ASEE^XZ+SrWvB>1wasRBR}@1y^? zdtZ1>SRciaU7+@L28fu4 zSvp-F)&)rIVAHKSQD#@0Gs>;3yd>`#_cIvj-9jwk(y2mBr4{Cfs2RaHM( zmD8xPj0;3^{kY#r$AQ`OEGo6lEW0GFDaraT2{+3 zTQL85LRWC$APRNv>0U-X7_WQxaPb)82KkFStjPO;;*=5RYZYvU35bck0`2|bB02j~ zNFT@uq?6rFn)sX9KaM3K6H%Bu%_?qF_#|3jzx<2?gecU`L8RHA5Z?B5Or-!YeSF&QGBK3Ge+GR1ZEkB6lfFZTi-qWKO`?17%=Zy4(O!A1Evp-`z9*cCeV=#19k*Ov7ZVyCQQ zH0xCLO2uz8#h4!=Ma@Et-vGwniDppuF4P*8A(HS$yShufb3T80=Yrnp>)=X=Wj-!5kA#WC+YB+$%Ce9S!7=Uf3yRzR8u3jP`^r+8e?~=#v|y zlKz5mJorNv{<9=?;Y53xS`YHymfl%j7Q?1Uzur4WgnV56ds{`S&Mr5S7D6@L$;`CjO6a*Z%=X z`2XcTR`>+zgvTbHR~-vJ`W0U{)k`ckNG#~NmeNr8BBLn#&d?u~j2#q;1!q3f4gk}U628u(ML z&iSPLKkuaPTxU;Du#a18U&9~8#aV(88o&Hgewr!g5xoAVv|?dQQU6;~MFO?O|0$bb zdgZ8ptLma4Tm4%z;aA=V=6`EC5#yCg{9BbJxN-?O%PfPo-}p3HxJU&Z%E6|9`>YpK zqsgSnL}0^3s$PyCC6SBz<;%}T=FHK=QS)DV16imchaw{Y40Zc>tcj8TC)h2 zV$W8D2{1x6mSMvqe3@@5)UCDl0mvK(pjkHqnk5Pg9N*~$MH7?nFuyKUfEFs#gLrtP z4GbvhlyXdsje`Ivnl`E1ynfxS{S^Kn{_P_W=Frl{=G`kadbOx8KRIpTSBEw$9j!}d zBfOM1KTtngTQe@+NTI0sctVH%_F>uAB*eYCl78_fR5bAM(GMpgq-UDRk%vs2`n8p{ z^)Kx~fVkjsJJ8g!PP4xE6Q+FlBL(~?c0NTd#74`E=-AjvD71HNjVjD&?HX=rXJ@`U zS=6#@_l$`E^VTQF6g+fs!J((8N5<#!Wq4SYfJyU%i3u#)|BQ;78jM>v&$RB4_JWk_ zYx`H;H_5W6%g27r2S&6Spmb?^<fARUsiHmPK-8}fE zFzcuvfwx1-$`}sZyjy?8^X?r~$mfm&?cR1VJF^2p?+CMCM-Ds=JY+x^z>JIxV7f0ZFCFi19NXI3 zer`E6G&QMw{217~p0=ey^RMSH$#{FVM>B^^!AyE>U%!8UUs?ID(kBpemIv}>D?*o-M`tQ^T6c>x|NQww zMTTuK!RsqTDVNI94?C>^8U{`Z+1c44qWR@&|MTVSk1ou%6k9rN^r3rsd1-d}@RF00 z12q`!jO=SQ9om;UxVh_nZk@pCSb(-c)sg<~Gx(c1vvOQ)EEo(9TDG(3kHin@T`!;c zFapBr&}Rk20BG32;Nb4@af#;CW9)w~v76H<=RUacWsXiREy*h=j7Hm3QACKR3HuA_ zSEnMPV#kk~SKkr+Tbmk$8F+Va^$Zaa5l}fGY$U6bz~&ipF)p#95-m|wKXFulgaU1P zWQk0XGhP(U827jKuC5$FPJp1LX_M|!{`>gN`=YsN7zv`Vu&@kkHPJ#v377kX4CqfL z^PlJVJ)(JIU*pDE(5KTTz*rrVXdvQ^Y>Q!Dr!A1vMKKHV(9@TU2wwLUfoF$h5DpEZU4jjDjT{k;}0qJ>$On2zc#M z^U$P?-UOJl!h$Yv}jk~tLjBD zI6-^u?XX(GdU5rq6O{Fi&eux*>X01w)%G0ttounyYoB>o`qBJ=m;sqtzrC%Ys|Bvc zeTs@CJ4LBn5l)F>c0o~5s3FKB5GHS&B;$4<*qtMW=pm@M;&^VH;y$(RGPg_0HyYb1 z*ilm*-o1{l&YG=cVvForjXvdI9=Er!pbdP7lC(+bL#cGs)K0z(#XtMK=59A%HSwoT zPU(vwe_%jWh4Y?n;tJ^0y>79}Y(y_466(ms{fN5c@#%Z2vli2w01F=h5?YvZ zJS&?}y3xf}xI%mOcPm0nL{F5K9@hXx)N|5hO$^Vw>JFz?9CLIGbXqA`p~G4=`a189 zQRaBmtmUBb^{X$Mj{Ft6Di&{}a8qZ4SC7^%-B<1N)bhS&8y}b=cssvX`0cj+)rq0_ zN_eZ-U=+WhaEIxtg(0gcPMT1x2CL**Q@eUt^2K_ z^*E(;babb;K7?6EdSHc(GAxSbr0p>J%9u|}@Ui3u4)NOg3P9(~z&RVCzJkE#FrYY? zu2@)B?)TuYR05UZAfcg%OB&y?IQy%60IRn>lGt?C4MMTJ$ z-m%u0Xn--vfd9|jhXH?ZLv_kG_lkmEjgSkf@T)5aCjmtgATQ;JjuU2OG7ExY0Mjjy zELR8H37qscl+?c=WgFjis(qZiUYd=&e=Ub_cjyzYt&ORO3DK<0gJP96GKSF07oUhz zB+dlz+m-!^851z*ra$rv$>;qzQBFA(Pbl~$3EC(I=b9USmmV;u+o)GP=18w{d+o;W zAfC-J!_Uk6)dYk7InQAT0=9M#$Pe8AdElLDMlzw$;4Rwp)TECX?x$+spG?Zb$!KAR zJcnErMNIQ9DMRAushl!=8q@|z<-IZdL^OYpqNW3X?e{y(J3K@Az%}MVJ*4*j=}bu% zso=SQ9qN^H*sp;>UcoHt9MoRpe*EvWYjqnfcY={Sc}%xz!roku!W6=7SxxX`m>6VX zC@7Wk(ChxCrw0^M0G^gg!^q#li!ip7ejRX>GofMr=2N5lq?(38BclY1&`8d=wfbvZ zr2*n>ANJX+{;BqED|t4j1EfwVRN{V&k#C*#$!&W-T)9<^2LA5Dg(?gJ6fY^_b~*;N zm{BHb;;tdqFUsVxb7y756p+fNMfsBGxY7-c!4c2rY}9SI7*o#W>FO2_kr1AP)1xyI zff-jWNc$C^k@4>1GiM*nr-u{wo1u@aa!+|ltNMs;I}(aUjUq0uF|`YL7;Wb&X=HC@ za8N0?3?46Z?j77&VUo{FxPK}@&WUncO45@r)uWftOz0?f_8||iloS-%RU&`4m?K_4 zt&X22(9l|VN2i>r%46GZO`r;oHcz^rvP15pd^#K(5iarh*>MfwLP?&*!JNMYZTwjj zzdy5|TAkiLsWX-cx#YepWB6Lb2e$DvO&gU;iVhcG^3@R(&ZOKF)|Y1^!}>i>u%@pO z_An}laI@dxPV^Bcht1Dx&I6yk%s37H&HMz##jAwt^RH3jVx8XanyqKc zrAxg&cVVS#L*W4@_8Du_Z;3T@`4Tg~m|$nuc}5SO@c)v~MOMb6S-}+)HCtaWp)_Tk z*Z*9jltaYoOrq;Lmq6X;QLy7YCpXM80NMSC;9BvCT*vLec>iP4w6znS7uR`j^*yQq z{7Mm}k`@nIad#qo4tSc53Rd>YQ+kI8KlHvE{S*fkUK$@0lgOeFw)T6H5%P7%Ew_3x za<0D!`5~3ka=NL%(Q5CP9S*s8*Pcxgxtn=&BJ3aZa;Yg1gU8(aTwzUxPD-Ctuz!78a6b9LD90^c3*Ehs464nCOfHmz1_#Jn9Xd-+*?zYSBpL&dyF@s z#g<*u)*W`f0w4CjqgAd@iz&IDbL-K3w=dn<(dlGjB)EC3#qw^7t=k9|*^67$0*y=3 z$8W51$DFG)^szovU|K(M=x{4J{Q!BG#Tqh=SVr=9@f9FE7|WPKf{5-!abJ8j|Q67&@5mf2qxX zyPQIQZqVGrHC%V?7un>F&$i6#6H9nI%PQ1sc%vxv7!27N`-~ArvCi666V;jj4AZ|p zdBFz<+ds53CU^7k>7oAK_Ym}rziS9i@$?*?+8I8x@C-`W(zJTke64aV3nclm?qEnXKoe?}d065sj8n$+boKN6V9q-z z;ndQqJjkW$^Y(UfWkd7SnuBhOPv&S?zsl7o1mL)~1-;}UrSuJ?Yd4w>e@YN`51L+; zcD8=YJaMj2HijT<1k0r`g=!e&Z! zdlbPciNALH3~wV?-ZiGi_W1pbZ&l7rDE<_|%z5m>C$*Jz<9x_Zs^1Xbw{+o|rKJy8 zklU(EO(+@dp9$UH<=-_;YlOQkp_?;BZ{DMpcwQFpAj-cSZA6Ln0WvFbz;IDcmsKz9 zYhd3UR1Biov!rVp8GjtwN2!?5@^FEMj$9&!)Dm=SLuhoUliw%uU;9<7QRj}blQ5nx z)d!O~YB})Ps)_pmm*c74dWU(q)%+~uaQdVGUch}zz<(=b9gM%(|gs z-b;DfM9I9F8$N4{Dz#@(IeomYxw}>}QoEdRb%wb%7W)BvPrq^Zpii*72H zXSpU58(Z?`JYnnvzefge0C8WM8?&`uwESM~(aT)#ceg~n>q1fjE&FR(J7<<8dXAoJ z#govw8*{_KhU#f^LHHxW$0S?q+}(|pQKiC*U!!q;hq=28_iJ)XDXxgy+A>GY%sM&k zNalEM5W$sbe)fgWr#e7U;^pEQ(z33Yzco(Aj-&IGm)TWqXOAKqJ|l(oMd3y(vi8}Q znTce-%vfaT4Z?P@&0WckhSlmiZhRGps+TGQPyH>uPoG8G_n0oQKmfquW=;7#q<6 zr>c4oRui1=cgw@AABR{1MexK78x8A>?`BHRNO$0zBi9r&+TJ>wizL($HF{pa;VKzH z4o8P~oxgZ2gO47+9&+r8c*EZJbk@dKYB&meeib@IvFaPXa4#fK4l*`(5iUdYcoYbdF&1bkKSu zj3fHo1!ru-USGsoj4le>&P?hUN7pua>b=@{076m(8QgoFaN(ZgS_{3ayLx`F0XNd) zvoEi`h0+eM;72N3WDG-wborulk9rB&;%*6815^>TX8JKXX%Ze<`qD?_b&4jXzc6yt+den#YkoB`p}Cm3*tSlQq+ z3Bnz8>pb%_w5_IF&<@<;+b0%;1uj@Ms(kt+AwXf_<(2W7!^?8KUb8gv=5~&CMY2|t zdd(RZI}1`a-wGfYy}iAFm7Jxh@D31k>zLB$#tVTHZc>kDhMVYIkIRs=WB*62DAq;> zVgf30sz2Qtb%va@GO>cA8p0REbx-?@9Xl_NHoCv#Mjzi|Q~DWjA0^75lg`*+d)o^m zmLVL{pvAvU9m0v*ITe@tTKcWljgym`wYV29_P7}yUg}s)-3AH~OB$(aJ8(%+4Ogm% zm{3$sdv3#jaIDMIb1~qtlP%_M{;0?8P6@mqWyZX?1Wh+A>q< z(k1CSB&k5ci)r5YnU!_VJdqf}%BV}mws{XVd}F}*X>``&rB;=NRm(viN4m@O1YCWx zUYA6@hwMx?!4er^XNGYzlR}TaZ7)|vV2K3VoNfBMbva5`HE>AR2z$HnobVY4Qh!Fn z^)Qs{&|-{OF4P*K5QPgmQ4o5V5L15dDD#lTOxV_BaUy=Gnf--VhNtYH~ z!m`^MAs*D#B}76(a^h9pJa7Q)ZyNMoK%AHcqhtQ8rWzJ7s zc%k`hUQx$|W)lM2+*yKEXcu6<6w}08aUE)xrpEw1Z*cTrK-t5=?aJ)UO?y{g+yHJ? zC%eOJGt_6c+8JKuzp=Ld?I5@9j#cNGtf{kBju%&8`Iwk<`Oa2ZDs5Ooo_k;5?EZQf z7yn#EngXYfhZxPV&IYYSFsu=O?ft@}M9Uf$w&*x$XFq zX01Q`W|Pu42IAu)oC@x1G#!BCH_h8{aBw)BtclRl((2EP?i-(l;*`+g{5?|ailbC7 zcAs6{MG3KHj)K|PM3@L*GdlL2g|z?@yNy?lsr0-5cJ<9_9s{w2VUWXqc*}X!izQvc z{(U&{;~?vyDU4fq&|lc5d;iQBNz`MT{9R7EIrz2l{8_W}cnQjFD&&F3;3ix^t2eUR z={0$-Pe73$9V-Gfz~~b8l6AWiQWxUyx2e@6PmJV$IlTz^Ic=08Ybr@MHvucAUduZx ziTmB@p13gWx8er(5o%vRst)a`WxK*AbWroq?4%X1b&ppqamL!VVY>EgDQEw&ZowX{ zbfYy%VBU!yYC-#l3k&1KNwp3KcfPLEv~_`r3#}P+JSC)f_2N_)f?1AkTH&FyUsnAR zMja)@pZXA4obS-jJ=F%gc zvnB}Xe(_5O4SX8bj-^{}ZuX*aeCI7m%wG@_z*i>`BuW@a?qhOaVh)k)F;G+meSz)0Z5zQ>v>*PZJ8tiqOU=b;;4Dz^$O zG_f<=6>{U;=XL?*PkFBK%DW*UHj|`=)i!_r_y?|K(P4^#VedMn6DYwv@>#NioR;@B z&Yqs?=FF->umyz?1izfU=ib%b+1iH8#P1J6paF|azO)?9DSiwcdHiGEgqpsJH&<& z(uS})jr#}zF&q|(RJ_#NlCmow^;H$meo@nEU681_ zQ|ADrMql=#rJD1(0bF*7X|?SKlbv6In24%CoR=>&1)=ihYa@Lc!qbiTA-;+gG@x;E zSj<3nqrvdyXbs=V$nj=zI~8f!K=ad-5@m&^%+6@JW^>E-2!kP*?6AN=sfr>lG=kUw4iY!YzR zTwPU?l0wBKWKmNEzkcm0=Y2Lr$Lo3ajuJjMIIM@^upPXc&F`*%(XzK^#mCQYkzY`5 zZDkdSO6e01KWdNbk0MO1jMW>&z3*>EHFt@QA0Oyxlhe6NVg1T8mr7;O(q(e;&@A5i zG&3AU$s^{}N`{I}me<*t9T}M(@wy){+Y??#5^7@YyS1~nR!=lmH8-aM_&Wgd0-VGw zwzU@rO+3CrKi$j0P%a^Bre@aEVkl? zoUVjLQKHGyV%(oX+}P6TM;tzZp+I-r-43afc>T*;JkPgl?UviLDr7hBIIRN#8+u`3 zfu11BX1)%&1UeLijCpeFqv3NTn*RgfNfw*!>4>oEye_RmErCt_m%}gS=93;wR^5vh zxn&g9;T=PRAf<=i2|2zd(+qh!{NidX}-&sA0Snlnwp3+Mc)FrXQy+k?$k_I*|PK&^LqnOME^8_ zRTUc+Vl#ZhH(Y#kFKzmRZKHOCI5m@2U5Ih*PoR@!YLU0+JE{f-alf|OHW}7{Lmx05 zcW^i$Flr*K$(b2RJ-zH1g?|~dpV66@1aoff*`GONEiCA~uaC@ZY@z{fWpfi?Zjf@v z!xs++c3n0cc=XZdfSI-7lH<#!O^^n$v2~xEfNC|d05R=NmzR~6DyRL&S7?1q5i9~Y zq`(gWu7KYK56{m)L{yKv-4b*pgsItCRaI3nV6Dkl{*(M6d&u-lzi}3yYb2n}#Xni`e<2RN$IcYVhWzK;mT5^ z6UvQq;E`8V#oeE&e2a&%?$nA`{4ePTG{ULeo9;SoQR2a$t@ypX9C&Hdi8r#Jy5IP9 zRDTd)1_3S?E_|mR0v-Ys2X63Bi*5jY^tWt|(tGC#{W7jyyYxEs>fB=ak4M}rSONc~ zA5E(w2Vn=R5C}lhp#zfl(btiY@dT*9QS-M6(tnw;x0$0|W>?D;C>B5(umSzYWhyggTv6^|CIh(CcWT!c-9--y1QLfbb4qtby-XA;XY+!KD@88N= z*6EC7*r*B8g-d2@ryc;YM>H5q&gjnI92OuZ00ENNY|Ds?sI4C7CU12E&^em|H0w0* z?;tJ#u5R9@=`WE;5m!=?&u0LVDU32B^{;Z`Wo{wgdNCa;`W(tJ@o;?r!a|G!%zpba z)iOLFWmpC02&aYckBlK@TcWW4&Btb%5uq&D%l;!F@&8Zk>;G=z|4&Ny|7o{GmRfE8yxZd`<{3e zgLf?XVBO`(Yc5;Qs-^$9v@g22z)#>0u|~vWTb?%iZrGPsDebiXHQn4G*4Zi0j{UJ3veKOE2?39$RN}Zu8yWr*0Ql3Ct-qUK$nm-)x3VdAPbKs_f*U zrXpg31ikd`mH+k4OoJ)etI(Av@FFOx^6R*ffD2i8! H8V3C@;+5Ek literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530005445591.png b/README.assets/image-20220530005445591.png new file mode 100644 index 0000000000000000000000000000000000000000..19bb721d6da41fbf2a630f116417e5736e926ec1 GIT binary patch literal 123217 zcmce7g;yNS@-_j21Pj4ExCVC(?(Xici`zm7?t#VKf(LhZcXxMR-1)e_SML1_zBzMd zcc#x&cU4zC-A{K-sDhk0(kI+c5D*YZk`f|H5D-u^5D<{pa4_#rPEmZ{f4)LUiU_K> zr=6_2c@xYgUx3$Fe9Aq~XRB<6S24>BQkXt764!hek}!nIJEecHscIfvs(avpEL5MxWt3>SZ7o@c77v+SpNj3qyfq;cie z)YjrOm5~N~7J?&wzl4M`CCenyJOAhZUk^}7B?|-pxsj~U_@ibrRR8xq920;71W%5Q zh#O?6b5QkvFZ}01gd3JK5NH375F=)?Y|OvJ!4XpkezE$u;LHE-f={7;=mN;!z*s|MwlEJ`+bnc5$ zp#n)`0HHrnt7%Khg2G-5XPdsRoDLKPG0A+9IUWCwf|vMZ;dXq+bP~j3A1p*gX))fYh}I`*PFL zI>+-|Qp<1w1pn!?v=rFpvigf;ICtW1hQ-4_HX;4UW9CHj;#Nr6$H+=z1ywvJNTn2L zW#4O=8aaoSm+q=Nb=%&7?@IQ5p`G`b zaW&^HDZB(&>6@&&Wf%Z8X)_M+r>3y30`*^h$&X0&xF8o?;fb+5WxQ}j1MOj-SnRg@ zm)kmzM%=$Z{$WjQ@7oh-6?#Z<@%AzOzQHE^ z-GyP-bb(+xEmxlcZ#URrc?Y&P z-yM6qwjrr|(~VuJr1lZ`ZuU|VZelfWHCV-S5B@3afOq8sGlJ*%x26RKQ)-;h-1qan z{|2aN8c~1&)9*{4a~fFEV7QXn`_ko57rpS|ww;_5Nd7?T1J?XRz24RJri|pUpGXJR zi^EZ)srRQ>swZAs7`OCNUuoTNaiHO0Q@AQ!SnSK!2RDO|xkLL1l}D<)&Uf}ca_#hs zTJW`j>It8y-=5U?`n6QACtxyeAGn%M#9kk06BV=KmFphZ*jrtGKt)3J4(JVZm6Yu_ z4NGgr78+xxpLiT4w$zPAmv2~|z0Mye6;WwKSl#knF{iT6D6v=@cvboz=Ne+$p1gL; zFFbaI+t4{ppCMn~=H59T4e)t`_l6%#Ec>YbocwI5<-G``)nKBHv=9>Uu2tcEWAt6| zi2$i$;PXy)r&VBNuWoAzN-6U*B1_*f2^I{%&R^FNq5H5zds}g5i*j~GQdaOb zXzwtsr#jZgfdZHi$b9Nvs`$nH1Hu-=i_^6xtXS^H=h0pJ>9o3^v}$otYv>dRJ(x^h zi!^0=df#)lC>ONlPCnor53jI3@m@DI!+TmU-j)blT;pjkD9uWiz%ptR|4vCzKt$fv zVos#Y3h=UAc*9(FJ-S{1NjMid&(}`H;6_e1L`I!GR?}wwg;851xmi@MrF)31fAG35 z+M;a_4?Ky8TffMji%s)5EMRU_jCGm~3M=wASsP}~r*NT#Qzf@X@FX@YXgNjXt8wVs z^3}MVnN6d~gIB;pQ&*VP?v>$G%1I&3{>AgJJy&aVIl3HGbyU$gyCu{&_PM3}Au$>< zV=KeS?PQ4}+P~0r%|d9hO+4VqgJAq9#IW_vtckMd91xcJf=*uUac;HhkipyU#Z6LF;eRAl~|J;liR+ z*DQxAa*kZ8BD#kWx8xX;zTd!T@jJ?jBkO4J#?eS6){D}M!WDk|%b3&i?X`IrBqn89 zl7|jQZotQ04-xV`r#t&ZCv{F4veGY(>eGs^tOD)l@a(KEo2Qo(Q2t-65NIM%p(dyRgpPG-tAE;RJEV<6T#xN)9dgXa`mk27@Mvg4GR zUF$ws)9$`KYOgA$sdx@b|g_(_MH<1wW0Lm#z{uD4fwSD zj^nDCcLCh!*Hd#^k!47{*`>$WO+jHFicvC`gU=)0rY2knbcsxJwV-pWf6BJIr>U2C z!tIP~KL*Y__V-syK8_K26c`^Ju@FOr#{v)6Xf@xV4qNm?FEo>-2?qMF^qn3;*XufVLii$q z&wTtfv};OqBt-E$k5jWJ*^j3KF+Hz+B=$R5V>>YG9z%L`HV2@?jBr(`})ou7D+3`(;$u zKl<{~IR+mewQj4ek4tPgH_7rZj7L&41nn}!yyQ@6t43{Ve#fRL%YaK+nT=q`(MP3E?7{cb}f){~lhzipE`eJqAiSis-aKs2Np!MV?qGo5@wD`tRVTFt5Q)^HjPwHD$&<>a9tghQuf>1s52?FN~n2#g3=^c`b;A2Bu(8exNM(kXVQqZDD$V zN`m;?u;}_2Y0LGw{x&%sr_o7LEgbUGy}Aq?JFIH~!s>E&UFQ1uT$ugUAK0@UZ6aFS zUAy~x{4(sREAwCIPD#bx<5#Kv3>Q2lPzA$*!=+hT-Gx>G4kpjGvZDXY{D}C%jJj;( zI`TwvaaNV>`8!+ZznPDYsC7P*hMI9^FWfm%6d!bl1W&5qULWiqn4&rh&*YOZZw(IGP_*E zfUp0M-uIM567x&+By9QNZ0TcMUOz-p-u`-5x^H_F<(m&q_*Jyxyhi6_7=jA_-#8#1 zD;e6I*O2c_)U+oyFW?DZ`vnmOX*-Qvi+e&Cs7WqMU^mu~eeSR!Awx`B{i6#S7IXR# zT2naM{jjJgr?EEiEKBOMf()k7)Fl+z(e>peBbR=U_%sUM8SWgOeV4#nG@k14(=9HGyz-uO_&=BlSf07WSEqj zP`W23To{`8yJ)6~jQ)ocj@U?bn1p3qzF2rNp#A|4-8u394=-b?rbe!&#uZIox>n%$ zNz@qMM*a^m4+&3_tTa~2Q9$31I}@K?E!66dJKOgD9|mbfAtS|VM(!$gmxBkic${fH zeiZukU$SWA_Z@4q0$y~mBaaipbmc7>QTHzAkgr30|C@3Gf-c10DtzA0G{i0}&g|PG zI1odbWa?d@BPP*;YC7xw&QtI-?ZQwz7id^W6&6?|wK7iGDEu#{BvwUos5&CQO?Zh2 z3WCy*{hinIipDgC$CRo(_V9{Gf*nMpd%m6Pn5cF3U+UerU9@j9tIy?g>EY>FED@0z zm9tQ(#T@DaL~O2w^R+aB_q<(P1?^h&r& zkXA2pk5-c+$?O zLwA4sEu=PKjXzzCV=cJma4@YOuftWmz z&s@J(oJVE0Ae8k#nl7glo<|zK>PinJPeB3|ZYCA#B2ymqx~|T*s_-2m7U2xL+SHKS zpXr*9fdN$sj0M+9Wyv@!48J8_;cH$ZW}VU^lSI(0 zVhq&rN~#()wmBE(Hgn7L4sP1RuNBq!{x`o}MFyo9<=TI(HzMtsuR%McMMbb1}5DHoZzUVCX2Mj0z z)#G10Gr90}gufm4)z%gi`w~1kLa!-x_-lheH=|UQ$YuJ!WPjGj3YVW7d+EY}-SmX= zbG)g1($b}aHh&*Z9G@)c1#`U0C793{zbz=YLUSWuEp7W6mXrD|#5d-Ra6VxbqhyOS zuE2U6k5e+~H-+^mA0)B9yAy)Vra5(%Y0hMmp-EoLmg%Tawm9xFo#aD;H~gC_c`o! znJ3SaQxrP2FW=h1Yd1MIb&HAj&PF?eGxSA+eY<3l(_;%C28B_}c{3nKe22o&UN`Hm zK6kKsgv69V*g%or!$8DBhzwa5b`yqzW?QpYmgS{jBY7p{wu%Pi5I(P|9npFnT=EQP zYE206o9Ba4&%};x@twSamc;F?VMhsQM1%aYy*c#=7jLyq#y=qDSk=`NN{K?&u#rmx4E8K_=D}WgbOo@oluh5v z!T>SL5sNdW$aV_qM`b1MrluFe`_agF3z5FiH>TERsC~IRGuSR0XLhTFsx_n)Pt7@q zY7H#c1IgAT3`E|Q7}Rg)VBBpSHC|F_B#Z&cxfKC&Ct47h`sAM@4A>qnV7?Qf!zyA% z{whFfr^akv4IIWN#=n^OEf(|Hw*SFSI5W!sa|)^;OUb=AjR83gaRyZ)L9-=fzbriJ zryz$r(TdMs^R%*?!!rmu1iyVZcS2c%#)6kyu0UoLOT(q{B>P^kEjsC6m;!Ipy?yS? z<_vc`wFrYGXnRnpLV;cI-jIIjOpbxW-(T@72SvoW04d_M(&(;2_i}fn%1J-^r6o9m zT8kXA(yfslwk!hL8nhp_?%Fzb2SdpgSRv2KBFJw<#L^u=x$hzR}c7XnJki|LDHGLlF(cuHqNZj_)&8ZY)L5Y}Op zJBE(l#Q~U-({u(7p7yfX$v}#L*qzww-wfF5p~Qx1c^`6LO%Bcq&dnQh3}7S9R!_XM zQHAH>ZrP{Bhy-mHG`{cz|K`A|{?4+^oh}mC+VJG<{=Dgz%jxY+C?`BGQFmNZ?rhnOo(B~MH{lKec{AE8GevWi5%sQ*P@B_+O z6b!D=(1fQ3jFIgMfGT3SWV^y09PCU&vmFhq2FotmX;*C!ieoWd%@-WCbl1;#1gJJb zeh}jY&YCD`S!zpq>bi%v0}Qbfe&eBu667cs{K9q1n0%Ip-;Nr`5f{x{>hx> zz3>wlX8r4D{s{KH98)5~{reX5KE~VXhj>CAF53GMb$e5A7VZ2Zt=%^FYQ$SX`{qp* z&mh&oTT6)*58mrGC2s>f<7={gM~{xJ5LKVTfPqlgb3>EodN;? zl;2PSRM~z*whWgGScIl%pEo}7gE!0{nqkY$)+E%YYazt0q@TA^1M4}~0ruHUguFM6Lw$WPavvQD6?BHXDmslWSr0zOz=j0K?RpWSh zR?U@1o5%Y0$>B*ik_m&(=#sC`&+-JCo@=|!U423md13B)q?!3Su7m3JwV^Gy;dzPK zSI~*48xg-&)7kE;q3tg|b80T#PvZhtBsa7P4o8Qp_c_uUj{Bx2M}jh=4B&A4IRm|_ zG`urfGGhlc_b3O8ZMD~ZMFF?6w@<^1y~hl5SGTvI5gE^veh$I)EY1d&cF;?EQ)qhw zp~;~s(RO|u&HLUA^&Q*lU^IVg+Uz;|^&#hisPztKI?gQbi!%XZIFIkW?%DIg7fec- zjfUiC2a6{)LXVaNZ}!SoE8K)NLi}v0+sE`c-<7QMLD+_y)qA}C23=(#!K~yA5Z?Ws ze2Rm|T3#I&>eb06*sTdyZ{fwd?EwU=Vdp^RN~pXI?Jb&Y3{3QWXn(%FOD)1(IKe>S z?=%+xAeBsu(GF8;j%4|uCkEy^psIU7b<Rm8kNXXkPq^#P@aTQ~vZAMw?1}OwD<7Lm4puIRR<1WFe)@Hgjj^DW_M^PU zq{8OU&Y!yfT%Yp=*`6boh<`xC4<5Qdr+jK)eFMBUwMK)wqxwU(1t&2^!mF!oT=@g< zP-=<}>Bh5jZ(k-O`S;LcG`a3uTprV^ezXvua$Kj`9Itc@Gepd)zi;L`I}>hd^s?ZW zxTh#Ipme*xohM~Ty>Aej>i-1kXp-0eYh6Bf-@nHCHTpwvRVCjIQGDgB9J1a@={_`2)>wGZf>+YQ;Nk1 zT#EGF$%5TFe?mRRY|Ju3@bxi=rReVAn;-ewx84ulC(P#k6KA^qO!xNdtf2hzYxK)C z8{J*$){rK5ItJy!MN<57`;+k}WBeq!lRXP%uIT4Y#$&t8K)xZVtF?Mgjk?4-p0@Gs z#DdSz2JU9%{XaP-T66w0^qs0f#+-fQ;S_-fcvyGyTnxN8D#(EUkRC ztF|6JMxj1j;AMw#@eY`2U8PGFD6imE6Y56z3T1k1XY5Bvad0!e58vXo|09MU>TBdl zGLHW(0MA;0Kl9lT3w5+PYj8}&Gj;|M%*-}~(%ti~`?7wV&*Id$+Fe9nzvW`~nGmUe zk*!Pk{=g#Xed$HMW8RO9A_SRXYg5i%VN$yL)SfKn*jvI|`|6@M_4SOUH}4J~_o*Si zuu#|Kns7DhE_{7^ICD7rJI~M{0nY_Lf#ImHZ&(TD&M$VG@mb^ELn%DZ3M{up&l+p~ zZWp&dCXxWmX$(^dq7QII6l<0tn@bGd>7s*woRPT`5R`MkNYUB(z?NyPv2A&=tJCps zB*~xjUV6=ryqz?ja=nt!hytQUTdFD}gaLq^^<M_-rbK67>7r{8kixv6~seo9as21Or5{73A|d-RF88eZ1+t3c?W>a-BeRy zWnpMuI|Uck?GdoSL6Y(hL+7fe!G3Btah7fE<9iu92pYZJJJ@E0FVz}=@zI$`RFHW& z!E8-tN|Nseg8q1JhyK{+kXnY*P5VYi3NYwW4#U@o=k&Zho3mUBGIwC4x2qi5q@JFK&+#Krn8 z+=O+o>Dhx0)*0IQ#YKs|ljdf;31tDxRM?kOJ=!NA*K>DwbSxgt_5?D@uJ4M(LpPCe zLXHB*QiE6B&HbqLNHeWO2$b`pQ*z~&-rVZpkFfoF*;9De#Qh2?0fOa#zHBsS{FT9k zWc^KL{c&>h1u#_|&mkc=O=)cI6HziZb|3bBoL`fuclX$TFeV1Er<2Nftdo;g(poJI zASYQ^ve6;kzIX8(<)X2di|mdN-%(C(igM~5Z?=p~vMgy-*^Y}!J(KejbfJaqlJ3)T z5F`W@Z8T&CIc=^cz_~}V(4@GS%9v)#%wd6(xt}}tD@>s6h((cCOkp4-i{5{XHrC7i4s`NLaoP~E|Qv_jIhV#WQJL(_VF$S zPqWGuiDgQsrwHdny}sgjP|A~pX0y6!W1EbE$v@5QPEp3tkhyzWtrSdVYEtc97C!HD zM{_p(7T-|Ht8~g(6rAJFo|FDCqSu;G65K0T@;h#EdcLa0f*=)zZ~PXN%=xK&$GVz% zAOh#`RT8UihiiwvC8l=X42?y+;ABJlUQ2Frfg|-K6u&-%z?w7FvZQQd%7c0b7DI;b zlx(qeM4Jti7Kg2KekT7Bw=Zhiqk51a*lbLhu$DjTO*1_r#OJ{^qecf`u;bf@evj)dl(heR$Es$J7u zQ8968x|ZJJ@9DV`sMC$-E)e;X-?NWDXQw4xI64M-tHU-~7TQtrI#Guw=y%hIf0i$c zs^y7J3t(BNw!GK2ZPGi2MGxl{^~mN9B~1VEo=?wHN?g-8LNMgM_(kT z)u{5sP#2q>#+)B{d%odJ*F^whTlPdS<_-{M%E%2`m9;ko;43pR>H3;If$JBQn}fPm zD*IMFQy2#E9RbcGo+`_s^)3b^84+EgboxLj>&wo8;=PA+w+Xl6Ksm>O^a)Or&M#6% zOGDO;&UxF0*Ab3#hn?#1FX3$w%JowkMlap(^NpLAn4}+*{rI)L!7+^16CNc=T|#Iv zrv(e`o#I1S>eXA9kYOZ~B5$@lUYYB{r$~XE20wwSaK!Y4LD^`Znv05F@G#;TCYG8| ze6y~Eu&lcfRh(O~RISCQmp>2{&xPgJ8>!(krp8tzu~Z}}E5=cwi+M#I`|qw~WT1c4 zQ54}J5YZk%TXE-x2jj$zMR(^@eI^i=fi`M-a=@eU+`v{#?|{K>qGdG2-eLmxU`%`!X~e<##?9L^d3_#XC}FBymQV67uNY==Yvt~ z;B_NlZkS;JyejL)SelqEWBeAew(Qs1!nl(2OkuZOOk^UIsZ;ykuNqe!EXm5`G8(Ff zH=>4BRtrGj!7GGd+KWKI*b+A22afQd@maCP+Jh=VFba;&Z8`0L(~`L4*POw0_Q(f> zd^Gz>CP($EJa@EyTU}@8MhA46orYdR_VIkid8rx%Y-?Ls(x00|lya@Vf-#b0%{=i# z!MV00VWSycv8o7zvZ4Kl5tK|Uksn#2t7^%AGPJq|VAGIM=11`AlNPL)CG_r89?bE2 z|Dm+ty<}#n7iWw>n{j)RAgakEHdW*kS?PXKWRB{JFHN@Gcev&Z9#=4IY2%Jz50UT3 zSp9Cci)_XB;G8+Z_`5j?lpC$kmi^MgV}V=ntKc`XjsbYQbiD zkeV@OS$8Fxn6cmK>Z z28NrPS~2WKOCDc(04!j9oC+HpA2rf*gU#||8sq9slpcIKd`eP`3yt9Nzu9ndQ&6@O z`m@?ipZgQni}t4A(SgvipbJQ=>6)aWk0BHi?q62o4*bT-Zo5CRxjsGV5_jR@-G9A< zgKcrpgeQA0G@BA)5n1SY-0^AsWid<&;gf4=f=;O?^808^p-e|Xj`_Y1{pQvWJKZQ- zIBGU9KvG|TCN0ikTP(Qtt2!$R_Y&>GT_JZW1lK;Ly-d)Jl5g`Oi{hl62Q$$smy!@J zc(RGda=uoOD;f#J<(FrJCP?|6+rugGa?sayQ(GSxFyGYDFza5muRj{O{=lA@c}g<& zX+qpL_1@t15`#$cx0WEEn|ssZOlD+2lXHwh>A>2i0^X*s=eg~@K1)r^v40VUw0 zCm6>2`eKa%T{M)OW=YhWq{R(blv+%%yy)yqI^Oc6Nt~#~2AQ#mry2_V>^wWGbbI3F zaq@>giX#~A0mR5vw!a5Raj%Myz>18gT)1~cOZ0xQyR|9I-MkPy+Aqs-4_iw?Pmh45Y}BWi z#WV@WV)$lY+?!WD62*i%<#$D+Q0C;pinE-Sx?e#FHkhX93iudeB?RS}nbO9+pUwIA zSfrjJ_1l>G(lTBrNXU`Zb!L*QMd&$c!~Jh*JR9xo3B+$lEVKr)@i-w~<7{=O0*Dkan?Wz05E zzvl)6U%yk<7OWY}w-IgL)cI^=Cc+SOPcXt|;{gLm`{9cyC$0&xALdA51iOwTyR69H z{ZGvanca!$Jq?$l7e35oqwEIunC2LrY-Z7<<}|OBCf-<=b`bBf1C*LCjJJ3%5IyC* z@5vu8uy#xLvg|a2TEPPK(VgFae%?_p+*8h7K6KN8p|#%xo5mN zQGCufEW|KtzO8pzd-(oLUVm#Ub7ka2m<3!j8r>*|0 z?A^C@(;MICq~O@2L;j{v-==co9`kz%DRL%up8-hSph-#l`rzAyPJNxB6fc4CcK!y> z2_XZsQe;Zx+>i3d8|Umwji;g+o)^&~uMg4B!v)GzIT5XRt{2srMauQKR@_D8G9&`k!hG46#RR z>hpx&vq%O(oOat>1b6SuE#M~G3WK#)`MP(jRRLK^UH~IyoHoX~rST;%Z~4jWgvXz=@dMR~-O&vv4H1XDkJ9Yt0flzd&P+}EcS^)sMyta{~b zr?ke)?^h0L>?fb@ME!5uH}{-UXIdgl7l-q}57%MzS|qsB1{1%tCHu|-YS7^3CTAeE zkg@lw@!ZnOP~}!~=Zs0lCOPBMq>L)U?wee-e&A!9I<8>vqZb7KcmQ6%ND|ev8iCID zco=|zQ#BgzOAxQ-$EBRcxs`4*HK+lfx3&~CUzojaU(n0TKXy+rI0O2A2|;lld* zsLT5j9vO$%*DO$xde_#4#~{$3`C_fX+ATQLP_I*JpgB<5TkAgKZ?n2O-F~sS*?QuX zzdbx^>S@GVSNOgLZv-oDE$?t0faU20N5HT@I`YtCM)_;8K9TSEtz(~XO$yX2s^Z8z z2tO&Zh~&Mt(P3Q^HbDOg^vgGC)D%~75}xelZ1V;Q@BSPMd7B+a7{zxYdTB~XR2-iA zBbQ8SjEs~LNhsLWMv8QG)rYqm(@AlpcSi>0b7CVX@oi4*YoXwc>un;@cJ1TqBh83$ zUyj(%I$UJ+RLLl(*qN4$^=Gg>Z}k;A|8#}q3Xt!*7N+Qy-k`6G)$vkELN1JwUrT%v z*TQldjuR9TJsFBrH$4TD0>c;I&o#U9eVQz)%21{9?hm(|P574d9X&Z0aROJOu3*!= z$Z*hUoUwx(R>%BLY}<0M>#Xz4p_{|gtVbyqm{%M3r6!6Kqd61`L);x`&L#rs;0{&p zLOF>E8jqk_*CeV3-}JvE0l2$P=3{UIx<0I}cqQFt=tZ=NH61lkm$d%msy-nji$WL1 zPzlPSX%F}~h&wmtd9=jBNQuehWXC)>I7mh*wq4`8dFnL1$kJsOAM>b)@LGlRydDE_ zvrSQo_U`OfP-ta6Cd_-^@;3j7RiWwZ?DQGqR(cCRd8moejfr3-YeAjb;`)7cPdzFs z=M`f!f3kSPW{Ud{V^C`|)QruEVA<0sJ+MTe8Z7^*K#nonvW(^PW-os+lX=(HoO1aQ z6>JzMFzEYoBAT(Z_%kL>#L@A~AVBR}BEW#kagUmXB0S(kW6!)z@&Wvrul2kB$9_Fv z(D_<*lx=^svQJ$l4>7Lo>S{~l9b>iww5Obcx^cl^Ylx`Rp9LG^=w?0Bg$5oqKK?hd z4uYwIIVWU(oJV}3G#DT}C0q5oC*0?q4r%50|AuGsg z^%H|9Ln6U%K|2oL*m(4}I`z-<#)!CwYX#neD3<~Kq<7!`=?CRBZquYVl_R$Pf$a0< z`-cls&bcW5jA+vN@+^!BOc4+%bCOh!i0`G|osrO_PYSi{h@`x#7+kdb_b_H}=;M~^ z>m9hRS7R|89@p7?CP*#ZB?YY*?H=6o-jB#q)w(^AUduxPLL}8?`XalJ#wV{2cOHcu zfs-@gwyzj;dTbz@V1m?GxkEl$>bK$L=hF$jp{-GiRvM?XHopgQ95QjuL-xQ*qBpj7 zPZJgnhinV1&fP=I0+DPmHt#L^60BWD6H0a7I&6OmfJjgsZ7 zPEM758DYq?P$N;LtOt*v5N$b>3fYvVQe=W6V)kg3aw;iy8A+d1Z(HxVT@#V!<5>no zU{_RHUU`@00uDyo(!9b!4iE{J>eUu=Fx+mZd-c9jTgTzuBG{*PgNq@bky$I>0t+lE z^~X;CTHTCSHmL~2sUf^ z3m;|~_tetbEaWg#x9*F{wN|IwMxXy4F{RkC73Hwjpr~M+ya&1%*&0O2z0a7L9ZLyJ z%$g-+s~|qr6#^a`hdbgx-BVLYHlEM@X(81yU-k=@(WLp!@xqOJCPHp1BK7%8#(v@D z^hCXfB_mfs<@KB?G)JbFVG*f%p5w07?IDo0oub#VrxE4S@=gn?!|jNg)GHs(EN6@WXN zBSjUd(%(KO*86DOz7dSbNV!y`JqkIYb#siCa@dXf$mOXoFE_y6Pf>tA{P7E?AtW89 z<{!QFW2W;g?c2U?{TDft;o|R$RKBRl)gC*qOX`A)a}-Bo>JbRUJ+L8m76*?eYOj1m ztgQcG+JdvGFqpW<-#LD!g=3_@r&5VQ>mDEbB5R*_l(HJJ7rcL6VZcsq%--viol(vH zw%q=*EWGcTTbBp<={+)&wH8`#s8-X{on2kGoJI{EFKbuc21WB0=`?2eJv~P?(3q(- zxgt$OJ6XHTD-Wru((OE>2sbV26X{(DiJoRKO0|-v-&T@(WpwoDH*-~M=4O?4nb4w| z0>*uAX!i1ZznseS94ZW4oEz$kqS(H()rVM#yFGT}QG`cOazuKlV zjWl>;dNgw7HI?S|&Qv~q=R5sF;A{z4Kx5HhpO@?!u}(@(5i-;HJZh2qJV5Q)#LYC? z5b$%yNXm(MKwDFyYDwI@8C0YB5q)%!xO1;#t0b$4CFr0O|C5>NuPkirphV^7y9tbR z={?g#C(Zn70cTsu9&uQO5g@)@nCV~(C*&D+l^KQtD@*diMHX|xl7ctxnghvI**D^D z+ztUN{5*vkPQSHuQ;}~iQHxIIETo+xI%z{uxIE-6%mY$UgziC#P`Hb4Hsr;lQZjAv zO+$Oxr~CMC4Z8)sX#HNh(r!x*8ny-jjIdTkb~1SeVAd*@?O>U!2wYmZNW*^Hg}03S zAl||?`l;!HNgdy?pai%{4}^xZwpzM~>Mhnt^n$>V_ARA39~)#G3WPAy^qB+prY2l2 z#~QyeJqF!dBPqvG^s#htF;~=wGL~VZDvglg)WF&Y>~FR4_@_*05-G#8EV_p);Tu&|TEOwpunY_xd07rq&bwYDtmSpLQ^^?)5I0`io{N>!N zXTd=BymCEm|G0a|DH3sq`Z+*earhW&-+p!}r_r{=pnU(!7<=)OmW6}%lkxLws%BDx ztlo)c-x>54&B}a~=Db9h{B}=eZq1E|V#OtM+2g&VRNAL}mdEpV7>GcKHlEpT!_&k* z?Vo01%t$c#^#j?8$o4#{@*|nN89weNb}tGMijk6o``3OP@yFVdq(h~Uar|bx^OAFY zEtxPD|A@-IwC6_j-^hFg=!uxI?|I=C`}}e)b(0%TsQL;+e=^&GVl@!hZ3EU}UzJtj z*c^*Z)3C9GLZY*R@@-jJZBwU!dHEycw8qr*>O;_Ne~ht-S#uFot%-9~(UhW5Cut_H zGyD!$l?6pPS}Z(yQr1Gv+#d@-c!r3q3Nl$q3S-KSf2cl5F=DeKZg*d-F%$QpbuqeL zF4+3!k=v91Ucbk;W-(dY2o5E@+&VAJ+PlZ}sW2vdbMF^Q7{j%Ux=~3^!JdMAPlAZ5 zJfD3VUjz0H0_G0a-c(ihGtxk;in;iIOr#TbZSX59BW*i=AkiU=cU2|vRhUCWC5^KNnDBA&!5-+YxmzGDr`oGw;%q6;S-8C<)sP~Ke zf)&lM#bEsNLqi4}u8ykSHfBxNd43-!alYn`q`ZoTg;BJ0SM&0Y_g%qMtgHS-=nqPVNO>ot8fL^k z*62R^-+ZjEI|WDNbPMMi)yBU1AR2#Ce?AuYg}4t=&MKKEl~sFz#9Y&o?^X3FF2Gbm zc zOS@{IDW);@IXBS`ymD3o%fQBlL2iC~?S6g);%kdk@g+^LgJ+>~HOfb6TpabOfdt_D*`4 z!@-*58fHxSG5&^WX_*-qg`y(=IiOM89Exe`5&BQbPFan4nk!e;f}BG5*-@g=>%1VA zZF?DAH=U%w+N$@!+WQeB#O+oTi`?(u-fJZxxok6I*4^+s_bp5%x(wGp*D9AHCMhWv1m>l|~x+jx7tDf97<-Lwjqw>wQSj{9zo~2UvdB z(`Fx{Y<_%VlnqFNh)5bTPS?dud!cQrp@x$X6Kx1B_qc@qw~^Mwz1tWYxn@tjK>fu=}7vfXf-)x{T@@eO)JbxuEO8u9x1er(@vc{1@bbY39LQ{=}4TAC51g?qC4 zlweMeba4h&s{3jEpV@bST~$AK_GjNUqsf!g z^Hiq4H1vR5Sp7Rash+g7vBe-ja6bA3AN2Y7OCYC1G7@TO|F&+6d|bSo`P6;tyS`fl zUDv6}8fG8zlchU2KFptz?4Ep$UyInT+h$UEDg8!Q{VU5JU+@iDh7=D`pilCM2*~@7 zvSSYX`bjC1Sj>hiNGfsT#OOmjV~oI%P`^;ad&Uu?pJM3ks^P~-W9sR3cN=N>55-8& z_oXzDZCc)HjxWiqPk|3 z<@e}o2DJLbRw&4QlKF$1}gOiwJPhZERs}3$O z5gBdWNB_!H_br|eu{1%wVEbZ#7_}UFdP2N=LUMZ2dxeZ-w0ChJytpGVC$wMPEWeQ+~5{r(f~YcF}QcASuf_|yipzdg~aaK@~`P2 zCM|H{cbzQoosiga$0)H!aB>)dWbfbY8{mAPbF3T@@-}0NQjOfMGiz8gg-FR;Mojz@enb{{+3CNXY%45Hj5)Ito8H_k*nc z3q{~|@5GbYACx1AyhuMjAdynYWK#d5i`aXIDQZj%+*fi;D%^c=tP(d&p>&I~^lGN>|4jG>JsGJqo4@V%}hbuU>`2p6kkg0~gMoQ1<_0@2$e(YPz;T zBtQu64#6R~TjL%qkPzH0xVwem?(PsIKyY_xT!TyFZjHM%(~rFG%=MqlcYQ~5FlRuq zYgetRUF%*_>jucEPi&tE7*Mk{q37a}A0@o`@8iGU`=cff_y;*gQ_zVvk&nJJBBZvc z+~Z1*m!knpUWK%x|Fc~LLQZqCX%ahd36y%dWzT<(TMz=-|1(c17*Z}ay5{A)bw zfA&V0so1|Kj1&$0f2K@D^y%NBVGV!(SBhbBi2v=2Gw=h%OXoXo#Z|a&uMK2}zHf{?RU|C1S#T%OKDp7~Ie8TG#Ep z>q)-4x*7yD`geT=c5zEXHU0fXr@ker7RsQxGE(b*NHzv9H~dulmCyPQHdsS)(faat zhyTmXq?G9zB3DAjYqvgmrO@`VaE&dvf$I?*E+1g@FE|2}mu9z%Eh$VZR+{H4OH#HI{ZD>XxVMI$h&VV77g6sAHE$41N zWcz8c#ZoA<30!if6iJ1E7nK2sy$IfDQU+!M#s-w#>b!T$uan1q{%rqoIn!|!@t4T6 zU_(6fZoj`-eM+gj4+!55ABn+I2}^p^{52&7hRq>kme1e_X7 z6TbGl{T#?vz57Fm|7_Z6ghctQlj$$i;6z8b7a$nC|9fk*3i7?7=V9#W#@J89%wagd zqH~mtt+Q9fKSODIfvs?wJ>)4C;RrqW8{^&aX zyY1KBn{6~I-_iRk1s$z+7onD0!ITqX**T~?pO>$WQB{7X#K&j%X@RTb*eu8Igl*++ zn)m(NtZ}8+OG^BS%KT?sTcF7$z-Dkjp>4;IQ}Bz}tW6PfmWsciI5SxZLy~0Glq^46 zgy?}0%{Ji~aVZP4L71Ey?-EkgkoTs{2NE}~IxCWp!!0j|ZwB56I(MWi3lm$nPz ze5_`0B%ZfA?iVZ2oAaX|`ZTm9CGFwvK83Fe9csS3_kXSHce$kvKpdE83DW6uq{Tsh zW%&nX#fP}(@iM>FQ2UB+;(6tT&z3Q^GdhrHLHH)J*l}W4RYt{i7=z>+9LK z0^8Xo-4)CNi*aIoU5*q7ee{KBFYBw9C-?J#EBD&PvJ$VaA|_85f7Uv(3;YGC_JHQuWOYfJI|fi0c94HlU730zs!VuD1ARTWB_t{ZFH3!ZH+=_F&7AACR8% zxDq))`rctG-*kId=zNTbRoOdsrNqVwKm6azJ)QGwg*l@3GAz*zwD-(7Ah*T&Ss4|B zAK%yApQ-&zw)nGIPENy()BTkPay6dg+VnJS2CQ>&pyA9o9M+R&ME0IUN*%Z>B2LpGKrn^nLpw`zSq+HkU0p=4 zwo}O8A2z$}#+b+i;;~(7uQ5;Lq$uS5PVNBdZ(~fFUbT!84;O{+-gWg2 z*peeSvl&TzedjfQJ`l;INj6e+1TPM^Dx`TgHe;%kDSy*<7)2o(u_6_v#|HUfrYHWq zz2_{C&?nS*WfKW3AgDDVJ!ktD7x9!OX^*qs<#aisugt`YS_ei@6Uo&XM<1!c2=oZCTY# zp-Pbpb#8(3FQPB-O)(rpRuC?K-KqX!kw8y^48YCcDs%gz?jCEFRG<;N$;janwCaaH*vG=;rPGb%igXE{r771g#NyA$sCsJP8 zuR}$v&!A3Uh^@`i^2qT3jorir)`e@0*&MH%&5xr=zktc?&r%beq4#HP^EC%GW;Vi2 z0haMJHBzvJ#ku328aabnE$|-T*sE2Q-$f=f=;*qt5KPa!!tsvzt_Ig= zkl1qn_TUUOU*x{E=h2%>(7k*`4!nejWzd| zdlbH^MPLgpwy}NG@j^|FMe2f`)$a?n3RqNLonU*W{ffsIF z3Z(PBYb>K4FQ6)j>nBdqX$a>J9z2&pz3JiKCrkK0y;nTs_i)UZo9 zBdl~EWIn}b1bb81d*mRc%a4NJw3`xthbw>RotvG^7;^s@F+{v4i~N^vkI(0H>inQF zZUQN>sJS=yK7U2Z*@g(|@1)z4bwehr9BpaEa7M{}q6~y@eV^$(awG-yM|;C@(iSH& z;dsO-YAU4x_bsCjEoO!ro6A~3wHB(NE%rJ>hGAM$+|TG)^Xbtcvo(mc@Tl?84Y zwndLZ9^idGhbJ5)&ANsDhS9J+{fQsj+A1)>w1GK;wLxFew$xW|;N86j5F=`P!2eZ{ zPhaG!9^GfpGwy7ZijY10o~0Knao*Mzmw*8KICjc0FFPRtJAup>7k791)cNp)xZ87q zY@0AJVXD7!SLI?h_BB%UcW3%Y$k$e{Hp~2zum!vXodiio*C*BAV6A5+^2eLI2MEeq zkFO8x!nkNCN^HZC6lqCOI^9D4-gzJ;vp<454}M#LA$vqf`qjgA*V$fUS6hIA`|Xs) zmudbpVv(o9Dregw@#4Cl;eUhT;gGw99T!x4ps$bfD#HM`^46XJ-VSMo31fX6kwu4c zS4;FN%SICHm|+iE>Q#8=KKq^nHP*WiqsbK4EMx3(-+RfUq7iF`oLF5{*B#9fDQj5?!y8SD?0prR8ytBLI825Q#wn zgkEL8JUX$5F5+_WrBavwg3#I{Q+zmPy0>zd?XnLeH}9_2-s!lhmQl`rFIr=LV>496 zbnp_ZG;NSJ_qWMb@@n4Mbn23Z zhSW^@%fJa?vM(y|Pxbb=P%Lt}rHi;_neeOU9rMi3X7cG2jI@plR z1XiX2$@%2lM2E!~0!#=!&H(U_paaS^0+X}(k4{x}Z%yY^wK~GUEF_xk?U6(?S8wZW zEi}fAH2lyA_LlEko9c{Q>9b8r93kxpSsMJ`7gol&JV)ixuV-eE?1{W5M=0ZFhU$sj zYwOJTgzjc%KK&8*xrzi_$Rupw=9%EwlP>lEL6I#Ft?Aq{f%i@Q2WKmT6Z<-0MP$nE z_HKWlMDd0mNLEZR>UGW47d$Cvn!{Xo%_jmr>sClC-o1qCDCzn}Sm)8k&%ymRTJ6br zT`jRgJD6+p8Xl}1p<14W>8~kk6P~zHWu}kGuqnb2!pRc`lkBEQG8PVeS=L=`5ODNY zzM~tDZH;<61cc;a8YTX|F?l@md2wm?i#dU+{{06~YL%I!KywQ|3yJL!E3vFRzgXO7 zYTRqb;dV#n$+i9jp4*N0CXJHfc0mH4%fh=3%Uo3blD@CYF1wv;(cKhA@Ox{cnOJ}1 ztn4|blB)e!YBf}1vR&8y2bT(TY;5pZC_am2W4oXUusO#R>W)={IaI0e&`swrp~DfrHqUJeosm?ZFrbcLTX0{lQXOxS5Kue0R2j7LC-o7)~3gmfzct?16HfUG&r6 zb^|K3Hiz(1tdZhIum3%XkNb1V)9F1g28I6DQ2~k<8a}^A?FlyWb_q@A&1gl?r4H}v zh5!9+qDWr6b(cusl?7j%J?{+BNJ%@dvK_ZrH~SFL+)xsRZwk?!e{2cC%^wNIn>x|% z-|O0Pt|{U}Z>JpA@c45Ei`o1_Dd59_$1gB5zL`sWXBsP4`x@bKgLH9n*$^0G-AVUA5ec8O`c4gcCD*l_ zW(zKd_Z^pP*SC5F15aSsUjW6o*B8rr?&pab?|T51_sMvNd zf>wgj{lY%C4Q=;pDhB!Vu`9K{n=aIv=Qqu2Ooye#* ze2vwlsdEnp3nwlrvaLDE1(PVoAGB^^w7J#7d(j-pwllb2hiHF%W208{#&QAJ-*@?d z9Q5OUOtO%pjo&R}Rt%fu9KC8GG&qthHql8@u`Af@M>d>4_xDNmm}8j@9_x8b^iU$6 zBSIXruE_mVyUk$&zG^>f6xgod0H_|Bz3O(DOX(#+6A9VS771-D@zB9mbnIPiT z_H=lB2y`X|EC~B3c<{oiY0*8^*|ui+m3gt8K7!6TJ8NS;Z740w3TL`-N`Elx+HJI) zx!lB%d3(QRXK=NNLB70z&XY=${xPvuj~$iW_uhfs*H1B*Leze35W}%15n0WW1jNOm zh(f^|A{sTh59}RKMvtpTx=ZfyTlf1B-|g@^r}WnnnaUA{aHw@M>D>P?^65GE_Q(l0 zLI^V@dq@i~x<@vDSl_g&4c|qf0s3&;JMr1GM1sM1a+`f9#73L zO+v9nZ6W1{kIwRcxpqM+p7Q8;v@NExfp4Bg2If*Qk-L=gLxOjk!tP@`?n_HD@V~N4 z%!BLz6y`&NQ%Xdd5X^a15|${o?mrk_yPntHjE}k`gHfNzheHBjBMKh+)Etf7ezboh z2Thap!C4|I-mMBvk%&A~Qb4x7oX_g3$gEi9h6sE@ZEyB`pQ~)2eqi~WoohV+1xN=6 zS^owBNYQa(EQ4yQ84CP67MF`o)0UxVI(IWuWQDcdu>zmV!_j{Jraa@>we* z(kx?VUur1gfNo6^fB_in2a|P!7L?lAWHJf59VD;&AJ3oVvE3qq5_=tOAHn2m#VB<5 zwn#H!hNyR$fWP0Ev4}W)ODA>DiZB{TS!P834N}sNKyM=vU&;SH4k;;gwf{x1=NtJEWlCbA zq=p8;@j?~Fk(vwu$UZbNL5KMk)s^vYpMU1mwJEfcwrgYb^`4b3y zLIAQ~AOP>9k4w`%d2+8&ee|){FR2Ztq}%t+$RFk>Jv^S*G0C~COFt6)J+62oV@)J0 zP~%dYJKOm9_|D#*nx3AL+wDg3W@o2JMn=ZL;bDGRS;WZ5N1x7ZZ=tX6r5H$QnMV1a z)0%E9PrVPcazGkGy|JqUN{5mPUY1&2VWDUDtg-ctGb_$~?r8N>bI(S0PqQu&pq%|- zQ9y5?8t>oKskkiw#~*y2q8>r2F!5B(F_LQAz~D7Ln?^cJ+f zPm3K7JYOr8x+m`47~6GFG#w(GLLgP1PM^az(ps3a z5~L3&yqoWyFls!UQNa3Hnie>j2HL&lDkrqUUhifq0jZwO)(jDZX#+xdG=J}TD&SIe zr-W?=ou{WKE}=osZ=Gd`XU<%a_u+O!W*?OhJW{<~=^xY`01Haee!5#Qc}_&UXUuYG=n99Ua}b?Fd~* z%@!wGn2wH)FB%#%i;Hr0cBjYe}4d|C0$sWFhs&3dqjD!eX}77fyqX3`3`!C1+{L7~;4^7SG}z_laME z+o>`7N20NuPtxkouKM>g$0sL>arH8NXa9IR zsS*OPlJBYF-!?QzI^wuu=5}R;$V;1|*%$$t6g;L3RKT;5&9^Hz?X8|zY@&^wh5EVe`=0eF|JgJ2-=q+Z?)u(sjWU*W8lkEOL(hUWmvRq=+}=y8qv?KJ zStZ4YU!;1ndF^q}pU^iee(7EgUwPc*@Kks_GM>ihjjz9+jXt!2ZhQQNN9+9WQT*vb zKb>;3LXK>8IfQaUDpqZVKm7Djgf|&+4nyQQtpCSjpWgfT;cGS@=pl8X3!qm5>>54> z-m{<_51|ZIDhXx}+$u8r!-!g{St2c*Z{9s!5RvC3Ql+~&=)#Zg11YYJ1Og|WNeKwx zfz{P;u+J$0md(vEl7i_2HE?fU@Kfk=|4Gauxpp|mgx;5TLylzs(PA_)F$bFOqsOLt)eF>nb0Tp{knbuRM&H9!F9eP;q{KfY^KX z+1;=x2B;RM&sN58CE^_O%#o#v&ueYX=5O&mq zZTx0xHQw+&n7Zjh?%Q+y455hqAFB%13fNRo!>IOcc15EsHwIyzvkFF|s6;bE?1`km zmK((?_#!Y@mK>`sbl#USN-ijC%f?nT{xhq%zc)R!YWy{YA9Li&me0G8evT8GT=y7ot%QJn(M@;h!dJf3CCwQAd>c8 z9NT?kFB7}gBV2ENDj~~7id-_iO}{_0AXMyN7(mEa=C0BnVw)Vy9(ts0*)E3eG-{iF zWo4eVrMGy$4#kRgAy`A;Dqm7Z(?ycZBHJ-M*68qGF46rwpC~*a=Y<64n^k@xlNf;} zi^C#FS&R)?aXAeY58GGIgI#ydqXkv9d4SZd{7NXYTjRqmjooQ!c7yF1LVCFL_fKM! z*4lynqf}uHAM3Yo_m#&dChNy9#UTMprv8SR#b3CVcc$F?h9xsU)p+R(Tbdf}6P1e{ zZTDyEMX`$#sv+tpR*PFm)+Rz4DFkS&SEN}k87?COJ@AtQ%9c;zSze3)d-zz$aje#y zR=<|0&kqnWQmPBH-*-`-uHH$%_;EfFZ*vt=Q`q$~6&= z`%u~2RE`WYsHmbPn*)jTLLO?b+sWGf|>hN{C|>xV}*?`zv8HfM7zsm`L?2dQ8%sj>9s}2phOPI z2I3B#*BSS}b8>dJw6Ou~T}n~)6i7#=0X#X2ii%2FS`&vF@~wsJD_rHHtT(boC-<@v zddjD2YRzvU#sW0nhz4t@)|3{l>>dpV9N_>qYk}TV0)~IO!0DaDZj% z`UnCKqS5-r{PftszP|Z|bNP}YOj;jp6RYV!-@6Dkvg`v1kUj)S~=#`gmVw$n75|!)8w;Pn6Au2e-k77h- z<4jr?*T(wRr-K9>?`uMDJ4uZX;YO-HVjZi*eWaJC!A8BNmoMHvF?fYxV_hAYhvy9v zlDj$GU8_63pB>X4*bkL+0UIsEgNnLxQ_!kveC$Q9igl%x#PI{>`D{~j=9u-c-|Huh zM}NKyzqT{H*k-HgU{T&Y&}J^l3?O5x=5%FMt`9(lC~qlMUG5xdj~vx;Y#|%Jh}-Zt zXfU1VW9#X7n7hV}bY=H`xq|tX9jRI4&x#UBg!sZGjaW2e$!othR%j^5>`1MU!c3X`k;C`V1&X%Ti~Bbx-tbAV3-xu25j-p)umcCy$LfyZ=kbVNmp&gFKZ`Rw<) zxjX30j2|B_9q`C9&F_Zf-DGF3;Ld9cbJ1~aV=(f#$ZU>_ubPnfQ*=IZX<6cW#NaCZ z!7PeRZVC!PAwKJM*Lv>s2CXh|7A=tvGhA#=Ag~I@-Rs)N`W5rDT09%wrrh&XzrH(> zPco3or-#X0o88WF(yP%~oo4txp|y=)ptGW<3<{?gGXiJTd0uS|;l9Dww;Fn$=&Jr? zQ^ihp5Xj9KpcbQn#5;7suE6Xo8yU1-?^%F$C8Q_yUMyX_^oq#O{mCf>(3r4F(UD&M zdZ;~rBDjcjABj?WY`4YM1!3_ffut*lzKT~eu8j;>_>cX*`@OT$3plz$Ib3c@PL{Pz zEqdO~54{h~z2O=}2&>y?0qv6eIh?tXzuJZgtatp7!T7c$o%a}+_0nH;9{woOzTmxB zJyKLv7%9~QbCCjXI^G#k5F%)vOCdt*J*XoRqe)*=JlBq&(|^6CHH&m=rgZ!P(hL~L zilm0FgUwGh#uQe)kFv5zEG#Tg%g4#diGhKkn_J1ahA@-Yb}O7d2gdN_@dg(cH)=)9 z_A&q4hZzguky||L`%%f@FQFEyh?;L0)4VBD4dP`R*~0f>D=fU-iGs~?cVwG#r4Nrq z_wBnngEZ=DiG=E+hHH4gz8tN_xMpg3o|(Al-gtL9?Y`Yh*PP2qLzaqXvYbQ<#M=xg_JO}31^^ni8wd2>f*Kc)y@!o5D}KrddV2)=V7 zU0$zA>FL4e6Nb=$rqQAvDAqS~_q9&^kF0$>r)0kFsI$K=Bb)N+4iNaeJc`UqKF0&- zR_;wY9jX7+1W98+(&<(FiKy&r{9e4ECSzE?G2nL5#Ak<^BEO*EhatNhXS(Tnr|(~X z>@()@^7bB{nD`0>r<>O%r#dGkO)un-1)fyL-RFm~T+!SIg4OOD1Mjp0g4gI#d_^<0 z7}zANx4I))M3nEYdag1K7uSKUscid_sk0nqoNv_UlGKx&AOrmspu_^M&h+AORj<3O zK{N_xdhA-m6S%#xw7%rIK`s4)#MvBI<~0wIB0RG%8n6#HxCZBVlZ!m0;>^l@ju5U$}Vw`oKO)NjMiElmok?Yxw)X{kEqV- zT~f08dy)x12`z4e1qR&G6~SW&K32?9z8ju{%d9wr1P+!f?J0OHaZWIMpY(WQkWB)_ zV9dwzZB&@%Csu91VKqjsTy@1spOX9^jcwZNqJ6DXw#U*xs;a^!S`8!`aHN!^R?y^p z%x)BvT2taC-c8Z5%P%fQ{I1vL=6JX2juYAcy$6Jm>vLHZzZ1b!X?T0GB&l{hY-B`; z$9&)Ge*yGwiy;BVo^N_yX|mgsU+wt@vAv!<>RXCFLXvA{=xfdk5Wc*j*0k^qV=B>( zLUWy77V)Uid8{04^=-fHl`>Z%l2-K#%aWf-<2FYm0JJ5cUC`*Q(Pi+WkssT&KW^06 zt$2>5bA*@2c%mOr5v_MmTd)}pq{%C0Cc!@>OYQ3dOXx#?4U1g22ksZvAx_FdgWeB( z=gIW;`zD_+OHttkJf+?#lZi=){3-bpibJ<3dgW)xgL z<75JEzT$hrA~CM1+WhGRO$ho=M4PMhh27`<@;t0W<6o1zGGZh=yr|De^;blRhO_ z*6R-qf%dZn_IKD{*IuihU9hg{9uHSO50nm581`^12hzO8c09#IZg=9mzGm2-)H0(m zcksbVe5ZNyp>(;nERq@IxB}*P^m069y>U-Hqiw0fDS32i;qUJlaAK>~HN9cYhm(+i z3pyafcUv+8JwsrI@C5OB(t507}Z-=P;@ zdndMV-wg-z^9g3h&?=-D)@Uw5tx31G?EM^X^xt12SM3JR?r=y+$1ZnA}J&a$$V8NmIO|?;YH}0AjP=y--G}QZ)TK zv0@q=!@CHXP-W)|Hqw33Kpaa#bG(>HXPPlg_+g4%*Bh|SWg$>>(+o1ge2w{s;*APr!70p zFx6?R252G)4lZur(^*&S(c;Z%V%REgxx#puaPQT7E>BHu8| zeE8^AfK@e2^5YMYk|rUfZIb+%oNt1h{S8cE`1_844IGgJ^KNj@oIg1w;+F%*t=oHn zGw(c$=M%$=biGXUY4WzL2L-$X7K^7rJ7tO-@*(rBEVzOgf}c~}w!8x>@^q9x6J?@v z;!f>!Ve!`G%K4SrJaox*eKAG0+>p*h%!)k^EvtUEPfHjqbDzFN?)CXKKxctNMkai6 z!Msz+rbO9m+6}{>arEuOYnZQWr$h`GyPv90AR;EFxVf1yS_T+HCiLywH+~T|I=T>O z?hGdv7Y8A#3E?inhI9VB-&o?@6b)Swl)4}_;b*?*1iz1xf1&>w`iG1&Gvznmkvk^3 zH|)wwtwbyRaMBdhq8#QsCpLbPp@Hytpx z@A21vc`>Z1L7S{B7I35!sB_s7jCC?K;3DBgi&otSkkcmSFwHJAk?-C)O=GdT7A!KoFwR8TOHn1z%@V?3s&iuXSD zGHKj5r;XD}6Ob1@$FT5qHtSHGZ)09En1r{^mPFCxdVeMLm*J@giSv`pyt>e#v&2SF zt{O+dTt9ZIIaS3Du{rC9{JyP%t{e99vT+(|t+!292X!Hw6Zaf#)~)hr$aIRfgKN4f zS_C_9V6NoAYO;mC-@RxfdNKb9s;m*AVScpI2RyA==5K!!Y9z7mBmODte_22K;ncJ&|#IYK(a`lw-BBxue0t7ah%kAr*ChPKa!N^yUXh~F)~K6NjKx9qs> z{W2=JZ4pE+?e7IA9WPU#Q+MquPW(6)PqQ18pM8grLO>Ij-#GnecBC=o({%4mTHpjH zVpcoGBj)uyw-bx~)SqcZJz3&#e5AEKV3O;7bv7OFE0VUQKy~0<&bs{G44adVDmPK5 zt&Jzx7v09Da2>0gz_n46TMRYc5kH}jp51N<%pAKQ{^U1LK81x%rd07jMb>8YgL-C2 z>$=0aoP(;*j0OP6I-Dulb`ktlTH0;bWYVBLJU(vrczu|rc!`>cnTwb3$$*_>5xXG0 zIWNM$VnqgexjaBjAi2S}ek@%tfaWX6#;)E6h8>0P2_ z4&#AX%~7zpD)eZfpaZ2?8eM4U`H#hm4fkp*|Mey@^AT(rdSHH2rky)U=l9qUa|HkD zbi)~#4q>wT*(W&^3fT*^ae#X%ZuXj#rZG~s_u6)soAPGpIy$YO;Ki&P2dUxY8fRm@ zgfTnfDgrRy91;Z93(#~xBP2)OY~LiewPCr)~GX zts!jb&9%nd`oWp5sO!G!T3Yr|NeS)n@bIr+Ovq9&x8M?k9^u|i4w)SZubZttQ(RuX zg7f3y=-8UGb49zNNIURx;`pyn#=f}BzFgyXo`*>oTmmkc*@elvzZWPPo!(TbKJIKk z--m>QwgfU|8?b|C=e}9~jx5|EF(ibPSvI4YtVyN#-4K1?y83mTSe4!kNFO&p z?YPtbKH2>=O;2*7V(+)J{uXj$0&sj)ggo7|nzNrl?48zM+cJ;0;3ek-J`WX#gebiZ zkG+<`^F*>iZt$8Ctq!m63A+{LJh+DiYBc%3s;!2$ zH6`9I6K6d2*rNg~uCR@{^P)#6d*A|c3b`BI{!BxQ;aefcL;`0I>HEz46L6K^N(LLD z&ri*RyTj3cuSw{-A*%L#SeuYp&S*Wn1j&u7ygvzg;h(X%Ie=#Q*;p48kMlG)TYC5` z(P$zb{I1Gx0ESMIDmf{0<3D~A8h=EL%+8)=4Uj2oA~T&!)YE;s^>Fz<KJPQv(@94osyY z@KXX)nuvm>&lr#Y7Ao0R?1rf6z#PO#!1beJBgk`ioNl>UOix|?k3TUSDME$VOu6-v&x_3yGq z3G;;Vfr6H8Rv0n2?{c0tDI@%!&?;N#0`J#84^nrv#X@eWzwq8|-;^7&MpK-I!Z>B&~ zlD-|eY2o3TDtvAz7es10I#4`KFQoJC8kr*nS2{lE@#AMz)gBxbfaCJR-MYVMOG`^C zdqLe{$<>gETgSt@vQ?lg<|z8;#;hU4_-M-_d2b>$*Q>}?CS zy>hNXHqBWJ6)2Z|iL)o|ti_eQ#A+62Vgbd<;Ef}}KI=5}CF0W3{g(ToAt9F=ff(4t z#Dd)Y!0(0et8Aj1w%ev)_oRWZ=EYp@rr?B@T>YWyfSHkTteau zLyp5{f+c0&emG(nt@SBt0X3I=dsuRLw(>sFll}K@mBq4%v2<4 z)rqG$wf~UuNjN|nGX7;Kmv{>$M*5fcjI5>Y??9}Nuuvj)2gc+4%QpHtud zeB-WfYAT!=UXTjA+Pr%BW7S|n7ScS%81X~DYS6A}`|4ppkd(5Lfi+cOLM5nKafnYf z4C}x}aLk-bNlB@+OmKelt)nz_e-lOz)Syf1?%_&Pa&sr;7u3<5g1=(d^d%Q>3xI%t zfJH>aD0)aWF?4n}GdmkJbJ%xw7wgI|p{siBCH%EKIV~-%23lSK^FKMvv||JaBi zomLjwXzkP34e)Oj`ZOPBFoO1}o#n|ndJv-s{K~g}oWt9a>gp-^%b~_UY|EjG0JmOT zNm-Bc=CBk8=F+8vtQI?#Vz6-(j(*bE>^G~=?GLEdg^%Oea^In5ajvI`ggfHU#XDCr z;cjsOLl;)1!6~k!HqJBKL`GQ7fEq@vv9yFBqED=@VJ4Niw`DKfO#e|(ddNJka<7vA zMvWOP+|i#tSRtDS9zJ0b3GFG=N@D*`A?iMhfbflKI6I#my-E%B*-EgDrwL2!^GJ{I z;G>&#piH57IYTb6ZAPOM-VAeE!P`wxwu#5l-ir$V<(smJVmCJVJy1i_$5tdAxX0b~ z^4YJ+iX~RW%BUB(kT^t`!yrAeJ3ukEiRgO%(q0#XQT(Qtes!Eeq}$5e8OdBMvqx|y5Zeja48&lSnN6uOhwq&GoIUppZ<^N+Pt zcq^lqihNceS-@>VWVL1(Pn+l6piiSTKMZ0Ej)6cM3y5K(@ zc-*U)vZ#4r%}LN1#m2TP67p4YZRLmDB#0iVWkrec`}7fOz2`xo#8c8kq(2aowQgG|t@3-hU0wTYaBV&!rTMCh zOeHXeC01xRL<|kdMMOl%WSzMPdV(7k(zqA1SYc}nY(P~G9+Q=W;5K9DVI*^#31c0V?4wf- zZX_+Di4$d=CCwp9NiP#VUB-%>0>GZ%ANKsoIDx5iu5$G331y zb|G0vGL1X1E3mjHR8J7!k`@WdJ%|5Y@md{%sKoHg^I~zqwgg=KZOnZ2;(js~@waj; zo_`c^&rHmJP)mDCPd*53AHh!j1;=}qq z+TEU{+?mXp?;ebI2DR2>dC^XjU-!Dc!_-0z8e-$cZDUVbiSGlJoj!M@RwEs>gWddG z?$6hWB#ev>GYxfFU0qv088&G}7I$~#M&&_-kD$`!dyz?~`+pwxG|AFb=SSNAMcZ2j z)wOkPqF8WucMa|i!QBbLg1fuBJHZ`-1PdD6gS)%C1$T#D#FYh?(M4P2gPRX zC3DU-hd$#OnMsmE1nVaH@Tm-UMOX~1ysoDO`T2ppkytq{X*D;!!eO+bEPN2qBmie+F30A#QXv>(K|10JSFfGUmLROqBT8gOzfA-VTxCOSS>ujj?a-N zq$LPgX>wyQU!WI+7&@`3H2sVTI`vth+M5o-V^?LnnO>ZMGsiV6{XUivVIXZ{QRweJ z+)AEteW`x`W3PJKW_kQipAluhoN@ZEl!_r(0UoxTjOotf!$Rvf%8x@lIIbtwD@@!m z_c{be0`R@7X#>Z*Xi}4^zkY2|j}5S0cB_Ps4Heu~JF6BgnU|GqPna;GoyH0Q4cc*{ zi}K?h>CY}4&P7jY2MVYsSuQ`2Tr};tv@BNXgYWL{rjD8b_JT^0JimV0+?*PR&59)8 zvzL~#04eETzkc;mZ^?A;JJ{{ycT{x~gg8Im&^267ySvfGR%XiHvp30xUv0X~sI&$eE8U`!YB4oJ@+7c=G?oT%{) z+ZIsshIYX~t|a|vz1lB#qhc_yX#}mQOpd|i)Ox){Oz`nWKqHlHytOr1kGVNk(D)tS zWe1<_A>D9WT}dBgF0yR9aE<#zBBNSCy{lY9yjiB9+NWP2pgeaa9Ya`g#?53sRnou< zJ6Xp48<@_)+Hgf7^0S79>?m}hefM;kpcnhziXOv`G0_)OUVZ`2m)y=&oK{-x2A>Zt z7I@YBy2I9s;?1r$`X{$-5TP1P{EXNgUagMqwjo6 zbF$K;_^G4a{fbX(57X&}c)FD@!MUB)n)s9SI_TcQ+}5G`LBW=3_bxJZ&xG`9a%?d+Q@p^o=4sOOM>Y}BS{yKe^NnX!RYGZ z2QED@pF+L$q_4SoX~^6^Zc)#SxgI=DnRxuP;9eqvoXik^NbUqZy%siH&k0;4f8kJim zi}m2g&x-V{N&->WQH4Q#ESWOxuP9U(9&Hd{pt!iW=T9%GvXnp?ed6ebjgwPFQ&SoM z;DQL`Aa$$@_Mzxn*+4!XEnajnXsh@RW%kObo-H;qiFfPp;#vyKuQ($GOJS0FdoEn;@esb;m9sUQCKTRID{2nMN%Q0AzJ9!u zt3g@%6+zX4IH3x;0aX_WPLw$LXP9EYqVnQKIC#vO;Q2{LqBvSI*HM_HenE<^=?;~M z^wSOE23KP+j|x~xbpmyiEd|TZ==DSnWn?^I>4AreNhsAC)0>P&UKbR8D|rPudIFSi zbon6)LP5=?V)eQdOkKjJJFiGvEE*@9lMRXS&yM7z!DFo#B4>I~=SvPWnH^D3lphWR zTH}{oedNSW@%Iwxw*95Rod~>AycKKf@NUkrWj zw&~d#_u~YV5BOc+FM^|VAD!Eog}^%4Xk2TK(`7He z9zAT7$GY$Lma};k`MKfauL7$G?$PIclHq0Cj9_^s{kmpuYJBrh|I<(5aqRTerru^% z+Rly%z_qKFs~x-W0)iGmyJIvgM^Bpd>|aGY4+w`TNTL2wx!!a+-U_5TQZJfD%MK?uB71)Oq*JMO#nj6i- zF$x|xxe$QQ#_M@lpF>f$V;}V7V#wVZD}qRi(DEp$Z9qx?I%1yOnEK4ct5vdCozxyS z=u|(m30>^eD7@IJ&--DO#(8KN`OS z%Tx-;V^ljXin9jMbwY4BVLwpL^u#$a>{EOIz9C2YNJD+@zV&;nWXcgA5G~ znc3Lvoiwada&ckTERNisEH47$1UDKoW3=z{m#<=)noH`T-f=gZ1Y9Gp)|&@?E%wf{ zb_4U#-RWbE1W#s`SwacxQT}?eLO9x-R4Mn=a1i}^(c{JzbA*LD-d38>lt07Gd|9)y zd?2?#uSI()zSS6Uz=(ekabW&{_R-Eg-P{b)mnSEx%b$=hMq2s~Aa`s_i&B7tq<~d9 z#jhAvkG*pHVk=Ua(HCR|t_Jjw3rE{`^jyQwJejSXdo;UXo1ED0?NJn>*TuMD_wdl9 zV)b<)7Z>y2F@U8k`!TH}ha{kis9d8f)A7Mz<>pv$C-~gSp!9Y-vZQE;7bnAqZjA(H zNEvdFXxqj4;e&DJpM|L69J$wfG1k0n0}((aPqDTSDZsBAzIrwg*ut zj|iRvPMRNnR4O{XDuI-lu4vee%@+B=5iKknHed`n;HHy&zJBuLigklu);kNvbKI#S z3y=LiQOknFog0HIlVE?j3XGbDM(F44Fa2&v0IaP6lv3bEht$@x#o%*y4JFZnLL(s+ zH8!T2PZwqxM+=7yXOYhoVSkjq?W@W&iU`P?%$xR6-pX&WAR~Gkw|+jbJ~;gXb5F%$ zJeft;WM(gB@B=ODh&ThctK=t*Ni|J8`Cvxhx2%d73y!viw6@)4w~bg>SWqwv)VT#c zm)HH)+@Qy2GX$X?g)BLFQ9sUI>xcnQdhLKaOAPAdo^_?03G%$sv$G@Z3SRcR{l zv%gtgf+e+H4RE?0H{h~GM3nx4zIT{(zGiJo(eI@h|H4L@A05OsVIibM3Ij((Onyuq zn$ellMU`JQ9Ndu~ykuWJQk6RP6lW2epD^{N)#uwj*Hz(x!Tv3b-GciHlxOMS^d#4P zVYx4`ItY~jj=#TXuG+d6@A;%|ok`u7)o(pz@cEe!mIvD__decn6NhW)7GXEhMzbHz z1pz5HuTOWAF0-a8~B{>7)5T0;wG^ygboly8a21;KpvL8%w1g8D19mab1y zN9*N8mCK-kz7S{vk00xEardGdK0)`R3-Caq>euvi_%9#F6(sOh#Sf&SDYI)-QLy&Q zfTVb2Z`akhAkuGOnU&CY-2~wRz3t`Y$JB$VgBtzFa|L?SBI5~Ymwx%kk-Z+R?H@j& z2Q+j3x(xQPSixc~lZ>AhHZMQY8})1{N#jb{7=SK|P|d<+ZF8<|XrYe12le&xCK=47 zjQZp{i}-QPH}mC*$jIUOp>l59LHTwMEj6BWar0n3T%&XOmg0C$2f=NA7KOUpaR3CWk`m$e!QsIY^tl2T2S4d665nr_4FcAF6IR3 z3tL8#G?xdR5a|?N4>6wSwq{> zjY;V^va#_dc+&~+=pgF1_Gu5Ex^y2J`h~+Ul4{Pjz4@+IDEPQ*#85aCqw6ZNFo{9A znOl)#R^!^APFvh>X1^Ssoe2ssa&e_**tVx7CZe<9mh>_JaSgA8@h`S$H=)hN*0ID* zMz~_rh0Ntlk+s+exC&SVUy-4;??*pkhe^tl(~(B>&9aj#$dZqkB>UUKbK}KMn4VEO zO|Fj6r;V23u%0D@uk*ry8>l)N z$>L233WBIz8Xxv9MZOMUb0}on;?RN)A2nSHB6kS*<8JGUM;`;qmQ$KgH@&3M{ghE^ z=jk<36?wS_dTZ{Gh7I+&sjFI!AtH&H(0{fuF^T&z_Etof>U3zdRhRdZ%-evLBGBl7 zz}n#Mm6#M3HjT?0ce+rPn3Ek{<$KZ?gCHS`q~sL}VO^}VRx>s>G<=`K_lTPtrc~i* zGK!+u@9O92{jAo~pekfb)IV*0DjUh3~o(qIZw!?v{~-e~ale@0S__Z-T&+c(FhC0s&j9e0$m^=n4iQ5pyg^9Zb4u3aZSFAr3(ki{hwGL;xXvPN8{ej|*anGlvR^#dI*S}u1q7$BzUlv5vY zSzDe7_ap{!_T;uZfY#C+f3>&wpiBtAzIIBc(-4*&+1M>h1wdiI-yR-3lnH#&ls%@w zJBIsGO5Nd6kz`wDWKdrOhXp~imd0|&#MweXann0px%qUnOXO?BK1tp$nbjv#G4+fW`(!#pE#|evln^Ek&xBqGDVobU@x2b-j zLj8W));iyV#?N)AsA^({K=ND0Ap}#-L7%iF%eeLVj>;{U4lKVu?yE%0MQKWH@{?(N zr{4FfD&&S`IY&oUdwYAJ3lR|BUDs~lP&|tg2 zDQJzGnamS-kxbmT50&doLtUCZ(db6nO$t5Rxv?EcCI{D<94|>M5TFcq_TiUjfb`+r_vYu^ji5IV}z^1|C3Y{=TZo6pab(8h?)Kr0NG`OkY zB_?C6nw1A!8&gd1dUaF;4q@z%Y-q{7jo~N-$BX^_Zwn(c>-~muv1BYuenmCGORExt z9p;qgFiJ)m89>@)w`mmM4V5Of=n3)w5wq>Y#*Z2W0c1-;^Og#)TJdqssjPR)8oKbU z+`92lq2SeR3(*BiZjh+#&aK2A6Ej67a<9BXRnkBrI@2MO*(ar1Z22_Iph*KVA1_#? z&cJEnOzOZi$!(o%-_i(BS1{Igu2?)Q1#*WVi9ZVA6qG22ukd>dvOTHn2k@N-@@q(r zJTz!ejW>Jj&*!~V4-1>YsTVzBq0EN$FscamB+YuDVxS1t9loji^MPdgklP}x8mU-P zk^_1jaeQZRvI5VfpU?QZbLNixWs_eDzPXFx1U=v$+A!>%^k<~u;t35A##ZY2E~Y0<5l%CD(D3R z9GYkUTo)B|bZoDE#eA`!#SqW_ol26E@a6m0)2is`(E*Sc9lBzZW{PaTrK*d+E-(J7 z$rLP;+kW#=6;5P7STV%h2U2nW=Jf+QnWk9115YYSznifasTq9+zkdNmkM7!-ml1OG z;>KV{CPr3-DTdX|3i$ISG-4g}6{J)=Qat~A@kda0Ki$t0(Y0BIM^{kL#oq_k{TksD zQ&J4saHV8r@sAWkGRt#RVeVfbz(iaNFc37$U8-6jRoVS;6@?rN%>$RAAyffWY_PK0 z>z!rU`hnp}j_)8njNaTwYFq@|=so!LY5nT!`6;DWj`gN(>Z{kYVLF|3iIAa^r`*!w zQlgGG^=A=7)Zf+ZJL)4oZyRT@IV?5=mPMWImUd1mkPZ1tii$!60^&5L#iHIee1u4V z`)g!sYFHEf+}Bu&*caqd@I@mgIydkspU@HuOr+nzt>bCXRPpn(fOFNEfV*Hw-<=yFBfm z50a8FFan8RfQ}#u%tdjXE3K<_Y3C3YsqVW974H=3B2CPd_&qKf z%0L|v#XYQ%zMJO>LJS>9lN=DdXtW^fkfNv!K}pIQk?PatKXGa}-6h44D*IZHDs!&h zfh?^3uoGuXB5rpp(f$tfc;LUJXOP&x9B4o`Fna&}4uII1cm5CLA#C#hoZ0{Xl-K@0 z=FWkHH-NyE{5cE6QMny0%wR>+QeVFkyu7?fVtA2^ z#SR*ga&ROU7Z(Evhj);{R$hD%fJeE1@oCjzM5C1b)?y``Sp;myhp+nYkKx52SxDRi zt@>H)^Jidgm;jJ9K@9R2^k{LiN}0bGa1@G&hxyMF=Mw{Pn}45}85Tg@{J%Kx9q$N) zfp$!@^v-It&etXv=Nuv92dhR{#+|VZgFHF^)Hx03j{fh-kqWFe!|!gO<{CH!>4Li- zd$H}Nl)ettV=(?|Mk$-NG3^`?mY!nR>BL{@J58cJqNu^yQu4s6ejD9nWOs?h3*uCLSGQk08%0)juDM64`x`m(*Asj;}VEK)D~5`cch z;d`QM&Z4AoY@mQHi0_85ZC*V1(U_sswqgPmEukcddMUFj|hD4xBs=tQQm> z_K@6PyQMW(+R+#wO8}2KiRkh)qR7qrMt*3S(JJbnh49iDB>1DUz@&wB`9t@`kNZMj z6m%lI&7I7*bx%Q6RhF2NHjX+2E9YlMNd5_zH|VpU09Rtwf@ZI?E9R ziZG--n8EZs&?hj<*W30>hc-5aS=3uwKm(x%>?+sEnT23HMNk!W_)R5d(exPaF)>?9 z-mG%|YZ_SWa&>efN=xj*D(Er~3}6kGg)EO-Pym5}Non-K9iJLG$w40Q6d;Ee65buFlu2xg$Iu>h{;xpbhL7 zzM(oaD|Mu|ga%#ToVUlD(2<-(zgg^n55yathPHZVT9s8czGM|NihPtO6bx8jzkWTq z@u0&T4!e5s5zNZU3JM7^V8dm!cltZaUoe|Qyyc_JoR!G;@cT9oyVu|vaSs>oxC9$r zNFt@BfwcmR`XGH7*fepO*-Sj&JaF-Z*{KRC~(uNF!`sIb6LDbsx4X33qSA?H)n} zo*LdZmc_)-M^nWnR|U71bsrJm?nW}o@OjTJJLGvg z0OVFtwnxO$(vl2z()%{+Ns_XW%!d2I34Y_b;6+)2cdF@CN-vPr|u=X?0#ST*J-W&afspe z-k0K~j^x0|*Rd-&xYTcpa*L683%}+@>KMy5H?f1ipCXjGkB_}l=@ec2CMOh8uE`-FzR%?)+VfvAAQ=BNBJ^%WAkMXl(#HRVH}9Ep>&y(}_yMRt`z zaa3`jX%vWCmxn>dG1uRD`fOmtJ<`03`S{hO`E_$Eq^M(XD^FYYDcj_zLfOOj9=4J( zqI2qznXzo4bC2xfHn!K)#s=-1UL{q~wQgJQ9!{s?4Q0o(3>*giM=_9lf3>-e#t)&m zL)Xjux!y%ldxjZ^bp{+}VLuln%~$Drg8eEjICon(FOw{yYEUYF%5 z1?`ZQIBzF7A?Ya?kmQRJzUX=<OsSg)z*^r68?93;MgpnxaFXU`LS8`<3RPSOYijDQ+hv%Z^YeCWOaI0VI-TU-37 zC@PXyp3_YBP@FWAC=av>8b@ep#p*E{%4v9>l*s&y`U#CmaYg~KKPb1A(|*=qtSRG# z)KZb@$9jE#T$V;b5cyt07han)Hjb{SQ?$r3s+r36!R~Ly$NB{Iew9Qz(t6l zk6mmSF}8?@R3;dCuF9&<)im+<_i1+F8>ajMuiw-(0>j-^;rfZY-ux@yAX;S8O$)!( z<9f~o-d7NbPeNF6-6?O@0^4*#*r5AyU-2szx|550SNJK?{y2*x#)zqe4+BU{DnUV_ zmQ{Hf892avH)F%y8_SBEG%NV^E52N-VQPiX?U0g;Eb#vRo;l_(ba3mE5?BsZ)#v** zomL&=gRiD!LiJu1O*fi_(MV){&;{yguf0x7w{3%u2rsp~OXhTzxoBvhAYXV_Pm#6z z$Q`zXia_GfQc+L_V48j_F;dIIEg;dRi`mMs|R;R51W z_=?H_%OBM1)W^da7fgUiU^aHnth0bK z_t0enzWDwzR=KGmzO4>+FcK>P>*V`aLFI|9t1dkzCihFD6&p@~UV@FCz1sW91pv2- z=f{CVA=({GkN}ua0N4CZ61A|fP>rbd*Xa56KEFULpP#RldT|g?k}lKQN`vi4IYzzp zgr!q=BHHD8z~p=efkvKuJb4iACwjik>jGP`aSj!{aKZ1hds5%yod#)PFAv? zmcChDBXTCFPtb$9X)M$r_8zt^dpNF)0}JgzG&~WF)I(9z%G@nGez`Us z9*f};YnE>tWg8nycMmUTnvEyBf|tJ`@CHwaE?;HN&dYsyW!7IA@38-pX@=kMDMMTJd?yRJ&-+X%Vya>UME5a6|#pg`F3~Jx!t*KKelA) zdz-#0U|Qbh!Wlj15jC`WJUT?qIu|pVN2EH&F%jrg1#Uow0MUEjp-ECf zVSg)`47)t7XN}l_-=4EQ9Al zjYA2^$ll3t+0UyFla8Fz3+tt2{$g2d`eEAnkgLnJYHL&Qd`T04Oe zr}gNvQm`^LNhzuy_C&9R@|ymJ9cl|7w0q`Ho5By_`s2M19KpK{^r%yKno#4zZcc~` z^Wu2)AS7N!%Q+;6iGSELzV;z%E_CSPS9H_`4<%J9H5=o}v|nVr_>xWcu!*D|VJbI2 zf%@201VZSBwHcZ)Z~iVYGKwMop@)7Ia5kmQ`^k9L#HHLfeSfWZGnnf3Eq7EAIsu`_ zWTK}PCaqebslok_W`a%k3B;rDrztj>8!Oeq*YX9M(|CeEzC*RKgNvH3Hr zxK0UFWjB1O4d@`^Xd9r_ve1}^Kn`TJf>+sZ>rduiUQ}C)tos>I|Kra7=HzW-*V;M# z`=0{5(XdH=Hb;oZ&|F&$gv-w|z zFkMp-G_QU6t+!(iYLz;@rJpOWj&n{o>S->to##nUALn+pdHB&{r@ICKI*N+R={Y3T zFH=?CM7CNrVG4Ee+-JJ?z8&7-?3QXZ7PAg&bGcbBSp-DN}_ z+?P$p*pOrrF*|!1wgNL~{N_{Sm<-y*M(?y;J1UBIGsM_qPRbIy_OBy%?pJq$hIPFW zv?JjiZE5#2Su>mn6M`Ru1Grfa5$QLhTi%j#$U)nE;K$W}jnk0e1fF~XsS+!UOVb_5 zq%r1mU#E3z&y?$GME{jOcixcmN^1+E=E~(gixK4RQBuMQ-RFtzePQLo-{Eikc4h13 zs!C2Su?;6|0pW)rAqs}p;Q^!d`iNLruF<6&D^oF9BVF^ zDIu?#YV!ChOFF=3N*YYSUiNfC@VvYwSynQ6&5^Mq-ub#-$%n4vBEXxY(eLT{=6AN! zNWzVK22vpA*L&EP#S?O24s~Q@T&)J@IHsYJy?|Wr97X%Q- zIB&6{rrvZjGII+AK)Ax|+v7la{D$(g_@lyCt2HG_z^;il3B!;Q8Am4ZORp0QD2fG2 z)q48-k(|}vS?EmBj}&|#r*n{;k-LLYF1O(ppt%#M1q5@*Q(hKgv6o5hgL$PQY)oB0 zBZ01iu;Pt2f$m^Wde&e~$zJT~)~*EHHwU^*V&U@6D{=|r;tp!I14 zypRK_adImc^>=hTHy(!v2gK~`7(Z{g_?t{XI@ZMpfV-?rlD8bY<>f=ygc_bM%AisD z-@9d=kf2&I8)@@oOl~4)CHj>w$9ClUL&6IW(uf|PP;#5Hkrl-nCmw|*F>TzT!E%Su zrpXBXf>RJBKcz;}prPcwxPsEs);K31b8mcbxiTZDG-6Qj;~q^G==^g4fN&)T&cyp1!Bp&qBw>#x}9A za38)KA0Hp$cB_R3J)!YM&Qbzt6_og(*GhXR!55EM|F%in;|N~d@?h_KT|>iru~1Jq znmrdjRimok+MKv%M!NY8;eD|?!dd&2=w~}N&NW~9ZRiPIEioAh&aXbi2f-nC_fNXu z(PkcM;=6^o#e!fiUcB-a z7ZL48>tQ=mzYX=>WE`j8J<(iv^E$=0X+P7cXfvyV9gY>G_^K?|Vm2c;An@Rt9PZBIb1y+p(Gc)08^xFIgXVU~%Xple4q)%>2Bs zK@*UURaQ|^0PbiA=EGz0(cI>!kQPJ_M8C(>1epjeoYMBy3UXOwby{0NMucn>%Cp!W zB`HzXKpJfF7TmYt4{Z8U^TBoZYljvW3>iy!Y&f~HFXsckBGP-0$V>#b9jzTM$P~p$ zXzF*az_^+~eQXcwj z>+9U=KX~CbD{v!-0c659OA(L zch6|@fQb^PUs+ff0w{anwqttc=H>-OMM%!rK$BkX{P%%{wEgF?pW%J2;2~e7}2hTDAm#n0DZ=_XXeFi$#!8;>KzI9_?d-H+=t$g2FAD z5dXL5MOfH>J3m4&?+fxiO5*?hq~8HkJ+MeIAtWQh8ZGzLP4Myucm{uRRDcnm%h6$r zWQZ61wXOxU4y z&J_3d%F58_K{>tUr$;o?_WP{84Scw1-+mOS|J#lIjkhdbPgGj>$g6LbFWS7(?>BRUEMdsG2Sd|3Q|&*sQ1~4t5F0MtLeLFTi2Fh-rzbn_qFEsOy(Q4 z^|__H_0<@7j%UjYVHwGb7#*Kj$=Wx0#_?k}SgJk$1@LCPkqp zw24qJ6;TpwW(zyM`cDw!?ra$NzRFz zAbpO5)>o;T$GUTzFL$ynRIsB^x44EzL_gx65L8O>thPduSjo&5P|{-O_x zKJ<_I!v?}!xo+=LgpM#Mn*E?O;X$(bFacda4LoLsWcW>A+M%qq3V)_)g;zDZD zn%mfX=iB46k*1?eeS%uEcKuab7JE3Ypo|yPkBX5aDnHUspCWega6w*&SY@w(q}y@l zF(%_Yaes|l-=-V6&Fj0BJsb~H(UJ1BR=SfVX6$uw3nL1~rn-%5|6%%d*QH%~16X5amZNWs(TQ9YS#dnnwrXEH;i`BJr>HXl zywRtwW8dA|MJU=EP=LyT2X;7&PZ}1jD&#@3WlLt{;Yj&;nU=c4XhZ__Am3T-^hZ+( z>`~c~q$5`t5pQ%#%EMw~Iey`OP9{gH8+eM(%@bYo&Gg(C`Cb0%F*s$K5<{U?xr1d3`KJ(w&HBF9(FrF!a8rT!;=T_3-W=l8)j1$fl;wE8!Ja+ z-FEE*FDY_cjEK-UWT`Hza@sFR!)aM|RoSp=f-i&$jNX1N$0XlV3Rmqj6IdfAN4ev)ArQhL`9}a?^w8xyW0*NIhghmAJfYlR6_|$&~Xb|#>7e- zqS^&3J8nD8$(^gANB%nkw3@YvqainAYjSUD23*(&;*5Y2G1-oS)DaPT(F7&7n1FKy z=mtZqCrz>gnYIvK8(ayxCn_QHrRER@M*>S1Z8`rJ*80v(U4(0|r6E7`c!{yi(rzkC zviQ^)tG?#WNf#$~aJvLWzKo_^(XGhRL+ta;?7G$(7cwO!LYBQ4+?^mx;2kUqeIHBQ zJ+my|n|AXu?&9UZI)L_Pm}GUNiHIa!Ay81ujhsjvZnW}(Y%-xw`s_?s9!*KVB<=PD zWwo*_)0Q^)p&?TSLT}Mc@a@5hU|5>=urSPQN>bK!5=U2btQD_`qZ=~%?CKGb_jJJw zmCQr%wocVMY5AbG2Ssq-!KP`qD#*j#&vnjbW3kTJ%YI0r*-s(gEpMCO2)ziE`6zNF z5zW6P|M^o3dHf!vWxrA+#0ycq&=3SelQHOKJEFQqH?8kaLsu~}@4tFxQ|?_YLnAX= zpi($yG@ib+-0!aI=o|FRlIO5SEYy-y(iLy|r=-L!GDnO}sBu`W4hPDy(xmeQ6eqK& zwbcbT;2A(Knj}D|5A&XDl1eH>_xU3PdPR&O{W2U@OXly0Qkw44I}&uW(-P=)+>1}a zh@QoeauVgG$6%kCHI7flmE)q^D5|eTjik!S9NZ2Qq}%I3dFc6ETfLoSJcD(A9?WG` z{77TuxCvc@qHmk$poKBI*+h;NnlRNGDHhA9fBa0&hf#TX%|Xi^UV|e@lO5~S1@)rX zkc^d6-W{K&aQDG5{O+z(UT~9nlDtpivV?aPu*v0F+c;zZX(A9({nkMy5JgJw`*D8F zg#hi#+Hk%?N59OEte!ng<{Qg(sy8CRjrGdZ(Zrvpo3F-d?JwQ51FoScYIX>4(#Nt3 zj=Z|5EWzd~g-pA{w8i$ASF2}Zln7N|ALhLhP(3+4ZFC0`)3BI#dGW&VIMW{XqbW$} zFiq8%Yx>%UBL(01ecjDI?EdcjB9mkt-iI2-Yr(=uYzQ&Ptd!YtPowkmIKR(xNbB^I ziZQC-$7K79@pIjjmvqyVvjB~&G%kC-xQ^CLnQ{KmK~BML4qM!L-@|SWt^hJrO79fg z7@GW}rpju)OC!p0_1`bEk35>q_p=pFj6=4ed9J zv~W%nQxh_=<3ifY;%7Rj1U{5a(aawzXv#7VD??Ju>9dVhIfV-X3``hJ=|m zOC3rb{@i(PdP!Bnd%iP*ucweQJ`vSfecXyD>n56Qwr(;QGzcXpO~^}@9HkyP*I!`i zIG+;!gsB0A@@w~01maFV9xdR z^|19L?Lt)UPBPlk#@|Q0XA|l|xv_b?5!FT@# zxD3$HL@X>m0)Rjfg2I2inf*STWJTBMd8IMDJHGC|7#&T}FfvjP()rf|QrNt1oL?#V z*QdsJg(t0#rLj1I&0($6*fOrJoER7wGqbakv$M`-EQBCGXQeGIX-`g0fU&a}^n^{L zC;fZ*Wt?kxXR7j~4E2jUDvi&ZMYLuBxrCvcmf7kpt^(bfth)$SJ4wXYHT!g}A)Kv1 zn}39W;M#QU+S;0qg{9?Unpm`wx(gyZFgSfE<6ZTcU7 zcZZzI(4%`pWLiIUPzUYhlKuKmzE2}veo6x-2n0K zRA+%zKIdw^o@1XBi_qr8A3{K^ps%41otIEN|}M1+r`)Kj<{j|wxV2StC= z=Ja&jLqIreIdtO^k1N=Qr;m6e5;FG8DU1HxXpB_-j7g_N3_ngC4W_le69 zyEZ9H8L)cqOsC=Dox2VMHBs|NKib-|dU{05)Q-$!6oK8flRuUklwKkKs7cSp#bBfp zp0Hqs#sn=hs<#tBtA77e;;>lzlN?q-Pwn*VGly^MrNnbhb(Td>03wE@nSQWt|{Kxopx`VjPJmM zRLkP|zzd(-T}`XuLMPo$;nV5v-lCeUtQY@i*$Z$l4`;#I&yKbWX2;(bV+#&u~tQ?WRh#DHOB6|Up2^f%Y0YVOBLtI(%kB^UL=H|IgO&a_& zq%6mPKsaA8jJ1E*O=0!8K8TeqFiWR=x;@$ck)pG;y#C6eq@*N*Uh?juhmHZ93<*-t z1K53(Z&|u8I3;HKxV}7 zqBR26_CkX#Q6wgPUS(x0P(3}px;mOjqY^`1190L3+~VSZREiaNq)z$jf&&Ds@${aN zEhrTnUhc@u2@rq9Z*{TdhIe%jL1L6lTbbOA;_0GtME%8*RkyCyPi?boDRonZr$k^e zoC!Ovq4&dAeC za=HUX8|bwW0C(x3)7IV7;pu7L_Jv-OEu&V0&5w$T(+Q+t5Ihd6??6Ki;8;XtWEz|KlzmRk zdnl7T>wTLn3rQ#tC9O%q)-diS6KS`0p_(!Hef zJe~u`JESzQVlG?<18;L;<5aFT=gvrei8kdBwzUPs+@X=|$LCaHzhXOl6!|WNi@j{> zlwmO=BXXc|6B`Eypckvv=@zUwWT(lIp(j>WWC2wIKn{T75I}c^=zmL24(Z!rGq!<#MYxgv3hw5f}?|b05H-fWu z0E|jB#;K2droc1~zb+hy@hw2Ygl`n9h$;>Zd?KdOm)3F}JDh!4PE{4so@Np~=jr2{ z*Odj!UXvuewNY!P3E5Xu1b9AwNp}EGSI^ z&6sZ*i!UjWmF_@LtItRuXX9H3ZM6~NMg(s;J=n2A7!)Mrd#|mZKO^6@vxNmBKPv$= z1b{^ZR1~1J-upKtP$~2sKHK@&14C)r&jy^7p2Kwzl(>A^Y(AWn;ohy@NKo}gI}*eG z7=o?h_mK(wiIOTtFoh(e8rd6OKis&H@Ev>Ow=@XBNiFoB#gy8bUDw}B^t$AeCk4>^ zht1q&uidt88w6Aw(-KUiS;tLR;m%9dyl^z>Rgr%RllZ)z8r*TJ+*a;?-l7n$%Ev!A5=shC9U9>kxv%kGstM!4k31pJ(G1pAQ)Y#AW+XOCFrzP2{{%T>5aBSz# zu3Ru z^b}dRBgh!Mxcn0;oEiaLinzlmgo*AqiM-+8HiP7MnS~KMmG~d7T0XRDkfptp_Re-GHS^utycg z&*6yWzr}W4_r9Y_e!7VD9mxWcJGi7gSAfyP>bNKSUi2g(0R=E@DN;KfxLX3^>|LVS z1AG7FrqVY{hM{Q(ZJ2_BA}hpfOdBBe#9=i-hKB^k8M=1$@gGAuXACDnk&1$XMneDw z*tCSPrp4XwX@PfZzr^#OMu7i|Gt`B{y7OdZl1^#bC3_4wEx}`Hz?B?$sB;PXtT^xh z?rH1gdIV=`AOMQrvKlj5IGhPsBbhwS)7X953|PRlzym-39M2dH8Q#VH!vxIWj^oI= zM_XY?-@mztOs;MwHk$vmq55xgJRzfW>xJg1&=A+B@1DZ@<5PAsRV|+YT{35KLAvR3 zZ#~+AgmZHd|8=24NFsX!MosWIVCq7=BLCXy|4aS@n?s~M)&v{!-Ph?x<~BzZm;>I7 zT3c}cPkxHj0BIWjA4LHyF99OV$PX>60yDW@42Spp&SP`loY?Sy)&eHE+hk$uFt6ib z@s3k)`Vg1N4ah5{4Bw<39iE&R>*;Nfi#lB*90e^IC_y!Q`2-1*1auPn{SVH*F-Wo| z+O}ufwr$(CZQHhO8`CzYZF}0bZQHu_-H7}9MZAjoc}_*0+<9_muD#b<&$iF{*+K;g z>-!{t%+Fr_nCt{e9sndc?y7y}HgqsOMm~65;y%Na z=07W;+X)Yp#hi_}Kv%{=8?;(yym)0@Xt)EnT(v5QjlgwD9ZejwS_qww5qL>5%w=>4K{cf>d zpH+%R-?C3>A|CMN;wBE`a$vhP($MNHk;9rfIjO-T9`eF?Qdd7G(xQsvuZj7sHNL9S zku2M(&G$*;`x_a`IX&TwvuZVqC1k&zL_Yskgigol+*MVvxif~HeaYul(+4iYQ*@F# z#`MQ`%W3?@XOfkLF%O!o@A`?m{IB)NsS)Ct@hBa}ND9nHp!Ey*C8ro?1OXXq7Gon^ z_Fxx2Z(gZQ05&7qc3We@0+WZ(ug8L zo>Wt7_EIhHi1Woog%z{`aln+Rv5GTM59dL803-B04G(HxANy0)C@8a%HY(PE@fog&dBgTFU{m zy0zEEYO5!B32eQ{)ELqCX$yOdd{t3vPxid%&(t{PiL>#cII>ma1@LlrQzWbEn2x{U zFUK%O6UZm>VW+CEn>x1DUU=H0J@3x8yDscH8{P5s67AL1Q{vejxgk6JTtonL6n+pj zN#rGiL8{ys0YFmn=DvMjF!6ldsK44HMVt)Mw*=q~BRvmW;t8G`5{td%ukXwV1vv)V%m{e(Alf4xvS~Q;!)DHZE!D<%!SeNw#798;V_5EZdjQ!$)NSF7meeYb zGhRJybXOU6m;2zQ zlRNv?oiS47h6qNjvnu`Zo8z6~!Bqazv#^OaM=2Wo?kckV$j-1Eo;zQ&QW4x!Uz>tP zKhoarTYDSKEFqV76tbzA19bGDA+sR{;SeD*LS&er5E%wp1{yU$Sv+mQ@e1x0(pC$; zUG6WK&1y@lky)8RI$;ptGHA4DM+0wJp?(B1u&|*%0ucv-5CHZQU|4TZzgnl&7m+dE zrCsU}XlYRJgK-54xT&9@U^egw7I@HV&`(cTIS69VM+V~Tj$(T1$RAVGma1Ok|$ zZoMkpcF@867jeefPFMIu59FijY{Ql5_tV5u_Qyk3`)wg(%zSKTwhL!WE?4qJ-Yb_f z3^2Jti@m|sM6JWk*3Z}k=!>K1Kz$l_;sLFQ1%U{I%kHKj#>b5RNTv197)a$3lTEzl z0t_M!1QJs)2)GbPFkuiHgD{zaQ6}I~f|jf<`DbuXcqoMlW`!LVfQ@be9HDS0!8beg#rxT!%4{%uh%M{+_xZ{AkuB`o~1 z!1L~rlGR5;(c=lXAq+ERt3Dr;7e@{gnXGw?H+Bxy`8~sIal2iBB|#T5oG-RERZI}( znxoY7D9o*WaUOoG@r>j2T-N7ok_?8M=Z%Bx94dED19`we2wa@%w` zBWJ2_hX+&fmTC9<@;{T6mE&uXSrMo8Iv+bf!(G{f)=)(8Uv)K3-48 zMrZgiB=}GPV}#oE^_f*X^Y#mwK3%NF5C{zhFxl00C6_L2FDbX=1_w-#;Pp-_SL!-0 zM?QToxPVH1j_hi(*@MqI%Cp7#zg`HW)0h(yWHWA`&hDDI!2^9VGqtKms-*hyIr!^DH{*}fMa~RF(zie&Oz_zdn zMFP)N-k5}BmB`!|ursq=O)V+Y7Rn+Xu-pNaCSvAbZpL%B7YEGl#8wrjkwlg&Z8)D- zelAhi<%RZ^L0%OSp?0=xSqCi5FUIjs6Rraj!S0v=?9Pxeu^sA@X zMK#RF-ya`laOb790KdKM#*pb%$;l2+zQ`7}t|@Mf=N0ueH1A)zl9m_&{y@t&kc@`Q zK2BS(F6u8nZE?mnN>BIbtLw9J2E*v>q&t!yVWw4UDpDdUC@ZMAjnT3qaYHMDc{Ad+ z9*F28YmWHDjl7>8A8LXem$b%9_fHsMsnlg9`{w{_9%O$5^;HZpeby|_8npMn?zj67 z)RJ#T%LUlm0{-lsdL7}YIrabI@*Hy{7Y$q{se2d~WQV9P#7*@MvOS$9b2tpV;hQ^sOjN-^&t9WaNnI$sGoc z)WGxwnlE}z>aGrY*dHQ(=&MFciUXufe4JtCaIx3w%#gK-c#8G4MM}kBa_|a(UkFO@ zggA*QGccT2AM+ISa;qxh<4LY6Ml=xxKby$@w^>k|qp1|z}lF_2I?$$dMCO&RqogvYh5e3d*180Mo%;DcJ zV`l!O(Eg~qe&ZiE#o8#rw=c&6VTQc%=dzeoW%RVtZdZC}R&jQeKDWG(jx9N@Fa$Xh zM)vS>K}dN?Pwy*w3>;7eB`d9siaMv0qCIG*9Eh^sy}bvIZ}sxJY?o=f1M5k#AFA?* zn(C!8*Vn*NHQqF7Nozc8_qx>o!fHI8GWc5=SkrB7se>-rG}s6J*sP}5zE7!zB`gw? zG0_Bhkde)qeZxZ>DTgKb9!g5WuQ&B?jT8m-X`ySTZ~cPI_ZgLjLejv*1p3L8w~hap zCj(ZhT)r&-kAXe4s~F;tqauk2-jlBe*BWSo@8ZbvDGXEevD4rmr-*YJlE-Lri@(u^ z;?{^6fb|KlfZ&m37DtMFGg(S(QgMg-KyozZqzn1%l0yi#lf8RL8h)j2Z&zH`^wQb^ zQH>>7k`gQq?_l)^h-hANiq2p;g@!0eDm};LHu~4^ZLwz>?$B`6O(gLGkC>1w)?NMBWHwUp0z=;c;W+%SetaH8x}OG- z-7DfYE!mr%J-Fh_Neu(>ZKg9yvbcj|y1wSbV)i}y_g&wcWFI(Vs-J=p1Fa3AgtjQ` ztV_6B!&6qPrnJf#*$LrLItC;LmAyiL7GuaX2EtN*y0F@tPc-;)H2&mp52G;pX^=1A zlY@2I@_4SnZ6*TU6{AcaHVEdCAEne`ARtSoZ?*hz;omdPu8j9=!9Icn!R!)DB1_Ll z!0h7y8JZj&?PlvpR4oOpR>WX?<5zw)t1JchmGDk&8gdN4%bZ$;0qRk%qQthkU$6Cs z&EiSf%t>ty*we^dvsmR+)aLpp;Nm=DY2M$klbue4%Es>uA94C|uaPm_^ihz>%#i#n zTK&@c;<%_cwa2mMD+|i^v}7|hhB0Pu-;4h{MYi31U`wjtWDnn0Ip()$7Yz*{Lm6bB zFNLe8=l3K6pO zK%zSsK!!5-Ddyuw`yz+ueSo94V`Y>j?+*-(;ZmVMs$|VdA;G3Q2^@;U;PRtkwedPa z#q++358rA!cGwOprlDnZ1zB|6iOoIeG{N%^lscjPS6wm+iL2>(Y^jE1(%ep`a8 zk@sIt+FCBm^NgPb-luyE5%>g5SR^KtZ_7h*wh7p<0EDqSEbZ2p%P+`nFs_NbqncXY z(T+5^_298Xxu4&yn=j5aQp^D?Jh>3xwEx!&aP6^K4}QT>*XuK1A|Xc?{IxQYY1Xm8 zZNW%5csXL@6WsfKNT{dN9^8=-ew#k#b5Z}%=4Qh~EO*-4E}w2=vkNkTYZ3+lR=L)F z@A-XSE3fcWE#CH!#3;i_c|*+m0ocxBUUz-Lu&_5USA&R)U|cuJBo&@#d_8-O+hNC3 zkB=1~iVE_x*cQ8(!xbd)Kskjo-6j`zhAp$vZybE%|2#~Fnuvw&{a$~mD!Yv3Z|weL ziyDbD3o(bU?o6xqa>k$djoeN{7w6&*>#f#11nu4}umcN!8_X}3jP)K+ePg?KV1>HIb znXiM&F!>L4ayy+q{d0UfI~{inHI$YknrMjHZsF_b*dwM-mWvoLB}*7E*lyRI$X&Ac z3j@U5r3M4%OjL&2Bc}8nRAniSkefBMoKgR{H?KEkJCG@jzagk$E1X_M)?A%sTaCc; z=by$DtX>CAz9y#}aWrreITM>b1h<72G$fY)8vy&Q$wu}EvT_mWPIGfu?#sWZ|s_A z$>$ULOrwc5?Nr}4WK+xSd~L3Yx(OL%Xy{>h&YN$9?^EidTPrg2jTKoeuDGKiApo(K zp`kQc4^gaIZ~1e44Z$=&5NSd#&;LjyOAHkmA5A*EB4=((jj!@AnTaj$b6*JR9ss}( zg%U4HNLwT1{TQoV-w@Ag3@zg(aws>9(Ng9+xWIW5?>lT{o?YM1Er25opr0BZrQtTY zxEVh$FX*jIw?vH{#<=Wq?!U2PgL%f#*bE|VNPh@mg?bWG)?Jyb4d+yCZODysh3G_Bf^4R`ETiTDmFKn-XiY|1r$qNkb{qg=~fawtaMQX>ivjW3;259?T17 zyu^4Wx{tCtgSRtZXraTn9h|1MX&#!-N*7WK!uB4Jh)Pfg$ z-EPs!tT%2HMZ*0fbR860%x+WUxk1+AmK$cgwBL`&nVCe1YO|$2-J(ki-UB#~Roi&K z@KUXFJD{2+$Mo0hJw7>3Znwzu$-m2en~jasg&-ee4v9iTSLlAh*>|^RR&Tl4>_M6w z9wp;j0_pvY*BBk?>ELR){=3c3sJ5Zzb}36LKt{~>^w7a%5e7S$IJSscRNr!S99yPm zVwx2=gC(q_#?}sLXLM=`j(`#MD#SOroZ9tzn@qEFL1a1or`^hq?`>=^ggXTdF3rya z1#{WQ#U1o)b4h-W6;h;KHy}DaMyFJVHSucZPvd*4n_G<|vN-%NeOgpq&cm6Uf#M_= zBmVmDy_)#raXYRoTNK(+vSCvkF3WbKeMzd!n1>%V1zx(qm|_tmq#_GFotb|V;)v)M z!I!>0kBby%Q8d?$EC-JZ{!B2lySNcN?-Ax(HjBs4N({A7STk5uN z4=$_+ueW8*<>7U=5}+^y`CHy)yPoFdTC}y!Y+w=DKD5Y8!;lYnyX2@bBoAkBhptIe zyM9)BZxwQ(8=asp2F;mmi$M=kW`;Zbjmn1LLn&DKY?O(RA!l+YQAs6Za=r1qm;D6J z#>G9#sjdV9>9j7g&fJd~{q5)+={o6%oHB8(cWg^KOX8QaFF5&$gI0;%#*K09_tH~8 zAYyW5zB$`XL^>R`pwb^obkeRh`n{JnC|zIn?d{FXUo@EBZh05bvXV!u)?}tCjGnHU z)VfjyK9`Ioj2L(a$;U&9d7>j%bcNoAmE5{CXN0r%SMwCym3rNQyw&)a$xIQ(6om(D z4Oa`3MrAa{pGz(xnniKbY2Ss1BeThwfleql1l}O9+0=>FPV{G*o|jUte6sw%kAT1Z zpRc+3q8{WvU(LpuRA;r2no>w<6bqnmydP$Gq&G>Rhf4qSC<*RaH-K$78#7{Pu5oy%V$re zzt3p?ytzRIYnq6qD%Lez-nti!$e3P+SjHgFZ04m!d()t}%pF*i)pW$_#a)Y#q=FfL zVkljSO%8gm|7Zl#t!L`A`Dk5c)Cd30hZx`_sSrRH9@n6EDnv{c3n#bwwHE0`^EDB; zUd|$>`^CT?=bvS+xBYKewz^Nipq}4(M1}jT<=|4wb{HpFVwnV9QELejJD^}^0YP%I z++^NWQM}O8I{slzvy?)QXHSC#jCnzPP|>ktG7&>eevj-8`PSoZRXmx|m2u^|)_D97 zq>#8NU!K(Tlf-p2QsuDw@!=3Z8Q=OcFbk zku#qAdT0Db9i`4O8hWz+RLLoWn;y(J1x{8&$hHYFi!Ct=vd;Dd{jfC*lhyK9tIvto zuqKJip78?}QMzlcG`MgA*VZ3t4Y%;(s0H3t1>3xu4q zv)rMc3ITf&!UxJ9Qg4&%uy@1j+A>fFjt#77YS(U&W>X3yE^ zj#AABTPuBA(1jBX!adwMzfF3RnhWGX`@R(`J|2gNsT7%JQP|_JVZ)|m^z+gT0d!m0 zYL-@)1KfM^oG~#KCo)Jg1>Ea^-yxrJnNk3IGw?HQjg^9BvBb>e0M$w%=bDi?^JuMj zmUpk7dsb}g9nGP8_&<$TxAjh(*?zAG#yi7LX%p0uL~bOlYPe188JD{5#)Y8#0Mm2659TSe2?Xf1y`p6#=*GX zxoN^5QENS2uj#e_;&O(%+IWn(g3}kojQ^gMI(|5Tx!#%Rm5Ar?q&m+1vBdWaBdJ}f zq#!0R66C-EbVwk=y$nI6nPN7-A3pdFDfY#s+TY^u_$CKiW$f+|a6(x%=G4Q}AGCXu zCH=AED%$0gda%;_8MJFz8OBEi5=EH)Cx8j4;#she#K9-rnmPttg<`CtsA0G*R=r2!j&WP9)cED#P2y9J)-88@A` z+2KC0{XH#-Q>~T+CPf4Y9p_m$UvFw}O>)7q^n{X7QXHt`-eEs2&l-Ie*F}q15c-@b zXR7>?DwByK&$d0~M&ihwIrAQ(b1(*TIAg_vhwf*3J!bYCb}#(DMbeHCmE(*1-QRV) z_UqPfjw{dsdbUmN{0R}j?&gR$-?ysICVX*AbV7a5K?D#d3ovMWkEqAEs4j3U#}rju z=qmVcG7T}t1M@7od8or^wq~!4YT61Qw=O6_O5-=CGK7Wmr#SSbmH`@W>2#gT!&sP)m9jBn#ch6TR#x(g;&^hx z%%>#>g%?EmNd%i(^23fVHdWaoD#$P%w?wQ%YULs8<$3Pvc`$*?84{)tRFDIj?vv}S z9RUL2`mB_h0#QIHDcfZcrSWMhHsz@t;$kwLwVT6Q>hQ^qsCK4eY zx`5{N$cL?6i%~2Ss@Rz<d_){poyPp|vke@N$-N~?=QUA*$>#Sl+jI%KV5nH%wNYq`I{0KZ|((j#naw39& zuI^6`zU^^5zrOHWuNgA&FI`;=6-APr2WC7>a>Hwh<0t-0F?E1j6@N!A2$2?0^7lxSK;ogWi$4eC=O^(a)`lv*8I2#!l5@r+#KE}=>rM8oaxK8y!-yrDVw>c z*&MV`P*$qgjL03o2#X>xTX$^PK`d^!SrwIu(j}}K?Jwcul2wMZ>Z54h4^Lx%?!Zlr z+1v>QmmmTi8oEG8S8U##n}?5Z{>%8>l@ScgnWvfRy-d!#Lyf>LlHAeG3P0drpPIY9omZTBR!>284#6uspXH zo}0Z7@}Cp*xyS0A7l9Bo&u2WJ1OARH|1{DEpB(4FzZZph6)*1 z9ICZqrDBjl1y9`}Wy(K(OMl*$_aPBfE^6!-)x$#(T)Ml~{oKUg4w&Pjw7%XwYd|o^ zXP_UpfeIpoNUy-uU}7;$;t0!_fXs5lTp2T*+L8D^`UF(kMU&^^r0b@aY*u7OY!PP#GLdTv%ee zLwmNKYwT9+&u(+^?F4wxY5f<_2{|+d8;%X@1XE1g9}#uMO%EO`pIiwdn%PziA1uq$ zCyQ7!qBATMo+0VJlhRJq%W(5Ga>*4c!U?j%h7+fw9LImMRs)!if=6(CTg`tUDnk#c z7a}kUYEO{p7&gfw(X`5!B@-@lJGWOx(%pmEO;B$zp-g+ z+}5+vU;tCuYEHZ~k@1HOFKJ}q70bR1IhQehaZ$tQ(XIpgrST)D zbxmon)H$Ewuc`zYaA^V*EYe`l_CZxisSE$lYPI3z6T9<6H{d_dpUFrmQLO6*4&n>I z;DQPUNE?N|FBS)cNHrKrV8oWb038j9t@||NSltL!)|S?@Mv#AVU|UUM#2Av;GoyN6 zU@-F~T2y1*ak&Ft(Y?*{lFG&?VSO8-orJJzKjO{}7MD^vL!aW1(ia!?z$+2bAtpyd z>e{NWBoc8d+&!qMN?wnejF~nNT(v98`B;d2N=l=zbFT>b!L=M=l|JB-Uoweo`$hmc z1vw6IFGtrU1ucaDm@nfxF|6ksGwZ~#p`9#Aw;`u|p+MoI;(wQr0IXWoVreJ?grK6o-i$Cfs0f1uK}|4I&v{m2`$-^4Fq_3q8>fCyVSMccyTHR69eXktxI%wlP#)6$XEP+}cZA!O4IJ9g0 zGk1Cq^K&I-bbZ+Q-#1)Mq>!|ZP|mDK(;r#!Hos86-=}}>mUe(J0x#aKE1la+71TQ+N6$oIGLW-4e#|{F&LVsz7nki)cr7%oUNHEY4D^VlVpItGdqS#~T zH-HdTjCL+G*9Lzz|ca1pf*X{78OpQHI45p)3F@V4xT+r*ql*W1@0y_4nDv zU~6h3?p^tQacJ}N@xsTpBSaNEK|*Xhmgm!7?c3)o`Lkor2L|9M=iee))|^(`2MFr$$)#+2Bbl7pf@-%gYbcIB)>>Qi$*mGPnksBDFlD z9{l^+jf2u|+8ElcIK^tNJ=CDOUi7@i(04fe{<_~-yjaaxjhCR>Tx`|g_N{;PdNU(Z zBw_+Y5aiXtb#r(hL#qCjY%u1KzzT9?1Txt%V9Z*CdFBa!q4nsz@bUY2jwH?)nKM0Q zYI~kzKSZRGOl!-aocKYpUmm8ad$r#UfoC8YbK;C1$pCnKLInt9$!CZ9Jc1p$!$MSi zZ^ZmwCkSxvJF)JL2geRm#=XY{kVs}%eJz!*2li@?5OE#6^7gT2-^uh&Ka=U-r^D#% z0AnAi5~13ayhm@T5A-UpFW_x2`n+}HZ>xS3&csgtJCqeMGyq)z>6ul``K#96G>9a2 zb7>?2yyQvw`+h=8CArjLY0w$NJB{28aKMqm2$Ivv@-bjBjAe74#Dx5SeDkvS3vVD( zXUIkY0{&w9muQ*4H;JCDUBdJF;t{bT>2@M5E-!!mw$tuo#x!1*Knv#`dIy|!p>J&dqxh^7=Mm+|%dm8e2c4~aiJ!Y9G8~&QP%@g$y}~A z6?2=@eO{q0u-X3;_6Fzo%iT4#yzV&e3*Av*$w6cfMlD2MIAAJc>*4Pfv{nW^^?oA$ zP`D_#+L(4b7`HW+*Iwa#zX}x18PschpSj?|f%EC>OA}1oS8Pl_h$Iz9``DE;88l%^ zH0QimHY`UFa^*}S)6r|sUeMxnQ?r6;;{d*pKac%T17~M+p8>9wFAXJhK|=t8X)*s$ zTkfW;%m((iA!sCdK89eF#_O&wd|gP-(<`g8n$1vV3_KLd*Uz$xnsurEKUp5W?nuzr z+5$0h!D(zbv9K!Ndz9Z!D@B`p+>tP;;oEfh)v;rTUj~dtwqi6u-)=nBLx3t3DO=@@ z$TYU>JLU1ypBMvp-6DFj(02736PmRidVK$=RNV#8>$}HoI7@RjdXvasY?w0T&f}Uo*=9 ztW>U`)kz4W_{K;lj|ITOEsmcdWJE%eOY-KtPhz^Vvn^wNC#UC03Hp@NIEIZI3km3w z6XrfkS*N%>@An@aL!Cnmem*IDQ$WvzWNiv}s>>G@$Ij7RLb<$~Ro;x+I2x*@(5chb zMB(q(BY!$VjA{2})I?5-zJ>p7gm$ixiPUV#;q?-m|4FoxVKS{dOB3 z!H{4%eSbO0@7WY??FqC~C*P7nLR5kfuN@X~i7$%h6Pp!dmG&`POg51PIcw$G#GC-Sf&q zbfU?)!RIH0kuF#g{e1Lq^Nk_i0<;imB?yax!^SHV)$%#H&bW`8F=LgV-TLl-1INwO zp56!itBmG6$1=EgVRir=APSw%Xet5;DC5#tq_kR+T zx~w+akZiV;xN_i6w)xALl6lV5$jRQ0SNwgs^lnN!*!zv_EeM_`G-UA&c_)Ej6jIpD z-qMuYYr$^Aw3}WdBuTPdO)j%4Z5cD;JNsWREsS(;R)q^dGN&+Whg&|}4`7Au@7ia7 zHzn4>Z)Vq90^Iz;&KiK-zxeo8wM1*_A^st7Q$=U2#F4|%)x!}Zc^kp0Z#ly=%R6io z&iiy-tyiq6O5D{zohtyJ$#l9A8H=q&5=itNw+0Y$P;;T_U3~ayNvA zolCi?!o1TkXL?j(-R?TCG`<8^g%A`df) z=}&E^zNxS+A8ecU^{|DmiW)~)uT8vv3NJQw05NkNSR8M1Wtb$x4RTIy`KOT#F<7n3 z2t6|}s?BDXDXxS{y*%RdUcPHbmw$dD;D6un{WUjd<{ONYghIUKDu1m?zdf}$v_q}g z*YYxx?fchvZiGS>^p6spW6>FwQEWDB{r1sqo~jHv@O^YVy6oY13nCRk>?U=M>Hor0 zEWaG%9B&7-SuZy<#1?3g>whzKH>Iu2YwScGW!Af(sLe5th0*)%{;t9rC5TiT*fz8B zCTHkJ08$6NBBU17+%IR(Z^k!JH^l6uT7PfF)p-eRl#b>!V`+~TPll$LQv0ncCe-m- zG|^ofdOW^WMSnglg$k<+`R^pocmOa#aF1-hn$LwOcQ6jADcgOJWW5{f2s;C?iu2YFG^Uq3Gq-Xetl% zl#WT$O&vcM3?@Iv`H+E|2GQCrD6NhW58u_pG=9&2IECIaZ?b}PUz)Tu7tK99zAr+X zIsIFWo?4vMn~q&pmXzyK9P?Atjcv>|%j3#FGg6*z_~@pfWjS61Li@%fR|l$JI5p*( zvUI74(0_`rbb5m9K?tUF6P%LLbzwGns+Wf)_;9clYfW-Aa||}#z5Z$sR%Pip!LQ38 z7>EkDfi?FPh1;wWtb1MDUK$jf|2=@6U48EbG*O4msNvysT=ICD1e$CqLdKu}=Kp#D zvURi7uhV>>_`cHP)l%k-Sa)wE^4XMTrVy3W4WSR5R}z2Le-x54K~z=y}ueM~$iug=@BC zE#2voX_WjOsF~4Z(Jhayq_l$%MFc`Bv+5>d?PQ>o0(<#G6F0<8iLXS;wHP>f!qrny z{gJ^ZHaKQ22p_1CXYJpzMU#+kd#5EPf;dSsJ zfbF#IdkqHHX{%_gM=+FND?ZBFY_&PaQ?>zW@l^+*{P+aK&Cz5hDrV&|tH`(#d9{aM z?$7gwFUSfy7)A}43#r2UIg$Tfva5Kf3?`QlEga{(=ACOuQ2<*wD_m^;)zRl*+NMgA z#lITQS>kuIT`WwC;_=cv(;N-l_W!bQreNLR;sp;kA(YI-8@^!COCcp?=B?_ea#;S{ z7(G>DOG@Pg*0ARd$gAV`-psk}*KCYh|1`oERp8otpgi9}Q96q|;P3MHGtRW`tu>@I z-=No()gad%3YVlwSj_Z0c*7+VTUBg7fck&sftAW^$%}RinM=cGzTzkWD`PbOlZ%;) zZnUB2=GPjkd~;1Fjm#&0me?M_{KX%)ZhNWIn%itWUd}8*L5GX^3z_{wMh9_6@T21W zFtu|{56#R`iwnPdy|4LrgF!@FB4N`5hqTK333w9zACn?3Q9~euw8pB!|-`i6~~KY@#Jc9>d&ulO6d{@1Qmurynns=@&PzW zJ-KQ+PoXyOvi*3bi5#JubM@z9R6owsC(rZu4On>dX!~FeCL2thI z#A+t!PFg3P=daFZK3cXoxU?!VAKCRhKaACW-XQOdf^4=lWa4ev^xv*}9fpcG+Ah97 zJohuGF%}x*dw+&UvOE398i4_gpEjq0f5-6p351_*ibiGEGcx3FEx5Q`AYv&>OqM_n_YU0wV z<17e}^Rz9MK0)MNr%~Z^Ynar29zC^6wYt5!MdiRFNkzOxzX4cf#M9!XP)>?0X zwtrsO^*(luw|&f55DSpDbu@?b87d`?O)j4;N~yRhtnLqPsdlT1ii%>lGI^X1SevT3 zMR$;I1&7EEE#+@_AN=>>XD0FAeEaU=+P%^3d7E)3RCkU?ZfeY?qSQT}GPLiyUg18Z zs4W$M)M>x}vR=mc$C3MY2QAU_4zi<>Jgj|Km!CcDs*bPS0k);6jju=NtW`RVVeEOB z!X)6H=1+tKAxL&c7Y%1UDn3krx?yd7=seGP zn_OKKPH@(*#Rzd%1=hyd=~d|R*o{K95XAnrSyUymU6y&YNGOh%^I8mO`h&Lmv*QKp zg-tq|SYB9C(;2Bhr2d1u2sG!dOQ<}KF*b@r9e`V$b2L$H+I9AH$c^1`X;~$jwKkIA zIL0L5wQ~I}S;6!ao)>9XP-aZp+h)zHCF_5iQI}_+Q84DkE)8eDAx)toZS0I7PeKyg z8Hg=TOF)kkxW!^L=$KQ$B-PqI`RJx6wu_~!vsa|PaKIh2YoPQ{b@ zdRng|2NpyNYpsDcG9M6i1;7&^c z*LCPxs0C5afVcMB1KI!MX|8`KNRe5y?$OK7#d&*=t-i>GpO*?bY|}=`6%5IYW`D_u zymTF`23tq-a?ZuI9ikO&AHT$WrG?=fn_vLyN}TnbmLmslol77tiooz}=B;`rV$Otb z1fUbz&e60kI+LGAsN7vc?!C7yfubZScJXyRG7CMMRR{0Enb;gKdIZ-)crAgjNW)snQ;h* z6J9Df&W~nr`0`6Q zel3jC>sNdaHzp?;RdN*NR{?LVne-shVxp}vm}-zG0|@3D#DO z;8-hOUlZ{*r?>r`?FgR=<99h!XdKTT+N~@Um~27b(`k@kv=+Dfchm#) zc&^=~`1GfzOL=|lAbwq?+$3RgQ^nqGCB%T7)@#b7!(b%@OK35h1^-%OyUmCxp36`D z3<)+ABINHEV8@L`Rr$P;r>H+;sPsOya#%QxFcs2Hs8<8x)rt)*4`ixQD}oCi#wX~T z?UO`zXPMU@j*>pj@V|(ti<;X7?of(!g8p`QgX9qf4Dm-xx8D=Xgu^X ziO+co28($?37V3s|-Q;NCi46%BJa+}# zEOohOvD?0}_aZft?8&zc0mGP>ENOfXN_t|MRc#17*|9eM{KTA0=MBx~fW{i2hzb@4 zhg0gR$m9*&ase3TJ{v)4krq}_E>6oF-ntN3!7x(sx~MM@i7H!SP4IMQd8|ou16h$Y zwB2tz`m~e;y!hRcQo~RYL~_1t_h(Zo?yDA}r+{fT7%`1Mc4LS~Z{vu%G(-to=N%vE zZmGBf;46f}P?=-A?Q4^(3M@I-=~RNfI(YRn3E`qwQFqWyX?QRFgk z64Z1fNyflJ4oiHsyv-ME6)j>)X0kr=D;G6&g-RENj*Y=p(y>+Ijq*FUeNMabcj<`| zRxy+i=|CyaJ4q7POY+TCe468Oh(*5asZ^D#?NI6uwFX(H29`(M3MeTJLCkHL_kAQ> z@uuF~(=;`#y;B2$U+BL^2;o$U3wj4)rl3Y(rNZ*`#6b}|^-5=#WIHD&n+|QvHs_?T zF7%bI?)T2F^NXC|?Q182O7i-J>msZ=S!pL$KPK^0p>7 z(oTvdUGmZ^Jb*UeNNCt#fQt4*9sW(e{SMb5L@81rc4P}k^TEEh#_1VZA%c~H!YEk2 z?25Ab4*7R*^I%}1R?Jw+Se)}@9afo?FR@{(C`OdHj}noX+Vi0{#9<($&aJbmNb<4| zPFlb5ygD}9B8L&+0xk%^Gil0YEoI{4hbSZwJV6^jQ%`kMQ(DNGTn$>oOpGi^7aQY~ z?pglsGizFu56fI6x|DD*)n<#MTY0snEucXaG+ml6EX$~nF*_>nV?bW`{ub~jsFT01 zxSQ}$RjcBH?|yY)-i){^<2$L>{NjcVmA|!f0Yc`=$!YU|MobEUqF&}i{1-P(s+pz$ zi`85{rT8DCx7ro`%9Zf%MUabEQU>R6h#IZ)e9uYS1?+ot9XtmTMAhHQ*yViG%3nO) zxQ~Slo0JtKqKPbqR0|~tQ}~y~m=G;X3QBE%^t6f2)Q29c-NHXcB1g6+Za+*ktA|+3 z$i{Mi2f6Y+kDEnlEu^R638t(G!u}bdR-wzeDl?(H>#k+-)Lucw$^b@pNDN*M4hag( zK70UC=p83+8*rfUjz0H1scCYxbz$e<1bH`eXJ0#_IW1PKuE!R2#dcHf4`1juM#|h2 z3vkzwt;moNuv8nNGUXyTx4lyr#iOjzYW_B;WU)|{_O#|azp)?f)EVGtrHGzlvchr(K}1Sfy*eRJ72D7+K=TM@UxFcl{7xS=+LDkOmss**GZnL6Q(ql zY!B$J`|f_D_CL>9l@I&v&OStATg@)qIxZ%>!|;Ax0gn>EUip*{`DUo@Wd@3iBm=ts?j;x*{r z{gINw+dbx4zdNi1yEP^LS*6wQCQlT*BEW6JkObMezKp#8QyYS z8UYMN%__U1Z^V5QQ_n&3mOUF-fC$KNS-pMPM)T%>h|~dYVEk;ERTgxgk;qzCj-o&y zVT;iCf$IDdHWMl9x%_2GXLIw(Wq32$#mf*`qnqmRviz6sv|8=`W#67j{tPTe5yCTP zN##9(8W)&Mv1}4E0(;iYqvLrMrJ>@HDo4JNZMIhUZ}VQ=upt0_o=%6Wa!8JWAKk7= zOo8}#XOB#dA==f)lLT~!wx%|%c6IV;CFS$|-hzjLTSz%+s#t?z9LJ)h&?t+thmxqX zGi_I#-Y5u#S)F}qT8=<^jFev~#K?+_VtllAa`@}U55VcE!LmK7xIi2c5xLMbE*?6x zPRvuhgaXN)v1&-<=76{7gCPrxy}da&&d=bc61G8^ zw5g`ffd&Tvd82w|TIihO$dvQU43ge^j7f~d-mp2Lk{hG#5;xFQjJu_b{7^Kie^qyO9CVE>7Ca1L=$95mA!eeHy z$9C4|t>~wjePHdrT)*(g8O~Fv%@@Y@FZdTrO1FPX*wqtDy>{7QLbgItGBY)R-DH&U zV^6X#txXe08$SkIG%&L$XkGNJX$h`%IloL*cl;IofypE|NW8g=+VMDQ{{C#uX~K_j zOO}R{Nt0Dt&x`^@oVrtL&>uz-YtQC!{NA$fs48v`nxxg)E=N{r=E=g7|h0`Jk@QYL?#VV75)Cl2EQy&PX!Cp&e498g?LTusFX*~4ogD8x zBAF728FTItMi60pTOWEZawI%ks@!p3>In1gBDH!SoH3a6NcnR0fMRdz^3|I?50tvJ zmA}6KSZ|k-{>z(G>byCw4?jiBKbxxueP^ZGM_I0YaMG^5@BE9qlvPul2&XQ{oi7RH zJl|q}^=r`jD*ojC!GE338fN5(3PQ$?Y|l#fgb>QWpkpW+r!}1S9$ap3D2c z8h|r^?UyBGz0+5&Am59=Xudvvx;%PY!#V2H>FCkPR9E8164`UW`M5wjG$hq+-KUAu z>>?Tw5IAJA^4e$VdOyi_AzYon5&qM_5|!%g<8&RCK@IKcMDz3Oj*voO*3{;~d-JPA zx@ZRt;FMnkmvJS)G8uhJyP znJe7O0b3I7AcMiC$mUZl$<{#T;xL!E`{*V3YP%cwsCiTZq8u^u$4pFr?y@iR_4RQa zx$TEgC2>9JyM5llYP%n(yem`+8jBr`8g~z!lbaTtRQIgU3HHcd9(5%%fxRm;{Ms6^ zgdZpN&HXOSzi1YkohE8jkX*74V^<%oIX~KQfWxPCrHxF(oKKg)a{Ys*C1s#bPls{ zZj>Y`WiD9rRABv()2VScqxDYOdiQMoJL!7&HLJPcdLg zqqtbjp?z&mSH(AwneRjgTK*DgwoUft{jorItUNL_FLIv$m0wh;jnqY`Qy;$d7V76j zV8MVhrTyvpsws{QO0(-)<~?2@`qx%uDm%NWT*4Yo8>SiAhaT?(UksSYLDU}$D=a5ob5BuIHBvykaNO2abel#AUo<@9T<;8AO zIB-tHj80Z8`EeE>{9Q8HOJ~F=(0>>*cV95QIV~Nj0n4~V`nGVj;Feo|7uEucTN51H z&u*UItTvc{0GUj-Y}=U}c~}dLkt{!nHZ~5nbait)*HgW^J=o>@?F+M<*887MOM+XM zc{QX(jJ94RGcc~)OOX3c?ee8c#}CEmi|&{uROH1C6)!EZYw$J*F$;kcApv)>Z*_&FM<2C;5_C< z1{+pp++OSGp&^pQ=7$C%82lHOIdulZwJzY^ENLcOOji@d9V~o*lVq&484@b=y(@#^ zSbd->@e@nK?L%cH{aaiEdrs2U2?H`V9b;Leg zW`G-NYE?VNngJNgY);c<9Z_>d__hiYb*FamH1@QBW4z5*eoHD#Cb*HK%i9S+g;_xn z^6R2r+(_r{_?yq4>^sTvnyD9EQi>w_Me4qrO-d^!xr{_=J_efreJ zy@rb+@xA$@4qmq9LxD0(&SRl)5!}9IS4MG8z_8hMOTUDNGD|8u2GNQCv_{{i?`u-J zPy)lX8uDj|P@Elu7{`0frT8n(%ku*v%JsB%M^x|66^IOzcRN3hN-)p+#r=4lMG?tn z+y;{QMfA8*(L|1Pp>{aSrI-(F(n!8NFSF4ndxK+_^OWlXSGPe=JJ84tbtLdE((m^< zGh(V#L#-0tX+U#Cprz??I%$?NH%Bm$I1;iMKbua!&$~%qmfX)iyH+^4DKvTSsm!s) z^Q@WuQzZP!mjmZXTBkgCHhauS@bCkvWSuDV5#-aK-Y7uv`u`j@i2q~+lxF_>U<1_? zp#I;_@F0!(fZK)t_vsEy2vp<$or#y>i-;wn5l4i0pwUtg(6`e!b0)k3o+uHRhj+V6 z6>Eq}ktnf$#7=N})oS0Gq$Mm5ms}c)Q2OYBbo749d4$F}1Chb5mIMU`@}<=E!@sA` z+7B~S#3EF#d_lEx@uw%cpUooB*9^EL0hBe>x&I!%5sMSTLqK?Vr-B0aH@;Xv>8%y| z;C2SaKb$?d0sjPaI#nu*{VaN`m&~{uyUNfx7s9nU1fCBU44OXSB!U*#yF&*=(Gt1| zP}4+1{a+>YVxZSj&inFx3+}Vcg%?DaEVE&YSi1oFhH4%Qwr+!4Z6Q9qp934}zg*U~ z19=i8lS;ae1`pJo`gZ7cY|xA6Tyxq?F7sPkxwScYmO65oA6+KI~} zgT@=D-~*pR6prFCX9hT|E&Bv{up-Q5G#QC(dN^l?S&@Fc9CdTUT}4N!o6E zuUcf!zo~aGz|ci!o#Q^XVv+NJe>AxNK3W_C1#eX!d!-AO{_m{qtJ>Ssf#Ap*(>apey}eXc zYaF1p=RY2icCE_|rpOeDVNl2}M4E5wim zvx80dD`Frc%x8XH>9X@l8)ztn#cE}+)#ZuyEEaqfr;)4O<;1FUUbY=(s{ak{>+KS& zNN1Z6`TuIj188|0nUMi7P#ZL0zXjBB$gBsO-*H{&s2R|aevCye_E?}wcyPD<%n~~ z>ON>-wDDlQo&Y5>LGFZd9C(}fez}2tUU~lQJjJ5k<$5K3IFd>4hexI1yoGBfuct!r z95SZZ!SEBA;Z&I*z#`mWvs+7=1RJHZGh(VKSl{JaG{{`*1E*vPBXMAh{^MR=V}*|&D(`+)|B&*gc2m>^F{}elaR*?6 zf1v31Iq!0i^CsQczSxd=VX@KAvCn%bLm7Chs7j5hFliJE^$E)KG;qrlk-`0!b;lM9 zrP?F^#)>apN?{7n0?i>6+?2713e|D6<6;xJTXn>fV(=HY`%F|`5S9x4(2nQq`u9hn!;d@GF#!09#7+9 zIns-(@$Gp(G4b5u_TBq&l8bBf)MEYV{LO$N_1s+mNdT!Asp*@a4_*!)jbpjGhPlR? z*_lfFbN$7Vy2e{$c4JdvrAB3CdrsYOQAJz;GjIUq6C3W5VMrb4x$5ZVjl&~D+V2a3 zy7JW0RB<`#U_9bFa-C$KQp@ru1a2%I%mY>@5uH&6L-^N1@OmqRg&{HE%$z!gHa`;Q z!Sh3y&g57u^rTPtot7S9obkW>8x-5!(F)B+P31)XL`4ut%n9yoW_nz2!ck!31J@4> z9PwX|24*}`KCU{)t7KsPXrMcrvt9)?TyFBgHF>_<%-Fd=xHntv{^jd5Z5v&ww?;Fk zSPj;YOAfGKyTWKtk!!l4{=98oa&Z)9Z^ZdBU2}9^RH*+T9$lRW14`(~+iJ7d$HvSl zOmDy-VaU4?BIr8187{c^{>}*;lzG>*4@PMr2C7{SDt1PBTX4%<{C(Cnn3cJ>gkS!= z3bmvYmCffYH(sK z#fv-^BmCsMu5d6*jN9a)O&m%$xi~ItUy9^K5US*8f5vg=-iXq6bI2bKTf}?J$g73# zFvHT{eej7-B6Mt6$-K`MDrJa|Nf(y7M6w#!>5b(3`Zg#&#_4@vUHIJ$$%v6O{BuR$ z8_hDZl8M=warr~IC<32nH4GKaOO%^#c}?GCBZU}fHA z-P6G-Fy%2Z+x}_Zq`wqeB|uwsiK`NlCy!4Gg|wy)M0U&tqzDVrn< zR`3_F#)qbD3s9o^1q?q20ua&%K}k=pA#O|~Oqe(-pubB?{9@^Zt^`5ocy>QsZa?&t zDA%}wn@kG(evQ4`_aw7BoYr%}+n%`+WVOoj5pdP1G-;&>BJ6sTk(GYyJY!=6PpmPv zyalTQyL0?Q)2Yq;$NRHMHM`jF2aEIPNDXylg;7eUb$T zALHBRvPiruhobi<=%rNCT+`v7u0~hhwRw6endXR?#0dOjP64$MdMD;Wf_sq-eGu-fPH~sm&?G`?QIMG;u*%X{iwz270|i z7X)L31yj9kN+KD68`?QEFh^@WcY)xiC~N%Y+Zp$F*l;r03>%hl>9seuo=!6TvdO(bX4-s=pM5XyQ_eEHmJ6( zn1912bE1*Mu%>p}nJA*+uNWX_4ku;=l}w31;^n*Y#|`sh#p-}IeNbE=DoQwK>9zX_ zTT5`?#Dz=JSA@pyn9JLY&h6;y2cUr@AB)-lhcBjx_ZL)EDyM&Gtk!)~)e&to*J%3% zHxqFbF+ELYD+wA#w@YmLorM9qkdQNB)SmgXqA8a=31QK(ug6c229~*Bnfyv36zuXj zF()B94up(ZTjDi+zS!Uy9EiD&SZfsO&n5J+Kk_*df~QBbRvB1$9U*vC6NloiCJaNR zL$_>WB^=ZUkxqGrYYE?6y14vLFy7>0vXrjf5I8tZhpF^L)KSDqrc>j@(z_F0c(+39 zru>m#n-_mt`8{0S9`YRDi_kOMKT9~sGqKLj92rf;t-S~aWw~JIUaR!$}0?%40Vr)7V1n993Y5WMd$2T~jk7G&r4Bd93FyVEi zwjVsL5%E)#BJFeY8;>+payisPoX`Ht#h8Jv(_cxj7YCP$dU#0>(q zT4{VH;o6wlhldPp`oN~Y7p2;#HoQ=4uEEz9AN;C|6Vc0rzkL}JLrVU6bOlNz^6QUf z(%KW?sL)yB;$M#7-azIL1M55Llw?w&8(w&=M>VX4hu*0LYv5ixp7X6i@Y zgkHEFWn_Mz7uj7Rbz$NPGr*O(%i1{{!SS>h<4l>NlpG-NI-V9ev z7S&YbV&$@@oYUCcb>`&^Rb|RN!&U1=$@d@S{YvQ5x7t0_@SX}cb>euc+V0xo>;KD= zaEY9l(0Plp;LJ5pT{W4<=M|HQ#d73t~Sn44-k)5B7KqbF;TeWz1%zQmTE=Z2t<7V;bTX4PcHBj810w z3|5yCz@SW4sdE);r^|mCQd|1tp4^k=>x-3Z^J`5=o&IE?XFDrZ z`v5ne9gNe*0rr}n3$BsXEo=NX7evG)D-YO<=b%a{H2zyDBbwBHj_fRxe7EgC+*;Jq z=bI^#%Y`w?nT>V%)93MySo6wLhb8wA|x`_$M&OOA=pzArB99BNL zn+-Otr?4-9+{6yGJ2~&2qbR(U4lZe2W5MSGhxYneZWVEqyyCCh1D#Kwft#EwOaZS4 z5D-G~E6$Tvq>J@E5fkeo8cyH5o+hng(NuKVG(9ZOOe;5lk73FkI{*@dDe^A|1dUS! zk!`EZCvYNUfVc?PNIffN=9jov%mE4h2A{yD1>|#a_X|C=BVTBBvT1!}j~FmCU^16N zDO<#5Z+u3?RS@{1BTWo#-k3z!hmn8D7h810>kKU@b|$>% znBuwOKo~b)7-f)od?x!;M>Gvpp7;FS(&lCw8?CpR+$|#?7Hbmuvw4GmNkg`NzztWi zl7*m>g{pI=V4oyjFQQM+1}{2_kp6dYSEt{`6-k_vH{#r(v~EOcx|JaOosK1u#LsCF z6@AVFtUB_~tx_o}DZK=fziax&mr<4`5RclAnak1-v38>hNwzwFK!#XL*%?y2Q=ygi zRG&9!Bv=yb4}Bv$D&qH`(=hBW7BuZ0;b!=TkMhd*aT5aKY7Y)=6F=G7F2IntXG!0&t)T5=3K%B&| z9FAaj9BrYSV>W_sI_}hwh1GZb`^;3MSdr_U(V(ya$%2(Ee-zT6UG$pMk=GXMEbnMA zt6HPe8DRQd*H#t?5kj(id#g7F8_1@I-H)rT3ibQWENZFpT55e2{gC(zkFB2#801Rj zM}8pqdF&Pp4-1B{valUe?P9M|l9XZwC}gKvP^_U+@Wa$seHzmWwa707>W z67ba|7o~oM1QQatuxx10WHM2Lkx9%^%9RTv>;LxoEo9eQQy@9uZj}~Kk&M3IC?4mh zL!;u?$fhbJ!TrLX)s|%E1PWzEAa?5D1DVv0y+p~xz)Rq}Zw}pjasYX(^7!XOKoraMPHf?N){jX+L!~UX zLHxR5L@*OvU&qOT=vX2e_@L8&4dWL;V-n9w? z#xWB`++JldFE1AIVt~uw1pVEbs8j57CDHC+0RpN;VSRPD$bc%zGF5-dH-ec$nZu%a zMs4S{n~c?=vLYg*!eTlS!|5M#-)#3au|;JqF+^D_{s?O!l;}Hq`c#l-4+m*R4(j$M zCHavl=JMM4ENW6xo5l(m%joa;r|z%2bM7I-3YBg!ooi1GYJCa1_F?b$XNu~6C-u#W zS9&~Pq~!5UFoD$-NQ{|SHX){A-nJatIWAmf^`(ujLo!qXnNi)1!!XAtlhA<`r7$Zg zS&FGQp=q7*Y{!DF5;T@NMS_!s@C>ewZt z`-~5KZoB^=4H{1)j%NX8q>QgrZhmzW=vxaDmk}v9^Y4nSP0?LumH71BoU`qk#8V`^ zZxc!t>O+rl`Say>DeV?CFSY70SuPC4)Z0N!-1*iTz(^RmF>HX#1#QClhfn83I2jTu znL*t(ceMM6?VkNY?NOuiid{{#?x2*>BqhNZBw0|*Lf~<>M358-uQw@SGGX#apZ)jO z`WA$@PB{bUgjcfJ;?410TNZ@_h~-W%O84yb;hi-S1aeKE_n@*d8v(Dt)mEt>sVctE z^HKXE2h)fV*}Ri|9v;n4rbnh}@>SDovQPk5BWs+4M~n~X6oNic=vac}3WQhy?4Jv{ zr&bS#hkHaw$c)wyd`SG)^{zSZY!NVTIx!VlT+b@|>Y0%Q38o}5J3UeTkO;nf?3!<_ zFjU|T6bD0;-?Q;_uX5@;BFfg;J;;f}0_K*A1AVm9;Fsh(-9b5>J%@w(K78}c(r@2X z)Tf9DvP)SH86O6%+%%l)J$ClarDb~)n9@@ROg-A4$NSxw)KM3Y!QnW-JQnXDsnCV) zTWm#+<-L^I-+BCUzj?-rIAqhy-LWRhHFXDJH_ET`l!tk?ud>fB3;MsK`059(~TNy{SqERH<1HH^t&lHg2d4dwko?Kmv!^#ykY?<$CkEWr_+CLg_ zHU?%IO2N({N?%QgDIwfrMi7Pii6UKs)nVMO7b^ZtRN)wm$kesLD=Ii=AU}SSCXJR; zWDHU-L=)Tq&+@8^!{~m;*U@H3we6KxcmDJbeCmoKp@s`zmpRMb=xCB0QmL-mnMXup z9!h6lSPX0~ix4E&CzE2(T@3Q&By@pl!DRO`0KMw&N>q$xB?!G^{+eJ+Xkw8tGVmOZ#t4ZFB%2&Ev8y-z=+Ut7c z)byUP_;r-ZZ^OTf01S=a<8t!)2+y+YK`|vPp9)7f&4$BA7rOrGVgRgijId?ZyhbM^ zPEVKIZtSNwNH7DieN2bd&(LX`UBC0CG%2@v1n6Rg+=c=@@hO8r6KWPhpYN3tK@anP zWEvpIq<{}_@E;6)kh5a_)K(lauo1M$pY9G)*U%A6=ry?F_44-GVtvbr)1;edXEX`_1$tXGYc+p zA7?tGu9L789NMz0J#L3n^8R>vY}&HM)mXuhwG4>#DE(K+@+FC6C=BOXl}ZWL#`F8Z zV$n@mw(vE${hk%?H?pM-nvy$xYb)B*5U|y^eQ!|&X#6mN2m^SVIWUP5p#n65K|dN< zqVw2`mvhhiW+?H5pq_uQV>a4tzfvN~gUKu9#K6-(&!5PPkj7}cr|<-aXT^wBP=N{f z@R@9nlG_u3M}{UK2b6^BBb@#E3beV@h*tLPC@B8#vreN=`&-ogo^TgI7L=?>-J7p};`D_xn35 z%-xdWbUhheetdkazj-evTnj*gnQ+%cD-KC4KU%?my(8lVLB4thJiccD0|p$Z(x;ju zGXYanyOO0J{JD5YmOCzoB{~9|2Sqm~gwzl$b~PPoR~xTrd_c(?UVxC&n^k_*5wn-` zkZMt3_8ZOLF>rdJk}H&px6cXLOV_9n>yBZ|W?H?O)Sd+aeh@z~NOrSCJzZ4M0&n{a zK&wP36@Kb-lo^+$(<)dj6Me|COW3dMABn_as%thVR_F*n{4ybyzb1KK2CAE4@8;pU z7+JI4dvg4siTmO4DgA?Wk6s?8@WX|x>EkrDT-&JW9~|bEP73%lCwEu=);?n28gw8R6OWZ;As1rVZokxBq;) zeMHNR@}W4@p5A1hbLZ&aip|}8@8I5G0tRm0uD3_HlVn??3hS}87!sUlkGC)T%^ z_JASj6TS?MBFV5gWqGkUuO8RWs*SsyreBbu+SMuOx8A*uNMR>`p3ph~3OV4*y8$he!H*RtMrF7T569GJz4eT8$k$z9qmb*`! zV=9^5xGI2i`DWD$hf?w=Rfn2{RUsM<0;f5ysYqA~r+V*QC08_W@j$WTShS)%D`H0% zlYOM}KCxu-AM#dVTGiQEhprS5x5(73|9vl)A+mvo_STG9?Xp(;4IO zDMD~-K|yL$4+ulgpMvSlj;_q&^mkff3M-;EoUii#o&*cCn;Yg{vW^zwXu8>~r@ft& zLHp6IHROCK67RMc2m!4NsdmD|mOoYPofHC@aQIE$wA@vH;-Wx1JGg0&h*>Lgo=Ux! zEi+BbLRByQy3EYwArp&S9UyzP1FD22aQ_QU4lKKs@YwFa@4Wf?o!XIiL*Bi z5zqpq7#lkihO^#LD|&-Nfx8&xb;$kDoBz#&<(ine>;f4$yAVx#AnF&&StyD5{-ym}#A3d+*z^L9HL`Mps9#kqBouG9;!7yZO6Gi1 zYT%M0;tmI&ls#yCH?za3CJOZmm+)zlp33WZm#;YWz~E-&qvEBF-aKwf*W0&pxgY~Fdfg_&SnsnBsXC0BQ3f%o zm8d)mYHv5W@LL{uxE$|}3L(o7quCGVx-VHQ)lOIHvsnT}LZAomXpQOjc~!=`RF5M) zp4W|du6mhBE^5q~d_5yBll>efpng2$q&qGYPdA5Sl&>Bb-x7clXURWJy`7c5=F)lZ zndPBNSZyLOJ>#$Unw;WjiMZm%?dHj$R%{&AKJD-uL0@iHW}JY2)z45!yNsQQp%o;N zI5lC8b4}~s(QVmSX*)!kfQBV01s#;9>VQTO7!}a!YkBeyWV}VYV zGU{napzBOKxtr7KjP_4NwOH8_EO=(SIOFH8Ipd|!2Pk&kdnOsc;!|eAs6DAzYNu z5gal=ibyJT;(}0q2qLEZ{@8LBogC2W036lXa$U}Ahd$j~7{B9%5qNdu+S;5oDTKP!0>@QnCUnDzUur_@+$=8FGEhFSUnTh!}qbX8WiJ zL9Ps^uxBZSV}5MUD5V1C<%QHbAOmb#4~`>^?xFU`Mx%+X-@#@Xpohi6i2IiPH!uhg z6mpkD^=c33?y3ru6z3PkhcglDhQoD5j;gc z?5xzfgDpx(lRLwKegt-oV77tv!=Vd$Z83-fWFb0C`qJXW&H~WNEf%2hA$cKd7b4{g zc}iZBtyG8sJ^+nRDTa9c5c*R2(~1Jp(%PpV2!agvhv*fi!c?us_{j0&syvQN90A*C zGir)rQjg&zg2fgf(do#}6N05k@~pUIq+`NaB7$ z83m>rwTJLmi&jSyn%^3P8AT8ZQVK?;g*>C*`vF?V0*6pSiH|UoCa{KDlz#r9Yqrtm z!hwel1c?-}-*ougq*;fiEb510(7#WC!5w2{U`b6_4>b@e3zguCuGmM*^Ol$gXIv}* zo1gfw45gsYeiyHAadZMV3It$Kz$}W5lQ5n>(yWVs4o2u1O{Da$+d?HT@IA+^UKJZb zgZbsbISLU3*4KqDJc?c@pE{sh+yuz5?97$Kq|S;>0cT{=d*Vu?@^Iw57y-VUIwhBR z&4`BR>`pi^;5RQG#}97%w|C5gcKZ_8@+aaY7ayL^!$|@HJ?9=F+)2$3t+xwO*iHPJ8-B!_1Hhle%<w)a_BWC2gU8=R!Vn-a6dG5UrXb0pg-w${>p&lv3&65fDIVIHGWK zM-cyFgLPcoFC^Yot4vV69!QU8rG`~D`#+{3GqvKQgSg4c*>9tyI}O@h@m}faHN@tc zi|ocj`tcbXlLE<pP@AJll{Cd23--aICo4N;ii^lclML); z|8vz;9nBt~s)R6_zY`o^zp$N1CobS_>yf_6e04fl?bsOJF!Y8uKha%%y*ni(JIF17 z>h=J%#+|j_u;zwDVgoW)`>yUz3E^*#`liny#E6_1skv(2HKf9csG9#si2WyNn)Pnx zeiE@#r~GYXyrVmQYevj`X%2wPER4a*UhTJ#Mace^bG#*yWP&g76M3alUFvn~KFXi@fv46DI$Z#y>y=q+j^Lcs(YRUaCi<4iy z*F{kOl|sMJ`?_y5f!y@}Bm$UNfZ2cj4-`~rIGi@|F z_}eZ)i$%W2Pd`2#oh=(3JWB^5 z?!(Jgv$PGUXa({+TQ;l=7*=eIk9fnBj#RWWgEa< zTK0kb*HR!*dQezC;rty5$ah8%MwCYh=A@}`@GTr$}AeC zfM@&8o_P7i@C>N9Gb11*4Ccf_LQ00=NB9R}Yr&GgU>3~D*%vi;0t8L#Hmd)V9S9K0 zDpA;LzyRy4EJE}@r3I?*Y}o)pA|iQmWI>#qU-AVU-M6P)>#?ss;X_AvJ2q@VoLD+! zvl##XmFhR{=v5C~i|qM;7pjPrFDrNhH-9P8)1lp7YDKll|d7c2?tE2FUIY&o52eGc>&awa(8U z7i;qIk5L+_6b|>;O{q6ySM9G)3w_sB?Yb4WO%rhDHr;r z=W#BhjKxS6nWW1jK2uajXxL>EI_pRDI%L9@JgdZW_K}e?&<+iC)@z_Qk?CFv9koCI z9rv0Sgo1RtuWc*nt8>tW3ZT4rvQ#)<)}S};B_ebYF&8ArtooHvaA<_$u}fnV3Qw0> z*F&Bs{&tW4vv~g|aN62B(S3~FK;;_?^x*^vFK4XF#gC>Zw45h2lJ3~tC$!Zi@YBh} zO8^IsG9(`(#O7N_A2W4>Y5p{+jPA($jL?}Bh zp*~aSeOf*L7Mz+My+{EEf)gJ@<0@U9%YaV7jXeiN1?|2htpy*L;JHWyq|z#L2tLSA z0Pli~s534;KN0iHsMaBQ@_g=N6W~zyB)FrweQz&#(n!Yfb>@&}JDpt;1C6ucj=&|8 z$@+z`y5nl6MN2vXj_>C&Bs3U1eK;FNV3@@sg?MEM04E($USs!Y@zXZNa5K z^)NGP0e;hKe|I{sZmPR8a~89QSd*g&gJO^5erj_*?%`g)Dt^Jg#R>hQ9>MEF!aFw4 z{c~rw*x4EU@!+KC2j@!WA4P@5Dl0|0R>3{?_e1OVx!N57>+$K&`=J7~UhhEeih)CP?_;6GEa7i984Kg3_NlwzXsLn}esYLml4e!e$yout zn;CmMPQx?SIwwbFSR-a0MQW@3xWZKr=sX&&bQ`t3tGvd%2+Q)N+bQnI6kopN$Qd~J zta)@Rsp&iMH^Uu{%W zzrgeclBx+7Lae$@);vswE8%zSqxkIa*E7rl_n!i9t5u%Xb(fi19rjYPex`Ig2J5l5 z1_6bF)OcWRrq$XL!IVu3b`6m%@u--&e*)P2Yiu&(7b03t?1lxcz;Ct zKNE+y*sFurdboAmoIFxshEsJMJhlF_(+_)u(+BHZ6_nh=I0sbXHGqDonf3Ws=ZvfV9G7(BMj6Yz!N0+r3S(Qz9XOKmwI}OF8nR zeAmbbctnbMzem3N`Yg%HK_UtOwc@!{dou^r{fnaY!+lI`O`eow=SQgk`fd08DlYq6Rqm0TB|=!sT+I6J!GRT_;~ zA&zmm#jRLw$b|UH5EzjS4}E|D>b}AJzk77bbVL#-s1(L>eBt1Ho;*k`mdKBSfoRKm zvl}qPkjoJesFcc)p$r=moY_Hdc4s^;Xk zc@qQS^Us>DhZ$+*iT(2;=TqJEy7*rD*7hee7StczdCxg9F0ELQN5Qp~#z)IfN0212 z;F6~p;F5Gy_dPAwYq_(FcXMQ3AkZz;z88`{p#272bn}z(i*0$Rh20-_`J_I%?!70v z=KcKZW-PrZ{)%j8TcdmXP^XIM@@6e0Ggf^5*fx(*6v(#orNY$&KV-C#NhIM&;8v1Q^;iUJq~ZW zKk8u0PRJ3JQQIY|+Sqya`E}{#bukkx6wli9F%eNIuRH;^JX+Ds?AMeXh=R@?1 zr71COXXd~x#84i>n!rfOHU0K*_iP=nz@jeeP*rd`-FN-{Q`@7UNeO2T9tB{gH6D*e6?S zH^vXAKZwp8>z?K6SJ)a$l%2Kz^i=GANymT3X4P%Y5(-n1=45fOaio1T;O#AR!FP(W zr9Fwgq%*NliUXFL8MJBHZI|=4ek*yvK(Mysef8`xRVLUxp8jKE+)L=|$F+B9|k` z9+lH8hs5(6wQNn*2EV-~4wP-_ID@;``y}!>F0-7rEMX_<(#>0Ct!gAV5=8OGkMHW3 zCQ%c;8JYarOl14uNXZ*L8P1e3%@5O1xWMYuSW(yXlmN0k`bPl8 ziVkH?PGHlaYDfg}BFnmKhms2-h!bYnVf@R2m;0P+o;YQO)ThqVTth`nP_L>&FlV|B z!ar^D)SG+ir(x~-vwyYSes)*1Gsg1=oq_v-a0rzCi{~WpMclC8IC6(b1OU{8wZkvo z9=3VTH!nj$;}cAPW2RkHY`Ps+I4n)k;IVIp3E&r(cBVJ8o{JVH*l#T8Pe~Y0OyXA+ zVQ+<(vwJ)Uoi4ILrZT2>42Mmr369i%_0@(Dka&1PjX7Ahn8DwSQl^W)tV$6K_3MHO z@UUhQQ!bZ85HeT$xTcCIf%)uNxH(Y{ts$q}W)8K?o%>fIHF-4ze~|n%eJVggHObjg zCB*%BQSrETf?UCwNGV2l20r;1=p*x3NuJwRNw9aS*T5M)%iiCgfX|Zt zZWw*zpC=Z#hqZEAQCRkZL^f|I%1Y{lyFL7Aq+q2PU^)ZrCJ!NA$SeAK z?got>6QA308P`$HQFff2of-Chz*YGDW#|Na-}fj++Zz7;(|SKm={pCODYM9*8e!z> zAE_lmi7a76QL}Rk{PwK-!f?)izCg($RrMl`2k32BSf`8Nc1EO#q;rL1ow&DJ=A@LA zfIL5+Z)HZS<`2*L<0-#sKr&&KG#Fy8+>(|aTT9BBa~O^5uic**1*-&RoVy-Rzdcxf zADoTSs>)+!iDL5f4lan0B~sVn7g7NwUCaFoemdrKatr{@K3(I$BT`ljBWhD>%J^wm^CZQI=Q@9h1|z%U76e^Eh2H5+WDQib z>j8ldq^uuAV_W5KF4tw#y)hTRTSl*T2md9c#OM=`VC!AYg@eTR`2YAi%b-ZwC2iyG z?(XjH4uiws?lQPLgEP>$ySohTFoO*4?t{C#G<^N;*|TT&&lk~uI-;YxB{uhJOnoDolbxBq%ue+BUsEg)i@%orUHap{BhVJsDS!ZkJ7G`Dhc_T)x2GTcdR}dbeep^2fh3}Op zLS7#96&$}nhEz17zZ*&YP?>!DIKq*VcKKrX>vEJZnxvE$X1Rc6l#5o)Y{TFw1R0{U z-2em1>0#lI`uUIA1=M>06L)(NyE zMN)f~+9%)V*I9d*Wh*MHOuGD#?yQgI{AZ*l3&<=P*y2oIxoPP|wMGv`mo%*4<}|he zj&n>1H079+CaQVd=igL|M#fAdN<+;B3+# z>J%vzq&@A}R}|U3dG6xGTf1vOBHQ7^`zn1}ges!QP{NdwMo!19LxvTayUgaGgIaDX z__Vdjqj{OKH4?}Tdzk^g@N}TLj)_?StNNwVKo(aT#22)NEoG;_WJ*0+6yF*K^?*^m z$^Jjfa-J>2GZv5R>wR4wqM?R(1RzNCDDLr2oakpyX6>Z7LJ-RlCA9j_LWWi043rIe z?exOY?2MTjX33p-TnhHlaEhbbZ^%O=Tb|4@z^o~2 z4FfkaqNC!dmsUuH>g~6c89eMJIPXTg&xy*(uf5?~d0aNkWKN)HSSUkW zf*Fy9`C#=;52omdiJO5#{}!>a>32UId5~CRERHnscpkkn`{!i?_K5hu?*`?#7%I?v zxKTQ8zNqtShgLBKeO*x4U*WwDMVf(<<)r*vIoFL288jX<4UEjznbG;r9>7YyP`HOb zj{JwRfS`)Yph&880}qA+7<|U?=HT>j?v3xSxN-;9t3V4XFJ+p&CYYye`tNFrpKEkN zhUGSbEdYl{u$kDN>21+8bPKu=8nZH{l4E;g%flLo+X*8B!(pA53)spk<)NHQP*HRa z61T0Nj_+EqnqHJATz-3ujP@()%1j)KRp1(ofdJWxgi3lSr3Yt6AzfZO9e09^ftCnj z63RX9(6W5M5IBR%%1)LO8~5*F9%N9WQ-tIXvm2w%Z{!yOBy4q6F9%=8!ckP9;hc(6 zyxzU4Gk?meZKm0pO6fPa?c#Mlk3IM8RGwWj7_R)Ckh`QghhZji29jiSoz;N44oEIG_9=)t-Wfd5ae`uSo;E&Yp+? z&n-&sVHH(5>E&Hj*OAMb59h4-&ABnuZh&U++!fbg4}2p!Rl{^(XVW_gym?nGM~aBv1*IqRj=FeG^G$0%37Bxgx8-l^+YVra6hWN1wjqC9#(D z-1^=?z55GT-NF6xL6BaAHb-S<;BpcbzEt5h7z;c2)=hUc)E)e2NW?t^GRY}Ek5<3U8BBr_Czhv9t`4TNNQ zZ^%pR!cpto)MHc| ztu7$-mhZ{adteh>A(_ZFkz;NUw+&_#-7`mD;M2Hucd>M36b<_W6s?dlQKLnF z-3>eVY`hwe#;T;wub&U#V!?YGdIP~vQM>zp;06vjiQql&_=xV%K5dVIxX5XZ5%l1{ zidwXSaBDekyw|%3$O8=aE%4e|p;T&~{`Z3nr zRn`79bmctUETR`rwEH5Q?0sL&vpd;C^ayrTG{oEZ8h)bO{Rb zhHdA5Hkd!3$PN(b(8fE zsh>t#znZxq+dIV^B=YXC>#{Orj4*;xq?-W?m{)4XUBMAZh=+x1)yH^dO3LcOyTi(D zbQC{0q%1}(A*<_5!;vgpEh=M1NkyYG`N0&TRH*9qB(v->_)fFFOsQT3u%dB>ZLLQn zT^F{FZ7^0s!E=(()fjrs(DmFBfz@>mB zkvuulTG&W^@UBIBhgNiUUg`=&wgneRm9|fCu(+6-w-%@~hz2)ggmyTS{&SGK9^N zQ6}|1K=;5CfFOhobUR zLlWSn@r~hwWZFOOv_e8vrzY>uUXPg*SrZo9Pf!?e*}>;zj=@Fk_J#`j->MyIH@|K7 z_O|w2YT4J;uC3|W>(@%_G8MtW!9_JjP=_T1Y;$sEP6Qr3$znjkQ>n9M?)&FO9^t!Q zZScPdA8ol!8~QS9E5#DLK4Bxs$Y`nW3 zV-_J;(Jzg)1bM2P%z5Jt{I=p5_L{~5hBG-qN&PVq=jo}3Biot})HK3P%{G`rCr+etGL_3gJV5PkZyEH#9c z$zpe(&VP!8pvpYc(+j3S3piZwmk2SVH9G3byw%U;T7HmZe+pyBq=rs=a^g9oW+-Vr zj}zF=oki%B^T(2(9q$?gY0b7SUwqD=5FXx&;#5*f*3oL9bzRP|LV8_K(m|FIyUAMJ zMAiHzkM{RI&cdrunNmQKBsOQXK&Fh0BI4z)mk%&3{YE%gC~?FF5gIz%=MA_nms>tW zld9%r!CJ4~&kfENXFOGlilf$C6uEU0b#eZ7L|U0}gzk2*xxoW^J&nh%-sAh|l^*3l z0Wg|Vq^z_7eE%(Q&}Hw!@Fv_2%759Aa)qm54olC!9Rgxho9A{cEsA4CQHbo>m;`=dLyBgY|t!3H9D3DW7 zCn8BB=la3eULn)+H<%~5))P?y7Z5aKTV1ySX9h=lL8vLU2g`!ZQb#zA-vV(G0}us0 znh#83l_>cG@InI%_XV)@80q2HSH0Y6)c9?wWSZxl&%vnY%Ni(Hk_Mf-uH75tjBNfn zG7)1x?7)-qMyn*x#g{j^!5z5mzTu1uKS18P3Lg zB&&_AiSc@n5Swh#%&dGlQ(W~`p0ZsSK`jG{eKYFI_nz(-f0$V}|NEJsbln&MkcX{T zeED;&!#4)TLMB6y{3b#nSx=Kntd7QfMkht)=0BT?Eb`_R5Ob5p_5FHv|HW{Q>d%p~ z8NAtawc$pqLeXEsPdtz>c5lsIc!8g zClpH^a$<1a5R?rws3wc;%n4PsX*NDRsoY2zK^by`f15|h;9yQwap@E6u7pvjCh^r% z#4DRH@ok2kzG+)+x21gp`t0jGHa%Rut*$*ith{H&<_jf5Xh6)Tm;Lm860F(oOE;tu z{p~1v)5c=;-p*&nC9o0NqAisisLR7&>+$V*z{$rm9$H18IhP$XL(u+xxc(13BLZ34 zO;eKXic746ismh#Xm}=p` zuK-l&J^gGmBgK9zW+R788A*}0I8d?jf0o9ZDV!~LeF=bGxZL_vR{n+04smAH(c-Xn zepIC;?@q0GR{7S?nS`*WC##=N(z`T&4o%6u@R%~ZnEYWUDS|VszZ7i=(hjUe;XAXs zihpya@K9=Z*BhT>JZf(1(_|?yAK;6u5FR4u1_iQIPNxudZx*=zqQ}zbh;t(_lE<03 z>u^C-Wlvks7kk1;TJZ7~v|np@)r3ju`-PnM(;Hu-adM?%ppFwgQ&TL*DE#q0KcV`! zKqzAxX^G{9m65SmFi?TnV!~8UoWi98=N=s%Pb2N-qB`zoe3A6lF%?r8_$Sw*G{f&| zp-jcH1om}4|AM=?+rS#XQK)J2&n8gpMqqZSXW zbV_V#uAa?&nbgOAxvQo+UNToO5uS$f28Nme8?Poaw(l`!!f5@CP>|C#dO;@>=j0a= z`P(3tB7VV87W;R19|o;~;TuCwKgx^xo}rklx?&>ggx^V#xUQ4kE;*ZN6*F0wax6LD z8T0^w6>X&pTDy&Nque?TXmQi}DB%#{V^aRV6(Qt7lDuLL()k?esi+I8AH%ihzFxGE zuVdp5qP=;mtB2s1=hf^(mWf&R1;Y?Kx6g6YkgmCaecR-MOJR|!H}C8v3rpoCz`kPc zP)MfXh+zEnnTOw7YZ=?cAN@?vAtv8xdo6^t&A4J9_nNVPI&bwuf(s|=bY6eAi+P20 zlKW+IR?sj;+1W*N`@Ylxwpp#~TyGHZ*<;ZALrxwY1&5V7*7|zd{`sjBra8MVF35o? zJ=vNQ4O|Lo$;gz#P~sC$2(2YNFH6QKaZ`WSa3YsIbcbcV%eOs&rHf?< zxAv!UX^`f`4|q77oW3636jHqIjp5Z1A}*keeg|ry&~k@XWoS+5276yzP|fDV*_qzX zLdTIf2Mx0OB|NO%!Yh_ljeqc;+by>z8FPZPe(ZN|UGUXIcGq(CGB5`rd`yUuw^uH5 zc;6gJP--L$Wce9S6$=J=zZ0e=dwAn5LAg`tET43Ic`4G8ks(t|&f$9P<^CVA zc{rFh_J!=${#m}0)eWhZ>qE<)JSq&Fch7TaZ+Mu%W1}_DGtYZ&dW?A6Ou0Lg&HvnS z1v*rGZEcM$d(x(5Z3kuQr<*`72vRC4>c35!jhdgG{SKmtY=~^1^kiVwf>?7K^gM-0 zP(8bdvnL}c&T$Z*ucCxV{d`C+2l@Z@`}7!{dkW&jKzA4@J2)`6w6uf{`aV&MW5nWJsOv4M%OU8rIJ1wy5*9QQd&?uzdtDfAO>yPp{A(1Gw|5N_WX zIy8zJs>BU6u>UPZg$E6Jsxqbw;5Yx>(1c4$IG#esJ!>)9m006;S^OIJxi^GxP)oe%8{}^j)rGqlxg@HP-vx5hU!)eczgX9#ZHkeJ(P8x;-I1rq z*S--_Ob;97MGCs0v^xj(1+|Adj{;V}Teh#ti;KDxj+C&KQ4NM)lqQgOfB5{B?MeVm^Td^j??AgOVU*!L_ z$A%yd3&glFFxX9O)?)p$d7+JHw_oA^l1@YQVq>X97c58{wV+F-tmIbPGxli zeoH*HqcVyzozr& zG$BB;&hu5A9m zk~9|MU@*u9<~~S2dq~StKs#78o!NY{oO08xOCnK4U0%=jii;;uDe8L9L1gNtlSRPr zdsDAztP-sVKR{}LcAS(>li=H`hFtV{eV+)#mU7io>g?{r-mDZlezu%Z88Y(BIzq>Z zqkY+-Gqr;l8%1783Y7Y;QrJVb2&?a#SKX^%%Dvm1(bq4AmYl?{)W^xAlX28*HG8|c z@S^7BYkedZX>vu=AXUM5Cptb=d{UKxG^K8g+_4u_UDRCnvnA8yV8;G*I zgO`E_=8gIKHh@ia-5*Te%;&<##4z-NHq>R;cRJz34xO5%Es-3ysxV-1=fLG|k1(zG zRWXNuFBk~qJy+)KLeT^>@#4P1#CcHYo92mSE+x5D> zVH~PY?DPeMuIJU3jAM(jK+4f@1VZ=uUzy@WcsA~wpsuQ={@Og#V*gTQ`F7PenZI;i zveKELYy3jo*T)ZE{XtXxoV}iR0BLexGJG5XwcNMQ~99{we*fk{w`ZU#{Ak31dl1if_5P|ThZyxN*F z-0GihuU^rfxuS9)JxEIt9XYrzF@`)(qC>3U;H zOS9ZpRoi)-(s;i*-e91_H1^;pUcpD*nA^<#)aPDMU|;sdaM!EXd970*ezMaismLdQ z^tv>JbKDpcL!b#T6z{N8Xs=HHBb_pN?YL%p#LWvxdZyo15tBcDFn+ZcP0C6uTPsG5 zh<>l_YBtRHept7C-3sB$;dsznzctBw*^`5`IC6D}!W7jP$aog?M$z|nhf=lw8SuvI z3?x=~m51t%^!XgJe%Y&E`e|q{HKset8t943Xl0F#%cH%hjF|-I)8(9NFgb5rFV^Ht z-X_!;OaDuCm(YE^()d%j_ih7xOLTVA%aj5_=MQClV6J{0J((Ndo>v+u)rbtX=B@v{ zntnMd3ngl`FwbpG5(Qo=mknjJjk7LE-=d#(`-tcSNurqM1%f~Vs#q*wK>MQg{Z53S zX8#b*Bcxs1u*%l}!BT7`DOvmmX@Y2uv&3;fL3ph%SJrLAvVPiLS6&;vF$59EKE`|N z(oZ)-^H+yNK*7HCm45I=MJ+|>O)_l^k7#Md_qlEFBP&*M`h~aQM|C|B|8VSj>c+o~ ziZo@x7Uu>xtGWW!>N3ZFzrPC2;{xA1Sn38^Ma|*T0mc za{^g@k_N`3E`5d`eKGkS1Sfia76F{TonieP%Bn@*pOEjcaUrnXc%bELcy;;sxh=nh zqyr}gyGcxXeLgmM?DPsQ`so6mIc27>{lO{vx?^wC*AYvtk<^gmnX}~ZX|mU)ue+Ty z$vuFXim3Tzb&L2NxIUbDU(M|=JggYjC;O0dlUwocKsyu_?CnlBwp_9GKhhRz@qqoF z5K+%6*OLs9mH!#rH$n=6)w1RzjtozOl>^HF>qw{n&^z(Z>JL=uH$@+;W|0_*`;%L zDQ+NaWS1={|0AAi4$I|FpwgSR+qDk7EJp8O)wlx)XY22D<*!Yge_2YE{{_G0^N!tm z!CHLTF2gvFuKa-y_w?yC0gnP8dU6`i@46s6@czkfTUnXmZgVRb()hJ1LV zuaA^&Cl`0A@#I3-|M*Ao$&?n$)#{+&o1pU&&)--Mv-i149l-F)1}Q4Y-KgKYY*z7| zyG>mu;Y;gpaTRNJ`;Q}Pk>m3+W(MMH?l^gLqar80Axn7~Gp^t^XzdG>k7oWTs?q2Z z)EKPbR)sMLEzQao#r!16ysB)Ay{}k82Juxz;XKdnlB*r*!mx}ho{Hju5OlEkSAuqr z8r_fS-S=t9dHafg0P%P|p@o+m3}2q^mM<8RiY@S30)n18uUnQ}D-VJDQ4-)n@ zOlGGjKM@zb*K+s@cnzsgn=j0ObtqMOSS70wtOB?tl|Nn&LA_MHU&-kQoaD2?;y)y2 zHz&IdRn#|khwxYBB;!Nkj{WO;nIip#p#XREl>&p`cL@j*q6z_NGLQ_C0zR0oBlx;) z1tNY&6@C9qN%AL_XgI`#=CxWa)wr>lo^nrQ2qsz>3r@{J*2ri4t{TP6)K7_4$`fmo z9{>7cT(C7S6GKVhksUeK;}h%07kSg6wY$q`TWe2sf9e>w$w`vi07yf?ek?PfF;11t zL$=s&ItNJ^!(IZt#gv?bRut zEsB`0Fz z7!XBzRcaT=qXasH2*Hf>5uZDMIUoS5c_$|@zY(;&lO3H7z!xj)pjO1^R2T;D zVnH)!C4uR#)&^uf=bM#oV)`M~MC5cv^3l?gGv0`Uk)Qjes4J1PR^UV~;#c ztMJ%wN*5w0$3KV`n>jE=R~kzmn-3=QJDs*|^v_asV=URi9eEl6If*SeED)d-`Xa^1S@B+z4zNMdm0qdK8Uki+@ zryyVj5MLbX(Na$e(s_DUUUea-2EHI;9atyf`{c333WP3f&p%%PxJY~>``T#SHp2|8 ztk!4b1K-uc4FXhXH15nBD#73dH8RO? za?W%MTU2C2Pk{}webu!-@l&TKvXf=jtS@cdy#G8On=GGTMGb7i}G&A48n)RE{jkAUYCvQ>R}p_vb7GS&OT@3K8j zH;u$bck**9AmbHsxI)le?4so6ms%XDec{_{y|Zoz4#?Vk-Nl1jRc*Ha=4re1cY#Ft zwfT?fVx9!)i8&z}R^yQy4#@9SP?sM=!V^`Cs)lMm{4f0-dp{L!1sPVZ)4g190^;rK zI@7S>C!5a$qX~JmcJ3hCPb!#>2DC*(vOmUfagNw^UlW+CKPP!b-N_$nLl3<)H9X$g zvQbAe9&$7Jva~hUN&P!8iW=$U_~mTRTtrqX$_M@ySx$>*&6g!6k*aW^A-rDmT$v8% z;Xu&qPK*IcPe4vDs7Y55&n}9+z$3+8VjG>9y&f$)mY+xfi>=mTEYh047Uh|YPPy`T z;M|Kq!bO<{_RI;zw}iN2*cE9(%Pj@F$MhXtXXM!%97VC2O=ar?lC6zPij&71DqDLS zK22^Lf_S=Cm)ItN`9`Ivw+k0ZQB6q-Og8F z%F~JlzK{&TNqADpA&1Vfu(%0erv!JMa2Z8I7xPPqpG03rNaJH$& zrQ4QDDaN@Ao{L+R#L2W!d0sF>(>_5~8iUbkVDI{`D>$X2n72y~?{wtcHr)Ju*NjLK z8%ItXCjJB^dLYVDdGfr-&^2jk;L*T8hVg=Ffj>EhvVner$9aMRx1sA z@F}ldGPj-BPZ!7=Enn%Q$SQX(SVxdCc$@DZ|JK_bRVe_Al8zWDg3+WN@OY>98{>y) zRe9CQpRqIA!mA*#^^^W1Ft1w*kh#!r^oGv-=Oz={QU2%R0%_aE3s>~OYhFDj<5oh&swERYh(R=dQLfL+jafZ5R=0bop`?N8 z!He<-S=Rh$ocQx4{1dN(l#1%VV%mnk56nK*565@~W6#LuqsfU7wDl-A=*vG%Wb0y} zuFaSGgex91YrJgaYn!aRS?7IjxH`Tqkv>bW3X!}VVjS)dnZQB2ET+2d*7n`aHcxZ1 zfZT{EuXcW^&1X8JRlo^LKXP_CN_i4>JPn7+P z&M*bmu8B5=^)u&R^dbNY;GQ*`H$rDdfm!8VVPL$5$Qrsl<^qVy+m-ul)FS+}w}>xh z6culbg&hgeyk&RiLZqGEh%(5*__;=s{tEDnyf#PToF4r)O*lu>tzP3Eqfn677!9F-7TPQmCg#JW^cWM_r!%wZwr>b-H`@)5z?yBSJ)&gnGId5^an*6Hs?(=UJ!0qbiNkOdq z+2gIVkj?n=T^sk=%hCry@7p=CqH_25dQm@Y@fH$Es{39V+QgM-tFclXy|v)MI~Wsp z8{(3Wyt>vOWv?#T z&7!!w{ze#z0uZTD`=dqgFm1Y1?|7ztktH2lIFQzdWtPQk>k0E*;mFpgzp7V$i#e` zB2yliE3;dQqaROfDlg=f4O&IYhJaK3it`(7zO_Ost~YiP{p0Y*-1ohg8QrD}hWPW} z(ci=1p-ZZi$Em_`a&^D#;!~PJyLKR@j>U+g32;;UiP>=@Btz?KK=!%~NtVkNFJLUr zgizA4&zL3UmcH?KdSRZ4+`AU}GNa$mIRB-)xWy@2$7*-#1bjsw=0E2#Qy#Or-T&6O zC~U$^b*GYjQs-FEI2YDzP1*IdtonL~s)JkGzpeM>B2n3(56G}}2;1K4On?Z|vu|a5 z4dm-h=s&NxlX7-X@HbjR=^p;*k)_}6jo#E}uISFyyzu&46O=QShLUsFsB>IvV$Bxr z=hl?T#-7b3FPYMqQuDd~qo*#$E`S;IypEg{)VFzgbetd%H9Q!$vGWjL2ZpVYm>s-x zxtjNz)IOe`T)2$p z@|siDJJk4b^Derg?ex2I_iV%e!NPU--X?{EO@HQ0u|$h!9zWq4;?Ot-O)BR^T1UHNozjm1XzBXPVcGl?ibY(&FK2YZbY-FD!)|WY)AD(I$RW(5vnQKY2 z=_Lwa+cr6Lr-n~ls-=9mZ{9SRTcXT-N~<;qsb%j~&HHri=lKV5%kf zkF>)C8*bNAc2atJe$t!6Vif)@RC}1*Z;9%~3DqC(EBoT1P zHMs9o3yoaDh(;TU5yw!^DH<&Zc#`&na^=R+RepawO+L4apchw_0+`=^BfZ2E?1{1B zyUttqo1Doev-a~ebtF|GMO?J7S6YG$3S_`3FQdvLi;W&m@4(ZxwItQX3)g#M5)^z zc4{0YWaRbfBv=Irghe;qZ67w_9cplWY)00av^5`mXWU_!_Xq+5Uf zXdCYpPkpo63M7uPjyK;p@k-c7z#@l#v5iUEdD=q^yBSg8dT@bKz@ubrMZuc-Fw&S`^zz9EIAq2-1 zSIUe>ch7J*7*Co>)w82#7^C(eJxMMdzEJ29+Soaj+HFX=GBGIrv7zwr#M)f^#@L#i z?=+~bE5mFuJ!Y0eKB4stb8H;ux~FDvNadP7Nh`TGsC&!glvz8tiZSw2ik!3r$SG5b zF02FO9?TI1#v*7^VU!yVN8=#EDjO*qxuP94NNP$+CnqI|y}np+hZAN(AcYR{E+}}N zkQ<47vpSq0a>bmqxuKL7c5gW{jo~sSwgnoLqJ)!YX-&=Gd;4Qd6^MDVs zK3z=Ng0~2|?NlRq$*?ciqJh3Owe5B&H&=^^27=_FD~j-5Z82r1Sg!NM?D#77xsqb> z1ObWy1gSAgjkVu|cOcVqFHN`uo&2ucH6*VT2AMr%xLn{%XoJjL)m0Dy)TBRsLvh2a zzGL;kFpCg*pyVuNXQmYo5O5XoLM1*dIJ;{@ud;*t-`BU8iq(!={Fw~=@b^a*6fzod zHfI$bOvDkT5e-JRcNI!bcfW~j$(H-3TqArda6Q(CsO!_l2ioJO{^i&pN-`ay@K8+1Pkk>wGOE$fsJLz4$;h(vEnRD7d zE=v1^3q%_O>&+UBizcih3K}1pX6g%hLHL}Gm!is$UB=J+SC^!{jG#H% zds3^5gX`jmj=f@dIyw$oD-{(pV=|Kek}fTWTW^QQ@^6&KD^=V}Z}flnIlW5x5MDpF zOW$dr1p#N_x6Mt`KfAs!g;x8VR(jB-2}v}{hu42&)F1b4lP$$f!m{tjAeFxCX4%qd zir!z+H1kE#_?DjNe23)fVTUAznNKRNX~{15`AT|Q7xi0TT_%(|aX$oN%5ii+e48Rg zpZDi7DWJ6&fDeqJIxzn7dr*_3CffM`R91NbRd_r%j+8{96T}V``Kcr08}Cv9gUX9@ zjpaB&vn?e`ik9x!Z{&l^MWfz<6l>9Ye=J@=g_4&fgc&S7nU(cUBZMQRs*5}N z5^=1Gc^wGQZ8jyF!&Z-W?a5Nfiv7ms_iryt1UQkHjovf1AJTrx&ez7@+$M|u4f<*F zBX3mOC@?}dTnmH#C~95a&m4-Ld^NMWhu$5nFD2V)bs(9w`t+vuW5UAAV?+Fq{~@a0pdGMMb@bKE?J2cB8-#_`uwhP}3Cb#p5gdN2t@6A|gS(QU9!w~l(=cDqg)0q^IT=`Sy1 z#&?XGzq~I$CXYH!Uh(&loRK=z0RsKOT8o5nh1g)!47D(|%ETYxFG3a^(5G;edM%Al z*b-~r6CL9(qo1j6XXYw5Kw7&U&CGWQZCpKAZz7!t^-}5L#T{*wlz7VIriQ$TQ--Q* zjfbw(b0G(PDGQ?Uz#9@{eZClbZN5b4{G(P@)*}_L{hv0Ap*8+C{K*TyO1=thTubKp z@4#z)bdxBjjv6~Z<$NF8*SU#)^;5tV_9UJ1M0RQ99FG}xEZ>o1_s~PGb$So!amw)- zl-~9WXWeu~*2V?(Xi?u&raxI!dN$-8b}0_)bVlc^X&!n6x5nD-waG?9Qnnr~d+%wF zM?12=qE77<9_(aM2E?ca20~B=T#zzg#(pC7y$mtc<+IO(zDnAD!c_H1%J+F&)xIK3 z|5_!QB zg_l{tjpa)a$ai_`6^|9p~kEI8qS$<8Afcc0le8{YnZ$tmX0_@a) z`v0dRLL@45?rV3$1JX%Uon2jtuOtvlHe6CNC?Z!?y&W;kehRjZZfHmfL@f3NoxQmW zVOs}i)r4#EO3msSxxo_Tv`bcIJNE_{=As>X4q)-c$s}#0qZwi;DEqxEYq{b=Hqi~z z1%rT|LgL8rP+Vx&@U)R$iqjdo}-@TlbDFe)%!-6)F)z*nOdOju>wD zDd+F?VbA+To8iX$Rxy)eBbpb3BRN@cbuBci9+u46u$OR;VY8ROv9s^V#YZLkkd!&k zF^tXyTh#WZl9w!Opc{u(F2X5Fr*G$31rAJ4jQiq_!5hX*E{s&30>= zoE*A`FPrd2cCcvv%uib%RsQc~L17PJ`Y@_>>Zl5dbufoWZ1jPzm1N5RM z-qw?h6M0qR;2Mq*;LeeVuE3Rqm|h$c5tr9nYe&J9sH0phYrXJWeB8qOFGQ1H$qBEpon2!{w2hlT)(v2?3=TB)biPoW1D${ zPQv&B$l+04U+{WdKqWmVN72=lBZ+EuanZvr7LF`^oE;Boio~x{n4?7`4uy)J2YjTZ(?2_z_h}SS*(nD3^W9Ofr&O3mc zW3C187B((io&uZ*h5x485J?TfMH7$AS*Hhb`Ctv&8`ug+QeJ94Y$$AbtOTrfe|yKPI7QEWe_R4&Lsc0Pqs+h~X0D zAJL5fxtJKmlB3dp$UIK1c@L)a$_A3F2D~R{+S|*1kg4bnN%XW$ zAmHbwBPlv-5vk*U0fbV*eR3dCH;^7_{4nQ+IDV=Wu*dz6-D)ZoynK?4lank>GP0Mm zh{pe-2MbkgMh<#{`kV>F;#a^uEVYAq$2SIuk;L0=?(Oh-k50tu23RZq0sfS$uL}~O zU0&}0Vf@7F-O-Wguc2E03;3f+W@G4dd65S8tbqRQ>nQMe-|^f?xNv6Wv>@g`z-i?^ z_(axhz|FTolnOy%jJIq^MR~Sjttc5;IHwC?5d}d5gZx_RFoOCL{7W)q!Eh$9TQo=8 zZypsa*bXBAWAz{R-BSA;@S#P7^;D-|rcLz4v9xRE$t4 zl_*s8UlQ*!DZWJUu=m47DMxH-c={^jS&o>jrqaB~F+u)6&Zu}@&3eo*q2H&broh|A zEjW;1AoU!cyP?TIky@x4Wui(!Cl7Z1{FlrRHI=P}jx@Lj_DhBUdp>oHH8@%Ns45-y z28oMVgsC+ejS5ve3RT9x8bC8TIX1LkN63Y9_NpTm0o$nP2+-FZ8&DGD z5**YBsRRHSk2QBlc>2G?M~`S=3Ds(qixpoHEW*TY_a5X%unb-taBy{x( zwJI)~6kNAki73@=CpiRSgwh{d15c4dvSfHvVMLjV;fJx$dCC;WPZ&rMaFr2RW%;r7 z3`pgcNY<|aH1g<#{o%7m45V;4cCk$aXm}WZZ($K%`yz}|J-}#D(fOTtH|LA5RTowVB(dZmm?;Y z{#0-v6iaT3VUJAPR;`k&Vyg4IN8KHDnAdA=H2_E{EJet#q=KdsA70h8#7^|YAul{|7s=B-qvbnSSH<2TFYg$%iZfQrXE&NEf(LhkySozz zZowtEySo$IgS)#0Ik>yKySuw{`1XCj&+|@A&7b)@bBa1udmnc1?$yh>d#!a@<1h$U z5fRpTVLe5 zSU*%)de%`oiyS1V`1&lPlW@3{rN-bWEe0IGN|IFv+ z!gSEAyvo9}zfFqx!J5~rLtbEy0!>v1tXdZ*Y^pXsR$wI|C_YIDZ z_x6So#7AS6hfJQP^Z&AhDQ36qNOffELyMTY&PP5!$1rQPp*fe;UdLY>1ufSLu5Wd7 ztk^#GGt4z1r%r6_w z2~=-KE-G(OkyJrPNUv$Qh4)1p15WQ_B>1!3JK~v+bW$C6`1}3Clhi>f=fXKCh_5#y z?5|FIpA(=58O>9n@}BL@R3{-bh$0x zcMV%l&WNn+i@6%#@gu5oJtMk;nfYJ48KdcAK_i@onpYpft-XCM9Qc<+(|0_v_m5o8 z*;TNf#+Atj=z%!=B};M^mbm?WW5D4A(7h=WBqKygs;jI2t>JswbdCH^wBCZ4l`!1E zNNGsOWR3!LwW#_}Dv!MR_ok)_|4af7dR3&rCv{9V_~-JnWDs#yt=qYx58Pa9&pt#3 z>(R}i6!ct?_|eZX9!qZ%wz7q+{1P{6mQM;B%1hSEBLbV7sRw2$V57g{^La<~IqO#h z6XlURTV?i4N6jTmb(z8~_gfw3VxII`K}E(K=*m3mZ9SuyCVfJk-&GxO!vN?V9g6mT z{d;dTso^<}ST2vRJBpE*Y+jyL39PN}cs8f}VO&!p#@`@0ZFvxH)_2luDYS=Pu^*6+ z{ubOFeg=Y%9ML$&jetU&UyJYu++6Vq&s@VFPV%rhkn%xZ9IlJ_c5`)aPnZ#s2DC)pQ|xiN`#|d#QIg(TSzMC z%lSui{R7j-SY!opKMubS>^3mE5dG}V5iQE)`ehbmXOd-SZR>3w9vKhO35Ity)Gah` z{1ZC|)%W8WTn_uIEH`Of2OMj^7V$YpaVsx$`-L6spxCdD8IYKA>37-%Jd%GKMogVC z)OcLbTgq}gjE@QEc~#H5m}y04 zTxh+q`D_UBias4p&mXrTT3laz-u+#iqOW_hI{ zPQV@$c!m6uZiBDu=tpHhyRQDV&(v_ZyW$XcD(&UL9>rdhk~A^p3`&9Yr%S7zUmqAN zJ5El3%Z3OmDIXTtGv3{mlI}2Y3^lEtbXCAz2(EWH?9{slUmrZaUy{&XQe#DHx@3Vp zQ_}D6T%P$=q(2wg#4U{9^&e4&+0(ktpWF>(DwLImX;%*DS7*;06)G##nBo5%*!}_? z{K@eF5in3CY07~UJH!}r=~d}{mc)3WH5NLkIkxeFj6b|r!}~0`^_qUZ7&p6fA31Fd z-OVA^tl=(kWFyzl*^Z>+WvBHgaZIjGjW8O+?-LtucvB>_Kh5q>6k+&|KH3YE6t!BC z2j1A^%~wXKI_@&cw759v`p|TdtkAZee>5*EqjdgGj%{pvAh*=y_PK@oB?RXTD~cwo z5DNR`Y;Up|&CSPwV_{)``@$zv#^$fV4&23bU1_@H%{Pchh}(vi;@6wHRn7cAYYPL4 z40pDVXI751=@J_@9MkhN-z|%v1uP3)Hxcgdp(#(LerC=aIGd7^d@lC6ms!qbBChwe zWJl^NB&|O=&mT4D(}O`a73geNWuN(yuZ8|7&3z37b={~anwfZtOSJ}f-M3k~w)nfU z`=1<+6)GhgZX&NB;Uv4Q$k1x>W##^WSQGJTy{YuT){qy=XT~hc6=a9nf_AnM5O)y! zFc$AHUjNm6LwckhbLrliq)i=FJ;U!PZh4b4PRU0x6vMKpvMj|ZN0Q%jZ{<#_>?p>Fw$%+C#Nu(d>glWMT^AX(tUny4skyvTj_PvXt_9WhhG(@9Ovl$R*pRup zSC-u3i68}6=&plI!WJ1dMaI^c)qnmWcoM`l!PVAL@PX6L{9O)C^<|3Pr=O7IC=b%Bun%S|^UTe_w>bzICz4D%j zY3EkGwa^w!q|8|(9((Cjcz~TJmdZSh~=3}OnOp}3>$Y4lE6g$ z0tcwlDugNHHzLPalsQ489yA*l#;tE+XdISj_#KbvR4GQ4`<|tyq2ISRkNN7Gx=2f| zN#X84em?}F+C5`09JbWA2jXRsEwv`v5oyMUPa2Ja{H)$l-7oZs@JR_~u%apqwL`xI zBS<&(?KV45Eq8?1PrmJHKx2oyN+^iRP+_4>0`&<5Pl_tt2qO)wgIoypU2C%h=cDM^ zglO$Urj#Of!EI=>T4HV~P<0nct@mk>x1~4|Hi+h;!E9)HvfxP9Qx*7}H=u%M(8ilN z?)Q$A@*-p{#()l8=o?9!+}^@$itoi93|60!COd_U4{XT195t2MBNN4uK`+&6GHSQk z)GFm}1-n0Z?eJQY4g@33%&iXk>2ftx(rst7YoB6H z&65x8&TS~=_Od!gd8R*%7SV6~9{GUvy7>AOe-JU1I6c_Eo$p9qI+#5*W}7u^+nl7flV*8B*b(BKI7-4W5baSK{nYZK_6OXXzcKVPY)Y1E-18Z% z`FvPQc~oj{_Z4cp2Nj3sW8+0JHMtyOy*MNt9#O8@BbqO#pD-@hELVSab&%VW7HPDz z8mf3!)PG|EFxPbOw{10h3=}41?pzO8iTPSMSJ?-Xo!BpQc6RpGtS%5}WXve-P!oAB z3XDaGpfEo0xZALyKgp-gv6iSY8039VUB&>B)~6Ium6o@;JJvVoG)KRY?n*F3moUbfr%GbHT2cVg6l;T+|r{ zKTnD}z3(Se+A6lwC|~NYdF|gE1K+h>81lYgWqG?L-t5&@2t;>nS>(*Q(<#0?bgGQo)uN-_dq7cMs+yrXeF3Su&KM5msJ{ z{#P!;pCG=7TUOA{nTeU(RVazX_Zr&QN7Pl939a&S=C-6iC+6(jKg6>NdFBH4#NG#O zI0RWW#(#en7~#uujZc$`xF9o}o;FmF$n_&~Z?GvW+m^j98=+E0n^Z7Vs5tdB;`rhN zb+g_O+pB0Z?Qq)yNYEV%6P{&3Tud5I!MIVpoSry%$M9YDKI6uZ$ z&p~Fhe)K`D?5*o0Zs?BOgH*j1u*_J9$cK^gIHv_gtXU%LBaf_KD|mZrUc`E zVkHybuuZhs2q>e=sCy;i^P2$v0~#FS-eaM*1#G55?I zU};H8_Ia%;+P&)3A_BxxTpt&Q z4h4PvFILAYvPww>Ha;!$hV4IG`O!`2Px%+JO|Mx}ta`AxfF+2GL5QU)imD4@qJ-S_ zg;Orx<2lJOQ-OqATdk0|vW=AY`ZsI6!I`tJPe5_k_t!&Y{CfTJgoo?E4z-crHJYb_ zxfkEoaKULAPFeeYrNpzH?#?o<8-ysWK<`jMr0@*QNz=nj^HlgyZ^S zKAD&TZSgus==$JaYIoqzkEd-kLqo<>cP>nL69uQ4m6zaX-d<)M=t%8*@V3Zveg5K> z_o155-?H^f43w{tyH*$1Hd!AXY$0rH5ai!qq4&MPjRAT&UU-@hG~TZa6O(vXjPKDK zCkxD1$ikKHaChrzlxZx{O~WmgT;8~<`5n#N5fpeD13`puEEO(3;nDQT5_LPs2wOn; zA)Bf9uA-+`F$c=w^E@*j)XLXGE)35n0?9Ryn(MrCmgvHUgxu;dwjw!cZvJO(voW-< zTrc+{P?7XyuCKD=Byx+Ci2Ni((J@uh(dN*ibn&M~z+YEyD}V_eyt7%l7* zBPGQzZc3kE)9Y0(CirlQY?69JS~RcPUTM(eFq8%nq)DP6{9a;7S-f9sd}IaCI0SW`gv(*x+9VIL(o>z*#n zbdF|mel&-*Hsyf*K;HGla({fZXWDa`{jZ>p6WgR|&Q-y|;V(|AWI4T!>00ffcpyLg~mYF`idhqQy$;_&iIJ zXW)2;h%86Sb&hVFuV5xBIuP~tE}sg0_2c*7bw7iwEZT$+WP+pI;+piI+`^1_P!}-_ zMGA&B%h(sU17e>KS2{vn&jyA@Znl^RJaTBnP*dxiSZ68|6n-ZEwhbZ3um{T(<6D=r zBZ&y-^@5hJiugmZO2mKvIqo_CId!nRt?+yq6$Hb=4-sq{;wnUxWJ=pr3 z)mqq+m0FJLVvP-@-l_XB8sVmdp)g&g<_I#TP_KvA${!*>qSRMe3h>c$kwPdv!5{_6A$ zyoF0OOhwMI9>Ik|0{v%9$Ti+}`L}Vs{*A_zqWG0K1!*klM+K^y9HxF&4(qb7H;(BK zE-lVS z|J8&YP>?b^0fIQ+1`Y~KPurTNxU@03_#e1BJ_~XWirdh5I6MEeJK<}cS(AL&^86GC zRZRZ*d{E_67t<%ZL8g9j5oj|WtR8jcfDsE~JiNlTl8j*y(BMPkhLm7l!6eF^<;&j0 z;ZRFtvz);AfMlNOn!tg;@_lxJB59oM_^%>kOk>a&A6ptaF9S3lOSMn_5m2H>BNYXc z7M;gKT_ydD(1a-)v`5>rW0t>K|R-&^dh8Z-1CSQ8>Y<@_!~ zCVmuQXeFB7&nkJj+pHjessE5ab+X;74|^1!`I?I*T(N>}E)#==OUjt~ZK^6$m~Et_ zf}ZGI|Ahuq^`P}$Izp*9VO~aHXDkUZHs$KWh`=RG8O{2Ndf)cIzP+OPdY3Jwj34S~ z#Kx=)_bVqYb&w;l?us;Ptn6!ACZg&bAr0Dsg{H4308tY4iGPhtW{QxVG40@?{pix;SKm&CIN?+*4p5a z&t^JL2!C6i2vqj!SeDg(oNdzFHmphiGWs|#{W*`vrE2A;Y~aTCu5NTRI!{6laMz;- zYen$0j(3_%ece~D%_PrjZm5A;><%aJY~G#A$W({s%3TrE!&L27(d&YXcFv(xrNd6m zr{RjcfPO)FrCVbjXcr=`Wkk&kkHs~62Jk1Sn=Zaugx*8@1^Y^hFzbo;>s=d1*8}Yd z;RpKeBEzX#ZD_Imo#IRxC8hyB91g5;ykeOxep^mvJFb9)_TOl;o7^@>$g@qZ<-hG2)%XHixE;4QmjfFE2sb0PC?puC z1wN0ml3}ovqgm!>7AG1V5`Sl0fpzAvC(|?^$DP_~ zqrW0VNS8gc?2Q*3`+**+Sv*a2f|KzMoDfv`=bo|bstcV2y=sawJ@E6kZsk^{k65pM z#CE^VxTK}B|CpIqHCz^LE)QubpB@~5pf=b2J)4__2QR3+b@&3BVrlkG z7CK|nPA&*@D2gVKDrjF$_}1rY;&DP}0PBt}-@Wg%>nlsR-EstFSl00hA$ft~(bN8$ z=M{zfHdjNre$8vO z$zx}?a(TN8yz&EF`^`}SZ-MI1SpL#^-tIO+?~o?!tQkXPE9;|HW+OHPR~1a28GUV3GAvFHwEOKA9h_Fs#E zlYd#a`EhSFogByBs;ZXs9)4@{V4qHxX1osXx4UcBOMnOPw-8(xS=vL=MKzi1Nx+b4Hd2{4_jl3<~Jct68G`!1EIO zYU>gqpsnpUtjij*u#?ZY5iL8n_0Zhp zErI{kMB$Rn^gAOGKKjQX+J<1@=i8hf)`x!VIo{FCgy8>>8U)MriY$3}k|?w{L1)&zJ*tUTz@N{V=#l zLs?Ot-P#-c1tElavMS^6I+~dUq7j>Mvy15Eg7Wr+g8`o#?lV&mqSNGK_ctl;#|B!O z>)1R2Gu(bXjSbFGHPYyU_sauX5Os2tmP64Hso2q4OG>c~Q|79Wy=BA%5j<;EOLbh= z6lJ@Ogv~If>heUl-#9hvUs1F1{%@Vd!ZfFHUCf zb4$c&Gb1#c$Tz2ZmxTOJ6}K(~`8h0(!zSE$fvZam3W)|?F~@pUMJa2+&rzPoovQqC zv8Ax~QSew?TO1*hE4By6Jn~U zO5~Dg!Q=4@w(hEgd1By+Ha>#QkAEi6diNlA)t+>Fccj1!>0*9%7QG}mGLV@f5?X6n zn!zDW8P2>$*BO(PgoPWb&QS7kwcSflY-_~f5Q}XS8DBdm>eQVf;zn{}EXV1T?R=^qYJOZAtfwO24OE0hyP+gg0{<6Kc!a2!4Do#1n z^fErulTU7YwL6#TNzc>sWFI!W5r}`YlTi|l zt~wkr@zKOGZUGTQ|2>K;0Kh3$R=&U3m;k>4oBXup>LBRwy|xm#YPE<39iI#}+WvGd zhh!EL#3jqbsi`RgCgKQ+l=_vk;^SSD6=gJ|=g+fKYQKTqE|Sn8)_Thov7Rk<^Rj^f z8+HO~0~IGOn#55Nd9+br8oBt(6H6RR*b{nT?g(<-ZfNkZ{FE?4phALf1MX-V4{kUV z_eYVJe%VjI(swlesXYdfV^IuQ`6Ga>n*Y2FzI_w?wFaGyZ>sn zxE^G<6qlCjUv2j(DJ#o_`?@b9J=JSSE5&0FygZmPM&weDrpiP6mQv5EBr&xV>eqyE zj^&3$J59B{I5|6hr$zW9+;uv)`ucK_H~m+4Ht6WYBHw7>q}AaRs)lT|-3no0ttEYX zh^7@;2!<#CSwF0_v=qQj{TljXvDOULy)82~7KNLKX9>9I>+37mY>M69K0=k3e(`-a zTwo~Kc_woL^3L?_*3=U*itJ-qZmiG2`)jLS{YIWjf5E&7WdaiyT3xYUfVP1b6gF&c z>(Bqy8i|wRA8K|w88ij~yFv>mMrX@)i$zOis^srnP5;vqp%9CpIrF_3F@l_OOHU;` zb#?4$-fI|@GN)K6=dHiZ6tn+!_@74Um6h#U)>iFD=m0QE08-ex!J{UejR@r@-2c2a zpmAGLN{XTd22&=;^S}3yQ5g%eep(3fW^`p!A84wCl+dPd-D!dTr`3=nE6LBZF@`~e zXNNzw&6w5-m~q^(k%<2tMX$2aF!U_CHD8tv>sw9h7dvw3jNfC~z9{{r;WEy4srA4)K3D z;+e-CF=UWy^V3m$nNNHnO7sAm%nW%8o*_uRdy8@D)FXi(eVFXuP6QxtcblaK6`HBh zVxaAH+mM>2iqc{TE6*8hs4Ala@vfz^;7d6X`NDHlb7keJBgZ%``2Uat8TF5BQD~oj zK2WDaBf3jBxu$w69-;WoolmyNp(gyl|E2$F`--!AagI;g`#LM`f9Wp%tLW?+^UtjI8ZLJD z2>1#5;#xQA)r2#X{d4-6m*#I(j@;HgUoOg!;wAd=(WHg$WeOSD^Y*9EdzX z8TNb1l$0PkPO{+Ay$wa_-_GDMF*0@n$^byxrB$o?kT=D-B$BE$!=8P9a$@juf5ytj zCaDdESno1VdxmWKU<+_5sx!ohMEPM z0A_|dq1%$(pkamK@I{OvKANJZEfBer%ByGU+pm8cXdTdH+_Z1{shnWT={eVdb7EPj zC1}Npqu%UD1%%2*MIj>MaoVnL@TFQF?mo@`BVW3$48Sq={E;J8r05aJzl<5h0;sN* zi*_mI6vO+|rTByd8Rr=Cv05ofW9AgKI&<_R$J92DhZ?gPa!Ynx5fPEYJChCke?=Hz zNL1}4r~2I=fb=I#nesY6DF53t!Eeaf?d_RkX&j15O1;AgG*tBTnWy?Psb(Gtt|N2} zRjyb1(9qD2bCups+CA_}%48fIn1BpuR|?#-N`5jSf^1E?(ve5Ib?0+#$!Klm{fDc7 z`G{I<^WZpHs2te2s&YPCw%|?lVPs|f z0U#RtYQTJKP1;-0uLiK$fl8oQ@X*-TbpMRrF1@CP`Ml#DeB(YdJ!cJUN*aSwQd4mN zt%MQ2*V>*(2}>ULrDG$yXREPLu@#O;R<3dZU_C={?Y{ydu|Jw3tgMVqpJeeL`M~Mi zvfZ@hq(9^V%m8~DQ`%TkiPHZlDHyxEp|P=yQ(|cpxEsk$+1Y(~iB9-lK8_p2PUhZ6>dh(y$@J=EFO2!GFgBG_sw_ zlHk83^Gp7HKVNZ(X$=58M8YYSShe`p- z>`KZap`v-IygC0RJJEPnF6E)JastuDf9Izc>L;2=?0;=$05U4k|BXy2WLD7sjRp8$ z6ZiigTK>P|iRU5uPI*9mj~N4D!9b~7RvDgqLf>3Uz*3Z!0#Td*ot5{zeE~5zqDzsE zl_m%He*q6jh0zvpOZt8kAxfH=QhTOTHY$o9r)OVD7~L_Bp0qKAB~&ycW6lLA`6EYn zg%R5dd1dtQzTdf&NlrY9#M$$#k&fIlE-oBrXJ@zf_b4!sA)7P05Q8D-fC(+EtN7JWqt_EOMBmSLuoX;b+#i7*SN|3iMJeD~?J`~OQ_*aZ zlGKvuPGR)|XvXnz+3u|>NLAI4DbwDatDkCWoF#j%;HLvKbMw?$W=#t~lVrW_QUGZ7 zK$qfhep;mVZ*G38sHkvsa>}8E1=Jhxc5@30z(wwSTnkj97GcF9LxY`~o&6y!48g_4 zrKF;wprPTubiw-%S0)Mb5)2$U+7AE;=zxdvWy&<(B+DyNiJGlsPrQ&VsGqz6ej)de zG#Yl2HS#Cr4{K|B=N2!85&H@(0s?ZJNLgnlzybljX|?H8?hySjTMl5)>3-E~#>9M! zLjigRI3;;?bqQdwH%cfZkcrc<5((thoH+w_2mr1h$P}cAlOT?P$;-=wM??g?ULjhH zoy{(P;6g!JIk0Cdd3Ng;K*!!60NDNhM3%r(Un4oN$*k>p)d%RhMp1nHgd!B10N*+tL*Cb!=PtV z3jrtD)Y{s3r$2HujUyTg4&zT&mQUA7&64G4CSMxh>Ehtvs5MyQ11l6D(DYAQ8jVBQ zzh(zeqnawJtl3e0`n9#SRe&W_DOdXr)D73Z=pzfNS~;7Yo71b)SgJ9C1H7REsibY^ z76$o}|2`X{s8v1Cm|8eBJuPHmLE~^RZZu!6?#i1PF01Fmiti3|8MsGA5Ur@A!%#{5 zUkz)gu2t>pZfpAomsNT>%MZ+5Pan|gX#>V8_Tw+8*erZ;mgrfiT z>gmHrGUI9Eh9;MmLQ6|sc?m4pSJac_3Z_r34|gjnJ}<3J0&xr^X>)^DT*b6kidu;y zr3EZQH(ZQ3vUKfz`dtS%Th1*<$H%~GW(%;N3+Mk?g9J2+YQ^|A1Br2fye^#Z9h{VF zuQg_I)U!^{&dU*}6jDw^ey=3Klc~yU&uEKWvs_#27Tf4Zf2!+K8|_DJul!fYfMrp0 zb2B9+zcsXIUVc1kbYPd(4{L42y+rx@i}0-s<=-0@ zo2SvOzODjmXWu`4VS&1lyt0kT`I|yHR1Jn(32NjVW4M~N+1Nco7`u3@Fhy|L=m`2e zKWaGaSpCm9IBwc(keDxS8XVSQ?dhN6nM41I3$86Jhyfx)pL7y2Vg$k=>4N#?(okdJ z^O-$7=9kK-zP8m@@;tw&bG`MYmErp~E64k&DpO~w0;qMxPv#%W<|Os>hu5@CdE zjjy2s4D**B*pZ0As0aVWzuV_RTiA`%2{4L7ULDv{)zK54_q|z%8f`6pnZrRYaCs-t zcy+HeO3J_8b}bECH#T;TL`~xOGDPd&#py4`KMxOmeN8vZsp$C83KK*Z7jw-FXHG6s z1dSpmM@$EIgzV?XM2uB^&{Re6P`$3#Wj>vUGs?LNYwRC&Gi;fU!=zrZ2oDW^0PZE;fI;I(sw^a3vO;U_-JmkveJ6vo=p016T`-0XAcEZ z$dVuzvfpL=<+BiU=0B3cwY1kHp2YW$O9uJr)!x(o?glmQbiCBwD6a^eU? z14C}JE%-<>PC);6tjLqNnXSK1;=Ex)sf(owmy>2##r5mte5hmvnm3xz2 zj%|7jlPadQGiXae2mzAf)~pqFFd-CWyBl$!+v7t zM*FBJ-#k#$dk4+S&L=_+vzKD`D+0@lTry1B@qrW@qUM7r1bvYoEGGOzKURcAFGy9l zq0-HH^(jz^mXhLOH@cQ}DL-h$q}!4?dxBiN7ZtJxhg>Vbm05}!f;$f?d?t7XvUEJ4 zFDKj35sS-yf)rby7SD(_mHQf#1+fD)ZOK;XPYetK%QPWL`X`Y&J?Fh`))Pj}XS}|J zY|;`_3XjZZs*W{*q|{*kUIRiM$-5Xiq>e`;AQf9{-Myc=+c`SrSFHQvBA^W6N-aM>ahxqO%i5g5q4oxu5% z$s;ASz1s!>1ZW7^qBvJxdIhroFNl?q5mQA^lsfj9Nbfy6p8AQ-v_q!se453Z*q3o$-T zW&5QZ{3yC7+L1zIgRyQZ_13Uor5u(aE4lp>o^HHW+q=K(k%x~Xo4nb$tGh4`SFK2{ z)##s#J6_F3QMSoaj2Jh&cA^;Q1cpu)AL^&kL!ov|jrOA~Rn~rw1&R>5a_2=L?TOgSXWklb8Z!4=V ztgp{~G}N0L_w!-oVzS+dChTA~Lfw>oqkqskBQF(Etk+6S% zHyIVP)ydP^gU>ip*0N+#>38z+Z2%C6LckH}LFJyw`I4(0JO`5i#xy;#GB^R#lBdP( z>9}PutZDUke}X!T0E&}8_R_M<&swj8m!jRaH*}0!rX;aP zNIS@yBSA7|Y?$sR;LR;GGc~)s6HdI2>0ITB!l17W2opZBM!)Ylp|x~*AD@;e8lgXTB0JQ?{&Y(s)oRLjE0|z>8A$h0?`gD|hn_uX(U&nor zUuKFP$EWd(1J?E53i&*Dvaewkv{`m-P%AYP+y-;H{wzcS7sJ&ic65XYSujUUgZznqI{lK@K5bp zlCPR1fj*f&e)X_^|AgduH@G>6Du1=do@3*eoNfRW+J0^S4mWpCt0i~Q_KwdcCUmTtf>lh7+ORLBtAY9bP)P)9)HJG z>&|Tsg;lIV1~h$#aDQbf&s~eJsm-EG1Y?Xi<9`MXyMSx_Af(|ubnpxc({v+8ZUZ_RMjmut!tvL5-zi2dh4C7n>qoo#7(-Xh_ zwdNukI-7A1F9vanWDMk&Vg?m<|3q0-y2{Rr+AS`l-?fN&WByanJ8_K0RmY$#{m{AK zqQZbritzR(ioGh#Q;UzqC=q`&J7f12stuQHwO3)bdD0v%W!~lYco-`GEKh}qW4^_R>#}EUSQbl@ zOMS!A>uCu#J;N)^U7R>JVrepSLqP8X&$Kh2v|Sj7^yw!{lRI*A5doX1jX~<3y9sED z1UTQ;$q`^%?}m zf)xn1`K0;E_Q;{mB zvfGT;eXa?K?1O+i#Swz{+Z4`}5>6H6tJiI>y6?7hs1olr?>_aAvh{d%5 zGBVIFMqDS`Wu}kZN^`$^^m?;Zi7Il7sh=IgYMrl{R6bB}i8w!tiUAlD!kziqX5_pg zB8w5wllo$bAbn6OV~XP+1^HWd_#;jYm7o_L6lfCeq~PC5uwLXIQQXRYc+`mpjMKG# zUL8+_-m~c+xm_DXjOMF%|8QpqpLIDac?13t?70$KYz_g=H1*Hx`;mm6(Fe=ljzeQY zK2PR?Cw!@0NAy#cc$I*LjJeZrHZ^}KNU<&NHG z+?h{lGDwQoBhQ~T99uBD+>v5+=1_&@Kv^aE)9a`J3xT4<#y{8s&$0fmd{h2E_LYx_vP+(p0Sh1P{xJ7U^ADnUb#Zcxn=U!m6tCKUXPu?yl8J% z>KyB*tjP3H46kEe8xiFfD!}98<~dlgMUF6+-#Ta$)DP~(Id-IM4qEKIx?ohTTrSaF zbA>C-_ioiW?4gtGZkxTz;>uXGHU^>Q)3YA($P78xOrxTxb>i+~ z0UDJKxIcLJ)4}KWw>p@3+z)cjd?~w_LT^qeJNJpfTO_(dkMW`*iTYW3kNF#XDa_3P{hT>_3Br1 zbuc81Px7$#v%Ig5$4wA!3l30`7ar6%lE;WouB?mzrw~_9^bP%|#KgpeihFmfU<#z0 z%fA;67in%FK#+Tr?3wY~5MAAZbd}P`8)a zIyNJtNDY{DYvQ6z2=<~I-u|eH?xeRcU(N=od#x-qZe0r4)t*3R03m19P~YUJGq&dz zwi_+l$~DdkPBRt|NXARPQUK>OG--Ic4SH;}1_u?&t4-s=gXf*t)CComzrh?6m%|?- zAR$(pCsqy$e@&8wMLl8Q!#tOi~mvM85vG%yWN!;`(SA*3+-zwQKG3(?JpVx6Wz(mWv0| zrvld`LL+Xju^+sH&39S*Hyg($4@ezd4+KN8%+j8F7G}*452jZwDNuzUdI&lRH3!ag z%(kWuv<)uezaObq>d6qbN0aprA4p_oZtC_5i-g8K>?3Nl-t9xuutPTPKfAZL5k>ET zVg$G(55zG{nvx<_ll1No8F>?p8LbT3HbyEI5^Z1WNKME;)v`hXQQj%3smC?5Mp!+*O9Hqv-CdTej>U;L};dNtvb#Z#(@EQR{Gx}dhPEJ%e)*f`QzQ2NcH z_|02jZ*T8{pUc|X8a(*Gh0m^{lu&c_tP)!Szcn{Pb>+c-?FH-|11GoC)YOzTG(FY~ z;v^1Vzs8LClY}%_v$(9;Os0unf#GLedsNsfDovV@uA}N|*WTRv!DUH`c@nls+r{NY zPs`|>m8RM27rmI~q^*1O{2r$phv}I{u_)B4b@ppEI^Q!)Vn-uaitj4Ep;hU*1Qy$@ zjN3$Jbd}R=<@wz0{kG>)*s=4j^GTdBP$!>|sjR0JFFHJmx{_S|?#ABdYj>YGbgP!0 z$A_`h`jU~IQE<@<&sR;$vd%gM6rJOXH)PB-p-tHgh#|uojTJ9E zjvO}pip6fL{1eoV1dc^&w=;IodtfjbYew@!L9%Xv^KfH}q;nHOTv_tfeb^CrXDf>c z!}WU&&fup|5Mz#|3j6A0bGeP z42|o^W&21}J1&KZ8d43B3G23U*~Q3Zw_Ii!O-oYSFjT^r%uXaL!@4ZWt%)5b#;y=E zoldJG-!6 z6(mhVMh160p9-aM2p=18!xu2wCI?=d$rMRbj&tfk`bZ)aQ3{!~_={JuM!Pub5nFrs z36S=@_>FN)MC9Xs=`K&-Rj!vIQD|VD!^9y+V$`(0za2FU6~r!R@svaKvm8MZkFR76 z5*no9Y%^7;jTlWGUtpVS;M-PTy;6`+4xtdHm<-^9oBJ^stf9D3Ea*^xLZiE_S5z6Q z6SH?`SjkF>{Af>4Prn3VpG+nILoF>$8tWm1gW+Y= zVN4^Yzo68_+2B_Kd*bBqk@{bpF7>nlgr;qU`z^{6Lm;dc+{x&e0&InETnX>zeL@U< z(V#i#xA6J;Z=>pqV^PZkSaWmp%7nG$g8nLx7(8CU&vLlUdu>7}zt_Ey+KmZWX8NenWHRAO2w2YGE8~%U+05^VqWHp053S3EM z#~K+@YX8KS|GB()*M!?WGeEjZT-Yc}CSAp6lxDV4oauyh;Tvl1`eJtHw_auW0Kwew zB>6Q#)Qh34{E`xqpD`PRorrGmGe;sPR}#f}B7otWn@Uf!5hOKJKEIAtCKULp~!BD-Y>6=x&D#dJchO z5CAd&ckM}Lak<>E(Pt@}1@Zi59TRV<4VaRI=L4%h(3!rnoPnXC-0d@8;%!j6N)dHh z$*fNiOpxTVkP{vf8cJgG?xd%ip->ovI%^7770t8%x1&R?$PO(jh5J*h>E!U=$z<~D z{{A*5Qz|z%_l4*~DVaiX^YwL#jkQoyQv(D@fyFdckaX7?1U6(3_#+Ptz_YWnpVih@ z#YtLDwe^;7OGTZ=(MO5P`lv^nM=q@H~BUCNf!+JhKjJ8M!>+TARytvh@E zIG5(%mU-VnzdfX8yjnFm5I!)6pZs*S%IV@Uw-T=1(*?ZwzP^SgTaicvK~f|w9bgT9 z#^89GerjX08iw;S!esv7eO8F;H0P4{oku7)=1hg)T337{IHQo-|M=fhzx?B;) zGx5}=lh~dkuDP8dRS0?iL=9pfJg4a55}j*iW)^&mTF_s~%_$;vzw_nF_7ejSxu$Kc zR-C9wOj@QXZ)yWZ-7WLe)>Q_v2T$vL z|8m!~vBUZs6$Pp?zRaual9G}Nc0`}{@Y-%$ z&@uJ-MP=lvbg|fKS@|5OTw{rwP;hQ>QN&5+DAS-%B?1DSYyAb-ZIei3&xtaZ(@2x#su1?XA})jE(2Vx{l_N zf!R4T<6{6;S98`OKh{Wq7kGpO_wUdxzN=K989jAYW~NgcpN}3r{XYrmW(yE5T@MsKjeUL9J-!jfqPIn7GdlPp zP=D9WIUne4yI(-GE4ZP-K}BS^_I{N#>d$@Z@b-XZdRA>6>#fS9&iSj>iqNM5OByB7 z?`PN=8zS@!;PkjB!M$_aVbP^I8`>_!txGA*vFfz!F>g3say*RhZ-@84It}Zane$9K z%6~@qZI4`j-_nuGWJCzv_ALOX+YD*^QuVp-%Dr<7O~kQn59el>;CzqaD%Xwk*9jN1 z6)8VCygB2)8|L3KPJDyEdOdX*ZxFv_`3#J%tvwFb;{hq}G1#Sxz3;s=5CUa|z4)Nh z`x?@6u<=PdluiZE2>Z*Fi`J^=K7H7fRYxCXV87K)6AO|LaLz`IEV+(*gHHSWrD>hT zgxNXe5Ri97krj57l;toNcSZ3ZkZ&;fwkDls+UJnnG^LhLcr(}FUxv(dcD>mwO-Z!G zGPXOnU3)ph)_oBLQu3WZV}k|~_TV&bnR9hpDpn`l~# zRG?M`3k2SJJN{MWyHD0>!*0xcl&>-bKRXj417Shpk%$(#6vAiAHlL7eWaXRL@f$lzl&SsSgVE6)IE|oD6s=zCh3012P zz)9&EL0NBAZtd|4L}{d|&%Sh>4u8a#x7g~>AMaA}s7|8qiMhKSBh~B|iE1^J>r6PM zQ6W9l3TH2yqx6eQ_tOp3fsl$u>KY4KyW72#kddRnRNOf~G4MmQSAvU94t&XWK~8k$ z@E+M-x$0+Km60_j`MR6Hbge^D-{fn#N*~&&{3S=L5rJrj(0KXiEHk4uUJiL;s;E1G z4zJqcz@apW*7{pq(1D3f7IWgF)^Pe2c41R3!C`83({O}JxlG}#Dvg$H@@;=B1PNjO zowsJOfKh`{`w}QBGfiyo>k=2+EUyuP7}^giM1By90*tnWqhwmAH|tgU)WUW*TGjWk zt94~|Wnt{!53FAKirGFc_BsL?H=Pu(Ud{K{`!Ps>j(VgQzI8g-5j65|u5@%HvGU z`dCDHO7`N7a$2!Jk$}>EVwK4-8#<^cb+(1W!{v_!#jb`A-5ggq+%DtU5PG+>+B8+x z_5Ebi%6x}1yQ8F+9V%1G69`<^mG~F*dR&aqS$O&4T{wE^(Uehtjl7#^Ka3QpR!PC! z8fR(KnW(@aakzz7<#TKPms{KI{V_Fe;$SkXHE5!?JAN{&|9-KGP|%h@*g6y|9FtLF z5);+}s9+c9D&%>!qdZtJ6y0@OFe4T=UZ*JtdQDP;xPxP!y|<1yIEjV(ZT|@AKniWR ziD&P@@)Yy5uyzJ6ZKgt$V#V{rDBrRUv{gDpEmQ6fan=Cp#9HJGx!_7Lxm#L91ii^m zT|Q#Vmysc6T^joeB)GuFw=l?S&k5Njb!a$Z;aE*zj&fkvM^qI6gz#Ph5?J;V8f8Y3HH5;QUn+y0Kl z@j#yGY>&wTGfVzQdfLD%=T&3<12nqnN_!&YX0_bhR1{4(f^-;dMqh`xY|v~M#c^04 z=;xpwpv&kVTI-3FtJK>}-CwLXV)A#bJ?@m z6gYfxc|0&{@X&`o6hVE7g+XjSSby>|T!)sKqQ({ps@H?ykDCSt#&^F{VhTY=#Y-@mmcs z)lEq*#kEeCQtO&Hl8NaHyS|`2&z|eQ^K#Q0n+bGe>xv3!I$~%Jxix-w1Y5LW99gUXNrw>t2c7l z?^k(3JKS+R-)YKy=?2ZN3A-0>CpA1UXj1hioI)|_y%MIWF}G6VfA`*HUI|q)*PUJa z9ymVxgubfNQc$tp@3)ff1j!=YRc2Es!Nd`JBxRT<`F;YYOwy9d|DGU<$pq`<>OaAm zsXrR~z1Vt~z`_SweVEu0gvR_z`L5q!*Bc++w-LR)Ei2C;lJE*P?TwdKCdgYSo(UX?ZBdjor)v88|hkNf5}S7)>~#p2zEY0ro!-dNh=+Th`E?n(~YpKN6SB`S>4LSy^e+YD2^6SjLW z*(x41<@Cs^rgadN-d;>)DS&YkhBBUpZq?C2vIR?_ZF~Fngfx#cv;e#->gloWJKNRm zDS1LtmoYoxfHuLANz&bsAr!$Gz`i6>;d6mQhYbTz>5614#kaPHza58o;<+W$tw|f| ze77+=Gn$ywRTNNzG3i1F#Se+8eMU`;WfO-HbHwzOr|HUFElSG@S_GMlmjcP$Hp0Pw zP#;7wT`Ii6Z(ScX;L2P#E3@pY_Q(?Nd8777hE&(a>G~u$%5+tDZkJ5L&D={QQpQr0 z@6O=_f48&c6ZjNBY~Qk%J3Ks+CE_cNJlpM3S?PcALW2l|NgfN*Md2p$ej6K^g-(pM z5QYe+qS|;UuEu>`_o0Tj>T9v*5l!`-M5?&SpQggpw`!oKBMBWma9XsOqOx^+lQ^Ib zV<@S6U@D2_e$Buh*`g%?7}8~pzqB_eUA~e)ZfVJ?+H+AE?@Q39jW=aATj_oyCx_G2 zTaKWV-ZHP&MZ12tXR29a74K6hA!C@d)uwoN^ppN>^!pG(qyDCx1_oF1!Db7@ADGj4 z0aQd$8695{7FPy-YCi#J43OKQfdf7v%W5n1^@RPhf}a&rtcUZzPktBGQy4sx?PG5C z0ZAT|7AGbl2Gk%t-L~Kt6&9u&7;>R7bY$PDDA4rfstWG+Nx8V%bLY&k5}5%bv!WwQ?R522>^+>^{{51VheJ)l6C*KJ7a++=ma z^NOt|;(ecaJ^kMK_ZJxPs#t6qm|gg#$NtG|)YrDQ>EN9=!)U;1@1p4rs|XhC4X zgH^NH74SyY{--j(zjQKu6lX|509?(QKDdF*R7io>Dg;;Vn5N3+pHhN{Tej7&9a=-~ zXn|W1x#Rs}{tzFq+nMlF-K$rXm?c|qW^-&RH1h?mqXyzLfKBKuieUkWsXCLB#w!VP zA8gs#mrkw-`dO^;;jLc;t`r|3uHU!l*B5T-z>{VVDCzDC?CGvUPB2P%W%Y3lCy`Yr zUvRb7AKaDO_69POrW?(AJ2jc5@diwOmQ}i*op|a?%vI%Yd6L+UAj~~V(~rt1V_DwJ zsT3x8Ub_fY?#5`>5JHH#B4TSoeD~?!`nvUKmvac<4y-WVJmKY4MuVf~;z`Q?;$c;hqv7`%e9MpWyG=$IU+e@VB0_=zy8J}Rz+GbDO7;=A`KaW`Fgwq|0)`@$ zYI$)J0uhLCueUD&5>j;7&DhaWF{GklL0&;12K`9T&{(5MWh~e#7GyB(xLC*us6+?P zNU*`-Vq``R;4sPP(Q45;~A_4_Yb_lyi9mwuAvv zrXu)HNYK&}Fs#^tPk{%%-yB|o1=OG(%_1zQq^J<-!+vsP;^dLY&~MNXAVH*L*j?~K ze8l;Ul=6il<#9t#zz#+ZXfVmx(Q4s3Fi0?9P!K|lpH#{f3g*#fMuH%G{7C6A!CH|| zpZCFGxdMa|gs@D>@PSWedC zC5h2~6qR_6WJEBc5GV*i#6MyB|05g@{x)x2h$DrrMdf{SBl~Ut|E39k?JBstyC=v+EA#_k@V%fjmKn5(bKHKHBWSg;!?}UX8L~lAh zbI<715kehb6twk??Zf@7n#ldGk5+6YsML%VA}Xz~j-B2@B95md4@`+d<>th?eR$x$ zbpuV3pFFB?A3`;v$Z1CwM4bL7YEMlhiR>>B_I9KT5wcmPYS@E%`3ULG-zvuIbC&6O zdV)2435OUiA}QUlkC5eoW+jNo_cxLlbCH_Nr4l&W#L9m`03ZSsH)e$Sh>Z%v*{6W% zOBm$12v$Zy`>hJXPK!P(Fpaa1EXtmdT-QZAFGEMXFXw!emof@_pln3{10 zSc@D<6d?E=8hY}4GMbSsn$;RD>?syMG?K_i1is$x97?EThavjI5*(r+=-3+l{fXG) zB_38G`PoT;yX0iQXDKf?g`?WMBocz;3j0l#4H-|vL`KMo`E`QK+=6ze;X0o(O*K0@ z{7uj#6j=>isakpNjMeBf`;8i(CbOBeW_BO1Zx#qT+C67{8FOK_yiM4(wUpWnmyXkU zn=+l{S@YA_0xN&SweJvmH-JRK;LlF*LS~*`;E^N3g2u)FIbOCbbzEBnX~IU!?jo^T zRh)3FbU}m)!F+^R)msp=NQgd7Y^+a*Gn^>TT}CVf#c_Wahdj}H1w4PP9O~qN8q6SO z*LnqBcXp>ph{*oCRF-_>fGnC7JbU!I42PmjE}Qv)6>K}vxzS&3Ym8Z8Q<-1p4Vt(V zPavfw#}joQo1~i=u~;Taofws8|9RXF-Rja%+nRPLa`+frAL4EQ2`RtieH}iGrHR*iW`!GumVzi^rhpgU#&d=JZ@MZsFh-Gw|gGy|9>IdXsM5 zS|6EcN#JjcO~YBf^f{u5BUEGsw=x`uaGMY=`=C#k{=$c~{w=Jc(!BEs8EdUfg_Z`( zwP!_;b!)jOB?CdH)qJ-KvrhlKdS|_B7i33j0^E*5Ef7mzs-MrO=7 zk&?`hme|ydBRZj-lT<9zY;&bQjxl*&0^}**gIaG}YV$ya>E5Jqb$4(@bt;41MJbCX zk+d?~%$1}WC+AONlBh>|G;(2R%`mmD+sweygiuncvr@+=;Jx)_Ot&*lrdQoD?T7@e z>Rz1@XpAbZp27eDb zHkf++BwY<unW!;NvqdQ_F32_IB_Z`~sJXHr9eP6{U6=_52IJua zTqmt1EQ|R(RB}@=?zC-DL6o?<{@|#10X;=avon^PWqQ%D}iefihOROFeHZK z(lxV$?^h(!2)U4O#3`tG}=_*7vj z3v$eXBS56fgpi8bdxAc|#~?$+Y}TPhOSN?Y{}h4v31cu}B%$4#`s4O4;E-(mjT|7h ziBK7?Zrh^pKH>8hheOhCA5}(X$11Z&KO>L<7<4(k89rHx-=6|m5NR`0+rMSDqHu?& zw+{W{lk8uMC@ssmaW_qzozdeFK265=y}LVW&R3DjtxOiaV*yHPvT4W-vMwsEx(Vv(Wvw)1TNtMjIN5Py6kdIU|6e*rA$ZH}PivXk~?do#p zP%Ls)AUdht6eg;?P&exB)bzX$N&nJy*i$VCucaxGMT5vgY`T^nZpQcM?w{H05}W;Os7fR_AvVm z2-uYqUSMl+sEjx!VGk9yw>?W1x<9m?GN8|DQAsPwe+5INP%Sr#hsk^Dk)Y zh`gdM6T7bJbX5aSNEZHIPw_fUxFWLbOYdOxhnDn>r$N{Ft5338o;OloFadB>hXr|` z-ucQB1q*P1ve&w6TEl5-=iR@F&LD8Z4b&?SFGl4C>mM$Ge7BI!c+2_qP`M&G^;=G? z-v1z*TjP-#2L)eVI1yJoYsycoL@2*GA?dL9k3t~`#}J#e2~jb-cY4FIZ+}KKiBoj0 zl!q6DdMPKPr9e(c5V)~(lp6my$+q|73FFk^zgqges~I`6-H&e4ezL2Amuo3Z9Ei{X zBqKi^dJ1Yur^lF^sc-lAZhys^o`$IP+DyT$r7%)SkwRpq^b1&5?i{H!zY%c&Dv^U# zCP=d``_qhegYqSXFu8I8SyI!Us!u5+l$Cw}#w;~ddP}lX@IGs@%>M;d z%i_-t8?>mQOwRcF*3tfXMw{@s_hhlFcU%A;A{`nVALCK6?Hw8610@19$-y+jcsTxw znl9k1D1-7V6$a^tRu3X>3;$>ABZLxy{jZ7tr?8E3x#nZ#JkR7)5Id6;*`_l?iKa{* zCtepq8(yi|hj(D1dpJsmd5qC=vBPY$D?a3i2t=80rhs-fXSUHGFZgn%%23{#JG*x^ zBYjB6=h#asGQmFUm;^N_c7Gl=Bp(~wwP)b3Hw3cO5wlGMe)F4?rT&|pi%P?BGKE?F zhOEt9c|hNfi3j0gW!{JP?QT*^Kmh9_)D3U3^~H^|ZCPM2E8Yt>2XNEIxh=wiGB<4` zq=4U~aOn-Ov!SookMjfM1TF90`JQ(}8t`+XXJLVE?4&-&Iz{!s}aTjpp|~rRvx74$!t~PasQ2yoH~8{I}A6 zUHt5(ZEmp9bw8>o?Z0V?P<@`UxL$(Jrxw>{4I@Gwcwn?TRY=|@@3 zR0nUcTLcjt5*pPZmi%;fj(ac{+{JW=y9uhLg z&Z4-0fCxtI_KM@`;OWkJcsQZqc34<-Nni}st0{U|DR2Ls9NX~awEnhj_}CbGo7~ae zAJ{r$FdYTy?%)V&P0`x!MW**UWUZ&qeWLeHs7{|H?Ear`wK^WN>z3@DGzQD3 zN?Q&hLJR4ELy9HN8YKa^xurZmY&F%Jqj03)4zvx5%0nW2KT^)f5N?)E(+|qA*Loh| z@O|NqaPg3xt~6%4BY0sq?m2ullKkxLxGU9K8>`{y`P=2H(VQ)iP%XP>|9ci-VdOj5 znV|$(sj}VE9Lb)E)#1@ejW0=3!LrXPG;dw>@t%KIe^>|o^MU5WH3CQd(#GfUenoM! zF>YwgpuZ1D*VQkMG&)+pD6usd+F4~63ogO_dE1?uIj4XLRM=9_=y_Q9X3B^dGt_`9x`I%z}JE64mvSR#{ShYaX(2-c|Cnm!~aq6O)s%);BDx zYm;pp^oSl`@cVIQ%A|S55UsVp*F@8fWy z9(whR4~pz3LxnZy_a{1Qxh`px?r-In(pfe#tns2<+PhNlDRA03}UP(1@FQ`0{xBbEcX7ffXaQW8MGxH(cM2Z(ND)E#3oO?N~V@PDm>Py)I9VV5Di(BY>V=_^a^~i2ToN zX7OUY z9FELT#z~%;T2cu6m!wfGdZkz_8Dk(#iE$oUV6c3)GzDgXF36UN%N0&ht2x{|Tdgq( zp{VLf=vHC5EBfU$l)oYdsKCQ2igOt&`5taw9B3i^1|I`SS`5ubP+#7N6&V{QF>pU0 z#w8yfba|wP`!`xuCqbB7{yD3U*S56PbMP!Vy+Mv+*q2#SZ#_k29F5hg^5F~r71^&w zeCJLqoYD-92oO+}nopE#>-i{fNNPJ&CPo+{TV$-Eh4$Bu&5xDO*t>^39Me&eyTM?c z*H5c%z*>+hUC$zU72gtlw*Czq@=2A6^nu*f=cCe*%uGK#SQhVvha01(n1`ADQ6hG( z06NKta}-LhsoxViRH*+8*o6tr7zOIq%xGNV)|K)i_oBe}^l_WRIWB&?H-tLcNUXK` z386E%I_(F}I&s&7yA!4I{FoApA;*&uf4l<5WiwJ#O|1KeH_40E+X)C0=WFl^h`RlC zE#JgLWyBb7%Wr?FO3`W%i6O36U7yFNY!OoE@>{wsA6JU)k3;IC?=LZ_J=l?E?H5hjbsLl^Br74q16J~pRc#|1T0pVvrvo+IRf>qL_d!ldmf{=JC0T;qt zrz`W!VgLo~=y1H|$xud1x^L%J^a_Um8{Ne}*D!W1dBysn2y*^NEZfg0x=f4Jxz{gH zqB!*hyWT;w+CYvDxMm*^W^~)Vop@~cd-zFBd*8JTuFd(HY%uUEp1t=N5sF zPJr^gXY8JZYwzW}336)iF5DgwHg0x2G76+rOqfjy(W8+;z6cd1xqeUe_moQ;4el5l z=_d`KQImg(!-PZsEgUe8vt(H}Kkc^RVYc}#w5c6?zoCoAP(~W^_pM%2 zfF2SM&*%+7)<=Y`=N%Wi#Y&R;YHsQDhb?E1TiJRfjxDpJM`NbLQ~kF8YsGyD!q8Pz zq73;MU~q*yj%&eEL0Yoel{VhfJ@7Z8`l5+CoXa?AyE$Nf4;A+>WkZyV$_Hyb#6Mk9K}>Y~eFLJ`m;*aDOs(7esFd2)=GYG5#Xu zb^_^^=KAB4fTv<4nyBQve-pLC(sGsI3|~kL>T31BY~Zp)bDN*x7YIuYCaCo$jExng z(i;dh#1tKX$#C)B4QH!3M>82sQc%!ja~22xN4W-r^a3c>3YE7cYUW7R)%e%6p#RgM z*P&;iSH~@8uhE~*BEE|zRHv>pGC}0qkn&Zhu;#-{aOTSGuq7gcCWk$lEko6y6;@$? z0Gv4yOOKJU`f@c^!^5P=5K5x;UMm$k7cm*Q(8CM(V=Mo`g{V%5$Llb&>%e^C9?j;C z6`e3;>MQGY5$b{=KKfJBbFWoWl39;=dD0A%0Qz3evuEJ88cdTUardIR;qy$}pb}vy zNaMvdN-7xz3jXr~C1W1>NwKY={6FQE{~J;pC2gdr-MbxpKWg%I4auA2eT;1~IZpN{ z)OuRLEHU-3=XN-&( zJ@k^`R&X04=S39fE)MS5^Bv`Zre};w_3pi*j>UaF8Iv*00T+$OH&&55~l! z&^QDz10#akp2b)miqr&}2nl7gUPXzLO}kySR(MW(mu3gM(9CjwKtA&&gJ|!zsIoDM zgEW`&7n=14YMWEQu2t|RSV-nt`yt@-3sJClM}o|8zO!DnDiDvQrS0_0{?8JNLmQ}& zL7k~Asp*CY%*8bZi-_rx!C9r&NeWG0hFAlSA1`lUTa(D%=jFx59+9~RK2^Dzi~+m< zuCn!eTni4caI(1JL3dH3VlBpOyBo0t z3VKraJ)s(?j{Hw|57%X)T-IEi9_J}Zf{Mg5vh=EO@SjXd1RnIwY<&;9>uhKuRCM$v zP?}>YBcGuE@@9WY#eU0SN#c1N)azThPa}eHM5Iq`;?)&^+L~woXqs@nq|dElg%%*- z>q+A2%FYBL;{N?ON};_e`1mHJ<*9X}%DLKD9@pgF&ViX{uS_PJ4GL=@P&i>Uo{SNz3q+QKo)So;zLxze{sk+Oei~pai?@f_M z*OvWc_c5D|bWaLRl~i7C7sH2t#TOAa9E3~NHn;&s3Fo%{Au3AwG#<~x%5$rCZpW2I z-!Vq{4Z`(N@Vg!bQ%~-jK0oXGC#G{d?Ta9Bu6CTP;$&4Cf$NCRQ;kos-j@%`rc{{7 zM$uGvXr)a@_KaM`{-r6K!os|`x-I4&a~caf+|&+t=hJFq)%uc1=Dfced-TjPZ!a8p zxRDt#*xQ-8&ZD@`M{8Hq-@s8X^8=Zl2=0jP!3YjKkM;}0?iG5QKX4=RFji}jj-wLKH0{JkSQDJGWVxs z8Mnyco#<(sJ02RSNRiEexcokXQHv!nd+OjLdo+sdKu;}dt^mXuzC1$;A{6ozFUX3N zP~_CuF`cbAYI2dVn{%R#?ip*5kA0w!qLnPxymd>oZwdL0hXfvu^5K+JLo3`C4keyy z_GGaviTc2T6}vjK?w*i)OM?8g#_R4^g8iUmREGuDuPdJ3*?D5FNHh@=8?SB`h%D>_ zbFqYp)J9@gKI3@O3y3Ao=hYq@Bv^`BgD7c|jzyV?knh7-NS&r=*oEzr;&51Wg7ujo zT?~1x2A3+(C2SU?Sr5>cLIX@rAxjqgYPxKmP;96`)?lMb^xPw!mZ2ps#xQ( zfA!FUiJ+NFG7UaJaef9m!UKy0I?~a#*@44=*`cop!q@b6r?$MEECzVld0d`#MP8Qod?Xd~g652;eD2 zhJu?R`@x9W!Z|F=5Lfvwlk)<{c+ea-6O`ksIc$O{|FkCmYsvQho%$xk!+ZlCdn8J^ ziC2V$Y0&N(amg|#zxc^|`Lq*kgLjclbo5MHtiIK6u~Vq#MThk~=Y{IggVQ28c(7CH zXp04YjSMi2{&Qp2LpPtf(wLo??Mit1_4NV2b@V^P2_9HQLWhQr8t27%M>#e(nn{xi zsX!*H zLgL&c0TR2bog$p(_ol!#wuWLKB!;+m!- zjOsEkLLL2+S|8B020ZPI;d*t%|&KX==~AViOQIRi`u|JUtaCu?!&1IBSZEV`nJ~&BmxtJmc&>FQ`2l%A()m zXJyJu@5sI{n}%Mu>;y8sJ}d@#DN8u6^@R<1AzZf??%5Q9hi3cxV?3OrZ=P5V@*h{c=NvA9W^=5!)*W8Q z+P$)?DRS;{GltP44)It%c5^%5dLJj{83&3^jn0}-xq&WDWR%;krjOlT zlE3$s_$MT#TH^se*bAf-&_E@`cjFLzope5&oQ~+qN7x1{!tD3y{N`b(sR=u5^`xIH z*7cUX#iaKwwali&KZb`A|F|T7yKZel&_vDgnRZFy;0R~30*HH3h-<^)>F-J3(Lkjm z{W0%n1>Lxa;BFMx*vz4<;7iz;&T&`tt_Z9+iX(k|^M0gU3D4LJJA2L{@Y?$scC8m@ z!bx@?FV4g(U%xJXw`}$ATUg)a3dM0;+Rkfw@zhK6M0G~MbEN+KvB2#9%`q`|eg}EXSJQf`!F6E&ZtqB^n zEcFokH)Jci(>&XWI1WZ=p+1OOXyhXF*kI)(=A9IOCmq-9DFwi%C5yW|ZW@WuD0Qww zQjA4^zyLBB*J-2`9DGNAZ%-+Ld9t)8P_YL1T_(l59MRo^%bbF@Dw4Zg_rfSSg}Hpx z-{k_GBqDWF;4dFiB-SuQDTS>v$m?YHJ37yiO2VX{G(_5H4hN*AKj@_yR5V|5!)yD& zT5}n(rqN7imghJ3phzQpp;n;#Kc18mILeBUVQkYGV#RZkITMk@d=bk@<0m>-ecE4$ z5~JjT3`;7^pp>>9tI%kyP* zn+`AVq}f6WW+6>C!?C}c_fxLr+S)NpaQ@-IOSdHNTM@O%q{@}G>-cr34cxk}b8rvwslAJAtYk`o)AN3_V`xv3qgKv?}_ zVGM(wF$;>RLILmQ9&9`SsV7y=G;Z|Wl4}%|a#0I;uc_>?p|Rrt1scGG-H)NB?+{fT z{*oW+aA$v#^esjs3;j+1c<_ybRlTKXj!YX728UkSWK=@{Jpb z59|(rWks>6-#6+-11=+#)0Gj8%tnBHULT15#Ut@uEtD-{N%ZV-b$1blk4ctlZrVHf z?Sg8*jyux9x(OMsJK1YEO23|}Qz)9L<+hn!okp=V7|2q*zsc&{_rj9*ovtMEEZNIQ z67LT@VFbnQ1V9D~(Tm$}s8kCsb5Xv;)hR!J$D*>Q2TlnzT zH9K?s(q2y)_A(P}hCGIir2YATe1!+v)ENF#j_G_zuwAR4aK~zWZT#gsPVDFJmBqlR z0{+XdpM=L-iEfT|^ZlxiSXan;%1m$BN|xcJRFV`)I{2wflVvPD^z{HUacK(mTj-Bi z$w7rFX2v-$Y^{v>zDPBh8z)zy8;*WciY1{IJNqR@=S(L_x;lk=-sJ|#ti%bclLnreDl<) zS~F}y-}Sx8>FU?J?P2EqH-WZ^Ol`gZr`*&A<5jEOk_iK1#_{ zDNka7g=rs%fSrWcj&L+fe28izK;l@BcSqjo^&6y(Cb~zll#8HntqL#{q<31$Ys_;y z5gdwiZ9yeD>qNhcY7@sud((8%zsau9zo&Qo#d97cihrN44)fbrMuT+9qG5(Ma7(}W zCNq`cu;J~}$Qpi;kxR*1d96y$l_{4mmoJ|uHNmhd?{AdfXW@=BHJI($XX?|&vF&lF zu#fq?$I(cGmxzUMyv-0l`k|Dn{wdcHw1mGKUFMLbMnK*NfYdOCePU{ngfg$AE#4#Qi7=5nJJ@0sVKvWe6Un&i2=Cf|JKAwldWO@ z=Jl7`=mvwt|GXK$6djhQW8yHYKffo~i-9L7|3^xpi*=aV!##8Yd2Rg7o0+cnurn&= z_EL{$WtuTS!CK|U5bI-w(<)X0@J-15a7r07;9vNpYx@0|1qXBL9+E>)?6pqfbtLd> zeab!tk6<6NhkqcZ7Oxk>72xTTF;`F4iLf=pZu1L8GIvLPrh91aH8YLvmfv=2VCUKW z#*@Le6&wV=ME;nQH|6MXWu%5{xlD!148nVpZm{1c;dX+?O|(5dSCn3nI%gMS8>>$x zDY*;oS1f;TcdTzjM~nE0HXeju9zrd%#IKbOOl0HzUV41bKadd%?VYK6PkWIN=E5W0 z!h1kmZQqVK0*VT_eg#6rQvHpi&HSV}ri^-f7uvjDJB_kUO5eoJDhtjY|3i+O3-o z*eAY@9Atf1t_pF~%KqOmOr5b<{>2drf^BKvm-!=-GI+?{6vXnpfWL24{lEok{&x8y z=n^+J+ak&es=;CdJJmfrQ_QAL!;!4x84+?3yw`RFr4xM@r|j;J$tXPB@cMD-VRb#N z+1hFZy7P0tuop`D@k1M!l65<`fUKv;BmNkmvB3DD|B82@oDft>9UXUQC!U#Agn4m7&utC@}}-nh)a_hduiqAd4J1AEJ&<| zZc9G$Q!@l_I)8_7u@;V=V#qOVw?t1z`w$0X#e6@4q}xGee^PHIi%|ct#+<-TO8DGZ*Z{JQDExKCIt>6y1ub0{^`jxE6)aRN)q!XQZ~NT_+^Q%H*`7dD zW4Rfe-$*BCs*UUCRX;gV8#}+Ae$YE@)ACTX?B?XhAZBS4AVD?|Ia0D_=NbX03yGiC zpkn0V7RKM>lykz%%hJqJCMR>#KNsob^NPaLL?)oVPaHTBg2ky_Ql-sO;{{m-f$0d_ z%`|M~fZ}=GoeY^#8D|e*<`M2%7GPJ49>F8Ugqugp)Mu(*xOQAHqRU5P8Lk3^dQs=- zM+Nz2C>ZACpTh7`vDYa1>vRt$<*tPA58 z2>4he6>Y^ZfziRkHNuP-)q(`*-vOi3d>Hk+LbIEPYG&0^3oscJ24~e zjM{rQ4CQ*cAI@-PV!0u$5I(!9zFYV{b8|`X6%t@jAd+DQ)4sNrMUlwP$fbQ^#yfIe zo4secUA_D9m5tlUJLM=Ids|)07kg&+r`gJ=v{^uDX$(#OF@tzM$LJXJ-Tg6B-0jXT zI4fCy;tCl5`_088n_4%|S)2hhnQ6rL0afoUF=B3e#%5?F`<69Lp#F*~rP-&aCyOEF zbt`dZZY6tf=j$i*rqo}h%r2#qR)u2o3+YySF@o!~O0s}LYP5VygX~<@LKuI_L`?HMPDPP160ZD2BzdOuvQTiE?D6b42Mm+&VxraeJ0r-`(66%8)jF zU7ZH8Hd89Q$);|A6k02P7y~L{jm|BXkPQ!u*`o9O@%_O$Ijhb~An-q~0kF0vPA%aT zsYy9>Di9O80UU-YMr9cL74@qFH4HZ++m2-WpGE;N|LF@rqEw}^Vo;`Xj!S?|f&SE( zPxe%k8`hcQh@$yrXLQ4hyZN5QH?x{HoOPA|oT8S{D}J>uY-{RJEl$4d@7$Gi)0U09 z(fZ2kUggmxD41yZl=>>^@+t{p#wATV6OULoJ%bs9Xer#yMiNvP4}c>2*5BP8Wj}ut{ literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530010005020.png b/README.assets/image-20220530010005020.png new file mode 100644 index 0000000000000000000000000000000000000000..5cf8ab7eed219566bca0e9398d224e997979bedb GIT binary patch literal 50224 zcmb5WbyQs8)8|P-Ai)Xl1cK8@aCdhNuEE{iH9&B8hv328J&lBP(8jGHxI4_v?|o;_ z**UvAvwv{tZl1n(+2}p#8hvX+&`zk8{zC{l6=Oag)rR+!P=14Vxy4 zd8zX?G5@cPI9;Q$|#>`Vg9 zTpP(z{qwdkP!%0ITDkacQqO3Awc0G2o4nY}GLL2(i4lqk6fe!XK#vVwQ#5h5nU5s{T|QO1djVwXY@HnQAB zUoEt#55<$hZu>tal}qYCJvOgfA+xQ)lU3bTaWN+<&Z7GQXlgwJvlMv4gr(5qcQ#Nwm_YXlsCUzsweLm0rUn7OEgHtiJZd(0h^k z@$t7M*-rc_$K>{W&ybezgCLn+g9(4G?b?X1@O7l$UwG0t-LU%$8Md=Oo_EJuFS*k~ z9xi8vJwnHA4_bG7odKDxj@I1;G=#I1>MV~zzS3gVgbQPOt#w^rx2(+l4?_%n}`JEzaVLs=Fhz7b_?$eiC}uvup46HaF)Y%l%b}F?aXD7Y@}f!2 zK&%hr$8~-YCjyDvB`5HYcWd^>{_06H;uxpfuJPy7&PWe0_u|J^ujd(8f0WW&=EHh= z@3GdbpWsexbw>4A{_-%NbpiWPrH)DeCpwODSlXP2fKp6DBl4_3RR0_GaZ1Hnw%J8q z3yTIE67-x@#`u5xs<0`1}6y9`Ppx&-+& z6bJNpyGavMJ7fE7Jn#}rOIFA}XH_6{Vy)c_S*pzGH2QtyhD{pGgOVEA{)v%HA|ea6 z)WU*zr^k}mMW~c*V?G3Y4fTm~p%6DMRG6t*N8-kg^FoSf*gk|4(v+G~#?H^REc?D` z{ntcuLY9|zXu>Z%8n5(=CTgHV^oCbNNa^|?oIi4Tb_g0qVF`M}CODbOxZl@@h^>oD z>17r)OS9r!?HEuTSd>t|r;HIJPlQPE7b;^^2uU{!>eIXIw0IL;oPZl9jP51Ypyrf}z-501EJ$bRcs(HE6%37o}B zdzr0CFD`8sPP+e1Hq|gbbSCrKlf6#!__6VHvKxA$FKPKf-bE9|V1<1mBe$tjB=Ljq zHld-P2aB(=Qli8w-TlsIE)NIC;$glq_O)lqwZLPzw;$1|BE#1F_)ofRsSg8l$^)H) zzBF31wK?;2Y6o6qx4Y}H+r#)GHhH27@o(>veR%}Xd`jYb4m@18=3dPq;Bk+Wc?Z$v z3HGrkW642~b$JyS+Cw-yJzOpf;NA3B8}FknEG_BN!EGxJSy@?WkF^>Mi3&8YtZZxs zj)bPIQa^Ml>6-=O_60-mhsaS27M)!dkvmM1vdJuOjdMz96{HuUDCK!xOGe+l&K#1B z8@oYHUS&85da6;S!KjI9$NDox&irRbusIZz`GX4$)GfEj zMnA30#(5-iU{mVt{&uB&Dxv$wLeC&QzUtCmlod|$$8Q+B<9DC8PSCa{l|K2ngjlaA z@?e!sYSN_Ue54IOy?^~Chs~#6#KYv3?^It3&N36Ch0V8O=`vP-rlzpv+d}~q6happ zY()wdC54}N0^#~mLtWo?k4t7L)F&s{oL$1&3WF$3Qjqr|M(m`hF>MA}@MZGP0>&D` zq51`C%$Tk2MFu7u?2;~~Uz43t%8O(2_Ne_?4U@$R`~LjFnYF={O?nqD#zTVcWwanVh-QD0Bt}86wX%vp}{vnF+hMg^q(r7P2z1610u+Zxkc1TSB#a?&vn$-U? z3{I@+x;xzSI@gB?8nnsNN$!;(ozFi~-w<2zcY^%s{WLj)+UMiVxMl>lD8h!aC{?*c zxvBU0xzzcfde~ZE-}ES(0{o6?+U1Zyr!o)H(DBfTVB;hT75a0I^hs~JAY~|YV@0DJWA!* znwm(6p@845&@i>JiN>Z?!bC*`jt<~C>wME$e|2Uon-L)5AxHb@Vx^T9$$j$iT$z~S zZ>e`EMd9ZkFMML3@SSV0fleMSFUYoXfEQN%b8=YJe<>4_wJ1~{z8gi4XG^=n-h+fRm*s9zro&ulw7j;I7feEiDN5m#WLtjCU)$Jvxk3G{fK#%f!Gzr>SxHsWHWDs1>kw?|IH&E~H|!|XKQ&Pv{65aZObC=T9Pz8_Ix|VD zKDJ$XWATRCeUFcAJv4Jok4?=qrAejqUt%@YyxFwX8SG25w>xk%DJdslY*XpruD5>h znUlCE+4?fEjj~;(6Mg4h=7OAfHQ(s{fM%z=q97sriT%@v+iZcF?Tz)xXf1zBqx}W) zl9&?R_Sin&?4Q?nVo@Q3vLDu^dP?j%=A|?>6(D9VE=m3UqQCb!W^Gd4_$J4bX)|+j zhBy>8uH@FRGWJqmmzoAwZVw%KfCv#-6+X%16Yskk-)77clwRZcu#LWbee=Kv?l(D@H99>k|ovU^4an zl<+#nGfen2Q@Atorj~bLm3#$!Jo84~5|x*D7+&D2_~CA(HCf^C9`)tvU~N;L{HPpu z+x-Yz^N)RqaM_MH-g+w>5cPg^^6|XE{Y?`0pjL zn4U5?TkI1RqMvJRsCQjA*q?5TUo96ysLC&@QG0TX?6YaYGYMVH32P>mss4&< za%AZ(IVp~g!(2X3Xgk|ck zCCG?LX|zU7pKLDDExX8X{cnpM1hya(Q(3oF)Rnks<#>gqgxlr{JTVfKmp3;bWw8ba z2es2ASqZ3;$61AhrhcX}?jIa{#6dRLNTbT+IsGs#{LC{rW&hY8M`oIs?rU6Dk(|LJ z*Ulm0%PQsy@y?TS79aJ!+fJ{wv|3ZWejbJ0Rh0)$#b1|ZPSaX}L9E$foR-J1W2&w@ z?%QSYR+qgq@x!|T4Da*Ia_`e1QB`tt8l4X-J#Ojkv}C*Oq3RPJ4zR70-n@X;XvY=2 z`_6nAzOe95Y~@%dMr9|r)fi8IVZFJU{{8EQiz6b8$90#yPLz2FBoqWD5%SAOH}pY* ziyZ798hW#6m!_D_RqwndHS>VGifO0^S8G4+2VJ) zqgr2vPtNRjr6|MIbQT_AkSXM9{R!R zF2=`RJzrVdI_oUACzUg>n?;iCx(42z95S~;ez%6#cs^*83Jj$On3(Et%@O8X%GVVU zbZ z16;u$*zH?HL;?bWz8#m``)ZVd1E?)ZpBxhsV~}_v9Bw33xu7&NL7jKHWBlTW0thlB zBBrTX;(A+%s6hn@50?W{$KA<;r;>7xV<_>+!P$FM zxW&>3O?LJnqg%ooVZM+Tf6s=iTKqp6snl#FM13zo)*G8qjS3ac%8cl5Ye#&x zeEluL%rrR;8?@NC|(DP3@%Z>10OXTENXDum?6L) zEKTb;t@{Zo=|G&?IB+`UxYSEXoYuMIG|s)F8>Cpb#a%&NU7=JPPQFfb)XUE_Sz6U! zK7dTNlO|vaP7i18OlJJwq~!{=7*eYEBB&`eU8yWxGmcpU^1Y7{bNfM-^xJHp6uadO zivdz0fuz{n>ExVNd|wbcf~2a_6}r8hTnd=R=ZZ78A3Q>*MTZ}~7agi1|8`O|(`KYh z4KX2cN2`Nd)tPTaV!&bhmcz9nj(dIN#8%?AG|wqjseFbb)`{oa;D)h@Nw6EAf$~Jh zVaU;~!y{(??V3Z8;N{Pl2{X-)O&0vNOZg_#k93jfBbi5bA9v}KWJzE{Dk1GQU$0Yb zPth^h)T=kwS|Uj2?M;dg=!CPH=l8J~Z9q5*uP57bnSHC$QDW~IP zwaef&Q&pzgkldt;!XD8N&!{3JEykOMjs3!I?b5n>GY{t6vCEPZT;trBC-oU(Hx!%> zOX*$qFJcRgyi3)h?(V$VGEw`DF%SME^er!wOioT-4S__xy7kh`v?5tVKHyOZeCnSV z!cla<9+XK|(yI4UY-;v$)->v2kc|%EUzT#C9Mqr(KVAy(>QD%G#Xlt%xL-ngYeUnl z7;}5*r5Z0LN(I6+k$43Mdhp8%Y#E=b#3jsd6_XPtkW0lfla$3>E9E0}VwXXUv>1(! zMG{WNZ{h7t1R`R$fBn)A2oWNj-5K0**-Ea=NF})w3%_#<7mG3{ZK%ors3|#%L!uVE zES6WTS;Ue4F}d*vsrNYo@fL2`3{E7xa$h`6`M9Q_L~a1(#*WdxUDj?=SXEwL-aX0b z!U919sL|)jhB9$1iCPXkwGn~lc@dXQZg~yE7I^qI?bWt#QEMCTy15^?p(pH@hdqbB zdQ{tUUyL?e|2;n;{ zkKUn)1x(r-1`Q=Li7nh!};%VYemm8<+pYENnk1LXTf|kEBiq2p849reUpk{N~i$OSOXlMwC zh{TepxEz+h&L7~4YJ08drNM!$RZR_$xjU&1efC*t^LhJ3d4uXoBb!@Mf6#1;@cY{- zs`a-?j7ssgc&0qufEUVQ#+HsQuUjDdX^DsET&pSKLIM*D{h}k4AI2GK7ic`H z9g3ND`zQWZ>wX&gbNVVT&?Ree(pIOlKBf#3vD;+DUz0W-F+gF+cZn)2{7xG^rx1^? z)uBYVdgC+yCsW?v;~zBEx*QNj(Iu<&#gHf=^mhVjnNR6tK)zk4%g(I}7A zcz=Iy<=|lWj5tRx^0xKm>?OA2Z>Qe{vC;a?+LJZT;(+eVa4mmexUl!UU>8hEIO~db zxiK)KZslRx@4Aru%v_npb9EK1Gg8LVA|p3u{TMp_R;VRYy62wh`A*%J*X^eBZtLZW z_VId<<-Bg~9w-0a27l#9(XP{%^YNC4-4(E^>{&RSxt@UvrM5fVcaOqPLV>sT;c75u zhxN4=UtTP|KGUvLJptrKFJQ~N@e$JH_9|pFqIN=3(w+7GP_srIF2~i0 zkyv799+I%Z4eBVJgSi^Lh#`JaD-eC6%t8aG_oskfs#>i`p_OsRj97dRRqfvV1 z&J$2j!Zbd8Dw><^r$kw2#CP|(Jfz4is)f1}KU7%j?cO@{;@7QB{{CTY^4FZ9U0_kY zxjtU@3$^EHKpyt@s!PKc-8%U+t;jSaUMn@C$%ZBDBE=uU_sUd!k> z-4dUY3ynkU8NXMCfuMVcJn)|$m9UGwdTwfDN?H3?A8uHWbrjbkgj%Y%BA2nJnRX1<#i+>Jz*DZqiXLo->O?#j?zO8!zkA&%2BQS%$-Z zp{s+AM*RVA_LNeABJi!4G*(D-^Y>ik6d1IIJ9QFAI#1AcBIOMOHlR$ z$Kw=mxTvU@=#kTRBptQM;GMMk*$^jlePg&D7duD+8}|@k0Yf3UZjNt>TOCVBJ==e( zB3rV#G?pYKf14=F$fH}|hl&_EzGVyn3%}K;!=b}L24Z9?EFHE(D;>NF4P+b&z7t$PF&iW69cund_Vih(xFo}5ReOaNY-|jvBzSEX{=^G~ysI95jg8AXAfU$( zi4iLbbZ5}6Pm?NV0_B>q!bv|^&X;~46h0p_BC$dZsdMTA&o&H^jQ+U)L%Z)5t^hl&|v9F*2QOsJ&%}Q$hMjJ_fiAkWE06hIk z{r{bJ{|;AKxq0(Iyn-j%MwdhtB~i_d>D-NF$fBX$6%^H+67oSGW#~%Is~d9#@&B+q z@xQHK{I3I4SnNHq8+D5^l-P~Fo9c3XXUKwz{~{lNsU=eHpEtQ>;>uH_4t{Xzmt3=F z1#i0|@^IuB($?wL%>ABW#66cJ_FRahk;nIzHd7mi(WO=qG(`Np#&)6~o8PU#ezElv|XX{XbFyVSzzP5?a zl4rIIQNEcZ-~7n`;D%Tb6+zT;4JmMOm;vRGK|(^}=w~{e}-wmr)~$ zQG3=siBsI+zF27)S%u`|r`y-cLT9fd%S7V=z2uM2?Lcbm-v>9c@D!WhK$}NhYAumu zUAEYlz3NGZw1%rCl(=QHodY>%{b~%|wQz8G7doegMou9)+9bz7}?szAaC+8Dl zi4kl>`cZ4*Q}!!KS4hLY(p)nxJu14(?eLe0^o_fRoAoYNZ2u!<3%_q4dwE7sjekqb zcg$YaoKV>iCy;Lpf6-|`xzLu1y32`i+Q%HFZPbWa&y$&1{1co@zCG+Ou0Z3O!u#aD z5@rBrURnAkl8jfROTRP>B~YEVsun6&hoNDeH$F&9D8T0YH>c&tb(#BRQzX9cz6EYl zSxNM+kX0TbGJK_VBROg$Nt{4$(0K#-?weH znqMhv?6OIBh8|7g1aIgtNWmd*D#Te_>_D9a7jF7I?>69Boaw5t_RrWo zFNLlZI=_#d6kJVt45aU9bW2GE{~bUw^m4&-tPa~vnu*b@mW#ulBN8J+lWte|WF*#V zc8=mL*C9%QOY3b)?i&Xx;N+cwK+Md3eWY-({#?j2G9x(pwcOn=5wl@mycVxw50_#1 z^_^XoAN}}PB0jHBib;=M(HO2>@sLFQ+ZTIA=Vtyy7syb&Fu1=TWIj8>^>d<}ZK4Aj zWfxmGMQ(Ds;EbLJDvBV{NW#X+ejH=QKlsQX}(**W^s=gbX($vU!3GVVSS;vy7>Qr~GDo-Ee<~bwq&M@iL@d@qaTpDV%^rZDT zD7-xCX_zt8x?6X5^sG({%ihz!atOGA_D*t%kliWwJT9J`POdO?2j0i~o%tu+&e7g2 z&-aYpMBs9D?ccPs-_cddCLnH4VBJ<7nPHoDFaD!ffNY$ie z>io!CSG!`fi!Msyg?<_d`z7oL8|e3%z(eKnu!WhOp^nQ__X$$h?d62TdC~z8$I}CD z3D&rmgvdArSL10a?&WUNPxXx4kwj3XHNC(ne*T}V_+^hQ>OU+5xw~x9juw+24>NHJ zxw}(|xvqX!O(kV}<<$k8@s=UJ=4eJV_Dkr-AQSO{=DXfxeK05$ClPcBIUyI2wFr$| z&clz=%Chc$fbR+vp>Bp{KSHCN5m!v^9p9$?x!JLOT^B*aseXRc$`lq2%KupfXwfW?*O+ zR`Ho3WojuPY1=L{{LbQj4Np>&y6b?u!St4AcY!Cgx&R}HEX#D#&2wN8dsImOS#kNP z!d(X4{%l0%cfv>2qVvPeJG!Z4c?$v^?ZGKS++K`R^k0GM!uhM#n|~s_%@o2_*bQ<; z&B~Q7BXTc~1fw{!&640I%aeK=G8u*`d5Q(A+m2dqn`(+GVC}@$!!>LFlLf#A{Ow<6 zJ~-(j(%aXN6tHZWWuFb=l=Din8|mPWAGo;b>XL~f4h|pjkT)2WT)aSWCOOD`(IM59 zS5i7~9Y9zfC!7#EG=!n zQNZEIKmLALoigB`f8V_j+6BVFk(8>aK}w=F0~<~(^4aR4fEieY1HOG(%h;uUJEj(8 z_j_ceDJ>2`+x*p-OhXt5em8TPfsGJ!|frPb)jTH5>Ry?=dqwu_;7al4xDeByc& zT)E-Y+HhrXV*Dj0@`uN;(s#fn9t=pnUDtMf+y9F!x^YWksQ;_W6r7(@DqE@zuDI$u zuVtBYMswoMQ%OGUzyrMntT#s*%23>cLf2$+<-X~b)+a=A$Hl(bNW@HHBC|CV<@$$U z?`q?3PV;=LzrE|F7vC9n^(%=%=hQmO>+R7TOHv(Z>F%qJUR+#etB-=xuI#?<(z7Te zlJVPT3^e^ixO2m95U?h^K#uvLUQL zQJ`<8pV#7uz`vV}t@+W6sSG!-KH8nJ(%%XrRU9=p8>n7i5jyr4oU!@E*tThS6E&O=#UxT+-#?;8 zCMzw?9~G>fh)sS=6nbP;7T}#)j_~l2{D+-*N#ggSTJI=%9Qq~p7mnWc!wYZsx3o6c zYQ{bOQoh}f5B%wwuj>8s(iR+Fvp6zx_26ye_4VPz_p4r3%llQ&p#CP5o2;WQYg=}u zqitRz$}S6H;`!s9;i&g{zJ~}(UeNEy&unXLfnUW}xz9%Pb!7E6E&aAGUivTQ&>j3? zj%VWr@Tk>YQE6OA)C5#soYJp!BtM&zsAVqe#})BQl^A@?Alfcn8LaLR3h~_4$>S|d zKCRx#n+h;=H=FAT? zUao}a-bjwWLe8$voaL;w_og-FC+^{##pk20WaXD5 z^79So$FP;w`tvUg28_Mqu$QwfzfC=co!acSyHN5CY;wQ1Cr5CjceQi%P_LUvwy>JI zQ~Z}LgRY}SHqGLg;G4%+lmvae2z;_%D(>dPeuk&leEKtu;+Fd85f%qq{Ew zuu#Wc19<$vFs&Tg=w4o#^aIs^d+(U@(PN9zj;rcQ3*P%_qwN#&)R{@RZtj)gT7!eA zqKnEM&K%WcduaPZTBsi^(eeDWwMwQI&gOflW)I=dS>*7fNKQfc!&{N?{b~Ow$2C35 znDm98lZTI!H$Ud8HkaH{!pVjEvDY5>pF1l}vng7-0%;H4`nIL-GfVc z*&ymU1exV<+Fqxv9+0_NCHqD>hosD?H)s1Kl4gDKP2G`kEv)tH!%UIh>l@O9`Oz0= zYxh?u(Eb(?W%lInLG#idHYFG>GqWl;?PJz&+J99u>?Vzps7xf~<(U`$rT$I$aWA?4 zoN$+BSBbPPf}4Z_2Mt?g+AB7L{3f%G_+qO;;qnp(vdlZ^Q|Amr{1PnpeSvbhyQmvBzA<0;WFq{7G zOcz7Y;6~rc4R;6Ae{M3O@by^3w=(NkhnRokx=g-OSp7eTk}AY2LEH@*48uT9AydI( z(U6@0_4m?}91!-m%;UV-unQLp_7YI4&=_brlH!*BhsqJtWltt4l_R}*4ZhCWcO!}) z{Rkjt9NNvg)VWHK<>hannEo;DB3ov-bUA7q$#$9sfW<4*25q|Wsm?YkyEp3&x7aU1 zq3Jb>nFzz zLdtx(4sPts8MlXqyjoz(8{G#5MUel7oDM{G!) zYWUgAl!CmNe7TVo$m1@qAgj?*@D>UfR!FwHX z_E4T&rN@95&CD8`EE=HDELR$0uCvf$z`}BH=9OUHUKl0Ye7$qw?I%Qz9tm$Se<0kc z&x~X4{k-eaPV(i;7fV4ye(CajT4+o9Bfo*Na{Tvv7X1eKj-^Sa?YrST(SX~rn2GZ9 zy$J8sE4xZcY;>P?b6@hCt}oJq@IUOuHMt3hvUhr<4L8@%WLxa_Hl7?;qPI4nEd=-@}ml@3hh^0z--L#^%Y&Aq(B^76=Z_4J%O4bbfF+RZPh zpLg>Eo%i(BT z4o=PuH@-wFB%QRnJzga$EWekBwYnF5UqwyLgE}TzHNm~CGMyLC`{tuO-(#H?I6ED@ zj@mB-Qr!m4*+4lENV{sSz|`7U(=W9aA@6rqJnah`IVZGwFL2Z$C>m~CIZ!Ui$F93w zcfZ?QZcHR^mK}2zltB(&UcN!@p5AQ1$Pv0Uh9OIcf)dMV)k#ONqAkC3XKh^Rt2@8E z@NfhY^tb#Thkg5QbAehlpLyN(FoD8x_rtY`4y%BGf~6(xiT6$C-jTsfUz(AxTq%~i zy86(TGwNX9h7*v|+uz@BXGq@yW(I(vfXdVA>gv5^u{MZJP;l~WYgDJ%1~*a0Y?1jl zu$356Wy&EMRhp=S1uAsLI(V51WkMY)4~wkdd_DlRI55|5AU#@HSycH~ha1`qr-d>V zVPZ@mCEidiUy23nAO$5QHRkkBirD{wRXMo18(ntfW{7*G41VKErcsNDVnDg;K9F3V zCexyy4g{-O>^8`^5Npql7;vMV?q<)wNB34u8Ck6Gk&6iHYy2WKCgHxyx=4MN0(Z-nHrN zZJgrbE$y@@6M`{I)N)QaKCNx`ms_}f{fg&|+Uye7VZ@fd%QoTfEi5eXrVBxkKYt{& zwD8eKXW1#$k|!<3cU-Kpq<|S_PLBcTrpHHtR5^sY`51fX_JucxqFze~OEa7RKfipT z%J&;8duVNI`&_boIb_>~mrAxW{`l6fhjCR3m<%2gx@ecV2OkTT#yLo}eQS;=4_Q1r z2glIF#6%K3qHNOGj!Ox|8V?UoyW58oNI-+NmTXT14V65<3hr{{rdRY$#z2Tp=1aRS|;r(YiZcl%89rZzYvgJTf zW^R0TQBY~)?{#^3ggU4_him}@4E~IJF2FdCZoM)*eoq_`Y_2n8`e_#iqsKu869p+k zO4KUWop=Cftd3{YHp}9vYkqgRu0&TvQ0ufAgaY9>7`$z^2QUOx96RVpLp9@4PnH?m zIFOTuKp=2H$>ZM7+upESg^rb-J+#caO`qAcexadBu}y#(oRLKptggPu_A7jTYv{!N z?C{xyq;ep)6S2+2mF0-35PYVVUZTdCk!85PaLRFk;=PnDo^ztS(gZ>rwXll4vyMf0 zhado+bFHKP1zcDGA^~Y?eBQgb6Hr%oR?6WSzrB6aQHza=sMGC(J8$Gk`t;-v{%m0B zWS3T0Uy5W3*nOQ9i2lo+B6sb^+|d&pl{#<0U3f-T;7Eo0{VwJ%+ zlEVagVJmWqy&10Vl|R$zW^9y0Ut3|m5on)_6;W6&c9-Q3(hfL;92 z8_V$C*sG9C;Yk4}o;jrV0ImeS$a@FRD#Wbuoq3deWgl6_A~sJ)=z4 z)|T<;=;-RsZ;%zhlK^W`R$eYkll&%B^nFm>r*wa{s=D&b-LLsI2OZ9xByLR+XWlt= zJzH#mog#>k)Y7{RiA*!sp~+_1xZ+7?f@^JUz1YAAYy%Xqvhd`^v@k}OKBbeHSxRUm z`X?bF)n3-itD4;wJ;%b;N$7N!QId0b~>+`hKjSq4Ds0wkkfS}6lQ$X}E<*ZHf>P7X{UK%ioCKeVE zVudQ?BXtOCZhYM(qzxc!Dv^49ISw22>24S#zieJt_>SE$p*RCLioh<9v__DC&cFf zRoLRF+wV^7!|X?kgrn1AlXd}|pyzaSr^j1oJiOmBNnzlffdl8pqVmYRym==(G%R$l z+s(j-( zVfn7loPW_)n=+g|m`E+}Y18j%X7*;#i&s`%Q`5)S7bzT1dbDzu0a$(D5K#~QO^4p4 zna}!cCQ;>bH@0~UHj>OY%ay9-n_Ai13swm>6Q^!$Y}}*8JK49F^!|hy5^dC5#<6i; zEZO9HG=;T&fo=Y}bXjt>0&-2l{q-CBD66A8Zcb3Nr)58Xa;BLbLKgv#Ljt3h`*}j3 zj6ClS-~hoQLHs9OG1BC|Ig5)_?fSsp6a^8L*3_gvob<-i=6U59vwj6=huKO^zsq8B z^P{C^@b6uKVXKEf6y%6-$S7%)$F8N4?XY2+umupn@$F4-K?A0QKM~aSP#PTM*-)vE zfQ&J^(L=%GY@Wf?MzuQgBGJ@LKSE*bGGwXxTtk_wlz+vUoo4<%N&@JTxB~4%th1y5 zVhn)9>fcAOOQYJ@oH*N~>#C+ukH=XGjk@r;`kz-lO*Mef$ppq8A0Ks~H`mw95AQOa z0@B;ic}5Gd)luW}dPRoXLDg0kkfojJ1$oQp93XkOw$X^cnIAuYWah5Sp8E5A#o*pg zXs*sknF_0)Lvdtublj|AVv42$0DP-70l;a+z@S=tCbssVskwRP_ir)4n*gF^ZmtEi zSOSBryf=ZRX>P~hMvNq**^XA#gJJ;VOPL6uA+HSPjhyxB=H)qv46fnqvSAU_#5RK_C#|qX8)gZK?QN1$ZRjR46Jcf?E_MH8uT&j08nb6#!y2e$;h}!dWNH zxm{n&Z{@r_WN|-uv7uT^AF)~g)xwcSv9+!s|I0*nk}jTiv#tT#PYPMA8LO1=@Nl2k z_#e_34Z@lC)mP_mHX|k(_pRf5%ARzyLz+050x^o3>Bp`WyCuZ&$uc+;%@rLP4R6k` z7629JJ?*!d9YqDw9%}*AXcga<&2s77#DIiyM zlcS)Zw5=Rd3qF7=xI6>OmcG>e*{VM3B@rM~_Fwwq<3rR6_5Y0ZnW>){2YCk2myUs! zmX?CVf~j&dKzw6lw5D0lCg!zBjj(Qi(7D*s^H4pC1}RdTnc=|Iw6-Jcg4F1(j8x{8 z%{M)ka&fokfD>>efe-~~+94z)q$X1?$d_yT0YX{fkfFk&N^aCn8@|2eA?9|VB0=Y- zLSe%>{pCNRs7>eee8&%I%22XkRXRYZXi%_KcUr`%2Z4(;7(TJHi&G}@*gj7HA`jT~ zJS10n=1l8MmZEXGjxA|s>U20?rHTO;v3}(PsF;b#$$!4wOW=yk&tCRt71OJZ<)1rj zXI@=GW*96t%$$lJ^QY%~lj=P})jNd%KSGmCkq!n!+o*M(v$%4ANxb`sN38kS1RV|d84z&xH>x@q;FWL$ZDoNfW;kusj-{FfP)t7; zW208v6jSexR&a8)m(k=hx$K!eR#UUr4OLVeE-cGi+IlVSGPxUA0?Pj3@M z)&GdEd%SYQLSdQy^v9d!w)ueq6Q+s3fQ(v6xRqJMq;L#Y}Pv;`@0@bdba zQWgtvj92&TwsX}wzZr$QzYe*adkFx4nM0B2+q^?X46W9#->f#52^J|JL$%c$6)XIO zE8iEA9+@!>+V}BEjJe2dg|v45?&$0U4kHdSf?5R*u+0GSmx(t{H*R2T>>V8UveRG^ z3}`>toYQmcHZ4XPC~dEPwa{P(D7Njwa*T_C;P;diDU<4-QEj%8B`6i(*B!I!N;%K6P2E2Toj3D4#Y_ zhE-6||MRJPyFL&W%`7fPL601~VpnwAM*y3%b}|aP0E+PAW=WZuguq#3Vq(%#%(W?p z$b#_1=iM6??YiR{is)ea+y;6;26*J)3M*!KDjUwd!Y1l7tSU(J!IA0X{e-Ix^tu5D zC3rZ`3y|AN<;gQMszBV`O_W9@>(y=8Vz)T(58BDiHFt5rl1*A@FqapU@8vrGpr6Yu zuTlSMkaf}3DMi|od}r}#P+{64Lk46F<%%+kAa1QL>1{179GpSdEUe-jh@0$AVc=8l zc1qGH3o^+Oq*{UEet|40dD!WS_Q4G2I4h%z)?M0vfMPhGp6nKWFVmL;Dl>~ zq=4ycZB36Q=4RIGWFGFuII%n_9Nq@Bm|Rb=B+u^d?i4Q!h^&G2tgI95CVEYzQrCeS zD^(AwBJ;~tqMfn2th`SvTSDl?TW8ChsG{MV#oDkTTy8GhXDsECHq;A5m2Vuib$y2Y zWUkdD(5uas1cH8BTifmltD`GhSbKMOx8XD&up(Ss5rF%=`a4Ux@t4SH9Oz`TkKSQm zAdWY!=X!IK&^HdEoGV(yLOEV>(Xy6jNG+?tJB-M zgD+MXg3;&vjU8{0aJ0mB>~Kc&JSHmWZ8cwn5}+csKi}K)7%0uv8h|TPyRY2y=84L8 z*RP4^6Ts=2@=WNwT9x+=xDh<*Kw_jqL-#xbdQ|&%O-iecFI`uq5*JYwC%mkTCZvD8 zVd~8A>k^-J{HQoUZe&ja_5u)WhJlM5if#tdkR~4!l=x9Vt7|V&+{5>#6n(r zxyt=5IO}!*64=_B_r?7?Fa<(5r17JKBqSy6?S%Q$p0nF)?_eIX|4z;MFdMD3<=wq! z{^rn_f?z_fgBRuavRK?k6tB=dn7groF=BelM%x)B9n$|dk0#(oy!AK9)y3FxaSn+= zwIWIEt=Ek~cKcHVr&|*j&6i)Wi+Ynm#QTSbX&p=;cK%a^YH$Pyzrbf-N27CXw$!b8 z;iqP5Bk8sr5_IYAH>O9hv@|@x+0`u>iq|lx)kwFy?EI{%Ob_7GNdux~nIw%DqHaH- zX@HaLH~x_)ks?lgSo4aQFB~(5q~$Xo|~(1d@H;q=aqe^v)D{igvJpOS+Lu z#Tyy1*Hj6{ugkvJeOa!e(rYl+nbdVZvhmHnd!hi3wU~hs>df+P4oc@yEb?-_Ej+r` zGGTX97nre9QNyOAPq0{ z@xpJHJ->Z@)Vf}qj+vQ;oBQTgB@f%VLzKXWudcF^&*bY+6p3GCENaQ1;&(u#70-PA zTs3URMV`NS(0zPCN-r#&59s5-KOJ$Lyn|yVoRMg~uKbCpy)P^ZWUwoHYYw)3bd>$L zKbAcCjIu;FG|hUnyO3!srFn7=!acVvNL*NpA_ABiSOvJZu@1{I^#I>}vDyx9>vXiPp z2i&1cJB{D#pFcJz&}hM|PEy5*KpHdV+0feGUoal%%n%e5w7klSTye<%Q5XJAO26|Y zSHqx_HrsB#BtbWs8BV#(WHy4`Zq$^6DA7CSrm(TL@^5By8PuR?$@vXD(h@qki>Zz{> zllw5H(Oo}j*L-GUV^iZR?E3JIBtI75$rNrqzlGmK{8!s^!t0_H0R0igRQvCqZkbpA zm4&B3Xkz7{yBl{c26FwtB&^Q71|sDyL&wU4|K!$Bh>MVP|Lct?m@&fyBqR#%2EcXR zZ1`_^kvnk^DgMu=;vAy?X{<*6@5XBS|8A@<`R~r_gxCMwdHsJ4V0~UJPNhpMAU_cy zsA0tKR1FRAdbZUJHcJRzK-NJx%Y%h|orb?3YzpTH$?#S93v>?(@59Anz&IQPy5cbKDN;TM?WGYW(Z(eNO(XO!`d4Py*lS;r& zH;Aqw$s}%Fa7hlbE2y$p($bUKBP5Kd^~zf_z45nm(0mJ7QN_hVLp!4m=VXK|Exe%* zI=S)ag`U+LESyjF<0QM9=}GQ+v=aX&lR2Uhwa?J{ph&JlWg)?bv@eoVd+O72+mQDPtrE?^-WcP@b4I{~~oUVNT^2 z`aP6Xf^X@&EqZbeUh$n3_md#-+=pi&b9AD}8)px7sFRpSzcCNZ*XP$ZQPlO-I=8j# zc1K&qm~-J&?0-rimQ!qS@VXyU^ug{=!e!PXgK44c1|H?`Dql?0?$UoYGzmExu_2~_&6UW?o&5ZqFM3POKA>?eTeju!K zTmq-1y&3n)VK(CR%u!L3s!C0yw%&7X_$HM$^G!Q~ilVTnGN`hE0iHzgM>v|%+O)h+ z0@BvOpAC?zpaYB#QWA5Ag~yiiu+E=O%AI5=zhD!N*hUhWqev^@+wVwK|%6+n-0 zU8;hw8kCw!@jC=N?nDS+?;0~k@)e_gM|Y{o`9se1Z(^{gy@kGI$xbtwu2wSmIXaei zSK*V3hy@pfnAQzhAY)&&{#ss@eGtLX@l6Tte-|3;3N5DENm8$+7Oab6s{8ZH?R(Tm zenVKP*4)_yKhv$IW>@6D?_f~yf?d5q4f=#FKO=YC>Cb2%$c4egZe~i~5%S=$HWc`D z_aJb;CQ7A86A?lP8n>as!N7bcHo|+%W_!$5hVXcJyOe&nc|uiWL*}ZrHq6vI{ZTzh z0`Xr7kaa_rEM7Vm=(4-I%Iz_ul<7Mtha?YiG7)DhxeEAH$%SYKGS&#P@mUgO@}et@ zrX#$QNGh12Agdn2I5E1V{|ScXArcKbx`?FFn<4kkG|$VT3uDZ+1z)SCBH~Q6eK81 z{x>4cf$OtD4`Y$_0gV9G945H;OlKrjg*e54_49sNE-X6Lu~y`ARG+sG&f2f)mESfd zIE%(uWiY^6nVQ_`hE>jZlMEsL#&U6l*bQ zH%ny;sQC92y{{{h#e>)Xh-N=1Zeod|-tFL=1QsY>ZRAT04&wI$NVW?Bhu{Li8O@lA zXQETCHX=NVoz=ng%~zyKX`g}iQ9FH&>EGTDcKYv|(Np$lRiEDj20NEV@-Dq1PS92M z^nM58Y#{Qto@VV<>b?0*tS&l@_G*vlnAQ3ZDZbsy-|RBHMR>mlKFL$t!kh0Qkl_9&oNQD(OKi$da zFNN2OCp3RoMpu!Hi4grwsWQjnyF&&8^c$mTcUK_oavXiIQ%P+_+E=p;tqvhR-hwja zH=E#+$z&rYyq13_xbroAj3(+kZ}m$9|GwyciErP^$`G8H{%x{S>i|``^G|$DP^m9$ z2Lca9-e-_naUmanChdU_(aCj z-_djpNU_+EU|ZDf@8PWDf+C`$)_Jboz8qobjk3Dbnw&$Nq_c;lm^1V ze)s#`R6zIa?xD*H>#!C1&zS#6BSD#FNLrjF)- z$y*Q|ob-#@khb*b56I=N;?RxPr0uW9E1c~peX>mc1!1v**85sCAdqQx*a!OD4H>th-nfH@bX{p7&zA$c)F>2&` zJr#pxuTmqF_;kbAa9Hk(OPzxg+z&bAM5l0Mqh{y;M(ju$5Z49{6u74vb$sLf(bR-S+cH_ zzePAeu}v)*1ijIY)W?fNUl{krkJHj-3C`gT_|8SOc|gpL6NzeCRISUdZ!;FM6z8=! zB&BI0X4&IuAmj`{Uh}HSzO08csukqkH|#9GinE`YlN!#GLVAfn@_lWOai;wO$>+)0 zetK!WwjSEp9kBOUznDjvW_!3&_C=ApDun3G_?(9}yNAs!pCgS2J6i$JoYx&@OgI^Q1u1k<4lR7vE03K z#Zsi(T!_`^L@wc!xceCX5SUjQJcOp1xy&412C+PE8ahjUTQlllm#w4Pn+NJWDNk(k z>f$0kInh*v(zd9HnlZop43t}B_Rcxc1@CN={Tp|gX^!1W-z-9}8*t6!gBUg2fhCWa z*24vq)@^A1KZX#qiLOgGJJru01oku_2CXi3`&a%55r}UIAypGS3oo8NO+~RyS!{}I z_w-@TC@ZK4vY=jYKUt?2O33*Q*Sjykep<3(eS>w#CqdmAD)%j>(-oXH^XVSMv^e(O z9euOc!f$xsJvcB1VcNn+xbsOFwQJ4x1o&5tpHYyX@6->n&he>s1CApO*2cH3&Tos8 zdio2#eBE~urZ_GHg&j5!kMBFMW3!T9IX-_M;&|beobMgv?I7PzlC^n3IDOQn<2#Sj zdTh}r>9C<2ol9Hut@A6Rw`ZEOA=F*Gu|1B()Zk6u3RV6}l0&R52p93hZQV)bgt@7S z{ImpURw)Vt=zfO`UDzExBI{8c8chcr6|L`tOd4mb3$_NEjf;$F6&20b-4!37N&6bgv5M3U|aavTmN-Z6oZ9oq4^`DT-1c`dF+bhKo$IQ^bpr?!qT zXA<7B?RCY0xUe_SY!~Dul7o!i*ng|EVF7j(3oQtg~TOK7_E_8HT)&VT+#f`oIw#yt= z_SuToVZMjuvQc`ogR#^CF5#eqjo!*x0ty1yoyR6*fql*}2NRRpt1Sow{ElcZp6>#& z5^)ps3Xa4!*N4wnLJH*Y_DW)}l41gCl;@=Q`Zx&U2=(PyBLocDq28{13&O9*&5qD~ zZBa2DLn68t8f$0JKqkew3)77gnG}{PJ#`F!wtmBWs^$urRsmz3qC8Cdbw@BErPh z@fJ@4E{f`#!8lFN@`AA8EQW_FU4fM^(y)SzyC_9nfgro3x%<9Vd*cOuBSC2V@4rVl zDStCTKpD0>ZFwc(oml@V`6Vq9(}C1cU_MsNp@Jd1w1_KYZ@#E0Z$TxK4kmkWSUE@FIrF`-() zRKMLyY%hRR`DQ%e?CP{n$H90gb8VmC>I3(mlXqF6_CyTRXkXn{A=i zJlwLi>;wcL%*p2X8rnwIuo1I(88XfqPrhsQptU>;nNrO#p0+FAvYhW;_D9ZSDt9f@p={W1?amnc7-{YbWwP*=0{S4T;$nx z67tknJG%@=s9{8T2XgMq|^!i_pzpeUY5> zN#k>_@NA2T!Z+nX#}T*X{$<~JK`afu_D$BO-u{{yQd4jkG59wI;#EmcooEg* zC#V0+|C);$F7=BxqYAEw>!IGHGJ4{OImrwy-U^Fsr8T`N+Y9{E>?3}Zzb3#vi4^Y4 z_g8DzVouO*e<5!LJ%?xuuDR7C^Iy}yrH#|Rf3kGw^d&$Jgw~d|96VMyXYlkr{LwSJ zf^B^h=&1vbF=8gsq$6x)Ow=4^A+4_73~8Lx={QI0TUzE2jCaTCVt1?Zj#?2NR2nf} zESIOt`u0ZpZInV0zkMe>$Inc-f9=5|S!hVsd1s-n z50KVVyY4j8Z1unxAhXLTtoMPJv}3Hj3e#fHhF3PB8r8txy*?z1Tlk9eo;n&UX6m1m zMcUDRn}ofdkuE7M-N$Qb0o(WoF0AvtN|~gQ{9HpN?f$Vd=}1!<|~3-yZXpZbVa{Sd4ZS1?}b3m<>wc) zFwB&k3q;sV47-;gFd zYlGM9!I?}5>COZ1=rsi082*Dg1Xf?_72#>@!5q`GgRFZKO?mDOPoZK-8B7{HHN2U>6qZ*D$L_jju# z=Q2}xtc?e?c$U*tBXCxBA_G0)SUGG&`WK2<1OhENhr?!w?p8?GCtTNiBjRvYbgenl z{BlE(q0bv=4JL#BLx({B?S1skQMQK#(>Mib-|&p%6dq4sDr~h;ny(-JXLDMJ4>hu4 z_1=lRZ$O)X3wUZA>x5d&FO;!^O)rjfo#?9_X@UJgjoIf#+*|6-?cD^9_lz!nFEGM| zBf->>2EDGp6LOUT$&Rm6UuH`TVcW8``}7dLG8NP9H4<(Pjn$3i7VYj}kG0>1TX&s~ zzP&jxtdE(l+;~2(O{)GVo7Jz`?3oz}!G4=ndzzt3%jKpajV5(8bdEeex;14o8$on? zpw#6Ba{wx#wb={dO}>HD8uT4n?V&en!J8XaEYUaguLg1PyadrWk~l}9dNea4*DZQ- zL?nVdEUfMfhiLj^O$YP9RYFlOc|@$5vcGeJ;(*mnM+Nfl-Ia3U9WO;nCWyrNA9#4Y zIgsGMdSoJ`Q+&NxZnp7|X=OC9LtKxvc>)2av}oZn-Yd#}QRdft7psbXoISjrx>TDs zP5QCLoRb*%#Lazle$*5FHN^ovF)jE*3rP!7N5mgDAWH`muL9e> zzBTMgNE8;Ug6}(iK)x)V+@-{tjpsM)D)VJ<_I$WWUaa)GkzS15XO!=469>w7*Ft&_ zL^F1pK?-9|cZrc{36!`ArYZ_^g92Bun&(?Rv+MiOltgxSl$0;-(~%Su6>RXBSf(= zA|H8Aa8g%;ZLhW zQCk96V@;E0(AMz~{~4;N5^PK&$csUW15a9dQX8&#=MNKLZxLsLEg9fO`wK5TZ}wPm z0H@RprR@*S9E0e$k}~c&$O@S#SVo}v8yR&i1pK~xIZFq99+g%0WmvXl#YjNp?f(_X zIo}39D0)P(fKJfhZfVsoAP%fu*=@E7KFyGPx%yiC?VF@Y2_a|fZ@n-Mf8dzU$9Y+o z&Y>DMqVr2$K+J*aM$ITI8@vFCCyR%sZ-7-m`f5NcrNl+x#qd|voX$@-YJ29sxRt(_ zO6G+KB9pLkA*290M>}Ag@!xkbSqZ8C(LCdZPS@=zi_TvC(}X&w0J30Vza(2)70wvu zM;|H|MojII(2UR};CO%tWOLeI#>D6l%ClJ8K-<=TkDIm@KA;PU{9}Ar%hG{>HHb>AHbOc`9E-f5Hvvdy~c_A zhxkHa{=y1VlEBx4*V5hWPscqy=C??sZVQ+hy*$`>wor#dJ>zFul9}Cr&~@h;iDRfP z2oST>v)i}t$`s93mxJCROtOy+_Plx^*v}b!ykO2m)$%|f7frFl`qhM9Ah*V%y~@SPw{tMxZY=3P?ES1bo~Sz?y;P+3=Egu59M zAIhLPXm-UWA5w<*O5|IW*&&c$V$B2v<&)A*RuC%S9L%JH5jG?`rO1f*Y^!b;O`zJ@ zof*7N8Rk?njQT_qqf;}<~9S7jk7ktivX5mHRS3p~>G zLOnJ+Z;zapx2HB4*YOCWPH#(ye!Fm@1%m^@%XK-2<-JMWyc)=)vDb?Kxqv zffM^f9DQJOR@}EK8iZM&G=C~`)>H&hSimJ$SF_FQsn3Day$kcz3Wb8veB z$w!*Ho*~^oJr`HQcaT66fkUASactCd7cL}JG{1kBTc{I+DLew@heABGf=V1r3KmRK z@rNPBZ}AE(NmBKP9#KN50NQi zn(|r7xrbvhUQPq0T!}NRT~}?OS@x!^m=~&*rQLQeCE-pM?pP2z|L~_5fG&U#t2#b* zd8a{k`GDR223>u=6~?{pw>p~O8QP5|1U0>x&VI)v>~N+IpY`9}?;O5dv^C=hE;wA9 z@U?p}s~UEQ*)BJjY~^@fkVjM;!P(&EMAzxUOn3Zk1I@BpEsgTlMJ@6ueq=eZEes^I zmfhW;>>nq^Z#Ub;ZtyJju%8cS!fQ^#=q4bwAl9G0ym#Yf>TMn9avOGG6YY$tWc~=; zQNLmmN9C6~2Ei8tjMDNHR zFxj<4Lh19H=ym*L{WCpVO>Fj;w+`F35@lkL9M$jLN8tS(a3}RgO|oLe0UDV=NBQXI z%5BD2OJ-j>`|XozImW0mj>?Wm$ReUG-{@QFL(gacneW z^18Lh4u~hOZPn-GYDqwDF_FQ~K$|-Pu91blA0>`fOxS2~S=@%m;Dg1wd&e_Bi<;hB+Q9q1(|M9mz;xcDRnsy~y{}Y1?M7u5 zaLqieF~fpx+WLH+Bh5d0h4A>sM7QN{_rE6<7T(byQGk*|cbwlzs@}O!9-F43`mB?o zs=9*zD6f~qIWIY&l7(l#GoT5EEs8I6U+&=a{~JKzLa1_)Rkl(!S()sL*~TrV3;!nivP?bPU^FrB` zjr^yBZnM@0+8qI->y-)3s~WeJ>pxYKXLi4$VEhS%`Np8vyOU}g)<-N}Gu8@On{EED|w!H4~QN|-1=xX}cC3FZ9{-d&6hgTYCL=vaz| zkckENi9WO_f-p=cq`{1$%5Tw7T16{!B#q zl4*>~>&-WHLyY}IL|w11Xpg9mjS7qG-)Xl8H+Lz~Vz2FB9nlz@zYR4E`eTKrgdFf) zPVv>fip=;CC+F?p&74z+AS{$BVfbljYL--10-OUD@0XuHTW?=IcCP!WdoX{!1RK?2 z0i+7bJ3v_>hs=AE?G7JtVOqjRI}#K zk5_6cs&0MGEIY{6cq4$2G=5=O7X!LS-ED{Do{eQRshYhkFy7Is-*3i%}XU#X`FE0yQ zJS{9Nygy^#sL!UzPGX;hv8Bxrb65tmw$Ta7t&Dp+t6!d~Ey%vC-ZlSV<9)iheEu$m zw32;r`q>=M$Ii2#I7<})xz$}=(($6#d>l{nr22yV;`$LR7=FYDK|~t=GbBC(72{#& z9H*cSJ0su6oXVnbH6HwemU$gSY|DfHS>Un$C#N6`mSyK`-nH$1rc;?d+oJDDJ?(oF zZi=f{YEZ>=-u#z1>>Jx%*sk_eUuEUFEKOcq!u_yKUU`*+$~^`;;`fXPnsz%06!r5I z!}G6@HgG{b4!toSieJ1V@s>NleE(+3xE7S<^{Oj9_(ai;CL|}{c7q}6Gh(@YJRdH% zI-k1RI6XnDCy^U#5Zue>PwO+M+P7${S0*_;em-1m2Fk~GGg?s;im^zSRp)gY`GJj} zn`ubnGbU>heBfk1?a);Wu^9eQXT-paw_@B4a;7ak!Y9uf-?%|4?ekEumct&Mbf|%f{hJ=ZYoN~ z1-_A{k5@^bj}g$9j*w&TTk(pInb~&rP4PMNe)B1#DJe2k$+)m@C^|t7Qy?vSdpHVU zHmvjT@a8OUIk-pG1@HD?;|cM}xqrQM;UnlBzZL!90$L}(iP0Dm5=;ft$4y~iV5Te^ z0IO;yMn?OMRb{{`kxGOJiHty?K^}`JRs!W;b!7DP4mvZFv2^~x)W|s}vfNx9^={Wt zFI{=4*Lc)jA6+SK)0{#6hi;fF+!PbrKIX@9PVobIU zh$>cG_Hv9j=A(OI*N!jxh4$BY-#RL---o+yB9m>*AyCLh4;}71MyXg3^w!v|KPb2t zJ~J4sW&DZ*r_S1%tv7z&+;QI}Sz~y=K|Jt&a9cH19NL5k&0q?ty;I}4j2OQoNp*UcfuSGa!lb}}X4Icd7ptB7RooT4VxyCS-3pVx4HcFlD7nwdOvil}hF^b7 zxkrix>Q)o-fRsBxE&Q0ZB+BKcaw5M5 zkJqm@6cZ=Kxg zaAh1+c|0sfwyl{wI2k>x zuVBW7_3M%OsC#WOeAQcOE)G3t#{Tgj#Q$?w+jMVHDZMW16Bi&FEIFwOi)^$eAV9@9)$x%F$0UHK{tySdMKaZPl?-<+9 zWLPm|qGWEu;zj1jq-ckSqxr520!Y$+iY3;8;6Z%_k_(gZG&VpMr&_5g>hAvRZl|V* z2CxJH3}N?M^|blG83Tj@D$|a5<4i%N=|so;n$x5;b9807=bf(ZO+&4#Zwh#E#3}m% z#4gfi->ATc9fGOuXaIx2M3)Tw_tosD!|264inxgSlX%_J9Na~1Flo@js;EGt1RC0k zt((^ahi7W5I;xcVG>b38kHf1$CWskY^)ZkPG`}hETS=AnvEAv4=*l1bC?C)BIz>TV)T}BdVJu)zmbTYB5=8+o8Rjt8VPDMXfb|51W zv`x?~Fbqe_`*pT@Np!|32?@w-OzGvm&vSJ%p$a8WxG^7Ms1Kg58*=~%W2gim?I`Qf zC!(`)jOOE+yTc>JL)d+MRUBk`2_qXeHZd_|mR-B!?b?izfnRdOZ1sq(Ekh-Qbhh|WDwf_m(;I~)WUeKO7by!#}; zcWpnU-&2kUj3flKrDVsAT7G8j|MS2wKtcX51?+!6HGL^rg)y@v5YG)#X-ALlU!=b| z>-<}=H~Lf%JeXjBXiJ6!l~tqt-;AbBXK=HW&y^3aveIZa8)4_=sbg%SX=fq&HowO- z?P2crMq07#(*k`T0k!eAB=jHit)-9_gpki8L7#Cbf%*si(1TDe5+F4Q>Z3$ZCLU#m z2n3B36Dyv@N9>Lx%UwL3yf}8N3GRHkZ+{*jzJskMAGPg2Cpe^za62klpGX`0(k$Q! z?*1PNZ+kWH)r)g;Q%g&L!v)*K-Y+Z376KF;cR~j9f)ng+BPKKJE%fW`Kt_7g8$v^cPufT{|R{Q?UB+#~HTiL*k}MdZfIXhpAGuMyWX zin-NjL?SP=%PfJbsj|<#(#Q~VK8xje-0Z_>`A@*@_EWm?;Ul$L=TSIo+3mNgCfA?q zMK7bCFZ5b9e&DbKd$?U2-Jl?G-yzd|-cdgux;FPYx}Fg`ZxX8kW!h%E6Bz)vYHL$_ ze$lNnhW6;lYOq?o86u6gKdo$1Qc`l%U7b7r35*iauDWANPXx~T%g5Q}WoH-M%XRs9 zdExSH7=CqaNyXv5xkgpPZ{N1VSkdRmLe&Eb@|anDM%zZw3Ik47&y2zE?)Y)`i#C1y z)02~OZ9O6~d0e(VkD_@Sm|?X}J+cIp`zAjoCm#9LWHG);)upcMV(a~-^LlJ^-L>bO zIK=}HXDC!*fPgo9Y&?;{1wxoKB0R>km>fe|G{nxpDEm zgS{Qd~AlZ)|EE7@F4h% z>8AqjY_O&Wu}oPn85vaKqz%P$)vzt?0WFJ@1zYV1x&UC_2IR!W#l`jJ(o5reDPY@wtvTSklGIu9K0j79Zv(r$-TSQcrefLXB!%0K@YEfgZ zaa#b2@ONpxhOoFiqqF7MOmBG#fEZvpHkkPt`=SVl>Vv+#vWMjpXhITigV@KV$I5E@ z!yfUyzRMW*P(0Wz4GbJ;JAN7vhz2&a->zv{pQ_c2Q+Io}>oa7gHw1ah6=CWLm!kg} zj9(`07ot1!+>W+hT9dp5#`oYSG)r9#h4X%la4aCw6qvO>a&4f zn_A+&SgijTja>ruX}2|3X_hy!|B!hIndLfN{iW}xz}ZXmfDBuiVl7s2yj{P(LS7I? zUS7QyWw+k{wmbT8Gt=j5xc<_0dt$SAHO*Xupw|+Xtng_1arIXq&u9B^&3Uq+f;Pyw znQ$^(Z@WjpW>3}|hb64KK&JSM;EQG}78V?`ShUz7Q4=j#Ilb7ETb_2x!i#Demz2C7 zB3K}|Chkj$25X>+tBj~s6vo@7X{MzYrqytxsVlvgN^O_C_g$*hT=KI z_X*N;EX84C6%VF6u;1|7Au-wH`R)>e(rBtSv15Cm_H8fud0HGZ-pP8tN^fm~M~aUP z5<|hg@!0x8W(GfMcNJ$Qu*oXs!W5~VC3_TR7( z>#*nsSSuOR8{4+za-YwynULuvryX&18CW%e0s?o=KA$@-E{YN!6Zmg#w`wiihm5P) zA1u*cpV8K`I7>b{xVNQ$%K@GNo$+WH=$$;~^*|HPaLXBt?d!}>7{s^CkWSbi=h2F@ z&Do1C{#<+^T0ZTm40@TuDiq%Z{5LqBd>6e#yWCzZ#Q{wT9~GF4x)*A&+#dRC1U zso%2qY!Gz{LcMxeEO&;srlgDJ+o+cnxUG!hoh^^eTG^Uhl+nV`HOz^V;}lKo2)6(@ z6GuHge#bqYMa0aK&QJi}R8+f+%rO>BnL76_Q`To-dQ8D~JjZx{B!Q&v5WWB{g=vkE zvmotO{(y)%=!smh>Aj!7d%If%e|q4jMY-L%(IO*vf$%y+&}0=r5sCQm*YZ7 z2gO3Y>Eu5=!P6%7CM*6rmEJYh-BarAo-(XX!I3F`JE*-8mZoOuer5R}&>vh0WPR)q zJGjczNA)RGy*$$M8e>+i}5lgDx{ki%hEC z?{e8bXtl6!!bIs|T=TTL4qWpC7_EOGYd=4Tz}}^=aw%6f{#GT|rMzaM(`Kr5qp_jt z3=JMMZ3;4geZ@XH&#l%o+(@v*DDqD$+&YTG`ja7S>ko8##ekwgSC@byKJ;%mre4fB zcBEK^>Zk@h8?__~Mf@>qkDlnv5mQo?v8p6SFl7_0*@V8X2~@q9Aai2vUZ)CcheHe) zz7I*7_F6r|ZYScsl48uS^^{-rjtGnE-hOJUXspoSp2J_tlKNXrPjOtt0)k{%G?;yf z7wKvKMtxBq&aU?h+WBtv#qiM0ks|SHsCq=sX7uM%9b8y4?QWe_GE<+AqdPwL4+Iul zFF)*YyQ?)CyLwY;79Y`IeU5Zp`+x1mxj-5D3C)@LtU7T?x(l3`qvX}*AVbyWIY6_!JmB$#UB3q1VIMPWKwS^0HUExbe{8-nTurKFDjVPb{;X<_o8N4` z2@)OC0O}R3@ls==K#lUtyrKV;9G;=%g3-2r$SP(fM1F_7aN*U&rF(;y3plft3xJdL zZMnyW5Wb4UO$iEu8%R>PA7pgYqe7!fi(CV;Mhj!H zu92`*r*&rKmh{iJi)anV{yvuxfh%HLRuhL!S|08#FEK{o$qZYK0V%9y!;-aXg(~dw zvc^9tDnfNWC#Jy1`s^#$Ne5>6sOSZH`p&ONS$iT-Ay{anxO8m^A^Kt2i+6HuqF^#I zB%(+R!|o-0#&P}KjW%EqYsJRtvA3`95Q=S`iFFL!!L10Q`_F|omNxO%i?NAzmLp$R zgK!oo;i~$$2U%aUhn3^E}&=zqQj826>#`f5pIxqA~c(7s99p(JO@-;VCXzn$(k zjM26v8ULClEF*$?|Fw?e?d{|b`AVvNKteKo5Uqa@(q+6p2&t~O`RGqrpo6z&np;er zlu`oqr&VYG2xA?C2o75{n33feudM=CiG=hf`yT_St?dj+Xn8v}33A@)92@0%RXt$$ zubhqNs2?6s+Mqc*&L1yxEMAY3xE8bK3YM(qb5dwS9Y)yn9;yG%*58m;+c!l~{VA-$ zZJoXehzng4qpL~RmmjY8Ffx*}RH^*Iby#dTDtNmWX@eJC-rcL|{0FGgDKYDTwl{nt z>SN|F5F;9!+j^gwkvml)36i>KS^|4^h^teZM?Ii${MaQ?Lu1wh>#T|J@&Y}xgt$|M zDc3H+)KOm>zWg2|*KL5@eBp3Enkr8L5w(i3zrdDLW28#@3TaD3mCsh$*;4 zg8%)EmIu*+%BN{WA8*@*U;Xa9a9)}>0Nz2G5r^&ljvhfXO56vfPvkyRIkx2D#k1_k zUmH|Ci7P1>fSsu-==C9S;MEZDcq&*ZOYXX3zDEGgqhr8$z0|BRkxReymIZ<2%z|6q10VjU=u7z;awh8cIbDB7( z#elW20D~`jZ4bI?^Ek4#%vpye#y+Ah_A=tC?ljqsTD&y$s=#JimOzp_xOV&J|HYjd zRZ>DlLPAobS*c#R06T%{K#feNzg-86qTt40(Dj-)KNwFRtTP$y^h3!k3Hil0>UJ$~ zxr_MPa{(zqX14;rcDopoic-3F>nno%bz6!2OO3roI;#Z=U~j>7=psDZXGEO)q-pD0 z6l0}5sMT%GsGc7x|HDur>{vA5%7o(I$HRaB*5Bz571oIWEtyK)m7tFzbuS4gf$Aj} z2SQl{K@ts0w)^Gwqwh$ zR@z={z;@+>uzHc_2yYQ6sgijBjAd|FuzVh{Gyx1s`WQff2ER3XEyzZp1n{O(sR9*R zP@e%eH}|hr3E&U(pz^0BL`1$KBO|NRVpy}U)=1^deImGVs#tO&YqWh8e5&KV?p%EQ z44Lh)fBN$uq+y$x1n`&y%1pTb(e)ZY{f`V+_&eE7a|D%&WnNsk#jR!y$FGo9PB0h< zS-`<*#^*Rm5g4be##zuCr|@;7F_(Vi&{7>7@G0}stb+*_nihyWbflD&x?52HQkRrt zS0e4iKCLmm`!) z+q?6Zjw{L!r+!h40eBxqXvqUsYKDdw%N2TZH&TkJghggV; z3%Q3ggcwg7=xYf0*3R`2L3`C&8)3w-C$|}Kgc`hTvRvik7&J^xL;w(yP61w>LP<%9 zfPCNqRWxu+#l~WqF|h-N9ZpW87NF|63P8I^fhxhA^(6iv=H5gV`>vf?kM5plWBWPV zhLpR`FMV*3ske-1YF6UCNbPA{OL6TXkViwGhDh{$a8YNx6_da~=LIp9ojES3Z}n;X zle5LilAT2kuA7+QPxbcvAYyI`dmt_Z%)b%Sy){h6?{&Z+BE#pKeM}o)-Rj4PW7fWH zM!;XMwUxW9-0H>G((3f+>S;68|)=ciPHeN|yj9~!4Nwn4vVv&IGBekAMdGZa=f zhIKgm6@$8tL$-VEVH71q9)=m7ik6lB!*}rDG+=?pb=n&O4300jY+H{hBE)vV&o8a1 z<4iOFSCXu`85Jrt;Nb4v?m1AkHT$eGvSxUUbvak=oxB|2qYKNDAyt(WGOAPTD_I#>9Z~FmVFd7posi0X0!L0rtxKT{8^vzIH#-98 zm`$%0LjUYeLrD15|+03G@j>H%+e3X;&Fgeo(kVp%(VE^5vF>v@g46$7AQ-)A>&x}BR- z1~wrkM6pk|8`AMSJTp#wGCeDL(4I^xq}oGi@=O(O zN-bwNM5w6F=ybwl{{FWK`g&tF#^dAS)SK;zRRE)^n_)@-8$B+!lmeiDFnheI2m z*}5E1x4?iyLqn61^&{4pK$&lKXTdanc*0*Ue#R!Fp$riRY+Ff44&`Q$h!Jkuj*q50 z9PbQe>3n}49W6<9M->ZfD*eC#rbjqRL9 zuS*#eV2}PS+xfe-G`TIi>gH6MejL3%0_9TcslgSZm7n@HWmrcZI(gG5j1-j1WDNQQ zjGh7*Z;5MYhrv?0i+h%^o=LZOJ<%2eaeC7}%1Ylkgc zxjHx@^0G#ib)?Z@J6C7cF;0g(VTl1Hd>C-lM4Jwpl>b}yf4BhaW-AmjoLf2dmXzbr zI%LnrTR}wlM|t%dk+Ydn+lxi9{l&geA62TY(N$*4G^JDrvIS&xIPanrC*ac}sHwVR z&0L^6&N!@5^xUVXCDn*KhEsje;DXH}a6rOeSy@) zv0z8op&KohkG(ZZ1e%>07Ma;ECqY5V@KI2;mlD9F{-9EKo9TP&KiPNlOSuX^R#KxC zy@Mfg44Q+{;@Gj#PPQjUS%;hBMmh{pO$)U_i)Km|-@mH?SKOOs<19iRHE~Mr)<000 zkXNc)$lsc2dj6uDaP`q0%6xz61%HmcVLD$GRq5&I3UVS2p5@n20gCCG7b1C_$R!s$qkBX=?(F>Uh4O> z)sz$r+BbAd8>qrLnfs^?Wx{1?9W}^RRa?rJ5hav6msSXFu_^yaUBIRkA;I4x!BMUz?nf%9K#dNzj7}Lb}TOv&4 z!5h!kAI)=(4;{anv)pC=urm={3x{H_3|*1hhODGM+-Jr!f7~uPQx9GTkQJn=DYZ7KTGgnrIb zOF#kE44Ycenu)CzL9tmRdeboTJglVJ*_3%RK(FirYk4nGHR9$+Q;#BXrL5TYEUfz? z3<*1WFjMQmBRFiTeb;EoqCj&d~evJWm!lrJt81|!3I}yp`e;QsXhlMIg@UY z)O?JXZhzpK>wWUrev%t!XW^Y!c&*#8UTzM>&ZTNw%ou&en}=NLx`VdFd<*xiq9*Uy zRpDQ0_AmaZ&Afh;6Egc!l9PK26%y?eBA%ryB)1#h{x%8L{#>jk`99i2om4P;T6@dn z)4YS~1ql4{nExf zF<4}tlKGP1QK3x9@$7Fso{=tXSq^4YC#>EpZg_R(Alj{u#{=(V(g1yXmN}Fwm>`I{JGctZ$KU+Lt{}mepK0pq_>tVU7@NA8C}Jn2R+T_0MDUDghJ zi^7wZL4lc{y&^M@Z#0z#Vw{J9lEUgsTx!blYYiI>(;2zUx}fE+yx`c!j}v4e`poa! z;g{R|s-h}p5a5n}_9bamwhXq>D8f5bVzeFsly6LA;#%FFhR@_^Qs8j~NBHB_Z~^VF zXM;y!Ce?mq`sylWwP1WRA|BWs%R=gyp zGufrIUUCW*u>p@y))`%TV>3jsOsGx%mJ>b^Y>E5h8FKvcl)1F^xbiZ$hBWRZ3d8~v z1W&v!t9ec1js~`XCt%49(*9=y8z(fZRMCP6m@>t0j#P?BX!)s#1(l%)-dl~XQ}U#9 zH=KqAzl9X3W%Vw(UpM$w>b*i-=Q^1V5g>O0mZC<$1i%txIJ7rLru}`h-g(8`G7;9f zKry3KtOC~u+3S}bH4X=;M)TWH7A~&#dwuH;m82pn(#sW2oz#?b?(Lbr-l?^r3JYcQ zWg=Gt=eMN3qB}Q9zr3#1&oMc|z=Fz2(%yQocS26M5WHwQ^gLS=qc4)C^_GIU#81Dp z?xv41#wL#mA`$#x6Te3f!*pmWyhhPICdmpk5Dqpe-l>X355$NK-#c1(o{KyX{p{bE zjch83Qniw1($y60X%WB9yu~)llPCxyC#{J(c{yiWa{SGL6>9*7>I=Dj3oM11jDOKX zn?DX3Vt=A{x?eiwk-?HrwO`n~oGtfMzW*qck)mWUq+I8+=Lyh{i(L;XwzZq81kWD` zrJ>233mp$^XW+|1F+YPi|Dv)0VQ-97NvCupLosniX6&12_W6P^obNlL%Ke+{q`p|i zUX&s#e~WAK#>uq* z&i`vmK->|Ui=M~H4VH(u#QA{r;Q&_0U@GTqN&57_>}jBjlZiqw>h7$rU0t!5_y&KF zYgexgvwCr{>yr4G3UK%{MH*|iM67wr_o89qP_kN+094F=ZQDtVA}2>u(^ zYO4Ec7}v3T#@RC~-(@IAw1$hLe;CZRD}6T;7%FC$)_i>fv+-O3nda6YORX>77@r@I zyy?2ekY)Ucr;irwW8p>%B9Cf^sLqf;Qjn@eO=iz3vuVlFmFJrn!Dg>@VvnDJr_yo| z2d~+|{<1F!OfuUO zdYQ4a=R^Y2ZZ#gtZlCF7wTZ=B92HfKyk|!H`5?(tv$0Al#9E=3n;q{g7 zT^TX#*K|Y&LqM^S)zhhwEXIZ>0lE7R4~_@Z{j`UtialLR%|3{27Qjr034)AlSo9`= zyI=cjHMSg5cN|CJpI+LQkMw73BcOXk^|L98TaA-0mVjwf*oVNDLDk07IEtrZ*& z5itEqUWb5fL}MWYX{^N589GPBYWWQ{e)3Pyqfv?d^f4Gy{9IWD*+*(tjQq8Yci!a$4%`Qqo0&{^mo`L@)3l;*UfFu6Xo zc$qM9FwG$2F%n-b1SRXQYKb_qDkMgS1!(Cg{)*_LshYh{Ek0<@xXijzC<5RmB_&b| zmJOn!q6p5Kfvo?bfp=5u>#|MjK@5!;Qrvvv?zWnrB=oY*;69bJcqtsGT23#ZAuM`m z#_rIkKA*U}jX{#0dx{5SQb&yOIDA6t@DHW;*6Xc7?=w!~(F{fhL&~fZFuhY(4axcH z&%Z-MyDfo+q6MvU`tI=O*T!9>|2O^O(XSao#3;nr2xtgUu#l6i6|>|v>nDk4ORX;5 zlcZmbuz4*G$cg-fqM0fDkLFO+#+Su^=y?c7QLH?44&S&M+!6f#V;r_ctHUF_t?>EI zhynw!hk{i>lG4)Bj5U)OE!AkYckFpG0Vw6ng%>F~`DyK#YQE3NqQH*JY2q?d$(_5M zJT|tkV>XhkV5b(YyTb$-JxNIEj^e(#eS{Ig?B`%(4h&EAvUSS1DIMmhnCuqYoC*k_ ze5!NrzTXTanQPLD7tZ~r)EXN+J)13TpL#c&rEDu+KYH6poS9T1i^A|lJOH&qSjyO# z3^N=u{4YznRyPeukg$Ey7yrQAKhx$4W%I@JmMS#!CLZxXcqo@I0AVzgK5i7Ll>zg? zJ{l0@>@;9u4%2HQ3Ou+1>woP3vD)iJ`5)F*@c(%5F+nhdNF@aTe%i1>a&l_ZO>$S& zDZCV;fxiS2;J(C>Wn}^%t~3@F60GHGk3-J1T!PqApbA_(?K^kLzVigkx#fyPie`TV zZl4P9x$qJ+$g$y2FWu3w!NI)hy0xZp9Wcemp!km$3&9TMf>b8;InnGe=DA6iz_ZeO0HI$|j5+nG52C&EVN0`g$N&p?y4ZmXPEBdtMWCPdP6l}0?2eLq) zd8;1)h-N5I$(X6rLU`p6au}Sj^%a^Tg#;ueshzpJN_DBzBm(#n;O01G&W5#wR+)bj zugd57XgTx4JL)fK{xI9GA|KASSd={_TK(^3)U zOT(Y9dX%o#KB33I)eK93jU+#hJAd}!eY?!>GancSGEy13lBJ69`7sctmRqCO$k1Vb zAJ&XbVwJa*K__ZO4jbd1H_4W1DcH6z- zwSoYSJnH!$5WX#6?NUO&4vAw$AJ|6lFCRcH~xSp)lO1e9EwKcb8XZ8 zGgIs9XSM&Azxq>t-k+9@XB!iJ$aIJD$a*3>Qq*BDO2H$^UcyMfM`g)&UWgSaF*_c}+`Yh`Dj^2R`F_H8z{>&zDtx3tsR})y3Y1Fv^|7tQA*z7%?sOIwF7<)%W=R_LyUris{0!QWGzyc5x0U!nx zK*lXBjv*O;7pu@rTQ&fgTAd5~t5?Tmm`JW8Bh=KSuE^gSLL?V*WtK{e)i&S!TU{eUdAUcyE8(vtnK>6}_D$NF(5!hb!i>531I6g+%HUKg4D=oiA=iqyLbv zj+P6RJS!Ca$eN7?eBZax*#GpY0N&ou3r(Ft)8@ti@NB)-eEsWTk#qk@XZ6U5Coeyr zIW^*Nty6xrXZ^1D*O4^*(9{vOpas&G$n^yE?DiZl86j$tWaQTi-9JSDppIDoi5*tu z8I%2SklgMyFX!X+4k)2$^UJLXr7xcOZQ1Fv9#-ZvwdI;|SDRTFt9iTiVrtxy$elc^ha(s5waG|9~^U0W5sm)pp}Jw7RY zs}I#XQP2u+7X}pMG^j?u0m@}?HVI-k;OOf0c0K6EM@S)`C1YT)4SC6mk2Jf!9`IiX zShgc@Ba>pn<{Cu;pK3|(AkZXB*uPzmLnt2;(6%^qB&G>vh!ly^PX+NeZODjV6(I!=v<7&&|I;EaS>mYshQR9=1q5knQ1 zF|1JoYR13}s2RW}R=df@WHO5%Lp2vT7z3x(NB)kSdyMk_ggjcS7FLdSFQZ_HG!2n|*0{zj_ldiTL3Ic! zoEjUZaTIc+0VqW&TG25!geOp^xs{;Em>sX2)l8Z6jPmHX@FIms*%AZOC}r#0U`!v% zQC>}BBtud1?5nNZM4^k+_#o2V)bz=~zB+m;;cwyJQ;*z8QTGJff=NXR~V@Y)LnF89w*d9hgh+XC$#uav#f8{72#2M zKlTU8jg>&}hEp7|uDbbYn?3gdH9tAa^B>TSXPNhfbq#dAgT?TX6w-T>-tUF_18AMM zkDJ$tPLQ>O{@%?{Ta69nZf_PoKoBlI&v~E9SM=nowsF8(CNFWR=RC%nmhjNF%RLS& z-H`etTK)NaoHRAVJ+?0R{>tcQM=>w5{%;O+^EOoEYB*!R_ zZ|VxFtLqT??R7U`F54v{zODrE&W)RFWubQG`e%8W+}6TkXV0Ht&Zl?&5Cyr+iF?8H z$&|_3N%&U6UrbIwZOCVE#WEWW=+tlFp`!Y0RRDt|BoE72AQ?)ZDQDgiYDqYHgX7mJ z;U{te>~xV}ru4H++i4rdcvnykiOf)%tixQ9HZ>wD8RG}LZ(4zbt%{LaFf{?uSBilM z99XIE~n6R#-mOb%(6v%l9P$5`Am3#s1^8TP07&MC~c<0_5OETHJ`mH%W(Fd|T z7j>CpMsx>@;)Zxxm;ygI+8akXa?s;a-(2Y&_uT`^~b4s9^NUN#MKHPPuK14*!`Z zDN$d)-UCfYD6%+-3^sn)Ehz*95-!m{WlcG~(>r1*4)~pTYx$#)8#zqQcrd#umUU-d z*{3i4)lmm6^^oq|&ZOU1n#^{MYv9Jhihin)lDavv>+KBXC#OuW9GV)wo5zUz<7ZNB z{-7*n$sa6v<8A)<;T&DRGGq&!e@mdmU%Z0(G>RR=hat)n)+21DrAQeJ;agoRGuvdgX>XufrPuU(Qx zHYqnA5|)k>X82137tEu{r{wu`*@~UwfTfmQ;7j$8I+2-J{0ARyFp{@q|0vRCaCW-4 zHW_K^s#`{BI=?6}*n9P9tE6ce@rhdhto?W_OPfS$Vs1^}mc`DOi`yol2f+<2@?R^GsD zFRdxfXVGp5^}80stz@7Cv2o6R@(1???xT=&CEHC3adb2UF?jkdjo~8HE%>z9NQy z%pj#?%W#2CD16?)yWDk5uXcVqkYLh3+Z=nZ?F7M!_5=X`=K7zdoJ%V+VNG;k!)3io zwXv$ByVtp<+jA;k-x#!9y2b`qqwMQN#LbZOZ8Zm_%g~-*zCb1n3^!XM*W4G#;$H_& zj}SLJ=;q`5FtH$&m8IR>Yd`;4k(rBBhJg?X+}}9GgnNi;G3Q%lRvBj_&>0Q$wWhQ( zr1>ru#rU9Rc~w;twe$=vPqu zp%c?z&s_(+i(eElHTp^ui5w@xkV{&qQ_bUF>MN(d?SfkB!mW@NF)@$?)VGh*m8CDH z%hK=GW$^Oq%Bte8G@Sm4;NkxQ%{_G@?E9Au&Drv;^$36xRet;<3%E!;>fh;fnVk;Usg2ZQ1dF_76v{9o1Lr(I~-10!9nO=U!7RiC0 zH@%*$%^&w$!RDLK4GPW`afgIo52Z94?y7_Lc)mRmDtIsNqtAAua#_oBeu9FnT@h%e z2nVq`_q%`3xE)~r*5j<%eX6kVmbrgg4^n~ZApKduq+9IlZz>#!XS6kZw<5~A%Pi$L z^QL`zsz916aD1Ac#AN1JlD#d>z7?D&m{V~L03_sCfSJ5OsA{$E`YRpY>(g+)GwIFm z)H{MC0Z-C=!?6@DVOd9TUUe*%i!3(7ygLnLab=xd!v%D_<;U>jjOQfo*t-O;u$vrL zu4k7A+r}Kp(cF4ssDcgYnY{Fr=V*DD1a)OOI!y?FORW`Mr&SWhmV_DY>^*)>VG^k+ zSd?f*!R#vfk+1Ah$OIf?xU4Pv&h?PL+_vgL)?Dm3T~ygxcbDg8D95+et=gE?7KH}P zaNuiFU9+F@Ciy8dy)NP^4F}Y_{%-oV#W)28h7qVFzgqAlOwK{aO<8ucy<1Y0Ylb-7 z`ZTh3`W}zAPybEO;m;(Kg&FDW?N#h5{Jtn9txYNLP-8z&C(cM^>QwWEjHq>HdW`#p zlc%gQ*TsnrYAsNBevTc&e(;;uwJ;_Y;}(yma7j$JedCMM&TZB%wgnt9VTCCY`lyqr z7#Km(MUhv`{m;C%qWB~Z1&S3(tvl_kxB_^cS``#1`G2Q6GRN*a^W!68Z>d}4;YUN_ zyl%_d+xy>$YFuVX5SAgAjLcK_i;LxUYlU1@4|`W>w_l`^HVDio5mxS!9iOLNMI%EF zi0R3dyYtSIH=z^=To&B;!%t^)H!GyrINYh1e2x)<@4KIFM~pw4RZSyMNn4JmLsHYN zNK0(HsJQNb(AyWbtOg7fx`8vn2?p! zlyGK}8M$_Z^H516Q@Txf8e^%=5O!I{xbUgZ8uY18;p`B28_{4HsXQ3?Y|XaX;d<3) zicVM9<&LsXa`ersTU3{2s*I?5Yff6!bI%qW_YBsvQ2E9I@AC$ZIYw9Tw1cFG8pw(U z@c0ai5PC~?M^WU`C=fh(76ytGDjYY+xQ9l{i^qcT8`oa{2C6vT%Jtd*asiIPrwl?TO#9Es z*T!Jd_lC&Pm2qlo> zDfOXZ`AS2vcqJ89hPnZX80lythb=CZAZWj3Ii}EcMJLv@TSzn^>D%19lp?t)!ZgGv zFVf(Wh*+3C-gJ`sQ>Pm*3hc-Ap2qcPi_^73ANj!Td^s9YSl}dN4Tsyu&}&Q1d9!3I zGI3xJeOq6s*<;xJm&1{!Z<3MS9(VWK`OcrZDP`Fjsc5OmsZ%POQ&;O`QanbM-N$6> z@I}H3F2$#0y`@PPPFzA+g+|p}8vkyMOBs0mf@}~>-&r$pa;l$MJ0TrB>)v!q$?Sok zz(vsTZkQvy=par*n)hDdiGykOBw*E7&p?bw^By+qAj{2&T4(F6@6){CrfL1Q z#}1`2N+SN?(K0*V`+~>JnI>1C=Thq{j6AzMg|GDr$fckBAE+Cuw2Q;3PH(STYyRbU zgz7_+tc`e)>o0XfQPZSEFENzaE_UaLv#A;}fem%Rl~9nsOB9!6(r(}Kxk=Ksrgd1t zSmh@Q)!2|q3L{B*U1xn%H+8NiCpa7!)W=HmuIC&0K9gNrUIxRlQ`3aCerJs|inQO) zXnjBIH!ArtOxs3oX;i4p!|?Hh|Hu$Uur7U=)}T`m5x`Hoj6adf#hi|xjuT0m3>&`s z{F?jIIzc5RuI+e5Tk5>Ogl;&JoLb{=6n)wAxVAy>3b(Q5-O*{9g}u4dWW+#@QXUs` zNyHzJNSyo)5i`q^mIXOF@^0gv-6zPbKor4m%lpv%n(Wa1KJY0n*D-XS4Blaf!2OC6kCg8a%Zx)d$&HmPASDh9! zmQm_xjS@q(#Q)EA!hzu6?B~Y7LK?`z7gwh1womEpZ-dx-E%N-@-t1@z-pOrE412$Q z`35qwL9oAdMrBt%L2*t9{?HS8%8&w(kyBr&z#Q$soq@snCqLITAo4i@r^jj+66 zl&C)hs)IbP`3@tGEe8;+cAc5ad?4YLc1TjNqDnQQ$LTg7*#NiqngBww?r$<4G}EXQ zGBhwDU|e{}GgJG6zzr;KMl?n%CRD6Kl)!1{taf$@`)eyP>g~6#(+ZgFoa87Y0xI-8 zrWAxDIUZPsR=ifbrH&_SgLs{rbwUeu!@tJ-2h>hq2y=eBzc~MVZMP4=wQvBTy@C znay(ijNiJ~BRg8+Rv2J{a~}zO*`&M|AOBbp2EYnFv|4KMiUcA|lkJNd^#WlRgV=X1 zk68tsgOgrXH|2-aZ6- z8WjE&9|;`>n8kXTH)sI?Qwmted9Z*Y7R*dD{23y53i5Fr4*Y~5L(OiU4K3eM>QzP> z4Yv1h(X{#0spl*_9s*RvKwSY+=UZ_O=k=?;ZD21JEigs_<}pwKeGD+`zMt5hP%06P`}0w0-nK3 z24u80V)eWbAi+;e$hH5dg6TdSK6lx5XaOc-&FeOKd3pas+YXJ2LTYVoJ-WCUFlR%W zRGbQ^@qTpyvKCp7{$9L_t1T`rX3sgqo49N6_xv}mF=H+UdAn%4to8l$QBqb;<#lC% z>T98d3+^)jhEo9f{Oi-dP^Mn$30%L9AB?9975VM$8G(Ti1Ce+VUS4lGF8D|xHLK@O z?;nn~bpJM~$6|IagA4(7wpzb=Pv5CHAfzwjZ7-e4f?a37LQZAwYre z+a|_G3comH%(df^k(ZB7>7s+_%?au=xVgOrbozakplQm8mKaVdDi|gvCR7-3G&D3& z4OD)>^zhyTI8MO}YgWYw8v^uJw6YSZP%{GjGPNpF zWGKc=Zu_8mVw9_{Hud9OXYd4^5s1m;$Yl(5BT>9u!?6$2)KKwOP6COX8nv`GFmV88%yoPfweAe!^va;u0D4tO9Hq^@cF<1@YsnGa(f%YFGODUza*Idj}YL0hl7WSu+k_DrQZMt+n@FI%hy>C zxo8C=qSmIku~1)D7;h96kpjBngS8k_#ze_9xGkc-O$F7h$~h{h6t}wp7_HfpNE|5T zPYJx^Bl~SAkL-}2WX69{E#~t(u$^0qjl1RLMd%r1ib>Hzxfl0-hdWe4k(`kpT@)6M zM03;Qo|3zNKx`ZT<1=J7veSLuzk3ywN7T;xn6kW|5M7OB+2Hc&*|i80ntKIo`o6+u zd6^RI7x`?|Me~nl?RIkeZuN0M2k4Q%iu&mDN_Y9wkycd_PA_ z0Lh+kQp;6I4;`&Vy$`C|Cw}}K%AmeYiSY7@pG-ktF{ct&*ETQQPx83-V$olRd zGblIO=DSyA+Y!J*c3lzlw_oQQy?}gx{E$oT;mO;bsq~9s6gdpm_kW8w9HwQoVR~94 zgp8WiYSZ!TrDXzHu3cQr{gR`#7e2=Nz1VoXQOUFN*HzTKN^6tZDDkwkda?*AqXYUy zR))A;-NlNz%k`00-yg#^-SVKj2b1~>Z)h{U0!M2jr$qHrTCOR6W$}HoHOAbVM#^Hm z6NHpK=B$OUrZJGk#RivyR&Iv{oZL(F*JsfzF@zbDcW8(o{!#XpL0$}RvV%*Vym4dX zVi9SY;;CPHL7^*;aJ+65xF6ONRpjIc`%%^S9k72Y!b`NJak))}Ok|7$%*905VT!x} zRs0evv*!~`!(~}9M~-DyGbSq^sG4eI(vc$U`DY}y?=&jP7p$SAfZ$K$@ z*J!IeIBqsm{ycWX=!EF0UTHc$Qh~2hN=yyi7t0~sGAM`y0F^W!cLOdDs;*$M*cB#p z?&e649Q+5n>5u?gsqsL{!T$aKqLsB`kIaJ{~F|Jj{n4kXv`Ds*IoNk&2S3mW}~$Igpu!HqFKG{=S1Uhf~4fo;n93$*>>KXgi5{8k=C> zTC*jsj{tOsg;kMYl6!SAibvb3w5nlVxh^0doWRJ7M_kTpGhbLKrAD0Ayrilympfe8 z3LmP0(DB3iK+mLrmj)A@(CdQK+8uZflQ@Mb)KF;a3rxdxzs|-fw#AtY9KuW+72K}y zwIQ`KTu;@Nar_LW`P0eNa&#yxLuf8wJnbskUq_Uam7t z3o1$rL)5;8W*zEii{Z*S?e_e~!x$g*N|}wEvWp3$;C&$*`Wvw69HGl-v!~D&V1tA3 zKyfy2d)phV)5*^q{uLwx0xV=%oiOqXYubf)>0=8O=a}K#x#pjg`DVEm@vPu+>m^I# zl-Qy5plOi$Yz0iCIKso&M~xP4)B^VKosUs+(zNd0ePPIsb&ei=yZ?9{|Am(WE)p;y zeImLUlm2+>uJnn#E;)yR4CaZ14b(|v^^!`aUWqfhMAZiCa7ob57jmMw0t+=rzu3PDL<<^$9>O!4m^9g51A zyYM;_Hzl()e}2@AVrIz%L!^31a#&cIB2Q+y9l?59{22E#RLgZVMGb&B8rHb^l1D0o ztyiA!-k$2+hC8+P$`;KK zN?Cu-?DHvvShmSGBpam6yuG)TUdDAYY0@8ne060^J`Mn`mz4rTE>>u>hw}Qv$arq9 zj_h?8ZCNdgVGEabC`ci%m%csvG5Sng!O{*dQ)N%mv1|JC;$Z&63XH!e3`GpEOXe!j8(lqK=1L@WJH?}VQ*aX~kAM;w6=N|;f0@v7! z>vid*MMTTxUMH|>3_!4YUUXuN?@v(HA`|r8vs~U!D7F2!3_@Sza{^0Z!VVjOXLqQ) zOpy8dxy4#fT};+XnXeQpq26a~wY1(k_hl6r{A_r%} zwlC134G4aM7V$)2gL*5$mBd$)9j*tAWu?kQINBK}AvW-!M@xhc!{`qhFYMxI_fkfJ zdM!|B@vM{#@|VkCMQQL}{NadlW&?-Qle@*DGU5^wN^MS1MV>V2LG~n`gO0>=KMv}; zk}Jdd9Px6P0!wYy<-m6VA;oP-@84r_d1*a5a?ZEV6 zGLMnXKd===IUginSbLeGvC9oPx+-L%lW^s9fQjJ|3QkzaytuG)(UmSo5gfLeUmPD4 zgi`Hr|81*9EoECgfGiXj+MU~A~L!|sQ{7>wo!Vtk}md>j9*WNg+cuq*Mo1PJ7rm z5KMsNMP5)4ncynUYIV%EVEq(Yddx5|2>x`8%vRghoYq2Z3ZpiyqCQwy$yfP%(I8yz ztIwF44tod{&AFjRDUP=U`851?%oD@Du@i`68LTm?ZIw(j{_3@i zxW+^tdkx;8qPkdDvmo?KB(kI{Y-XHysZm61V&w9=LZzCmBcRX}oG8h8dO4rmdV12Jq|Xq>_+EQ2ChNTFaFpA8uP_c-TVWRA++K3y|#69ir|siH$9;A zYU&s^w_Ao3!a6);eqw={hA5ahGv@YWh5B4i$YGXFY#wS3gOP-BP5hGA{?wx6{piwy z?;p60)^DNb)8{!f28SCWXR>Ld>orjLFH~`q=~Pw>yB&hQq7UsF)`{5;#Kz=&w9)uj z=JGm6B8vVK!OMI3^V*Z!H>NYQhShfUt13p{tmgC=I22V?Wb3#in};cO6Q_i;c61^b30#x7M%8D*9M4-*K=_$sg-<(ZL~z(Z8w$x+R2iV1mb z!*|d}3Q>(`CQPS%NN`Z{$PqV}_1(;kk@t~s?|6VVg^d)}(+;FzBVYqZc(Ehh+wUSI$bZa9QI!6-%O@Q6(=Dj;$u_3eiO}M}WhSYp<|;^+ zjdob)u+fnC_jCJ1{v)4^YGSIC<7ZG?mbOgmmxymWiMK;mwg&ILL3B^#PgHwJ*_*@B z7YxKCT*9~N6#;>%GQ(a;n_cbk=c=G*mm9sm$dwOmp1-7e9%fDa<}wjRUX>+`xsv6w;Z(ZW<_}T>W)m{t}IT{qWHsM zmVa(e$PV9_;T86L@{@B?P$0V<4&8WDG8c(u-OrKlVJ?xc-G@i8<$g%V^pUxEFfT?}SfpQ5^wj(8|in(dnrX00Fu2Wl5@^Cjfr{Y)1h6Z?=nRDyk_r zb)YbI;TPco*hM*Mc|%@!807%=uM4OVZIvVXNVcEr-M3BNeuvA@L$}z!70Z~k^6e-i zd$`%|2jy)g;1T!l>%k4Ix%h1ich6IzDqnRRb*zqt(gx4jRoR+?U~qKF5Ntuw`#0Cc zt(*}fJCN2&>_t~q1Lai*Lh*c^=#Or++C{8{h*E?1aMRtaah293_*mZEom|(&U3x^7 z8n#Jk0}(4@2`+NmD&k*yk~XHaMumj^<#4~3S|CCkOSsPXz&^NH+;TW9c{*JJj_+(j zG9L74M{GNEIci{cZg^K59NYJ0-ACPpC*o%I24P`?1;|tD3c^3F{IYyN2yiRn`^UJf zwb;|PVD9mb%_zOap{y@740m+6f?JWjoaQ)ZR2IJRETAr&uzt*iHA z)C7zS%e9-L0NUEPDJcyNT-kisxGA1$eh#@GqeDKAUso;5LuXT3k*%J@jrQkY95sW| z*kQ{M{D}sLHsKRvW#_-roP1*-VQ|(<21%OxlFY=`&T`9$W z)C(ciz909iE)hw83)=~j=FVyVc*?MP&D(X^SKZj#{;=uT!8nQAuezut{q9U2D>uS0 zB>m)~U>YzafuSI<`XqrUU%@8c+4X%{BUMe#*0jX&@U;iz%*2UUqi~dKueqGCCu)s- z%~&@UIB;JojEkD5E#``RMT&{i9%?S)MebH+B&DSc%ez9m&Wpd&sh9heA{CgEn687o)9?#<@&Gb?=v#OtY%D9j{noC*Cv%3? zzXt@b%X!25Lec1%`(vPdQ`PCn>QzPL286dNT4&C_+dZ$FW;?Fg`ws<1lJ(xps*gec z_Osg_`D-C1Pg3t1k5DIRJc3M6b#-&UA$w!8>Jo0|bI{k!Vw+4UVHSED$kGV=cm^hE z&nSPx9a=7}Z9>ZGa%6P>GG^;I@3lNSo}6~RJOC#L73O7{gm8=XeKGQ+gzy%sY!vvD35j+bN4ThOG1 z%B?|H-BA_QFZ)&>Bco-m4lpoGNq5J$sZCdwn6itkSI^RGpKH^Yc0z=#^2PFc-jIn_ zdi(OW)_KiE(F}&6;~AqFtLimgalgbkXVgT49fIRANCKaDup^b@L_WmBxDbt8RrGew`N8g^rAp8>w@9TD8x~X7tte zTF)S=V)z1*qwM>gRv*Y&f~o3z#IT2oeZWO7-oY$pO?NQ277h28^3W;&wp@894N`K| zenIl*#9^AwO_i+J;sZ`WL7Dq2HS%(_j%?%X(DRQzDWJX+Ura88^PjT*WvyxuYQyTNPfypW?^XT4`vGRspeNa)_w3WC_mAlwqbXd>e zyWxXtWz{i^f)G;-CQJqcsG6ScE@ z=eccSJ-|piCR-sq$)_Xsn?9DOz@=%WSs)oZ1&fbIO!YBHHqg)VO24~cvD+1^k~DUG zv84@^L+=h-iP$*lKUTSZHY2*qqY=FY)R709{jN&u{hD_=GPECv$a)PgU-@{k{fEh< zSK&!Ic@n>~-(g1zd2NF=S0(F<5QOxR5 zO-`kt_cM|_ruycKHp>A~VacAOi>=ORFv06m-2vprMD}D@DyHhH3kjf1H zq0wkpa}Teo1&~ytMIV+|Z8k|579LKj%T5x=#RypV`gHjoIV1rh{zM@!f3PKq%zLcA(b}R*x0#n0quX!1h1HV*A!&Edd4y2qzpU7BfAR1J9zQT zFA%l`Teb<90eO3aR-{^)SkHYfrf2;^-_u-Bce$NnU)kacM#rXPMnw}b) zC~5g!PtztPc{}cq8HjQcqi-{HjZn_zLM=ES{vNF%P{Xr>)TI#wv zF7NlUYJU=^UjNZiPR)uubjRJpywWO2pM!;{kS{NNNTb4zz(V7X3 zhX;5f0>d0ouSSdp9LGBiCDxf@^R@oMM+0;}c1-O9rHi-4f<1CgJ8WXplZNuvj>rj0 zLDRw4fLr^+YUBN%V>o5{)0$Iq>BDCOGy=LE@vc7>jeMVI91frqwKh!eAJp9gFbd`6 z&4jHn2rS`Sb8!FekdS+Sb&#yCxmG9!48DW zUxYuo*;^Y;F_bX&n=7#zwD{*%2sTFeneCvnrBUEX7%=++9-Tgk@LyS;urtEgRwP06 z_Mo~V0zQHH7#l7kI5@c3{7xbWa8Pt|^O0UVlk$8QkqeOAWWXapUsX7Wh?zerWLaPZ z%8nA75=i!mYyNMDEAp+=8xsuS(5m?9#S#XfiRyrn`Tgs0FfqWEU`W1x`+r;a|Mx{U zyE9Bz;6s7UOl;C|gGqQ>R literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530010050331.png b/README.assets/image-20220530010050331.png new file mode 100644 index 0000000000000000000000000000000000000000..39f04ee635002dfb90ac607601a9446355ea3046 GIT binary patch literal 42558 zcmbSyV{~O*&}M9PY`bIIwmMeFHafQL+}O5l+v(W0olN@u*3A5#S?m5dci*~o_O9Ah z&$H{)2~&_0hljz20RjSomy{4u0s;a-2Lb{%fP(lQDZ`Be009vKNs0)n{K+`qaPw3- z=zPAJKKCF8oO=inl7jUigNWn|fTJOyCQ`qar!>(ue`;RQT6lcubZ)A)TU>N5(OFbC zHYI7Y*MLwH6H5F|2_yqX7J7`5BnNnL9z6}q=tB{aO8n@YetSq$Gs()}JmNXZ;JnMc zy307CG}1_JjWjZ4?G46&YJ7)ZS&pI!iUl?zW6GHs$d%Id?hBX7gD3q!9TPk(5XqhM8}k(^ z#oPa4+8#E(>c4nE38ewOSGO{ObBDL!3`D)2F+|LbV9lGioZ2KLqPHm~@R11WH4%cP zgxbDv+&#V9=H|^s2p9}p$rGjpzrO!#|4QaRM_67sm&=?Q8a12WRzizesx=~PE05Hm z35U*`7B@w_oi}|_G>yWcT*PL;gu{r_sCdSv;+3C_bGz%(X4mEk_Euc?mjUbkcrng7 zdXqqkRjLw8s{%Mm$qz&Tfe3v4{%__p85XpH`2!{m+k~b9b+AS=Y?UMyYrUkYz+NMAF`rsfax4v)-IEhhCiR)q z1~dL~LC4&?db`24_cyA2;oB?_jYB5}KM-OcV+~+I_Rpq==XRGo0W7MJ>tS^)@2Uv# z1Qr~fS6Q>&V)!~j{+e`l)%U>V<*R&TAW()Fv}&H7_|~9(_q1cqhGeuS7N$2qwf*F} zkVC%dY$ITC`pQt;5Jp;0V@gF}_(xO6GjcW08(X@Zy!uo;+IZ_zE+F!fbAbEj<<1j# zJI5)eQKQm0z-@ek=k70jLH{5)1`#4lcfTVdfjH*}wT-(O-5^Qka2)%eo5E$c$BQv$ z2s>urP&tKk8x8%`J@{PM_$@GBnb!`q)AN4!QR2Rf< z9~VYZHWD!)c@*A|O`}0x`r7((M95e^H@XOXuOP@`p-7ul=l1P35qp(dpGkD@mx=`L zWnKvl2RP`Xso1i`>3U;vlBvRP553v9@x8#`;p>Te#87Cnse4r$^{>*Us4gEK{rOz{ z)zMM<@PFMTiuwHVp~{CPoEbuwG(Y~qTh7NTb>{0+oa_^zb@|B_vk}X4yhc9}P<%vr zRq+g7rPVDwT4A0z;1&GPIrE~?V&KIGoI^u2F7*luOY9dA36hAdGUT+tXs7^~6O0Ff z-k&)Mp$QSl70b2Hzh4Fg1%-vAd&A#UzhOog+~{$ZU!MjoC3MqqviZazsCYplgZVt6 zrj6eU>zwqP$Km)mdu)isXwHwpZwDs;-iETwdPn09dd^CZbITYkAi5tpg*%=qz?uY zdyg)mewb@~;q-neR^?Kz-izDf6)3=7u=yl`Wc!FK?i9p-c|}F$=z9}hVhZe2 z&7&C>{qTd?^s?YD-FgPzl4mx6T~P38Nsf}|9rTdrA7RZml$b^Q)jq<9?VxkWw1EzI zf5ukrdV%QH)eyH-!-5q?4j==Zb8jBzKM>Ru5e3zW!g0xVcbz_XzHVyjy6cU040{XZ zYQ&(~u@LNBFCD$a5J-Byr8~ZiwV=|F{IyNV+#kL=?ccl{aLl@JD7`00kgs;!rdOYe zxf&TlUrA~Ie5CfVPFj3+#W&1MKI60Z-TTp7u#d^cBz3VNoWuyQW%W9d)Wj+L1C>m{IiUgtV1ly8KYRjq zfP}G0X}7QXm)#TP`L5$11C*-Ttl5m&V&6MC#1?D6O0m;i50$uozh9H+Q$a=NpMN!k zY`!a1eVz)T7X^JSvJc5kM|k{g{Y}5vJYjUWa5nl2q!>B$?5<`9kAlq6wt$D0?X=(r z81_o51L#`}+k7}$Kx-(@Rl01JsQfeYN#B~G|Cc7!teE8ic!9DJI-%;64f?D%zS@!sVCA!^OhbQr34p}SOfmS+ajR$SE zXJIP%66~TY1tbPK<9uyq440F7_*jeMs55Hn`!;5f*O&5w6T!aOvIh z+6GH{d=K!c)31)#KDlVwDI+Tx?kM<&3Iz1qk#{$l>1ZN4763_YxmoF-AYs}kCbAC@ zKhYV;C=AV%)`pY71>>)f!8=oBGx#fMH4i%QC3lOjYc5EHgM_U3KGLKXL6$gg|Q+^k_&AYhRROP9b`t5_|e@}bxBKK_Y#|M_^BK_1O(1rXJvx_!nnbLyE*=Lb&;QG$B@SL8zI3Y zQOT;zWPBWl!znLLSJIDBJmS-WnHADK)-k?@d|03BsGfiO?{T?_tugzsyi>f<`tYO0 zHTY|a;#5P!owcp6$lP!;lgEyblw1nl;GcJJzE2~Jx3n%vKwda)J6%oYED-pF23x}J zyOC8O6u6GlBL1+glqilV$)(T(P>ehwINV#Z(%1nFG@) zwZ0@v5kFC3VNfqGFLfI9y1KflS3NyF0(f|MAR}Yr-?ea`9x|o!VhLOXK~jh#ihe>q zV#Gjo1f&Fk8G-d^y%O8@4xl=+6T z%mlDU<-M@3%N4LIpN09{Jyz|C3-y6$z?rFjg5ME^Co$#@7h$Sd!A1d!{er;Q; z2tF~ow1}ZFkjAs}Mmu%|c)9RYwrey}M2CGbrk9&$eh|r~yWlKy6P_q=SLwz!_Lo$P z19xg#9n@p-y5oYQ1F;SmCuHRm$nFha-5@Es&TXd+MHc*-v&wlGisNVstrd5fUvZ(W z)Sz~{(J-RJnQmYKwb%6Jn79esUtM2-*tfg281X9b?Sid{AlO&%?K-3`lLtr;WQ*_o z0VlwBMlef;`Ek2qzSCbb_3hh z&u-x(lc4Lj1>3c0g8lT7)U0}uuTxGaLNhGSbv!D4XqmtyG4nXvVheiq)dhInJ^72c zNch0ITVk_xP`Rt7e31m7b4<@}H4Q;mf@%(AC7 zOns4&2ot9TVTyS(Z9&&>+H?f(zNu()(sl^F;6`ueHFob2kF&I!A}pe!XuM%;EY_>? ziAh>w`NfGF)~ni^eC%i^E@&zpN+bRxUgaAP*+<#1k zc@4>(?dp03t`{VQWRc<1K!(Km%KI-tcj1Y52CE--@1A@4A}=z`0x!ATl_tUN3n!-L zke!-qOb_(zO6!QoA_jU^9-efXh76 zB&C>9l;;CUjs>f%iwYYdpX|;^JgdY|)vY$#lE%iQ92^{4&Z^oO(kCfVVLbT=78e&Q zv|EwuS0;2^HwORK8cs7~K!fu^wGj*YJ8>yM@grvG1f!0s-peyzGfMc&5QOkK5+5*o z4_@(mX2;5j_t6fL<^w4KUS>csA2b`XxZ1FTHQbWW&x;0^7Zv<|ey0SFdM|K<*vvB0BF>g54##h-y&UXh2d?vIy0fA^7K%RmGd zF$&%|;PY?X7{)qFf<=vr-Q24EG2yf;^RKk^9tZ(7Aq#muKI54JCX+GgNT-&qRV`9Q`Ny z*1cI(>~`SS>wCQ2O4D*l%^MvX9fm064d^y%HTx}EpFMpITr4%%9M&e~&35m$_3{$Qz;fPLG;zr{FiM`{E}?Ja@p4JOoT1cx(mPRSkb zTIj_AwP(Da*9mx5Ixkd>(qCci-Y)EmPYXHkQk>ERbi^KCT8gqi1=}p??W{%w)X+M4 zk*()-4-2ykQ1tGQV0rw=LGPu zr(Bl$FZF8fgXG=hnPPpePa`_G^EvdvmAWbr%QK){PP4HjQ%c^=Yr)?fR} z83!92?Jhh#+bV+^ink6hlzTPrV7mWQM_m+Gtbf#3*SkvcF7r2Kyue0a@kR7lGb4xXd1NNUCLKW;WhY0tzU4A&jO>9`Uvg0!%TOsg`{Gn2Kalryd-U1q%Ha zWa`#3j@LXmuF6UlViN@OMnfM6l=Kj@vPe4WcehqDdE+8+#sG#6C|1_H5|k2GcI-cN zR4TnQov*xv-kR|ZetW}VVZhJ?*VFZ%`yHE??F_79{8e$_7Y#B5Fx(Gu^`l1+v6^Gz zIpUmHT7@Hil4{&F&8>nJ3fg^k5}~ynKXB(7AykxY4-QAEVIEw#g1s`txcf#e2&`GbC$h4l z<;sbFPd&(}tzl}}$8H3+9|>Wt0Kg;ZaeFI5c*s#g8#N@QqUa)Y#afiFd&6u0F2qgy zF9H3h4=a%j^e+R2_He*i)=|1NdC*f~ZzvaU0B#aj8Gsxue~0{18+V0ZN!`H7YT^(*y>!S;ci`JuPOxog{Hsds^C z%srg}uY7NYbNCmDPUYnJOG~Kv;0ozqICTn{-$I|LRa$Djg4Ku~-`E}vFgvBqx1v67 z5ZF<=e0v0aztlU__JnlZab(Sl44O47sHlLeR2?5C@R`v2yv10sV8z43BPAte@cHyq zQc_YV4@s@02?2#F0A2~7S;2~|A1h>@F8sXR1`KneQYLCfHlaq6HQT9aLo3^!K+`un z65#Ot31H<#@Mk|_RDp7$LwimAbH7)0Xkkf5FM9!nv4&XdGp)PCdl4kw#TOYZk6d>? zbi^q+c!j^Wx5&2Jzz4Fa8{MeR;KYS>6$^dR0OoKz!cxXa4P1!dsVN^W2Tcbq&Wjt6jNGx7K0(s+sd*%L7xkClmi;vJ2p>Tf4-p3s|pZgq)mrvWy4=+}3_CuQgF#N~GE$H(Z`ns}y@^5$Pk-NY7{wnk*a(@%mWyr9ge5M9j&0 z>t)Fp)ApjgsOgZQ`jWujY8vNmX2*1gbOxtW85%dVPISeS>Aab zoRncevUWPUzCM7fI_?C5)glQbwBJb9NF_N1iD~EOucVS+Tr%W%FyJ|JIZI}Yr+MQl zlu1ld8pN34+IFH4H#emP#b=6CMl(^w%=r;)zaTF%NmimiK)^tBGXA#5A$I8ubAgti z@ir_|hK*(kD{{*q03R!qvzm#|)hhy*EK;I{3wob$*gdu$^P%aWH%2NzwVj&R4H!sD zkm^)}7|j3}PF0Q*cdScPutFu-L@w9~fUDCD9~l+Z1WFaCBU2;eK5`ZE1j5LXh)Kr- zn(bCyYplC7J1<1nz2y1A&{?U2K$1iQs=X<=zy5w|IH(@UhE8HiAC_Q7 zQkxdQ8^>OpL-`RqObLSMpqrapfGiREA%P-16DpO2WHo(Qd3$o=7&fFX(7CU9IdRrw zuAvwF#U?as%#)KQk;ZUq9|{x&ExAAX@*~xr6>rlJaqk4Jv@=0`(Ad-miLi@}%G z&{#p5B$$0o=O&)S{QwR`MdJ~H!~)Cr4+EAZJhFtbZ=7GQiNTOJskd`Le@Sp0$(AW# z)|G1^(G$lO#|w%Kiy{*=A6`D{zu1w<|I>|0k`{=$>#vI%rKRr12ES(1nvz{m_3-J6$CWmhJMkJZujtm7G| zj=7uIK$5nSgGTAxh6XBajhqS>$IBMd-O%OIG@Use?Q>A|dNW&XPg)Jee;17aOrmd^ z5B9I`Pk9(_U2b=4v-ra>kti@ zg?etcZ@w^oIP)>|QHEnosLDNG)sPv--x&mW30I6W{LzeY@SKKNvN{_~+TIHt6@S~r zTgW^oD)2~CJ6Ho$O%XRM^kGT2%AXu zwC~Fdx5wLs?1JExbYgsyP%K$@gu#$Adv0`uyr;!EPh`z=H`GHohdw1rfpXz9 z#9Sz_X~&=i074)IX_$ZmG}(}iw)HSaZrfkWdeR=jha!1SH!1n^eT|7RHZeMW>z(7G zi}R0$a1$?RLkiz@t;tOn^FP^!52pNViPZ4P_t2;^b_Vu9OHLCf=q%J^0j`^oOvkp3 zBQC1c`5+Z`cM?4~Ct7TjDA*Tf;U+TVgUIF(qA^pcgNc7Y(V?#)<2rzYS9oQgL0U@6 zh2rDmQ@LH~=u%*t*CrFGl)pLn*!3pOxFP@|?9Pu0tRN)GN!93pI5p!SgQlJeHV#OR^D46Ze?=N}KVa&Ez97&yZ^i3HG+SA^?X zY6{7qgMHGJg!$~|#sXvlTk^$qvF5AwMa~q2BXU5iqIIxy&UhNeb4X|9!7mnSjZ^^3T4C1 z0uynxS`8}F6w+)te(qC#iK9;cc7U>*8{^ug;GJuwnZLSNz}R zM5(VnjTZ1Fh6y8&6@|5}nTMB(1!JA}OL%*KZZWH*qKOn2qdo@YT&lb>o0nFwT%Xum zZ(hwYjyL#xaY5u!Lin)^bb^T}u^3VfDMzjfE8D`^I-J;@=G?~M8Qq;Bv9K@*(Cp?kkQAXrf1ce<5 zs?=deGCAa&?M4zNJOhw7Oviw^PtGs%awmbQ+-t6m^u>`c*PZH=7ARNYQ_<-BHwnG@ z13h&!GB55Wa_>AjwQAK9MgVyv&MzeEald=^c}8c^>5KQ(VGIT5U4N9DhY!ax2L<)= zJ2nvGIM#(}yo{>H0dYTM+Z^g=!l)TwF*^t@b8LS|u?`$0l&?t%%Y(97>)s}y>Q@)< zB&N$TN5XJkH(c#z>b+y_J$aAHy6Q-`Hbz%{*eZN%{=SB|i76mqCk*jyNpGri)+;Kg(69iAUbh@ zXeX_R-RgjGfmh5iW1hz$Djvy<4%=yl+lYJNU&}W0x@N|)8PHh|-sy5Y-X8RGUR2M< zf(5(vZi<_JH`Ad2aj<7%fDn%vTJ%+01QJ(pYE&D}C~BCYDphp&E9xUVa?p%T+1ov~ z=mVE0F_ND@B2wh1W&szUoHLSTqbB)Og}^apr+m>QP|6z2o`*r^+z>_RlBpgfkRP zJ12k88B7|?Nr;725i$94gUQcMOl#-?ibcnQy5K3CZb?;59x7hQ7o!io=V=Ol(x;HK zRAw>&oTiyMaF9~aW}2@?u@LhD;zUk}LVwWGphGWVzY;?V4(y@Bp6jc$X32AQ_U&x4 zdxq;*n7FCXc@7Cll*#)2YzBw!V2t-Ye@y30GbAQdD~jD;*A=s5cgaJ80fYQ@kp~FR` zEbT?{@#RCV%JQta>+BxpXsH76ag*}XVRfkjy@|FG0$}sH7AEKNY~WH3I6de*5WS5n z_bL%qEeBSQP{c68KUOtF6{Y9wwEws34$14XJNAt^1_v7*IrlvPt}b&ts>TE3S6J&l z#(|=KK>ZpWMES4_o6W{B3S{y1st>J+rzfzR=#^t#dAJUaRw@e`4KL20C&XcnzZFKC zPrC}{ye%H?CueuaEvbsZLF1RVh_PhSanUKWfG|Jc!JciRwim;mUnFz-ZrnJBftGG| z8}e>1ep|P5R|JPYSOd$`hx4w!aGL4U1|z{{sF71&x4F8$Zb3U<=dP%{3Vad*N7Sz= z$8Ea-?Iw?irmRVY)7}Jk^m+%=t|_f|@jv>yweE+)_;49|DaK1K=&}43r#=B4Uqtdk|uQvj}jwN)3dC+>9{ky5e!=%IEkzXz-Feja1ieYD*15S4wWyhd4pVsmsP zKW$_oh8z9iynx5o!zYgM>x(f4UQsZRhz;N-U$y5~O{&Zxax@;hC4LtTTRARFLvX`T z*l(I?$1IIMV$_$K(y|x*@?NtXfgCHNkvhyfQqTW|ZOjS1Lo<6!Y~s1sZq;QD9`msz zN?}O#K4##3-)8`02#z|eKMc+Kp6&JsW-?Z)s3+q$bhappF zwBogHKaD#Ft?NY5-WxM&m)7a@Qmx+fhwpAEeWzoCBG>MuQ^xbvSl8_jeqk-6-A3lR zK4WY)941rfsNRV1)@!Jb&u6yVqX*prBh_(T1eG*@==`#@eDwuLCSW?YcF#ridPy4c z?`m5@b0b$)6n4A&y_!!?pA$36cmC5V{KCV3<#vV0|3$lRS~&N&icEzoGYq`?=Cu8n zN@nV0^XHmh$| ze;AV?$FOg*8AYkPx4Qe+m?!O@LbxKYhxGNEe$k0={=U&Xz1t&-3>K&L@n$-c#NRu0 z%G#Idu{&J;>$l>lU{gjvA>b+fO`mExehU9^tC|s7ry23`j0G1}D&;OWx4MeX$V(D{ z(-;&rDqIbEGltq<#&n5k;-<)*8)- z$QHtidh(cmBllZ6FoH-Dd?Nww18${d!QnYfLVC*Jam6tsLvWRC-B3)iIX|S_-;+~r z_H5isq-6PMX8|u(bf+fmBDt}ivR^+=ZE_lOlgEM`>5o;+9}3VX$>|mO_Z3zh%v#Qn ze{t;dogNjo?{H+gu;)gaM>a7!9S$r|r;nACx)o5ALp8E1x7U+9EDA2zSL5v5u%`+} zj~3L#pp-Vm?CEtHORG2ImrOEQXj}Ep#Eq34vFhHi#ZvAlrE$Y# zf9WY`h7~k2!yvOoMRf3nO+1B3LLzR!iO_H``<(XnQUarj#(g;a6E5TWMI?-b@p%K! zT!JBkefVY*jJMn5of*DcWI4uU9?d7uQBBy#Fr9D2reI9D6LJzl+T+z>;6}K!3PL{J zVGA-{`#8S3#3f2#+7{{GPJ+?zCL?g-jlcaQcERGii5&HsOcDZp+<}uVA135Qm{=zKlk`Lc*HqoQ_tdnU^?*m)t^LDk!xAAM z_RA*F3U4oNcpHKM(@PSPQM$Bou%8%i{bdpqV-Ht#Z~DBAoq;}~9IGesQdEE^w5n_h zG0S)HJC=)s>&=Ib)(1kZ&BfY%imja@9Ey1UUFm@!`hf8*)Vw<4bP5!wM`Rcm;yp;z z9o^x0e~G_9A~tdmc1uxXK&X_zxKNXC%w!U#n@M-Zg_3)=MCWV!RerH$93itXi&^@f zr~9M6S6^Nff+3GkWs1l+EP-EE-XfB|K(%R>R<2L~4te7NjUbCf3niQO@tcYihG7SA zq($3Tl*N1LAn{ciGe7y2r!p#op`{4VxP?z8P;ff&_*!pz4n@h5{{ln%vefx3Li+B` z5=821pnHW#_a}t<{(y${2>lxilokU+|8Gc}iMZz92-r^i55J)Qgi<1*X#R}|wit=% z6aD*J9~lV>y^Ze{D?-x)wW?^n`?-z3)z1&5q+C8r7@D{j_;=MtR_Ys`Cw-`>mJph z6d2J6dAg2KJVpjy)L<79hDhW>eKl&JQp;~j%2`O#n*zNj?51rCMzD9uv=G%JCfb;#bVX!DSq9YtbVM*#m=K&~I-q#ms1!bEAL}q4uYsU4zpE$=p%BJENmA*# zrl{ygdc5yshS25!CUT{>`{@~{>M!Bq<>{;k$kEnXOl1eSq94nu|D439r{<)et3u6~ z{@tQ+GyMGFeK?gFF>8i9%fnK7r%0OUuY`kuxj*CUO9T{;L5c|G;Wxq(?{wIT3nD~W zfJ6vy*$TYO*VOgMRQ-M`{Fo*i%N}81i-Ushl>}(kot%hnc009v(0+SkVp-Js`+Vfe zdA^|h^+Ad}w=0=}BYY{rp89XQc}`Uw_w-q@IevXS-KBKD2Ze{jXwzZ1Zn_W6wv;_B1H zg-pBk5Og>UiN?2|c9zR#%oif{WxuyM*beMfI0B84#?XmVoy&#h>Dd_-9UZ=XherU?OT5=^|~$T7Ewts2GTCQ>UG);ryL7gE=b^Xz{i z{~b7OR0AhYw|%hm3R+sy8X8#5>ki|h6NUT=$F_%! z4899H{-9(2pjqN|7#S3Xzqfi{*<&0^HilSZ=yQiST7kdv ze=l%mvI9$VHC3p?SXJM>^Rlgfxp6Pcj}uw%H==!qL*Vox8lL*`gZtR{I2OCjx+r`! zIN>-^EXdBd+`(~=f&Tokz89^(DI}>BUI4ipi|Q`({79{O4N_MWfYlU%xoRm_MOCp} zNgyq(O6Lai7rB9zJ*Kl-?fH&@S*6IfBv)!;vsn!q-1A-&;{n1V*Dv z-{uRJcHtF5>B+^&7Sdq^$7U>+Oh72Pu;hli?_j6y(|pQlNu{Kr#1K}&nBTXL$vc#6 z%r~T|AChBbPBbLM4n^vSkIkwn-f;uh=C#;7@-t*v`=3+jy1$c|J(WZnuIH!lb9))o zYnx#7x;D*guo2S;C8w7mQ|p(Hlt7SBsaT{q}|4?P;0($^uLd zFpS1yJpqG<9~AXJGtpPmdkqOCza!lehj<=oQ@a=KhQm&X0>h9=HU0>af((a!aD(5u zxad8&*@1nS){A0X3RkQa^$>Lh{AcEfr*CNZR`d-oo&&a~|9P4Y>xcTk!1T8p4gG%u zsIGewTjG~k;mhj{$!V-QVPGj%m`1cj3pyT!>iHiaNeW-A61jM0L`r|$k~ zb`IVLeThM_uhN}cb=`mBzr9XCVMpEIMmGX!Bz=)JF1vxTMn*ZIixhJd z#4m~FeCnA5av`j7Pg}xDCi4}|XoP8IzFW(dy4Qk;xl`;9UJ5dq;|RLjqskVm=UGop z9ESH3Y}@yLVf-`r_~mz``u7qxHZ~R%7Jj!C-5B$MaUKgIfI~r|jM>fDaT(@<1z{JC zg)Vpit+-(tVPSE2!J=tE1VIGxK^Lw^RMf-csgEE(x0`V-1uEf)PvxM1U$^6|)Zb!R zRMF&?di}vsF);GyPsDf-gH{8DP%sdPjYK&hiG(?Daz%0( z^P{pO$(xW0hd>;Vp!`sQIFY<*gT@OKKw(B%??HZXNu*9zZo&JjM)-Y#zuK?7*?D|` zCGzof(!IyyI*0s%rrPgcIp{%&hsqT!XE&$?%!n5`FgaSc^;RGWR-}mXYI}}6! zHZ4*U1BoOG;+c6znCA7wJ-9D#ImvBB-Gg+w8w$_9etq>)(VU-&NfUC531PnR#WP)| z;9$J*YgayU1IQ+mc(=Ok%S8jB5)Irw(fl;Ohb=IA`}h z0CwG2H<@rh?@5JTsyGD*$?oAB%Cc+ty^)o>Jtz>3+U#-HCg$lSBOQXb4oj*{uF8%$ z89wm4RO1Cb<;g;{p6(LVsNIasiMZw^UAo$XCJDf)UV5)uD1J2Xa{q1Z4Ed<8%Dn}E zqk<6I|6_2TS>GTlRH@4Ba<2aE;_oLi=bN24m8#!adgVG@bRS3pzfaJgg-`-h0sSKl zNg@|mBjVH7kW~A5-Py`#BgA?1*F=^p>++zpec9MxTl1!HAw-R1S#9)2IUeace@wMD zZ}__aZtYo9&ECVs0xf1xuMsJm2hZR#T3n489ZE%xGr%5iQ*1EKz0EhS3h*y_v@O2* z$E@vGB9)Vq({(Q-L5=x5Ik|imkAF`dKh6(q9@t)A{XI_r4Cf#6d`4sQt zTTm<`Q%qkGIK!^KcOkqa6JKQx4=#=_`KX1O5S?t?e8DX#uY8g2Q zmCg&NrO(W$%5B6&hnCuOpjr|wihrr+8S+I44Be&~Cwn?XvvSCaEng*CpVWa9^CT1t znpn=1?Db7i!j#Jj0gj_Uf8k7DWt$O%k07^7ZnXeub3TYGu?#F;N#z*s!x+C~s^99* zWo`je;& z$#1aiS9wWA1t~p!O#5XUZ2bz)H#<<`Ftk@SF%WPZ*7$-&m~&(1>S+-mi133GTR6em zFF9q*q`OCgVVhSc=*wKwOO}%9+jzIza7|6a6$Sy4LY1O5(V`KX6y)=MB;$LoLD_J1 zsXbL>aP{dKJ3_3jb~Gv{{g-pUDAn#|N7ilFt2-aDznh;>(a;#bNf8Y?EX*L(<;g4o zrG%fvVP3a6DU!2f>DPqtt@zlR-W##;$9yD%VQ#3XCGPP3tvsiS+GOr2pIyWD>KndK z*{xk224Pf70Y|vWrT*Iw{`fgDY+05Ijs7R^?g;YgYysDw7nRuOs0utJQIQoabMe*# zX*^&ZcnwX$#~>IL|0dSQzlxSw3k3%9k1sJA4k@Urim9qDjhGUP4;APOH0@@{0glep z>>tUB159XM%U0SO0m1mNC@Ik-cNIRTGigkzO`iA^Y_v`#RriP>WfnY~rKw^#{%2`dnYcKFjvP zH$XXxcA+j?rjNu0x?qtLz%T9k=-1FANK_bBYA>GT zcgxxGcoEBhe<7SPoWgIoQ%~Zi8RuCXEBq;8?xSyi=;qUk`@qwtojaGyW}3r98XN-o z56HlFaKF*@e~zEyN8w%TD*sFwNRR&ii~axSaC%orFsF4{PP)*FUuudG=xG{!nv9mS zkjr9{H`R(*NCcW_AR_y3sn0ZB_kN-!mMFQ&?6K~M#33L+|Bj_j%|a1EDUp%bvWGg9 zv@bc&bGFF;iHE$*`9uV}KO&!&`zZh^5Ci8xZ8^yx5V>*1V(SX4Vk>A+_zMZ&dkGn# z<|yPTU@4|CDV)YDl-y^_8`GtI*M|0-RyP8fiWpZRuxFvjzb*C-sy*u$L^J-)Y2hG1 zEgl9d%W#i{5!|6%DNYb6iCq~ly3@^PqPic!3FAj&-)zOuTi;5hLgrF~=+4+0%j(G*p;9`~##<;D2YS|KZ>@b~{2t(Rdy=%<)MhAA+Jj zHNGGkxk9;3IbqrUY&N(smEijd&qUyYmp*}g^>K1Ju^B0O7TA4zLD47fuM!`bnAJD-FMDr*BNyR4Zyp@j= z8I1-BA!Pad-ehyfalKx*ROoWzLK!a9?~Q0~j+>nB3~u(MGEB(0ztk94{`n-f$r8jl ze&~2tXCBGNo4qd`vi;K@ zEF~BVP=i9ZBeN}kV?0bx3L`@L2b5|j@JG)046rechZVGA(LpTRZY9mXeDeF>ad-KQ zik{wdt;t$NMFl95qeTJ0Bv=U&M2xI{Z%QJxbL0S205tN+d{9jAoqYwL-8f2Or@9#m zLBa@m+u0PEX+sLuQE8|lHy@>zY_IZi3V;_!UDEhZhE$b=$hS+Y@?S@6{sMZ1=aqmU z7tgkgrgPETl%**pVFbS4zv0`6*hCgSKbA{l@0u9u;@A~Gh$VZm%UT_V{i*!t`4GAQ zr;#JZrr2RPM1>)|7Nx@MIQP(q9WoQ5NKCcS_{hSAp!6`1Dtk2lo}-NV*>2d(sg{vu zv^naJ9`yJ6K(u%Kg5-+xJ34T`Nyz0!`$~r!GkHQ-M@PrbQ)_GhVJopLwvvj#53ajc zCjjb0_Z@FA6itJw(+&89j2A#SQzzs6KEaev)OG{kVz>A^}jE~dG6O5*VWk|EQ>-CxMS?@W3%tS-Y5~LB?+6%(YoC}8GLx5c6vspb{f~r z?$MO4r++?gI+5w5eACzpx|H#)hg|< z@dND7^aDbPPYG3GJ96P4A6#uRFc~LWMDQ6))3I2v_h!yii4#n-OPi7(lH6X!ZDxO6 zfgT#5Ny$m$%$CCI;Ngew?;ErS^KjxBkAE?^qm!XT zv@qfj0;wp~FAL=Sj84R)zj(9}LNQTNS@t_s2W8Eju512pS(D$V-9a)UND@IopC%zL zZcsl|8xSI{fFHOFIw}-XcGJ^$O6JZ5^4U?J?06jUWhIJF4*DVCCy0e{`t^)2E{HG} zQdu2^iF##(BW7dWH`D7M7sl&I1OQ1F))DK+Ye8P6Kbun&s70*R-$u!Q~IXJ6x9 zL?97}{O_@y9#8Q}NrUe%cZ>j;ejmp#G<*?OHwn;mp1gDkf5IS+W=T?}7$RnLU(E<= zOD@q<_G6o4qo3v~5Yny8;}RW`5xV?gRLy_?SS$#+1DComUfl0Ha+p~Gk|gTEmW~{i@w|Vt+dg-k^`dU8NUalHu5r?! zaw{I6AU!yYqg@sJXV!>+xr{G6=DVuoaEVYUC=78Qq(_RSuML`@m}6@3az zq-FD&afMB36iRwIf^S-ZKf6rX*P=0U2t07|4H{C{TFiI)5VL7nJc|k7MgmVQTaK_)W2*n!p|}9zp^{I5o7YX?z+AzPrZ~ax74JQ zUEQ`A(IbG@Fd3vnf5*oLTBpWN!~%@6-~glv9SoxhjCZkcU=mRMq)0-9CWx4rIEGdo zBizYW<4vTNTPexzVr637~G8)Q2!hYwJV0at|p~2R58!jXo14uIjcFKBw z9=J9`qhlT7Vyuo6+niSkNb63Qx}$>x36LN%^JAR0628rmxwqnYqk4U7^FxUh)lD7? zq}yoKo*XUjRYQTn>vv6PuF{#4%VPmU0F-vL#Bynt_VWck;7QKa*i?F8~C7)%HN zE7Qf~8(4B`c|Q?{)#KV-%j%i|`q#(jQ@_HzErp>5Y(hTL!~O#GwV z;$%ULuVpk~Gdo7lT>lRJSn+}H`qk7OwW8f+M(j{u`t2&mLd>DzNHLxmF=MH#w&I>< zekRC4yFDs{c0Pk)^?~T}(5a3vP6U|Cke1c}oZ0vLM=)p$a@;Vw3g5h!lZ%@@#PYv; zdv>YB$~HkC8}~15CkXdGe}nt?`Yvk4DVjl`cCIdamp8F_ZkF&ogF1Knecd41D=`(d&zEQFe}7D6 zFKQPO3)lsON;3B_;4pjoWfSUz`M6@mXpZKT6Xk#RiiG7; zKekSvmE(z8YC>xO3I-1Tk=dlxn9t?F2#4pmnpE;gqfih^@~t+b{9D$H76+<1MUX?_ zi;EBfCOFp@UFhytuG%}QsI$PFsD52qYpmD*?gfB%LZazIpGQwJjL-W~fRqPy3ikerj$<+Oy` z+|x6l!(+Aqf2z7aZN%iQLZXv0D?mI7elN|j=3pa`^#WPNV|80hlkIknKKoEj-e!A* z%5-}$fhUIByE7Rlq4};iq5mp{)e&p?J-hh%5H}Pj(b~TUA*=h!4cp<6`3}dj#o@n6 zZtf0Fw0|5`=wyoK-DxBHK`hkW?C2>baYS|C@EvONJ=%FGyqV&E4wIDJVc0)3rzqY+ zBT#(L`5kAzH?O%l#rbT>epVDCEVPb0J z^EfA@cZLxT9%#@=7+N*Qtlp2vN0ybpGZT8iw0bw|O^pfK;Pb$`*Ff4xJ2xG5>*TS# z_~u&B;IzcEraripLIbbxVyW%yF;+>;skehcMa|kEWtHFgS)#0 z*Wm8%E<60so;|nf*4EzrKvBTU%=|{W`;qS9ifQz6@)o&+v@k!&eLS!}6+gYicnS%} z5QlYo1Huy;d?>H$0cv_-HBiq3N`;g!qRW=9S}hVLhm`3zNlrmrTwK~xyd(;uBq6wd zQ)mfD3d9!Z5XBB|PQ-Sie%Q=HDi%1aG)CR}sQxZTBKil#MgxM_XP&JR@35ciE3&c! zgwt(sys+peHsgVbNIAmnTs8)%g ztrzZ21Wtt23n#&&cR<#1jrY1f&8FqJjf&V0g#NAY2QYDrIc%Y zDo1g&eIF~6_)l6)>WoK#jT!+%AIBB;}SPVB*YFQTr>YiSv# zP*s$28ZS6H1t(%S*Iw34S0Ch8`I5{c{7QDcEf|wgq0;KX!SepXcjI8c1%qS8TJIxt z40IU=_|o+K3-IKqUoYu)aiZh#3-}#V{c&EJf%EbN^y;}a=`ybcy!#RRoUom>95V|N zPb~UrqDYpaLyCzJ5MnBnC?Hm-AXeCah8(U!t_hf-UQ2&A(2PXHg6h%%U9~Mg-Y(67 z__ibYS<^U%(oFMNm}`DlmWQ?ok>roPbJGn+f+BNdZX=1;7HWdenbINej0AMUL~w*; z{{EuUy?TF5&!Fy4nulVI{1xJgJr171b=6$zjH5UA(|IIVip@8#bsW-g7 zYp_Htx^;{)A+?%`1YYr#vCo71rSN7h&zVhU#)>K7&*v8a}iL zgPuf|@%^!{{^+gmqa+iadLJ1r+m|^gbmp+nycP{P{P6Hl?4R@`kx@v&rnm?m?PR_Q z?GppWW_LH_>5g#qW)O#4=#H{dV*i)~jDxn|0y+Y%>vGlOglj&yYk5i`J&_!XD9Ln$_`sL0y}(cp$M>M|ne1o|ve?nc z$X`uevq*;BrZq;jlD*P8LQHl-oR-5)nT12R$a4I$!}imv0&tcIWb`zLxKb>E9rO(^ zNB(PmbP1nqzJ2eE?sX$391{Yaa!%T+i$8|$@Q(3*6|FbnS(a@q*-$lo(jW_I`Ub33 z63`V>Qc`~X`c-8)MSgOJwldCIyv3@^wZ(}Ae`8q%JJ?1-{PdG+KnrnA5W|2ba2saP zn!!-3Eu8Ym%F4drkBhJdOO90LY82Lim8IcTg2#f+Ef#ij6m9CS84MIn!tXgUZ3Sm5 z6aB{hw(KTEb!?w`F{xdbluV(W=~CIz&O=-i!IZSBcw^I4Ib=EhIqS}_`T9eI1#(Xx zlLL9j#S8=!?Z^uNvN9;VLFL&Ja-3?VtX zFO?NvvD8cGX~z&-Yfsur8cVq@eAnnPBlLRy5Pr^VrrSm&FsXHkY&PNdQ~I8}`sVL( zbI0t!ZFP95z(Apk5RxMDA)dNQDIoOEjl9^xG-O*JEx*o&V9+`RSxr_U6Hu$d(`nKD z`tw3Ar_N~FF%#ceA07)1503zMWvAlVtdI2QH;{fAyE+48oW2mKt<0W zu6@Fs3t7#G(GgkoALOmO7Rr9^Wn+H6A4&a@72{r&o;}VS<6V5O-jy6rABu&pT z@a$6BUi_aR1$_#6lD7n(H}=?o$MHE`0g;U4d`@h6mhG;24A3-WDyVhw_RgI+K(Ond ze}-5Wde7EzVeObS=@ge|Ow>mJN%`*plAN5m{R$z`8%XQ}Gc+ldrtNC{C+~a^`AJYu zW5^2H0V3{!^T+!G(it89s=v`RwO*gu`y2GV{tu9pE<$U3y5*m7!_9wBFzQlN)FwIn zS-b1rff5K&3mU1zCm}AaoV~+Z&RDgr{0pwnZhyRoK9dUmG`sgrbMSYe)9RXh-U-@ldiDJi`$>hY}F~h*5KqkIJ)+uKu3;bDPIE;hDe1k}~Z@OT+2f zp|e+V2LDpgH)XxOE#6OF?CrK>IklJ1l?o0hXfZH*c~5f#uPZtkC^7de#n@aKB|-PnCpLbmb_a&e-Aw_ZO-zoPz{$loBkAXArR#n8#o#vJDs zct5<7Lo)0uC&OaTDf+l^tP0_e4?j|(3*e~(PjCuFMkyN>PEulmjJWN^#m6>+8}tPh zufzQBZ11k8<}~GY8{m(?W7TSCb~q|{kyylXW7b!$KG8U1vu*1b>@R_cEVmyToUQSf z4-ayzT*nb>+SSQ9!eL+^Gx%x_!Q9?R+j%c2EmT&(-b)r9anBC9u2RF4+6d0mp%_Nx#2R0c zBe;LSp#8I;b9gwOPRS-W1}R=tB+SACLHivnF>($61lpWfwe%c!Tx-fJn`^$&tG222&%55<;?hqDsZEDA2}$;hDZ8 zJAS|65Ab)xp;6!q#uSW{Yce^N9|gH?o-*$jj2(MzCETikZ;Cyq2MYdJb%7bdRy5Ct zA^k+SQ%}+bmW3>rJAU>syYrpXX4d zJ2u-J*Y}qR0;4Jyi=%DcTnxq&W`7PpcHH{dOY)*y zeMenL)pC)2?t(5J(FtL~ulWfAyuo&{XJ>`%ZIY7roQEuV1T8BnTEgnDZu028A3+v1BM%`eR$)!8XBWZFfD#gzsFv4~tLC z{qy%tmhAf1U4r!D-(b!J&P<0tp;&dhFO?!+b|1G|)sf`hU6DUsY;{SKI!2VApBfDk zWP!%B^(!f>jX8Kd*#2O0NeGPwf^g~g7C3}0q zZov_cxc(o;=ivC*88%GwdN$JNfCV0Cii3Bj$OC6m!u*uw^tQ*4C*9Q zn2iAtct2rY@4BQ5s#r;+JiQ#$FDDIslB%sU01`VEnK zl!20g2^j~Be{$f`Zg-ZmVI~lxOel#?E=s2Qe%k4UH~jwV#RsqasXSG5w?9eI2IllVc|0L-KCEzb0Y+%Sa7nY z!Oailylt8#ioCLS+&Hw`KJ7R139rjdse#d$Q^k@m>sv4J7as-@+K_1L2^GHBs@>BN znV?h8dSxz+b?#fNdu97&346zo(j_tPO*_2&IA``q+M0w_w>JVNbUE#-E>}ae1Ym2d z_z)O87unFdr3I39=v7{X7wPZ(JVr5Mv$ga?cwDM{&t|E}l#N`C$%BEtYa49Ic}o=O z^!VOujn91k`=z&ReK$SG8@Z!3@L#|^JIU<=-`lEMB8QOYbez*g-D%wJRWuM#{9_Kg zGXNqEkiVmQdc;4TxfZu$0PR8{)iJ|zix;Db%cEL{DItVtlg%P)qZ|av46%ymqCDa~ z`-XJq19f_74HF^m&mg98zM25M`+BtE^Rq-jkTySfJPun$8$lKNS1I#oMos@0~7tZSPC=h2CHEUBd*DRt4|p zSoWs4z$iMbkI&!h8?D~^o-8#db=sDKlP=5*$Ax!J1k#l?Z4NhjIjkyb`izhfdpk40 z01dr6dn^~X=c{8uJ1iF)1n+&Zay@EU)p|gTE-(UVFk(t}Z(mj!_rr7BugG|L@qOUI ze*gqp)L@QL;^fTyBWQTQHWy8{jC-|~``R;Ajnm5~-ru0n^q$TmORCZa1Iu8a{NVMn z-Ki^mn2fj;L!Fy;*6>fuXIbChq!H0I!_ZxPt$xL2kcu%oGwyeLXqeyfg?wjd@{a2l z!NEex;5sICEI>t4O!@inX?;tm<%1 zci8tF#)ej_Ag4+ zrf9POf11A(_L!fa?8T4C)k9)3Syr3fl(93oRRGibG!4@3xrN~1kl}N+MPk+u&@@iR zVCR#H%$F}v{BU=t79%50lmLg3R2W}Gx)?d;i|2B_CO=XWSvTgmb?04`hKWAi)^x%Y zBHZwCT61QB;^EcV#YI+D_G6-iL^v|Qyo|r~O7VIVln`SO8$$*YFIp(&MjS#<^|C#O zM?PwqQ%B2s)?x5(`qMF<;) zNSl#aTaWzx4C}_6Vj_iBmRaRA8GuCpUB-NqvL+mP4fL0SW>^TM5fj~12SKfu2^uRj zxEKv2wg#lT;)5O9!_Nv7!Eo2`mbR3e(Tg2X8O{r#GZ6bC3IxTDl`g@8# znCx4bxTWYAvg5`V=2ht?Ot-cIJERP6pKhfIETJLv_*K2RYswCxo%MSCSm`GviklPt zgk(WH%T7Att`No8GO1sxZ}n_X=hT|6ipLnp23;K;ziwqhJ3Jj&|Jl9R(<6Mb6j-MB zwz9M@D%a1;zBwqbPs22*`&KnQ7AQSmO9JZ=LVM0?d1;#Hqs)&CpX#wq<$A?0ZLm75 zF!t>ZRod1nqI-8hyJQCIvec$BY&jC~>mXo~8Y}k?v z&E{?}Qva@BHVodPdz#nxmz?NKb55;1)TWlEN2)W=FS=MXIM{|GF)SC~`E_zSernvg z)iyo2?gPY=hX_w7&)ROq!uWg4RB9hvUEj)9olXQJpP!81s9(u?kE*r-xMRR^|JRu%{mn%-JHs&?2^dzsRQrwgxnHM0vZXIW;c?@4eBj zik~IaVuDF#Dgaoi%vSgwSa{4YBqXHkefWDcTga!cF&$!R12w9IA93bY%yX#W;`{#V zHmj6-Yl*cynZsWQ`?sUtz84n(SI?LXM^wm!MFeelT-VX}-Y)Pj?IJcpjv>!KWTUpIJ-#?30z|GJF zbWgB)V$kZggpE|Tg-{iucs>MD7q0tY)mmUCiIfLsRCp&By={)XC}>pmQyIhGCMFmt z=&7c5lmLUb-k82t`sY;YT^l5vg~xqj|H87}z%ouVw$;VC30(p5`rfGT8OS1(@l8)P zPbjTtnc1YjCXzDW*o}tmKHG=Z=fX|j`;;%+BVDD83O0U!S$Z^*7l%C-u3>6UFpGx}mf zG=B-VVQ4$8YjoE>kzWuK^%>@G6i0LFu*S*&&r;*G09o`eQ5XM9zo~>TIgaIs>DGRTdPok*3;p(b<+Rd;u7fbxDk&rOls}xbo=)3>#)RslsB>nT0Ogx@0hJENvuc zgjy-{qz|}xO#YIquP@6>0WJO4)Cnmtcox(0v9Ey+V8?+!YaR|Lq9ZloK?zS27QPROn8a|y9;AhD(pDGKPqeoRchjTqjHLb zVe{^)PbC?=Y}>P|iGILt%p{~_Hle+*00QQ9V1D>7QEejbWk%-%6aSw>-~X27nl~)g zKBE{~wkOQVDy9Mc@3|P`yCCbmZJNIyYv@bUz3A>aSP^SF)4JL7VC`v7FcXa#x>-#n zEUviJq<+Vp<09@i75N`j+fBam!mWMXdeA{XS)XJRm}_V#h2n0MED}+Fpp&{~5opb~ zUi6_6`r7MVbc>(!#jN>2Nc;oG>OC;{hKPt5W60xu?SmTyImd;J>Eeo%@YeqqtRHdy z(>^`#z#bx0 zKlC5u@Djin%E5sVzi<1Nn)4U--pG=S+(Y{vnJ=})AT4Zdl*0qgx`N6|To!*tv335$WrRq1Uh7z2lG|~^gq0hnr5chK? z25TpTNB*WT(9zL#o7cuZ;6^Qm8p}q6z)D2Uk|IW^QK(@?6WC0H7%!8Qn21?>zCnA# z#whL76E7Cp%+a=-b25d(Jw6{;9S@-3?jiI01X~8*!TmpCan-i0>vk3XK_Ka>AHCBh z@@Q#LP#iYmZ`a;!#9|MGnQ{5|}EVxo6xb((gV!n2(H&4MKta<5#o=K|< zAnThSq(piMlQYw@IfVsAJ+>|zaq+!IiJO0bWk{I=w5$K|e0lHwwKBlA0u#q-9eQN6 z2(`{uCZUB8DPqKNCzTPA>c$UzHiyuU!=N))3}T^UHs>5oXQBn2m$lcxo}zxRPN|HA zoR})i^B@D76pg3#X|!z@IOBdt(b?t`Upr@KXOcnN#@4cphHB;Q{;ivn(dP3LCKT63hz&NqG%-wW_= z!|x0gO~#)Gl}6o@tMHO7Wg@(2555tX$lPeqK9ThLFijU=S?ydMhG8B46+FVY0`H~>Da*-m=I&Pfe^Mj~B&5z#d@;nEG9?7en z#d%bG!5c4_=J90~5?%}(iK~?E#0AaGar1D$W1?%fh}HNGMD%gQCNQzryoJi5KuVAT zYd-PL2;bsG&y^d5ak_k7$$v0*hKyhwS*`sWp9yFUq(Go%XB!hU=ttvjGc#H#_~~+3 zhdBU6&ANHPmRvCG$y7R;OAYu4J_AcU;IWx!OixeuydL9OtTKY+uox#4t2(HZvh39$ z!$s#-&?sRAWC47M$9NTu-;?v)k!9vIhLA&<-M=D38LfprBj7v6V5HzPNm0PLiTV7u z7vM;mz_Xm}6K)8K`g96c_Wa0IDlbhWjR)~>vqS_9JEpPQtY2dcL4T2Kk71|Q5O^`F ziuP+MeOSWjRahrT24^F)hxl-GNAn{UKlgl_mo2_VZM_E>?+GpLm z7G%sf=+_~O3_>7iraAN;L+JKnPO$9d>;+7(rvtI7Qz|FgaB6v3juf@amU|nJBVT`3D`b59x2M~t(J9q6(cIAbe=!csG4WecdxjuSZ_7l}kMK5oYlfh|2H*mQ) zZok)5oIv>tRFy}l+^Y0gvmegvZ9Z)ScG|Q9-X#eW2||R5T9=d1^UDjH*ppJI8uP@4 ztBf`$2_n00QIKT!C(5MnroBWE5a4w`%<)~3-n)dk)l|_-yy*R2x4AOiXWKp{g6Jto z@IQD=#Jgr#Y#?fwoUgTGVq-i1mzpZ_Ch>|Wq*9HmmWDgM%68Cx!5YkC0y)5H!kDNk zdoz&4W@&;zWS7M`H)yXjbS2O^(7DnWlNe}cZp+NWtdUw}!Y>DU7gKGH@2!WUy*tzu zB1>Bd@C?@Su=&K*W!k?}_5I`UCGbe_g_UmYd$z z$kx2A`57(VQ^*ZUB=fWoQjTVTWhFv2=8*YjZB0MhYYz|TR7+zwgJ)3x)3tq>OH0uN zS0h4ukY~A@-)TdM=^|%!u_J*Z)p*~D{JHV=oCDO~!x^}8>A%Gxva!oUaCmLwxZ~%3 z#@A&~3dSf3hhaX4?x?1!Z$iV-FK0fY^RgFze$~@p?LEf)XIyu00;%>kMdM+^5o3=| zb*MJgao~4C<_}qObLup!;a~k;tXk%5UUzIQJ*|s3Mg$>GhUaB3W{N}t>0ngEWiIU3 zay%{@mV7XOTk~p>-UCCWg5lkoCmbO(!r_r{u!B{Tf zonp`H#J%6N_hfuvM0ta|0`>{`(#c%5Og5Ll95t%-HGb&CfX~klQ zVnTxC_>rljEYzQ?d-3x#a9j_wx)%YG^>OTVXYiBa-=dI#&O+DG$;s#R$+DboC8E@} z8L?{AR)vT_h^Q!I=lqr$WxEnu>SqhrtM*R<$BXR+Ka&r=eiim_KG|x2NKE6yfC?0& z#3R)dKjfJBCW@xlUl+hNxLvyf~Vdm$-}4O^A3b^R=osjB6HrT<~vG^qCLndM1f7jxZ(I#Rhjj*Atq*ph5tvM~<_Ux#Nhzu28 ziUa0_MY75d_8<`Q0}Bc2k}DTV4FwFpkp@# z>F1n9S&u#Tj@wN4*WiY^{v6q-;A3o2!f{n8sH#>tr ze*x)4(Y^pYUwyQAwcQY1r|vEQsdf3h{+`XG(@l3m!zOZ@sv~d0Kv0?r-LKntiq3oI`Ma(ToVlFB~(^Z;RxCG`xg4HpLEMA`M36QApH21cQ)^~&NJOtF@c-}D z?4FRh!vQRkJ~N1~e5>3D?jD3rvi!_tL|m_5DmtwMI(?rc-_BRxp#V^(tze~#vq%U2 zB8*WwCvV(>)3_R>Rd4L(B?D4*Or0H?uIse}Y?ox?82zlmp;Hki5z6<0Wpy*i%=)+kpRV3-!LR2^BN;Zdb_0`iYTSTEY%r)i_2hL8Fae6SkY2$c06_qWSF zl9|aG)H+taC$;f3qGOCS(*3Q&?vA+0XKZqg++;mM2{V6F+)XlDblSS*x^dQIM*) z|7iMA#7@z48)M?V@%Ok*txdKcHO;tk% z4a&csZQ%a3f7^6`?ClbbW#-E_#D$ltB4~eeLuC49Jpq=4k-X_$pa!r@AY{xr{x38% zWw}7)ez=jX!j;zsTV4NRx;Sf@imQ3Sc$E(1y|CL)It_WbQjL(b-|)Tc<$4lZKIzQQ zX(sN)jyJoVncUlCcv{+_G`3yJV;A<5jg)*?Y3$G$je$pRYI?c{OGDS`42I1WQR26V zCMps#G?2DHj_0Ky0zdtiB2=5YkRx~mNLk1B+-GGl zj9s69RA_-@o$w=bPMkk32AFJBL_&IcRPUzY>(eb@xTIFdj2LvedvDMi&~Jj$cTySCSPh-9stERIiY$ zTIz*7(2C?4ll2Vz?B}YslW=?go6_u`Qv0@$e`5p8a(eSG&!dus2kOd~31smy+gbHc z*2WN82iVD6%0%C<%#n4p zy3s)wYvnToj<@X`xo?=E5jeGz-JvfwXaZcCrJ=2#G3|<5weoO%K8lYa*mq|6hV%L0 zKrKv2Mamv~+g?jPZzj-Wnu;-XHKd~`J6(IS2JGnYz_y?S3RH4wTCP7*U__vPJk$~i z1dJEA?}lt4i?#y*+$^PEU0r>6eXD)1GWr|@^)!4InK5> zL04aMiO|qr?@Kax;)q`!6D1xwYYsMxrs0?p&X@Z*FO}auMUw$k%0i79f`4ZYkP1KY zOpxMzd|E__damU8+hkaYeuzoW=MxHZ(*2^paf`P7hcP>-uxQ97mPP{H8Ss=zolVL8 zVFXkqiSv%I*7OgCE_m*Wgj&(HyJzVC^KkZ!1I!sPnuv~((e!ZoH&BISzk(xD6i(;n z}}=pPaJNAqei1 z3&{<<#7vRI#K4P;f$Bf;UOY%Lrly8{&F@|hxU5aL^E%S5(lQ}vMBls$ov_%zB~Vb{ z2#pjEtM>m~L zu{h5BwPJTE`rsyL!;BDpD7Fj=3Ja-U{NIOKM2sJijb~qZ;K>wDA>dHp(AZ2Ep}*4R zPhc@n>VAS+Cz*~2!#>&TJAC!Y9t9ZOGK z-w`mGzFaV1hPPJXDySg94>SCw65?mAy?)@1o9A@ShwS=f%4(!fre)^zRjG^;V5OkHOuEUj5Ha0aQt=(9cA3JMHJ6v!?$ zHA%z&Mv!1_Chg)l$4L&k>9;?CYPT>FMW_mfclsSCC|71evF!&)VQCX|m|a6HZNc)R zlfV(RixEY|xE28=rMk)7KZ@pBj*N6 z-L&k(eiaJabm*Jx`4;rikyK4>GX9AEo)&h-Q-~Ei)5Yl)H+rWa#&}m z(&}+YYnc+J%V@soH?(p?&9+nwb3<9Jm_>od86k@RNWDSfjZK*JRR42exX4bC$+i94 z1&oNspY}+rNanVjGd!RmY5FDuWbm-KJg5SOlu}5eZr1!wF*d+T$i}ClJO+&m-qpqG z%IX@yToyMUebgvnK<~TMEnaWr{##kon1X99P)JizXU<4icfD6FAYx0g(G55kIJj`w z1u|?ttX^`W)lw3Yzsh=9V`R*grxBr_NmZ>m(N_IQXvb7X$i(Td`geM1kH%h=FV9jgD@06%+ilBsJx|%Ei z4?;ZvpL`ZQ=702mhxFTMHV)~AMY8Ym2#I3Sc~}f!@O{3lR7u>U9zV!+fA?v-n8CSx zc~GtxS{z)n$lfV2Xp>AEi=1!#UitcT{3VXT>0np)Dya4x}sT()@ZZ zB>41u`_IFz-XBfZqkH&gh7!+rl$ZTe#hQL2a@6dR8lR3)jWeC@ekXU3=ul(y{qwS0 zYwiX4mlq^Z>mCB*+tt5j?rV(qsE=wCd1zy-80go!oRmPRwqI>gT`T+ZXD2V5cnkQ- zuc^60lx9ztk~@Mj(J zHY%K-)@cZ=3FujPpT=-B5?R|25&hIZwpSLjLq%1Bt)U65qO>I=JLcnCc4!XBO!^)I z1{YS?wg2czm~<`Fd74S;b^YicuzpVMhBk9WlC4hL&!ppN zW2d@>dkK5ug;DWv?tA)E@p7lYgAJxCXIGD_+%FoykLXWp3~g_3Qo`QWXrWU?f_Dq} zabWya`=P4)ua;w9guO`-%D{cnrEg4tNaB=`WSCI*(IFNcT~c1YyJ(T~yQm1}TY5S^ z&>b%;NW4El;6N$zZu@@2oro2gN1Wi_O@>Dw^U#HAbQ2b{W(N(0AV-gvrZt+1z12%J zXk`~a>GuG}M3X+bH%hrt@!KdXa$XfQ*9H$yt&n@f!NYMZ%J8>B;smk_`La1#Lm}VT z8awTfm@xBn;GZAi((g%cLu{Ua!YDWlgrOXfSazL|m~{LG&cVpT<;7-hghu}8GW%ju z5!S$$P#$MHGh)>l;Y}1NARGsk#F-me&Lu|u>5JtN^7kls%KJB)9?J+Bj)K=iRk~@LRMe0xglpXTi*x6-0wa;XbjiSh6<&VVs!(o$={IIJIxY zfDhFKYP9si1fVe1xE`{`8B&)b-=JU*P$G&m9VJYU(Uc>X#{?ValDI23rKMhYYe-CjKbibLc_Yn z@(mmfmFn|(K#0ZqHx2}SX<-x|^aw)l@f6Dfi+;}JZ^>4^bTB8pRRV=I4`*qk&(F(R z2TG*aznK2yE)jW-_15vkT|mlCP;jiuRp67&7ML`tO~$#@a1C8zxDPCTO%ZfzCFedZP=T|lf+5c!~R8C^Umbmb4UkP}B^*z>EKRPDHBX)_X#(0G`Pj9!Y z?vse8UQUYdxWsL@E7D->3SCW@Xp^M3G4M}`b(3~fC^IE=S2O1@^Cz-fqE;`r3e`mA z78wYRe+kQJZwa2ie&VFZH6SLZx*(qD@D0hXLiTZ2A*ff<5RUcQK3SOS-bd=)!|`%E zHsT)IkOxxBADMn**r@!C>&J1Ei8np6_LRuHQrxAIySF)blZaD=PX0gcJb_*=v=4eX z4JTkJDSXAW--3rdR)*KsE4E_8JBOIGkS*i4J9h~{mGnJ|0^MkxGz5VRI2`R|De~{G zEce3OJ&1)#jW^aE7yXi-)S!+xuCbqT|Dbn{NhKhzVTwnLL_G~r#0#>|<2VgR)El}x z$d8J3r%`uC(HIcS&fjx2#~XwH`y?aKP9UX>X-h1k-~gw(KWh3kE6$!|@+GSTuL%=H zzZG)73F1m_&+!&1I#o4Yt_4deYvCmn)LxSugvi1SU2o>?w5W2iA8WA`WL!g}F1Uud za^|YyieVup%qLl^by4EQn9Y&xitdq&$m`(G{J8Ch+baGGD}}@A5|jF`aRqSgw3I+I z$thJ*k$6kd{x@DRlVl*K)IXw>g@@eo!F}Jx)(%@^RZq>&O|^%u+QH|N;<U z?~xaZY+|X5{+``9*@~)lj(&8*EIj|bqQ;sef*gI+bC@1A$aRdUYWvQ|_D#K^{l+ER z+e~O~5X@E-%H#bep!z@x4)9?+@g+p{Te7=>grZ8qldvLGNlr`7#|5$G=-{J{M63Cg z87(p}t|vkjew76)@qSSY@AIkKQn=lAU#cEKH3DuB+y7?y69VKu@cRGW4gTNN*+5IB z)`0zgKI5t>;PZbskGslfM0}KaQn90LUTCVLwAckO{V~%#P#O;4Ut~vjtcv|X{eLg0 z_dcvD!gz4lIBXuK9BG zBASEGx8OU%nY?M)vOL$*DI%>yC6CDq9%c^|d!H=u>Bao#ssUsg z4TXBc^mc@dz{tpakL@%4=)mZvcG@W_C-(5 z!t*O-?-4?0u-hbk&mGpm`?Df*)tIXZCd!Fp5aasW{?^3n6Hp3Hq<)HK%Rk1ai94ZT z;y@`{_BbO7Go12Kis6l9HIg+A>xc@4!el5NlP~QcqH2KwaV+Xh3lR7Aso7f2+j`sT z)h%;Guw7__%7f!fr1|F42Y6@t)TE65gkk3wo#M*Z8(nc_ohbVEDVv3%xcCk}|9Nra zxyvw5qW;ix!sLVcaU&(Y9}I6@Mm4K4d$#Cp?-E$PS7-{+Hq?ENU`_dqM6Q(ph7dIt zEo1`SFbmJfO_GYA8;l0Sk?m=3X?XPOKt6;?%s6-=fj#z+N4`*{aYId%>Pr(vm>6Mi zJ{sKdH!O=NlA_)?JKlS|W*QYAb4C3zL!Iy_VIqVRPb5G(lFW#mFeg;TS)s zC44+S6*P|R_HS2#RU7F>r>#_E$Z&>*MM=7C%HA6{YF6R0ZB^6e5hJC*I<3MJ5q)ZH zjl>gjt#?OPxcWxyvVQ@i z!ULNlZE2mpTN$IHSKH^n44%DvudBz`olERx^|ZW6N{nY4j;0cfR66DXzC=9 zt(@<`(*1#@qqWYA1(|tVUxx84wwgd{3l7XSk4U*9_8;{bR|h2`!o3nlemA6KKp#H( zyzUbGmY09d_PMGn0`>5$u(el?kTnwhP!pH~2+8#defAz6`HQ=4?5~Hqvfa1y85cU< zf1w0yTbra=Osk*WFd&0HA4p-+GZxa^neJa#xjemvx3*F4FQ%fyEmJ+P4E!(fGrQv- z9(r*H*R>|rBuCO%V{C>`5BIuA{Cn2w4%OCtP&~|TCtVB$I^V~Zi*xixPeySslVA>3 zu7%eo{Bo8Zh$eVVaAGt5&Adv*FmzmNng77~&YhnV1FW{=W3^xF6LDy%@ZqXG2BDE> z?YpgORaLzDt6C*7RUs)rkQ?y#O-&>b=~B_6n~4a zW{aTnb>wV!^I>{USP+I0h4bXR{OxDd)Ru|Lj`w<@WRhNHrDir?+Y(oCCE08*D=8`e zU2Ve$wdSHXVme&_v+x*ByLPXF&xv3R#*zW(-3i=Cr*B3!?DXd$s z1M)XE1i;Jrwzw#er5G;_n`T;lhBK7JA7|NB{vb0#MVHXWC0Yr{>MTF{!h_NMdW0NJ z=Lc_Hh0pe#W~WgR&I{0iXD*85SQE3Lp&ZD~e$-ZIaLsf3r`%W+baDc5<*c`HXF{OS zJ^KJ|oVDsI1@=;Wqy~?0(zLqo^9n=>QF?3>X8c1k;^_QRbzOUsn4Jm)RYmBKHT#&g z($D9-@Y}QB#=7;0hs81?_uJP|8jabI;{`A}Nkk=;*=1$zU<$G-&Jx<+70*WhP5ZG& zRWvwG&pso4aWhorkQr%2O<@P1ObkC9wu$Y?l7^M_g4kUXIkv73io#Ei2Z0QJRG24^ zV8o*{+>3PXz76@<+PG?78loA&p5Y(17Zyp`{>0(9T)`Do6QQM;-!1t1O1z|dahKTA z30yPt*xJ;9X#QDNV+c2r+JQ&NyEx7XgPOzd4XJ5GI2lcYvCe;$upN@?*~6nxK`2JE zrv2XQMvW%|@Ay;)H;iJI`^0c&9y%gC?+%H(&SH8mZ74*-dd76>yq7Hpvzjd$=B>T7QCb#LUMQefQR;7#EJzQRdd8|ZEGhZLc%Yxd zsi`X;?5~oYKYJ8C?X+8sUM_ua6L$E|m(Y8*)9s>1$7kZZ%+a20gP~KNi2}~KU=H2~ zZBeJ)M19UQJ~^JMy$v?;Rimx_TMVF$a3sFQt5bO8squjWBSIwDU_Hz_1idl)E+ePs z1Oe$axF2;B5)uQ!$%Z+$!vUjijCTaDAa&1M|6xhB4wEteir~J6v&aCK&A6{X=u@lr zB;Sk>wfc!Yi$XlXAk9&Pz+gSVli*^g0N}q~3LdV}p?^^i^3q*~Ssa@3$NyE@S4OoJ zgz;G>xA#8#Q#&@oqi+*1INmE~42=I=q|fO@8sT2YcrbSRVLmlW<6KbpVdk6y z?gtH+)p{%c+I=Qd4En&1iU3S?B>EkuKowupFp_- ziuo7!i}HUXt7Vn{H~(cZrj%~<1gxpooI(UM6jumZ!l8xbZaI)*wl@>Y3aR@}YC(;Yx8f&!|neC0_Q_+vvFq>4^rsB|HGliXVMb5tfkK!qu%8!%DDO zG!0C&(o-#4;ZH!v2F8Dv?E7^4dS1+rSZi@OdKS9aS^EX`X|}T+-mh4_bJMx5?MRFL zljC}$4QSWoJd00|m>QSXM5V^}z<^fixY*HmRin!h9@_*)aDY!vE;jBn)=o#Rs z1sXH6`=TfSyau1+f`p37SWI$}A6jEsnuQ9Bs#sjZ9i!Q$N^b@iRW(0#{8(Zbvh3#X z{)7-*6_HWqEKUM$v|$Z0#1Ba`txXxp;zIIl$jG%64?EbMr-R5<`#N!DD%P@hATgij z9G(3=L7_bK|^}^H^_wT5QK8GUvK+ z8%T`Tbti)z1fX$uLUOLPI`&YX7V@KdY*`5xK~i#a=Qn$Zujr&B-o7kfdct_lbyorX zb`O?D{e-bxe!xUS_PYkCI;BUN=1^<+~N27|7tg&@=w#Iz_iZw!u71Q8Mm-oZ;mnX+JnQKRuW9a0q zd%y6?I`GPO#6GIs%Sq;7Q}i|71fQ463@DG!+AaMkz$IZ6w0y+XT%wQV;%^}NDjBfVFUa6Z)7re5v5erLzXFrJ!cD_E!o|24v`4ZZbWJB6_- z;WYPfg4EpKHg;aSHeu5x0;PqG~y4%v(X zHtBImV9PXWwkPD}WTk=D7}60?#m{pta@XE zzP5JyW>D>qLS;l#vdT(2pYwjJW(&;GlIc5y!^F2WbcKgY6i2A7!$b0P0~-t$y;%9L zmZg6H<}gzutkBccEFMo*Dh zL`D}Xok*PriqivCP%0`#(F_T&Iww$S4SonC64(?>l)GWY5w4_WadE23^$WoQT!fiM zh}6@}q5CYf!JP_zcT{}Nc1&d4e{2z>+j+6>&{$NFs*!r*CsNfkWRPa+S))Dcn{3vA zlO^0IW!CB;B@doJi8(VB6%pKNuyD@TanO{_-I%ui7f6dV zCwh~(UPY0x_l^vkuW7T0#Ztg=Vc6#3LK)2ne6sFhYWXjPT|};>VP2W(aIZ~Sf!wE~ zLez<(4T;}jiW}+mU1UP{;T;g@DDSy`buX`SebK>P z9HMy-QvEGHX8N>+qu#eFoGoJfVEcMqglRPJfEoLxqgwf-QLrg zlib}Eze*%76U+}7!Glxn_(eu%>OEZ}L=@{g6YHN3gyOp1aEGANKu%c71P^fi%?T2J zrNQJ1BPPco5MAlS@*VO#I}Wo1nP)e`;cWiKvR+8^8>{i&)E!*EFi!LKIJVWe{L6>+ zjB~T(dfq^?k`Xbs}iVQWi(E1#SD5vorjr-mO|%R@I~il>;ITt5xyCP1gGpr zOkM}N6lfEmSFI+qHN1|_@x1#=J{!AytPCT-J#=VUSoP6t8b0nhlJ$PuF<-xRYFe{} z!*TIj6KS+{*DGVKEx}i?%jt1~^SAHBG;#=G?u?w_Q?{5IK+N>4xg%-wvpmWLRK3&u zWc-Ni4=`l{)OhUg%;V}Qbol#tQR9h@fFK7c3wpp6mEJv%H=)*5#!SS{hi$*b(@^NJ zS&F7?Ilc;Peq?4Vf7Uj1-@|H7wMTPgglyWO^x^A2F&?6K`lU6>tX`C*GdV=F=ykkhg)#6Ir!RX$V^xSB|YzIEC%ux?57dgqjl#UgY`pkqR@z^W^o2I9Oa%Zkw|Rb+ zVGQIaj0mI2JG9ZVmqR%w@0$%&nwiLEEzFWpag9$uPk$v+U~nx`bX!Y5PtZnmyI}_; zaK@D!=ue&Di{83>oS|_!ocxj?NehV22^SX^C%@S0UxLX2-_0#0ga>crYi>qpQJ*#k zA$r_w;;d=XEI;nRo~mOqd=zq7sNEhMa}^?kZglYkf-H?bkj>ThS-6`Qk%2D!!TlJR z|8+bX;C~?-Zb1Jcz(jw0zOALH$+d2wKeKJtC?wHn&WNl}-ya?u8*AQJ-2O=;pOm?Z zP?=I06N7S6Rg~XTxrA~c0n07J8Ef9L+-?oNc+r{9xrTu(F;!C}lZ7y~^=C`IX_t-? zN1kJD*JrCzteBQh-?|B{Itha-iRHZM9D+Sx-+$B1X*aaBjrr?}(z@OR=6XA?l0*5L zcV@Mr``G6*v~_ydIPlsSjdYlLuH?6#%Vs~Xux&5GCdWqEezxFZeC;kyuBko!WgK72 zp_rsne0~k8R+je&SJ_=3RaL3=DlVCDfbzbm%QcP@-IE`w5Gj- z1AN2sAzhuZ{)|mH7>>QGNRk?dh{M7R(i;;(MfoEUKF_Z%OUMiZ7-UXM_sHJ-ylaC! zl~czaM|EfRA0vb1Cmv{_ z-&6}LG9T1g?B`N{zcLeJ@t$CyZorxaD6%wQ9f)o6g>nLkhX9Q7X9l9&=j%*rjN4L< zj*dS311)$=cF@croa)9DDhD|!iTqHVl#X=;4c?3XfauZjo$!u(9C;-TYy^CT4ZRP( zXRjB1d~KRH`KwOPbdy?jWoRP!@#V8XG1Hx5|5>4yJsjafb=*J6oj`bgv6?7kX5t~u z^l4T=?53Ql66O`sKd6B_jgdC(Wkz)U-`dZ z={?Js1c;zNKk|O`-zEKcza3ct#XdQ`LiBJAa}A)YKPZ@>#10ZvQLp|&wes{HSyZ0{tosHb*@Lux9)pX7Ei*||+D{SLREL@r1u79lN5 zTnTKyvNhrLyEyLQscN;=4^<9=y|Gon@#II{`IVsv4~tlFTg|S={_m%Pq)MRToymZ` z6fz0$o1Ea~#Qwh$Gdw^`qbRpB(<5n)X3JI%RV1{FO_Dgv&pVhHfko2d%_`5XecA0& zaP0azC{)RaGVt2uy1A6#lHlC90dsRsOrF4srD#HC&`PWFcdmm9BEo8634PM_)kl%1WYhAc-yF5sud0aL&esCc8K?xd6C27<{nGTk-aUJ?Bd+$ulaXQh=A*+t=h0ay76+aGejXv~Lvs7#Aj}5JRto@P^6>C{2E^SkBy=Ft zr+>{?VgOWO4e&mImKi=VcF$h z`+_W)fAI%Zs*)}zVzutp$dvagrIQXe`aRclZa-QFC-a&32nLd&PJLC3b^Vi=<{JE7 z9br~HWv75KXXHO67CSOP5C_bRQLX}`|0OaHVVUm@pW@zqt%~RiIZEvII@B&Tm-xB^ zUPH2gqvWA-DJ>O!1;d%b?^yIHP6>IR?&!chCa3zn){1ui@sRexi_r6Uzq9*$&OL1D z=jlY+7yml5qKZG`v?}+X>#i(#yrk^nu>STRz=))VZA-!ha$vHLefS<~XYg_YzQvJa zPTX1f4*i*X5DP&yEO0~}{XYzA)s*I$M zFm?B%T=%UmS@P3~7why&tC|OXLe;lY{{{ng=53)!`{+D_(Y#v%a%oS;W!JRfbWzt$ z%z_(9bXX}8LFP3M*73hF@LZ#1o@Bp)8d_Hqmr5WM8X|6My%Lyx9Tp91I%H|D30;EjguFsUILLZtNyZ zSozL)TO=AS!D1K@8^`ZL+;>mO-RHM8QXm3<&^5@pQ#3Qp>9`@|bfp*l;XFL~ET4`K zp{ahGT)Z=Xnt=EnYnGP`&Hdg}c(k+sm%?gwkNd<;b;twy%`R})mP&ETc?Fk{Fm##F z+}_^y_n=$iobLon+1h-MUU;32ik+z z3hRfC96P(4&nD0}Wr*KWGPLAxS5Uukr}&o$+tsa2^tJcr^&))3si>m=?442u);ps% z4NN@<4h&JKB+|rS>mChYRNW7x#&K}j)VDxfCdbdGhDpG=KqTYV=`A2H6k;av3)-xn zRWw*+VyoTH;JJtig>_NWQ7IBpDEC5mFgftKT>;LLvHNOlGJ8c~&!7mdT?Bvf_!6>}BkL`2(YVS&Pz?F+ia8H5BibdI2< z&rE=_>qZ1XH|udc3>$PqeQEyoJ|GDpg_M?)7StPNVSVP`1g0byh_k=8xHOHN&F~C; z_d9efTW#RGuK={1sqB~vbtXigE&BS%8hRyb7`-wSzf5iOphEV~hJtmShM_#Ba^5R7 zzn~)J1%jJQ69RMda-hxRKT`((haUaE<(dC)1^fR9M9=m;Hz#r!h~Y7pRimGWQ{YO6 z;H~Sv&q!lo)^%BLd-0ltzUa!Nl)01G&qRk1`^lfNmF+4@=Ize2kptYQ{{NEIwQPzO z9$b$ip#X%9QTxy?_0HUIg!M-%IcKvimwH8@Ls*s}hUkKX$F}s&VJ<$p@5>=T;w)_d z>sq&x(#?G_2Eqk-(nI5ucHJ)i1krW`N30Ja{N7wDk9FdJk4GHH4i~-F0c2~J$L99!D9=oyTk5pXU7-{BN<3q{#MfOK#b^sc^QmrG3< zq{ZES?;UB6vdK*HBWKf+W)67XI*lD45D+VJ_l=Di(gVW)GB|G6C znJU%c%CQg@%0vsSf%V?K;iA@Gl3rEl+pbrQx5Lb%HenOd*t;TtVDJU-tNvHX4UmJ@ zV>zB5|NdOhhO6Y}&`8xm$8Wl30}Kq13@+5_dYpkh1T91@6ltZP`pf3*K{o=rmE#@c z$-%xue?cF!_bN<39SypoW8)QvyssuTdJ4lmqXk3JHZ}ObS#E+XK0ptgABP+LOC>zu zYdGhF@c>rh^w0keiZ=d8UL94GFyL8??By%BcB82scT01HazMTLC-IXf6D2J+P~kd5 zS>w3b1^klEKqfsc5>%lCD7r5124*ye&N^HnOLh)U*vbMTTH}p6c|XTzj4;BGP#(@V2L=5TRgjKQkv1zrlER zO^i>tQmJ{Gjjj>Rn#lZk&sIkt)pF@s5PZh)6zF--d6NbQhcvA4K~h_kZ-(>F;}*X& zXhaM9WNXE~yTz7b=J)Es$DUZ~p3i;aPiI7E-g&-jtmO~KOcAXYLu-x}kp0U~FO7Id zxhEPx{m6jf^m@g8A||QmYd8$ake0%X>=9wGa&l6yQbKJdW2u8O9DGR4e$eZ9bO+Ph z{jQfXlQv;f_=K!y<0p7?vEeu~&3wC<`(XYhpYHv$+S7c-+izu-n$4qf4d--J{sM#L zRDNkaCYp-lMPyfhGWE9wjDP8Sk|vM&vvHx#8p!*FC63{kHUbd0_AT(QaS+Ss)IJp z)^lsr(!*kqZmZN`o}V7xJbz;Z-R{n^1;!NoycnOsOuawcb_F(^JA(SJQ~ei;3O6F;NkxApVoc#`L9^ZBsd9J~$68b_8g(hHYYH@x z0b_TU5MHB?f3sIz&ZCxN`zim#P3VHWh48xAw+EDT4H-j?#hJ-ko8;A0$^q)}Et)gG zvqN5zeww^xg+*(FAvz1$asP%cjU&{$@$WGP9w){H{Bl+AhpiQ!f@|-&lfh)Ng`Fli zL4Zo~L(>xZ6H`={$TWF|1~udo@H3{H&gl8Hcj**%XmXw32QgxqgIsio-nJm&Vv5u zD`)?t+T&VAxM!`_6C$lI3wT5KVrER1VYveTumZ7 z47n8F$|!GXVr0v`O+O!Y+vIX6if(_~OmUUOWCaow>|eRgJGTdbr;MyMjDik`s{vZ; zOioVr0$rlo4qKMTH<-I5X$p4mIPX?5%?H&y(=WQjc0i2OvOKpB#wIke@cCL>^HXI` z=Ce7vF-V|u3z3^4mz%|EVOytVxqV^re^D-CV@lN2W#=NW*}}xW<3o(xN-va+t+&M` z?^NyOZ49lp8mxR}e;2mbUbLf?FT+b)ok<9c|EVJeko9*3 YC&en$(t+4}!T~P@8PyMUQf6WQ0dJLI&j0`b literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530010125596.png b/README.assets/image-20220530010125596.png new file mode 100644 index 0000000000000000000000000000000000000000..9dcb3fcfc67bcd5e62195a76d9196df623ed76b0 GIT binary patch literal 49620 zcmbTdV~}M{&@J4yZQHhOPg~P=PusSwY1_6jZQHhO-tOm(H@^7(-MA;>#Mx)>U6qB* zT$xp?!W87hVWF^~0001BB_%|Z0001YzrQgMVBdFq1Lnv900;miMFdq`GtM{MJXH=l zpKqqpye3EzyyPJQ0|nIk(EO0lRRk0i%8sjbSKHQKEjyb_E*@MS9-CHwSza|dD|%Em zR?fHip(-E(3O=&_mh=@E?us*tUrBNB_8A8WMiBDX4Y=*lt9CO!97%J?IvQs_;+}HI za=@cRfue-)CxGy0pkcYVxcHX|E{Fgk*kWLAq=9$I^Yf$+Rho4j^ZO=3Aa$Bp^%A@b z-uE@gPB-vM6yY6lUdQikmcoY6N#>8bEjlstSA-&WlwxF{!g2cN z7NV>g^5)K_z5Yr$)b8D-^j{}Z?h8L=fr;+OT#Nb->xsq@91m`F!1=t%k*LHuLa2HC zdT!;zv!127KVi>}%3hrce($l-)%#S|)oPBh2Z-#^PVRmOh&V!tKPxRho5o7sQXZ-( z?jB@yfEtO?6@4R9m1x&$cQ|X533|cYCeHmI#rC9wdZk>6oa8#}{Y4pt5l{gBuXm8H!tS+ZkAL zJ*>Q~Hz!WHjq=eQZB9v!^>pq99K~+jc$BShzeM%^niY$FqHBCNPNvQJm!ZvZbystc z!0>?gc|A@PeoiI>kmcS6*V%jPp=)I70S`yuwTpws_sRq>7o6IwYwa@AA!4Ue`sYpT{w9Cwm5U|4#{Zk7L&)&XBnS~`V1V^PnI-ZWs9KD+W! zcItMWn%d3WaPI$`B+}!zj}KKoOkms)K5EmZH*i&N`@|x?FFD#bu;%p-YrJ;C)~#l} z3~>1+#ZBE$Y3*k3koYuZ%CI+-m(Jyz7ioiMZ*2;u@Vq>B1Z2ntD5R2x64?_o1F>AT z;s6?8CW>5Ucu`2d0>Rlf#TQH8F27~JazprP`Y+CqU7PJT{Pii|QUVX12J2VutLjex zRHQG*B)FBUg8UV~Ic$zOcP`>@RX)xw{}&zu@F#FV{{1iRL+w8At;gjsH2q?&A?unY z+f5(7ERVYyp&IWs%8ASK@kz<<@Z!h2bx;WB6wU99jmU{q5g|=BNYC&Y`*0XS^o`bwE(f@!k8SU+-0J*Vd)%*= z6c{`$4!>C(bXM@Do5_SX$&W$!7w^B29y#HE|1DU#-b!wIoeEZAVhV@<&Y2bE%Llw; z3Ne2i-W^h_-;G*&nFvQ_X-ugjAeqx67aNLhe*UxZR#7FJ>qz)PH&6Pdjp7sY$4aryd2{hoh9@*r)qcV^1h^4kD=Dsru!(h+;uH}^^C;q>ief!tuE zJqtX`K0!T0Zq_vQ;Ilbha_3y*J-bkO((@_zZ}UA)l1l_K$&odtk}zKsIZ@5}3FubJBG#)%|NrNuk2}Tt>3o*);)3Ai`MT zog=BMEqxAxu@4sR58mg$(YH5my0hLKLFG2-qNTV-KJ3wm$%1V%fZ7LNQ`5SHM|r? zM&Mwsm9yQ<=sn)rI6XUUo)^l{PLg+T874z#mxssbtw<&OhTE%7o3eJe3quJQ+$U49 zwb|{tWc7ScGB{kLQ{BwO(N^e(8FJ>cS}>%gI+z?-Qq+G8Fa*JU%PuIpBM@IBS2nXW z+LGc=1~2}zAX`rXiL)Kp<*$~tHBuXv78z}xTh$c&t5*mwjXlMDg|R<~%$~%VG-^%v zP+_lAMygwa0PZ#C(!ecEIIJ|JZGyhWTZeNETRwkzkFoJ-Zi3>iSFv|czKqke4!n}{ zfGDXT?sVgArM(hZ_T=mLOos-_YF~C?IcW-z7VLtLXB2SAt)#rrxN_U}& z7K7E5=4xaKlU-SMCUY4y%u~7bi4ctkO>|ie+@6jG#QD0NdydW`$b#Vhei44y7k$0l*}WJDmA%V){fIPcHG?TzZ5EGh3o;{ zEZ9py4JGKaP)fm3D?CiW!7W#h!5YM%LD@HlB6+As%G@pF=WBl##~?mlsASyF90F*$ z^NB9e8LN_E0O>R=u_~+?4`}1aA047EI}S?^m#9Sn8L*LuvN0yqSuWkW^6~tuqRe(ZMa3(mT%-tNl9PjCzmw%BJDuJfE=osZtI)V+nj4VSULbaJy^F?oEgwsvRtq+U>3V_od&6m607NNyrt_g2QpK+X=?slRQ zGibr4j!oiKchLmngj!l!o}8TYS~SKdB{@xgxx2fUR91o#P*X#fH-2rsQ3*4x&bvui z0PpO~&H%E3NCBYm5A#8ALN*5n#0hvc{emGZ*gSZPCxx(3Slhj6;rheHeY3j9a2(m6 zwBElii9Zu(CW0rWtOWROp+biJ85?t1WwLHgi2-QY3nNwRdk`x#jj!=YwC@`dy=Pl% zbK(4$dEQ&eocBz9@;BpOU6{uHkVFf28E4lA>!wF{ye6eDJ%*6lf`pR{7km^PVnNj4 zU$VAl3D>jvX}3t+syL9yFeBNBy^hp_v!1zz^dyg6j4%B97Wc!}BrfYyYwauF0%6*g zHo+O#ybe6bHmBt=6Gr=e45$hKtk5wsUP00N#h9%mdi z7U9J+b|p})#c(cev~QykC&SjimoBN+b(~tpaOWM#m}_$&xXD)bbGd&8BUox97#V^lDIam{K0K$@wo|&E9{%Jda zc+lF~y|Tp}Ot9&n^A5$*7)(hRpM_y{y!gFgsl~DCilwClC8$HA3`|%DzG~V9$0O^Z z-bx;1*~J!?mcT^B3yMXMQrb+LQ{)Vb4evcZxmZfl{<;-hX@b1Q?%C6BiG5v^MsNti z9lgM4aH*D-pe2&k=C@bAW&AJX7mm3Dl2U6d3jcvlLYNjCqO>P&1%AGW*R1*Faprde@t&OlZDn9w?wV${Rt1m4ihsr3-5yS`Y$84J4kH$# zvZx*_w|dvkEHPMflaw39{EOug%Th`g&=}Zmb#U)Ft!xo6>Af@2vxneu1D2=4$c}jg z)yjf=e?!&RIf86Noon2vX`fn2j1V#YvEk(LMqWH+!$B7Nvn9c;TA4k$%8Rqy63lv~ zHirjpFYh~A1r|R`)336y2jQ+zhHYkb+Q++m>*)u>iD0`@7j%1T|NUt>t7@-Nr;&&c zoI1*{tBXgaR@JXn|GA67>wXWqNJP97kVB26a=`4z`p)BOgJoa9y526cCC-nF7R&*Y zwnv%%Y595G>k)YGj$}hgh6yQQJSYsW&vZQPCO56iJ=|CB6sz4=AW6;9;zV5iMVY1e zrG&;gg)O|1qrdt1hHL z-n;=TBYjO~6#BgzX7Z}H5osc`3Fq*X&hfc1-?_Er+rbdeY13a)B_UZ&|0>)M5Jp@! z1f^uCaltMBz%_jA{Za{GnUBO1mt@M|4xIKSEQ-a(dvn-#iaqoaU%nZI(zN-)-qK@; zKDiyL(6~c{e;?vb?09#QiU;H}hXPqH%bE)2|MXRva{s)KIC67dNI&nmE4F(62QTqZ zu@}R?F?a~yRCDD=WKs(Fs5BEF$a~|h`&z9u>+%)ej&jIl6b$@myx7li4U!><28)n-Q?>*Q=KSdeV0SF7Q(J z4~Hv$ayP|$D9@3hv3m^Pr!9b%nlIOVgx_vy>Z<5Ai%Lb0(s1OTsL_=Vb6GjJgz1Cm zX)sWO+VlqL9M1!(?z=hH%`f`f{;kvJ=ln_*8g&^ubgtpI>wCxP#bpUYTct6$Xccht z>zLo(SY|>2D^p<0AJWM@UyxU$Vz*bBBJZ4Qkh2FUx^W5+DOv`1uhbdQV^&bsU?LMDQk91W#uS3a7QKKA&zGlh?n^*P5&=v|EuP2Kv07HpF#xHvuf;{^@wz z6TB-B!E+)=!e^zUh4YYOG-_XYe0+c#L}C~Y)gPxlxn0D~EI;xLtWzqdG8HCLDqkLs zG(RfOYzdSBmijrG@IP~Bee57zvUH5lDi<+$jiMCEX!HfhR~yXbm?oX~9BoWBHM$us zi!%_d1v3&ybhI|x&kX`QvNkFoafrT!!8xl=6&m^bfpEuiMrgQrraWb9^arXFi%F%i z*kCP9$pJKCDKU@OI2)Lq?D}gcS`v^4h}1)_eM!0Ty0%4MKi>M7x;(lv*-#iZt;p7t zW)bHSYy@nGHYnGgvMzSLG16|ihl0K^8fnuYz?0Dj;Mnb#R`2frJz7z>=NApi$7H{r z~T*6e8?@CH1FQa5}oOYM2&&JzP zDU3NR12U177Oz%LV0d#cGCz;pbdKE!4A~Q;TuB3sq{Zng1FuMc>|eDeDHJOfwI$|( zxZZA>S!Rv9@}GoAust{o!%QRtUalq49tyC`-b;@l59F85hm>^(8AYnwr+?R zojh!U!X0@;H;&{N0zkkxBJNy&ni}okWMZun{{3Gn-mM>_vqsBCC}HRgYWLV##+ zu)hM^{Cb33#1bTSno%kwBJ*GqrDb3Q$q~<=$-^F%AcLGXQ;<~RuLK64#6!<4&Y#O` zLWC0ZfPGk0uYe3Iz@GO7a%U#%#OkE#fd6Gd%s4VwGBqLIb9SgcR8m3>GG9W1Y@)n> z7po#sG7Tmah*J2)EQiaz+}0h?Nh`YUCC?Y83Tq)LWWBIkzA`e&|KJVYZdMvjY<~Zs z?NIx{c-)pNn$M`uR{HNvwo|bH6Y(wz<}>@R?E%A9e~2%RQ8UN z)3gSy-z1XEK?H`Zk$JXwW6Ik(P#_$~AyzP3RP%4JFRcWDNH!F{2%OW*LPxf2485Un zBwYQVs7pkQvng7BdH~8A5QsG!i@CYc39;?c-&za6#+^RcaQZlDtcs+>L=j0zNbl}! z>$RqxyB7>jdy>M!LSRR6@v{r>Xh-fRFl|n%WifDLf5qNr`IP&hwjv$c`}xbgAmtUB z)Kt;Wew|yn%-8kBa4dXj>?5FRqU6FHPfAkxh||Ih=Oh+c z6p-T;wRJtinR=?%per^oq^;y2_d2&B0ZLmV$HT>uvxPRpIvdzzi$@ZI9x`qp6}nxZ z7aDb*BhVNlCOS44hHu-bSK1GN**qOX6T*zg+sqM-k(GwS=lr$;$v87R7O}2h|ItEs zQ!cGq|F1*bwTDY#$A6q&%^7-VMw-ZDXC73Je>)n_ee zwcC+Ca~M3%)VY9@%Q+#=@()mtUdYTD#c5IOMUwJJkPpdOsd7QCJsMW>jrLArr~U?h zNc&zByRs=VSg>q}X-Qjmgte%I1D-j$@gL3w;A6+&e{iHhbJQdj;|&C-eTH~;(w`23 zuSj75VMR;#VnH@d%D^>KM#2+N&jF8mLQ*wv%8{MQef|S$Gvvx8v72ER%)7vn;XfG7 z1Lg3_X(owue1H5-SRil>q=t}z%iyS#3`vrrU~t;M;2D{4D&6TU2!^9#^B$;N4BIc4 zF*0tYyl-D57HzXWxhYR&#*oP1jzh7LbZ#97{=~cJ`P!DNWLaAjldqqFTn=1QXeim7 z_pAKar$#l=dyOsbqe4mag8{UdmB5qCzV>-Pq6~(rn3iy+t zj=hHt$q2Y{ zFVOZs?6!N2DNTlNhndSJhY40-Dqdih`l9KvW2xg<7N^)83k<Zt zb}DG*QUFd{rTs%%5{)c#C*1tpM|1hA3an7@nHK9mQB`C5=256_%!jgpVMUl5E=KarRtqDXOHR2^BXahek5b zwePTOt1k4%H@5Z%&x&=8?oIKfAb1{dK3#n~V1yLd3>x|sVz*=+j6o+{Pb#eQFB-7R z#yA%}k(YElxFc*CYMwJ({+dOs4IvH@s#fy}J?_RC{cSh~)N?_0dfVEsuI})Ah^AC$ zx|5WUBj7g%Z-nJ-F{sRG*x}e1C6s5ni=?{GE|Z^>)H3C6oPd*H6d3Y`Ya-j3lqIJY z4VX9RCu)Uo4|x7SxOKB@YMdqwp+gwAQn!}emzhmyJ4d`6W-xHh+BM5hnUkUks?E7* z4Yc~Z$9O1XAb3rWvymJ{x-vfgZe%qq0M43iwYv?;TGg*qbmZSvHTCxEd+~x?tvhJ7 zO0(>5=RUdQw4(5ZIlDC)2BQ78`O3gr_d9ga)kk>xWm_`S8szFzx7UxJPG!0X&Lb zWLUrFXj?9u`bg%Tf>DRK$TXyrR*34fZs!}P7j&aNchrQgRJ_qKhg73*1o?zig&*J2 zW7J2m81sv;;8RzMj^itkUQE@F| zu#KJ+Xm3oI5S~W9Ptw&{4)y|#AfEWk)ri$XEXheQKt+D83Jov zz!6PcloY1&Gx75^wB3nw&*ZEy`;byDvblMV;9B#X)?>i=;7N6flRn`N?M8GR8KATk z+J?(#Zuk!NXrHf5*>xV;fd044!7FF|EXNzgHL6ozj%j z$m}V#%MY?8a+X~)VDKDPO-7AKGsm#V49(ut4-du_Rk*=2}$si@v$U(sqYZUtbnV?q^=+75Mkti(!Chn8A>ICk%1 z_QE*puRCVGb?tz=Oa8lKn9z$SIXGfWW@{4i7`5v?{4eGwoIfs4HFdshcCdWmxDH{Ex|uyRx~%&wPPrm^0VFAcvNBKL|sfOy{9T}m!* z@;+5D2cCU5I$m}?aAp&go)^;4Tg;=-C``^P*r;NzcJdpMDOy)yz_(04cF+0+YqCwB+ViE`$p?1+_vV=!O*FLYM@JZhLk%u?vd@7^P&&cYzQ4faft$P_GHE!*j0y@gG>84)CRT)G21z=&5p7YK3j_a zt#urv-9<4jRoYt-57e2XnZC8#-pce}ve*0eHi_;>wP<7%Jwf#`uUw;AjioR#GFd>Q zCGXYy4F)*2%J_#ajzuQ8iyAvGuP#uEJ$moh`t|y>a2zpkWu8`-7x14gee4a~4O5lI zbv^!YP~#Hl|K$SUO7}JLv^<)2-1l6$-oV4(g@W~oP8#k!eMPOIPa3%c9T$L*@wX&j zb>9P2cRYg^@yxbs2^o$1BpNqwjq5PG+jcXikxqHyk5%jL(7VX*q%pG+MVv?{+YQAe zGkuKfOV1OTQq0JshF8dW;gAQaKYmfOWk-6ncJH z)=P+oxFZ~N684H8t)-Wqo0-l{qAz#3fp&+z7NOAVPF_6G9c2%q)g7nd&)HAey53=T zZ<{_ME)Q-@(r5kc-H+tJd6WOMdky%=xmx-h(^?S&)i$_nbjVkm4BizlvjY%NDdde0 z%T1S@5~9wwzZMIdWxYN@<4urYm#@1Y&3$;2Z$nQdz-Iaz^NwKZeb+MakR;H9Pz;Un z1AEJOPIk=g+=XrxLv}|E?Pl)?T@k~wUt+0vSQ0KMBhUP9Pv*s#_?fw7hd+BexXz9w zN3coeaM8nw=XTXT%V$)$uLS3|sxvN)B?ug4rA`v#cQMCJx0^koW9Pk3tMOt~qN7Xg zOO}@UH8pFOJ{76-)n2rRNrK#UJov)B9{InGEal{nzl9Npj4lei+=LTn?}u8-sl~w68NKt>-U-~^4Y6rA;vB#3sXuRl z$r~%5ZY!l*Besp@lu!=tuHs#A1pje67rg_or?b@qpNC>?GOQ{8J(3=RF<_^ zFCCwlF8(-N;b6EYHQlR4{5aQm^u%@2eio+ZObQ; zzZ8Q_yco!0A0eI~$ouPnuHe~q_BNsR!FdcXR0{jp;m`b^dlB4UM`)?*9W-JlqIv;5 zf7}upy?GwqIRDfIJZ9a!J@o+#+>X>fP*yL7Z)T0{Lt-vFS_ow}vMi`7>w0{G3Rz_O z&F5+ClVX8&G!`IXS?T5>fxkz(yPZ_<%4vn9D-5cLtzxzqU!D!FsZJaU%esEVDU*AR zV#8^A@o%Z`#xql<{tduY*eR@U@{KMjhX~8)oqCyR!8T z!qQ^HbV+6;Ixe#9ylSs*P^D%xPfL|=sg)le%(4)CX{n5W-_qHI~lPMqJ>qt zstAu9jVgP3C0y+OyjLbq5R)e*=jHUYFz?~Q`z2q9V0Nnhb&qIOUu`@|+{~13%e(Mb zLF>F=Hjt|`a9VLRdOBz43j(d~m)la4W?lG59oWqMd{*UD zGKoQ>w-p-iY9wW3g9nF>o3C<|Akd+!SmdH|`rks~OYfb4LWBXV(7RRk&leXPLqNb}X}rXB#;?e2OTUJ9 z5r@9GMUgu64mvyXez_cUY`vMkI=J3+>Zm;+NZ*>Ne=gqIDZ(B~;NO>qtLFJP$6DEx zt4@aG=!^{2l)DXHa9zTqL4;%icruPNkipCd;u|PcDP9*XYMJGlOAD!o77p|2d>VsW zl-KbHl)|FUumWVXg;KCR#@A*jKtQA5~0V9>m~>NroXtgaG{?MGVPL{pU$=97O;BpDIQI zRQppHh8Qsv^t;G!4A`m6Mn2n5XCqtM@M>13YP&!pzXGr*&|l-~BvGXAnm^U>k*kRi zB)2;wlzkERE;=FH2Nnyfs_bZ)ltq<{=TD=4fH-}#%ofG&Rn~u`U3Z^^AOD4G@)Eed zcTUWqNAg`Tz0$(HN48hp<9^1-o!rVq(RG&890Uv~a!sr5#iWkd)$!#EwWB`lt znfrvpDH8WAdiof4`|V!qXMnl@=-$w3m(Gm$2BTbg@T8=qB&4LUZn;zraY8dg{kdkT zRQu-e^K%FYOJU6n#d2#+h|D8%K>i^cj`a@TZKtt_+K9#T2CUo9gRD}q_7}vHywnsH zA*RRsZo~_1K4TzRd$(CweCvp4`qEUE6ZlALErx?V%pqZl>bLl3qSkZZTB*W5gWBsE zar~X9w=`x`II;wDiL>dVNnxo}ASxY>9;#eEKsJCnbR&3>cE4e!I?u;eBp@LP`_OBV zeRT9c7lvcy^f$NF{QA`cFmBA0k8I2~J8EfmXA9$IUJ>Nos{a~&C`7ed(_nqvLjK7C zvu?=~5z=P$b29G3IfeWX6ZI%kya<}qY1VzdKHeXyeT=`C>|3R2OE2;DJp`E>!IdWds5$zKu}`#mJV}Kr_1)n_eo0B_=%|#g*Tb)M zo2PBHJP?7$Abdi-f`_xSBg9aiJk3!l0xDjBaDJQ|a1?-1&K6F@gtkD-L$vthB;nQZ z7j3=7(Uz93G0T~BS#>Mbdkbc}5w>x#i-Rv}$)91Kr+X9lW{^=w^!JN=GXgl=?l1&v%fUMc#QbtkSEZ|z;o{?$h}6)4C^s64FHm`knD%U z+2hQfRoaDq>O^|!V`;Onv^2N0{P)c^$j**YEysONPdc_SeR;Pz?An+=a#RbM^y)@x zbB$0}?78|^t(?DPfgvRKZN7ojBx9k;E3se)O=s^x^7A(2_aj?K+8+puxvYCTtd7tlM{>y#!xG*hTQD=xC! znQ}k7E@kEAl(e)5-&--QfsOZIi<>q_d`G_d?N!EKFEPv;vt7ey5stF?z+}u#4dKz- zaD2=2aNh9e-U+|nPFEJ~Aw~Z)jKm+qpc&)Hl&fkz#QHXjV9ygI1SdGx9L2d_KJ#9_ zDdI{)x@n@z<=!^-X#0|ZN!FODVgz18w5`Efe(#?47@w%1G*t|pK-qHRez$-|086gN z3U#RS>YH_5=k+f)?j`vNLhIu~)E_ex_?{sv1`G;nYQynV#uP_pcz|#A9S(%vV1Wqu zZkNu?MDACF8R8*}0V&s22(3x0BE3rS!m=DqTEV|*k2*K0^Ckx8 zcB%Jjwf8%WkrVnRkw5;AW7PI++FZn?V+!$jR9q z7eSD^`cm=5k}MRgl<)cLjteHs1U#il1AKwwdZyMGS~GX9s|zvkOJ zBRK!~+!c62dZ}TT%|dZgXrEfnP|{eH5*9L&M!bTEC3_{W}hCsYk1WC*6me%5vN^o^j#w@*o1>H-+YX<@0UwZ;17K?NuabhmJPt;(B+&+? z(`#FxVtCuO_*0#iN(YDYgAS$Vs>*OGytuTj$(O19KTuc88{X}7DPdV>xe=%+o3`BdGc$x%G_TA7@k1B}Q~=spvgeS6TOb;# z@?$Sq6z-$3`LIE74C{0fTs^ui2))DGv(`Z&~ZI>bLAPyP3JrB9e7)9H-PQZQ>odjEHae6L4UUbtoZBeL&;=6cS@;*XANuy`tXQ!5;xU5<_O;e) zY|dAkQF6uk4GoUh8}m{CM({g1R8Np)UbA_6$UvO)#lP0Eb3*!pro8+ws$XhoyTUab zst?;*oaNM7)ZY%{wm`C>spJv^r##H6y&}uwai};s-cX+Oq)I3Z@tV;$BHLL$!i@E9f@MWR+_4 z)f~anbj;yArzF=rQO>xD0UVdQ7w1)Qog5`pvSTaq86 zLhEAiTfT7KyL*{7V^OC;Qz;`{&s2sK1Jf1tzf4oLy>iokIR~ih0@Q>P>x2^nJte$; zfoN==p$WOplAO<1B9BeX6SF;+z1w!eGx=bKzpK(jZT%{NwcJ%Paijv71#%UZ!+Nwe zy3@{h>k+vnEp-|n8xN;^?H)c2vaNz=*U92*w|`PF+#fBaJI+q@*MiR8&UWO`h+_C!QtHL+A-il@q}n^U3)acpjbNZMN6&r-b{Jr5;J8OB!KQ zXra1e5u*(CTc9vG6{pGyaI~1V$JW6VDxRDZZ~<1togJ(Qn zqL`SR{7so;y-%Wuv-Cfi!{W0=SPYtk&h~&*?xx+%l6tf;&uJPPeI_*=<~hoCcRYkC zqDvnek=1&B4&ueBDY@o4g)H%p>(w+l=Oj+8GlE&u_3=}4UR5W}E@Cz#n=5WM&dtJJ)fS!gyVwT_bJSN^E{Aeb2pn*EVy zdij~p#NUa7b8|V7Y{s|&c8{4DNwO7~!+k^)?Jw9W?<-NZ?2-cxNF!AA+Ve%E*{B?4 zbOoOBXuK;(?{*t_Tma03VQj{5J9Fo83x$Z0{GW(Hfkc$kR=0;9xAlg8x*lJs>aGf2 zbrNLdSYTbgMhr|cXf)P8@s2k%jbpqJ>8Ak9cMx@BN?0)2zf_OzbEfOxC8sbccbG$g zWNJ%^n+B8T;!GBF?H~}(QUZIUepfw^BZt)4{iC#|yQ5}^Z(Omwvcp|-6oft`jqC{7 zUYqGvBD^tjDf8|u$uRSS{nr;vKgr;Za@#lR{-lT6RdjD-Dc_<&cE)7>-*ZbH#O4+i z_fg2kO5w{@P{OShEj22nlKT>wG&B24VdHUtq!z>EpM>${8}98&yohrLm*U#t^8$eY zD8i{csih@D3gpEE1K959R2DsBt3o%3ei{c>6&i|sx++~#3?&385Cr3klC>`gN$8;& zXQ?Nuh^e?X7*Ig^$~OmvBtb>e2${qQoWutyX^oN9r_Ds4**Ii=_6K=1byR}eY#NZ(-X4v~#?1=|y+k?d}&1=V(=#t$#@ok3jf!^f?p z&AY1<(cEh^=SruC7>z&6j6S`bqo`pxb|mEl}{^)9Ve z-!TdKhR5Rdet2gbyR5q0lsuky9J8`q8RE^#U3Q-_OlsN z{fJ;VsB6#qLlXD3j5L$Y@Gtd0W*hu7_3oWnb#+Yd-u&$@S0-~svZ)g$x3{-oK9lN@ z{^#M2jAM#`9FC6n ztgPqm9}KTrdb^jFw`l~nrXPRd-Hu%>TWTFqnq=UMo$+>#3HeXHo)q!2G6k$Yq`cqO ze}6h7^zoB$adenaJ9P;`eY$aOr5ELS&H2>5U*zM2jrGUb4n3Ol^ZZO?UKhijNp<(9 z`}Z!qh_y8>wQ5Drfj#W!gcO32Pr(8<#~M(yH*O{w_+%D#@*CZmX%8ABnByyol*wOn z8}s}_6>#3-wbBh2fQflK5;BrFvs=IUzMESytW)e8lgXpSAZgeA!8n9l;W6*%3@p%K zMU-fe1``V1!M!hc@FyKhze72yCcUvJV~v7B3}65ofNVN7)W#tgM^@c| zKJ55!b`yg=8R=d`3nMlGK%#Qvl0*(~bRq^lEpBGu;6%=`2=%F9qe>9pL^0{Nn}Jz0 z-Xi*xq3D%BxUhyDJ8Js#%{QDCX^su>N{+y4K*c+8612$7x;L+9cyB@#R|5U@*9Puf zf%zhr1?k+GZ1YlZwsJd6tLS?_0t8cXh5a+Fy}L6JdzYAcMDF{PgS60A5_j95#zrON zN$WsZWf>sMpqv??i%Lh1HZvm9)2RPp(fRMmXu_`PYE9s)@&7Zl0KMKj9X5DO6&h>; z9!Y6v{#gVdeC`9;h39+r?euv1#@>Mrw>yUPi2xsmD+sf^ww!}5o#`2!MZs9%j4e@I zjUiuJ1A%sKxA z)IYY09M4UTyQhx308IHy)=l~~1M&XEW!(RQrVer{(c*=CX_GPPgPxC{c6wI!^6nfR zH5m(`tACHoQtoF;*2jMD6f_;De5Z}i+CN5rboaku?S#osSbLnpNErvHfzCxwBii@UO5EK5ZM)l$jC)Q%e~^-5~3`{1&vPA16J}l zU-$GNMkU9#ry3<5HbFes7FLvHRfhfY^?k-S1LYy}>qhO@*3$j@6DTvx)1NIO*Bqd{ zUBmzzqy*PW?1{m1vUZJnNw$|0vTmBoDI-=318w#hjQn0`_<2x7!RQ?%%xFN9;MS{r zkJqxYE&L7Udl+CKBIeM;`M}V}aucj^`#5)Dsk-kju=<80?3} zqt2|1lRG3EC545xezccJmr_i7w~-|6+raUbk9Fo+*mLCWwX9eAwr-&Ks=|{I0&%KHjKKA`pL@?k>6LgHq`AKmBov z=%DY8$Et58XSCr?f8mtC8R~U~LasP>EQ&ypnJO;VhAe%(64~NN{#$8^g3VTOV2PE5 zG|>myqnFp;Dzaz$+#!uG=F-2?>R9H<#7r?|IAi`;3`7vhDEp1yUsks3+^$h)G?FHN z{M&4%SJjKK;t75k8Pw+8TF&e3VZ&%$Z%B@fr#myIjJehP&{_sOen`gny#);|6-k4G z7PuXiLU+_ydGuttH6DNC<88SYy7lvOt>x~l-e98+bNux+)A4gCf#<{L>d-~qx3=Q> zMLxCLk!&vh?}_#eEg9`6;n$rMH)|r3@yrCz^?gz#kd?sWxMgZU*k63FZ2S+vHYhZu zQ`x;)$Prho8AbO2>F&|QTk@6GTk!Rdw@s!ZyO(vw;R$IW2s;~!;2TQfnBZlNwB5Q# z^J_1hPH@+n&+X@;<7d9zXYZZmam`d@{eIwBhI}7FO#mO4&{&hcxbr?Jil0Be0wM!h zslNYEGKol#j`N0=MAd4Z^s(V$pqq#A(j$QhWOB-}_0-@6QFzb$0glab0Y0Oh+lcj3t<+U;BUS=WB?hfQe{pJHn%@6{{?;eie|(`+ z!4e;9fu~zUvu((<^O$P6tglopV)y*DZbc^^n{N*k;o&2v193j6P5#)5IzhrWir+Kl z*$eYlbW$&P6WLpUxs4Hob#k&XS{sDR(ZpwW-g$gxctsf=ZejOZDidUJ&xQ&~2!e2O z7*vrM?fW8_`UDc?=QkFl7C{JtF_0uQ2tg>6kVKH?yJi?dNCUz^1Oo_3gzpw22ut{@ zLl6dH2qE=<7wJc6BQRNHa)--zu^KwwjL8i##5SzAphQE_!a9r`pjcEjBMH;0}MmV3QKw+`gC}R!Eqc@EpOF9ATAil84>yBf4KnP@{R^U z5&JdoG>NQ@5g=!|V;cPYe^cZH&3Gmqzj;UJaSISiXW+zL3s3Q>QZ355 zR?~(o>6i+ZXvf6@l(`|I0&Ox>tUXrDByg5n&kLkV9qmo607=-7zV+QA_Yz>@UE(%@ zoN$|ax?==rqYYmH=+6!KoRY^bPy(35E-!_Pl1UybQ1;&wEg%b7Gu^R=P95)Orq2_~ zmYlBZsIE5!ll#$IRr`bUw4TrN+iwRl8vU$a?<`NUA%WgL(1E^{9e=){=Z_`~Mw?at z9Qf|aKWKK4-le*|(QCBwgcu#Ak(7YV*IdSJDWvhl`D61PX!1Qc@+#b^;k|?el++*E zKe(VPzGBLee-C2%w>^Kau>2}lwVM$|kIT;XF(GHXKduW7UgbA}1r=6Q9G4s4WK88H zRv4dLZtLedo?#7-TGs3j9|=ZU4at)Q1}lg`>)DDEF}P&9bknCaB&;$q?KO}#F^WrP z*$R6s&)@0Mb$(y7=6U!?(q^Yk6S6(O{sZx7)1Pu|C{GcpxcPr5d&{UgqHbFdm*B1k zcXxMpNO0HSc7g@h;O-Kfpg|5U0fGkt!QCOa1$XG;yZ4Unem%w;{eJL=aYj|`+Iz`d zYpz)%X+*>HFF)viqzl>KkeOfNbZ?$aoi(_oW~e+K1Y|KKj+7kfa*XT_96Zm!s{NUe zyqsK|idq6uJQ1n?&k{CWGoK%Ci|vR35LwvTde=B^u9g>U-yCcaU&HQ52&v=c;LyS6z4~l;rbI_2y@xY2egPL%+3N&u@=w z?)g$WJ!W*~|0#Nd)T*N|!Z}Afy~)1O;`cs!K{newQen-bGh5B*8VJ%8H{nuSK`kY&GK^{bb3D=&ZkBvZrlasmKPih1c#s77&dOAEbav2$W9Mb)&=J?%#ur zKk!ZbR!sq$(O58|a6V9t8$tf=8w(Bt6Hw2`ff~uf40(e)E%TQb>s|6Yy`<4G$-nqL zaBRhY9>yV5c&V6$ECrjiMS;e+GjmXzr-^j&rzZO-rO?HFeo34y4BdFm|J&n7PvReu zbt}uo(p94^GiR3<_lpwmzCsoiM2|g{p0O9|x`J~i%!m&4ys7rim9Cg36trNXy&*He z=<3hr=Yu@E5(HGiQfsL_UP(FUB&#cigmgEBgy!V!jkSzaeCUOvCZ6+OJf7LpsH=)D zt&v-@cc>6skRk9_mP7$;aIFr*qHKDYwPmHZVO;EYjd91nd%qQ*qw3aGXWShvc@nz< z4@nxBeMsq{!f_eCfA{)jD`q@~qtC72dzCO`cp=-0>Tl_-#1MPArglX&_pg2w$*aMF zyrI3tRpo;1so8A58X7lhm;T^is&u9ExU z7RS_QPBa07cmBV`e~|3vh<9aWpJ{KmeWv7pcCEO=LZM`10K$i_vDc~x(CZVs+khnt zd;*`gAF+v$jaPuaM-(@$b(zgRARd96)?b=7UYhpwf-vma$!kr=m$_e1m?sO(p*|}s z_P@8M8j_9l9B}k3Ajd*L zMFEd$VwL)8CTf0y)o`%F3wLr@ZR?=nUohpy2P&PtxchqVZ9Cj83N#_(e9 zr>ul4h9$QAb_2cfU06{PSFUwm{HD%iktn-b|Kw133gs?1@=+xrt*)-_KiKhLkR<65 z9u2_|vd$r{7+%I*Vc0iXKK4g&(mQ0cnaS9p^J9>H|9EbuOeUGM9M0-mkAha@z{;a@ zsP_bA+{jD5Tg*#-F`R@SP&cT`#mduYu-{12aCxRw@w`Fs-QNb~hzTkOad)K$wn13! zGwYuc)cPTslwBB2f*|;m;qWnhl%qMJY{QO<`43=0)k!g1Wje+RXRc{sB>PFW8%uZ8 zKJ~h?CC56|yI@PC-Xk9vE@`qwdap<`I*1zh3UC%+IZ$ zUMp-+lT83CKC^WSkwbT!In^f8Ce90%Il=`IX8`KjWL61O0hg}{f+n3+ih0duWU1vH z3>+HliF-EzW!N1I$&DmwluUVfx!G#F$JNyphyQ~+KAX{JA9_w6j$YUY|LvSo#JO;w z>DT)VBXHW<@JHTe4Ep9rS5$Zff1)r|DDJwmnDbGQ!_@kD?ist8RS`&d0&-?NlJ_c> zaAI%OlQ!@6EJZRulwWznaWsC#CE{&mt*=;Bx$XKbU%w6AaaDV!3BEj@=KUd@X1B8) z37safouFL_>oeD7#;AEZw?x6WWc}KF>;0l0(RRGfZfW7nw6w<5E-b{@cA)f$bYdA{ zLv`3}bVixM*F%^$B?W26%2L$9sbc^)mY>08Ww0u6ZQyuEkOs6e+*OyGUZI(l-V?M` zPf%sa;#RZRH~lzLM^}=pJ0YM*uU=8e5T-@e%hSl1`iTc5&PQdJzOBoZ#=7pV%*9pxJnAMUk@JR%?eUhs^|oHC9y@yx{7Xh!8{e&K zQaF)`P7v=gOp)c~CgwQbc=WW$v6MD8z3uw;PL=MnGROOeTJLj+=|8sy#4;O^-{kku4RU)MvXtf*v@EYl`PBS=S&z%Y zb`)v76}sTdv+f~T91^5h?>O-v^*O6?lrPr@%b9`ZD9pX7?759WFUeK}bLq`MIccl9dpHOT;U%j){RK((1_SezwY^#&qzrVp6wf6= z7MEg&P;u^`%r1oJM$(T@=Fn8q!60HzJDBWdfTpMA?@wUfTp4^JdJ9@O;; zG8SIqP;C!O&Z5OtL;^O$=9A>ie*ng&Qu`(VF#dl6jbw`dV3q&DC~UD=O;Tg~!A!Ac zmX7ELgwoIhaMt|xy>Pei=>!a7MBu!@TH1#pqRqRZJ*L8p4QDKEw6d6 zHzXd(2qummh++8&WS3h;Z4}w1)T%Bxc8g(H$b&EoGyG+ZSjdGQx|mOQ(2dR21rgy7 zp8!~7B*7L*44Iq`BC}7ZZZ9z-RC<*qYveGvrG&{BiL_9LRe>~R6+N0kRiX{#1@m5F zj}A|3R1ZI+*gZ$`2I`NQnlAsD+^(TOQ@`*#)$_*DOg8@9F>-I!N1W&9j+Q1-vfgD~ z5F~rM(o^KUO}Gt>1ncYlTy{2@&6$@>Lcm$oa+i{tqr(+?Z~9Eh9|xZSzt4K>l~exJ z4e{0e8P^)$2O8~v4xrHJMBP8cJP}9~Z zP7RF}IfL!{jz^@M1T|)mFr!&R%W+iALGE}|lBuUBi5hUQp#p&U3~3*)mnHfBR=E(k z*$H0~+AsIZD9an$ym2Vy?wgf!_(*Fw-<<5b=NB#Fx#Ca%AsF@D)Jm(bIwrEzHC?>c znYB$s#!WPvHLb7Mw-tPtRr$r2g}{xjZMEHmn?x-8;-*jHX2;| z^RB8Og|+>|ufdi2iV^OQi3kHdS7WTKu8slJh=q$ebd0|w3c$l^t{e2rovGvErT`3e zhS59`+y>ZKBtqi-q=id`bw24@`AJ_jjSqZn#buYXD8nZyNV-WQ^6*NNpEQN6Y%(#6*7 z?w4aC6T^m};}S3pEmSKfcL+B66xn_WBiwx{I#rjy)>Z7!(l*6?=4F`Fdb0sz7JZ$O za?R&nUh%^C;^PIM$T_o2jt!L&3g1zc=#-u!m@Wij`}jIW8sXT_9d9*`7$(DC**|HzTY?wjr^Z{{V} z{H)E$=7q7EuTujQjiiC>Q(JrB#Pf2^_YCXZ7rjPXEVZ)B#y{r61|i8puv!j0W@t_l zKf@(4g4SS@)F_%0YRG+^ZG*y#9AscOW)?+ExReGp^_FE8$osv75J|)U0kX@H-`9ku z9nr~5pdmo4=v};JBQJ4U=rdZb%e(}*ek-5DLD5^&hFUDMRT?f=oQ8=w zU>G=oN_&m8Zf#De6EIH&q{hOLI~UrS^~yz2|5(rY{QuN>NoGp z+Aa@R^`J#L(wI*><6NG$d0E`Ef-$>JYA?#lOtowzaB7I;XNL-(R#I)}O9gym4Kz-;nO zv`b>hNiQOWif!0DT~4EJ<;__${pPE;u_A7U+dG*3;bVY2cWTwi7jxBkZ)Bt=o&5aK zWaXV`etH%<{q7adI}AUCokD9S;i4QTJ{-4Q+#({jCEuh(glrxEW`P zpMtqKoWgz#FZEN$;Uh}UT40*C_&$Pk?uK;K>}AY!D@VLFXR*R`tC0UCiDXZ{T*R&oC>@=mJrYBT7yveB zI*Wd9yT=g&JNw?EP5w^%QH}6*HUumF%P}OIHJnUWn5-@i`s{j{9s5X_Y*g~bDIg88 z#yf_lD6RquYalLJASLiF<48|HEC#L^%eJV>gO}N5dEo3gz02BhRE?oE-S@OL%zK*) z(#WgX?aSSz*pir@tyoc(xVvOcw%!`kp*%FmOO0`}BgnB>Kg^DV(`+YmwU5UL5bvHG zi81D;c3mfSoy~{j;$mI0U4^z?R^P!mc%Rz%e%={g+ug`qku~b{!{TQnmVRBkaQ{SS z+*AGP^6t+;@vjR5u)Whv;0IMXUs^03_4iKNJ*yB=D-3vlB#)lmJXoFL0W6h6C-p49 zPRVWUBy*(uQi96P=F7dQ&Z-O4|EhtaQ0K+vrJ}NOF@Pq3$_fs8g!;1?HFgK9VgkzY zUC?at;}yzAtF@gdc1vKGp8O@n*VZ52f7NpEK|I||aW>Cqm%#y<{@P+pp*aF~O-bO; z9|*#cIj&#=pMD)^VOq; zwa>8kH9hFD$euXPm1bUE?@~rRSJF8^P?hk>bQ%`^7>0&;k4Eq_xT(oDOUvDJzH*^W ze(roTu4a9nHv#ou#vY$$_?spT$~5Gyk9DdYmDsXXWezOHiyiI=BO4m?x`AzaQ&Vx zT(`Sys7XdRTDBx_^dr?Fy~WbK>u18tPB%mLxpWOEOYXG7#M76Sbu0jV&p!b%u=6V? zquN)A%b}{ptI^IM?Hw`RwDj%iNSmcX+5FBQr!xhO#JJ*&)SY-DIiZQH^sCBWtk{T;b>!Mz z>tU~L=U)ozKIy(2Mrr!-Fd}ax>_X&S=qxk~9(~GTH1a9K)2svWiS+Z1A6pn32)PX= z^nPoF2wJ;6-=3Mh%xV(3%uR#@WIxl1kRjgGjPVSa8s2G+bnY(&wB!OM;x-Pzv3q!V zUEXacXuf~n^HtET6>#!@Hds1)h~xR*AAyU%#r=bn9(CO!io`BRV+@+)m)kvjUW-D> zYC6X5N_~9S{n=5}7ri;}0s=~l_~*s1>HhoEyRYb^kdxsGeU(ff!Lw9<731Gge*k|i zdUpP|yLPAOTTE7FzV8YJ1cFmvUJ;6Rw45c*O_FoXGTN{@8DFdTZLU3&X!@k&#)IN< zvXNSAUglp$=TDsOfYfe(D-drG-#^kq=YfoZATPE+LVXl}@h~py=*UrK?@YCuF3r8ER+eC~ z?E^P0NoE&Ep)TMP{rk~Eet+d``k~qmH#UE4%(OcdgZy6oCDU5Avp;xSCbY?-)bF0` zf&|SG#5meM7uDzaeOOCXX@DF2t|9RL9pc3&fkP6<#7vAF{+u5jfqknPdm70WQXme| zbXx9Q85=S05)P{Mu!Giq;bAk@0^6Q|K* z{^;I^)|e?P4C3CTXzQstS%&2yqhzH&`ZAe5Qm(h|b{CEHoG4nc{)k=f5{W^Lft}tb zY2`YhTnjjt?Yc0+_Ei1StQGCt5lb60m>3&9o7)@fds=v0IQ!%2;qu1@PqCbl%1cfT zVOmc3@8ZO-`M)y%?%iLX4BvHg#~iQpS>=@*#iP~X07mr@FsfB&o6X)Y`A*iX(y*eW zopHmF7+b-rlcCpm@(+lu_LdXjaO1Y6ES@P-r{-|yuhK1BDy-%!crEAE&8m0udx^=1 zlpYT|D>v$lJRG0D6MQU7O3PC$!lDwy`+n}SlnmY(-)qKW`~EE}_7`grMIb3F?4Qjs zM)RkSF`3DTp4;KUSFxLMG zp(0=;%Ch>?1*esk8r`Kn+7Hj2CCY|FFL9`c&teeE>LlKAM6qNl8V-*_|2{iE4D@r0 z!sGaw#o(CMDG<$L0U~&r<-cgF^dVQT+RiF2|M!J&$1i(AS@RyfPwyy>tlm7cU@76C zU1LLDSz|lF#4?{b95H93M5Eo}1T?5Gl3WqAO13)JF%Id`j~EqIyWgcW(PZhSSZrn{hv8w7 zDjwE!x15Px7Gh6ys0?6jaBwR{h~Al4(5ZNI;Zabu`4!t86as==IZEe&Kk7j6Au)2a zARnT~*%oGy1%dHq`&IAiL{z+^o}dAU73j~)D_ZwB?#%Dx2Rj)O^|9OF-J zXG-n{@$rkdrlk&m7^stw@bK`gY;3mAzbf5<#v`xHY|V={tK_7cYvsO&Sjh1TP6~Tj zxCg?72SZ<}_Bjz2=xH1ul*`eFv)-qMw)#Ah{OEo`T195gO!8+7Y0dR_$TM&7;apUF z>ris803G_9dq0ue6*m^+_SC7V4~~4xcKOnr9U3f(lM}qDwxIbSTPIyvNGqgNr6*Yc ze|8I+8pgIDq6bOd^k~wlUFS>DBLM8eTni#j=h$F^%$>{n$fb^2)H5Y?`MYY!LKuQT z>h&ZMvl1BL`-krp72M5q@NnH5H4^h`$P^U%&2>0I{OK&Ge$nW=YJP=CKBl@Y&|&|Y zJU21IkSwKm1^<<{L$YQT>byb5C{wE|k_n~7=Dm(?8)_;)&677Bq>#?NiEkuV9A+!E z@BGBxYN$&?25v6B3ONMET@w=zqNvm%Qg9RRQPCRX7krcUlcT~BNS96H;4d~R1zTTe z$vT~AU7$n~M=eD5m-Cn0}U7y{>RmmNe7Ut8oCO47o-R`0pagq&Y@U|GhY%UHUAzHeq->cs(hVU4Hmi0OxC=BC!zd`)byIxS2m#IH@y-*~m)lW8_j{j)-hFaSY z*`_A!t?IC--;&8whGTQbpn5I8IAPMyI&3Wx%7f6Kf5tzZt8odP@R~6Af}aT$=5KuL zze(v?qGJ8v<-D1vBEAYx;P*%PIRc%aGh*E~AOA|vJ>M4du=)lG%eM{xJF`AZ(#g9U zGfWK#gf9N!X~oh89B?t9o&fON+n09k9nt(H z8vkloYoiZAt~5V-JkxZB{)cr%ZZUl+`D1?k8g{+Ws8HLfG?^g7wOfp z@UNv7)>yyePi(oFgTFRx<;VqMKQZ9d%BJa?0);a-p5xHg`I!n$J4eUA)h%llCreE# zSzJ3jA+0UVRcI!^KS~JXm(w}Q#Ls3Tz9TJa{!rND!J@0G+>4MXngy|p&Rnj~x8~X4 zkZ0z}jzgGHpS$q!C*+7ct}fuVxeYTe{2wj=E^7uJhqcc;bthq&OFe>`Y~t)gpDEHuzlPUIdS~-^}xPlaVb&CLPGYoNhxRL}=>Op{_##p2wuWQ++=% z{_=n_ar|PL1@g;~@Fifa4rsiAiU@7cH?ZwHf-#~^9c9`ixAC7_&jzZK>TYXrko7Zq zLR1UB9B{{K`Jvs+bgY8ohBk})qkU)R^Untev;i!vK|+6Ld_Vj(6zIhLq1~&FZA`tMB!5fdNz*y>VFZ}xvp zQZ76|s_F9gnV|B}I-7O%9OUzOn7rZBB$#ACP}|M{!qPbr+T*Es_xd={%T)$C+1o=2 zHp9uZ0KUTA;c>1!K+_Q=ts=VR(~j77e*X^SyI;6)vo_ze(7fi4P=S>rmmSSKI_$O#a*j~)8|i_ySsKf?fMC`ktdyd32BN3PsN;zzpH$VixdlC zt+Qg0GXt(%XO>J3LmWb0FP=k(CK?)VLQcwr?Nhyw*2}TI{YUbK6Aa+z{9iF0cU^PH z-6(_5s+e=KTE@)xVqSmebhJRY6=|o4%~o{NIqm%L?bw9#&Qn?snU_Cbx0zmE8CoCP zBZ`Wug?OX5W~ubOl1Bl_(2$Dw%Xvbe$P59PtG#A=W~P6Dz;rYci~7$ojj=F=7Wq5| zDbc^k+34-{={}jqus$#)2wL{bU*(^9zDAt!sVXa;!p8wQ7#K5}AITI=oDnYR@KQtr zpmC-tX~jXsU0-(VxkiW$%8!O^Hqmt5hGVHdITkQ%xaREJsukHzp<0{pq#F%IiD%Q> zzV~p7dvGtfy@rLUdLE=rvLT(NQ zJ8~lSX$bIrb9dy7T$=@k2F9UfIW6nUHW=GbJAf$yM7x9;_CY%DM-cUG~=K7}!nAzJW$EcQB&SU6OnBdO#jH++fHYse@N zh&N5RbHj2h>ezB3dmggieZ62dYG(-MHcETDAP4Z`IHAI$CrNrcH={!eGc`uZSQs@S zbaB!UpZIFY@A5@QxFksn+5Kkw5$~@~-Mm)gjj-wczofa?Enw#=U^D|^9%6(k={Rf< zy=Vv%jfV=FC>BRU>zjCwtHH{K+W?YI$mza z2`tRWFkOpWC#UfknH|j+&UJ8dXnP%wYxEpwW^GHV9aoA6JzzP!)C2Y9=GFUb8R4v!1_cGJS+l()`sQ*79TsEJ? ze4@`REZ*tNcYl(Yb8>GIa}JS_R>Dx5h}`KZD8c`Crhqlo+-WDNNNc=y1p0ek!8oj9 zdafcjc0`O*o1;Sz%U2IhZ!OK6jMtBQL&lj(rJQ4UA@QrEK9AJROW4DmQ?X4=A!9D& zJ(u6wVi_+cefFu>0__OoGybMz8TRwcn;!}@eLih+8fE^f5Ihil?f8uSh8}9dJ>Hr% zZ#5`cS@>{s4yPrasp;t`87eI;tvcsbAz&~(Q_TNiSlvoS;&vcA^STvkF23`0xpb)0 zt7ynf5*4#_=(vR07i<0HP;W|_{9-Rn{bFXhLr-{b-TS2mQWCMYje${Pxti{Dd_GP; zJt?ahnj4E8lNGp4W$pbu@uVAYm1fKXv_n?YwiyZaRMh!-=5ZMP6WQ6>%s;t;T)G~* zR~~zPDxKLWsU_cdlYa>Mgd#65FWau?485PuhrG`^Z;`%8u^6=`*3_`Q+zp8r*%8O! zvswU^0DAExEND?&6vNKIa&*5{lK#%+ZHHgBkfrme5P>gGqsXzwM$yygt@26yMXAhX z{M(1i>CyAWDVUB$%{?LMx+7EM>Db8bliO9_nkkX=Acc8dh*IL)KD~EPcv8nmZt*h5e0&4$LiZi-4o!--+F+K>s=t@`GeC_>w#!IV5ltM zK`~aL@xHB=PecJA*JS4xFH^(b#E>-Nfet)$v}*%HGV)A@N1EO^mO>djm%E=9_1P5x zTXW?)4%K^)D?)~$oX%nn&_aNr)J=CGeTW6T#ScfRV%)Zi8>E8Y5l1VX7rIM{1s`&@TFtZD$)2WmCrU_IMNCc>Ok`6Gbib z*I(+^#Ld)kThChruTSQ^QqH01zN_)q^kcH&l#fI;>(_PQC@4&V^-s#PbU!@<^LW?X z?B{`JFYI*!X2%xzbneMH_%s{bg$AoMHa_5G)=X_?os5XTsPGYracud#3w*%+_TUFN z#3GX9`(oce^4y8VufdAw1-klay8DrX{kmNptyxErIkun`GC2!y;}W|gH1y;>=r=fm zx%Qhmf@{d6C^_imS`LEM+WkfELJY1;K!Av!=~gX&VWp}To|MW3;~5m!hB(N);^f$5ckOkWCKQ!t zem5b#*EMHu#hTR?z$JeR76ha4lRVX*2hFBXU1O!ymN++mh z5al*0bGE(5DJ!B=1Ih*AcNRds2bC9jt6>yr2D`!^z4~UHu!j%TIA+YW+5#$?7Fl!f z!ze?h=57#GHw zK%J8=07^w>p9;$78r;G4N-4l?__6zKa`0s^8vEy1#64!FBn7dU0w+OQIplK?F!+=W z=-6*XGyi#_36D1~ze3=I6!2VnoRh|QUB?5x`ix-v1YT8= z$t6gkyead$%GsF3q;-`da+|MD54_!fqApR@3MVIWoE$pmC{<>dgG zU^vsCTlbr`o9#N;+)4a0A7hGNN5bi@5c=`E%`8!v+RmtvrZm!*68z;>d_E_83PP14 z+g+nlQ=T-=PDNv&AC==-=j;VCgC49i8xT=a=2CcZG;IMm8~Ivn_btUTi=9Gr0+Fz=~eTNJz|#m!sD#OadchPPLJbGz$J2V!&z3(D_JCuktG} z)oEOGWGw_d6M^TajkllVymXuOPZeou(KXYFT(>~p$97#;;?Fue4Q)$yW%b!*MB3_t z&M3v0=1`Z1%lYA}Bkhk-In|GZZf=75UfhBP#Udrx*1p2=hL=5p!W%2(Y!$-cia$6yWsz74`cg- z?7k?F$h1owMSb~1c!jjTX;~ZRdeubs2D@>fnHD!lhD&x{N0|ffL9fr#J67G7n6GWn zjv3F~wNE=OBF`@T$uEN)qyis?CM9+A#1vF*cpZ*v_sY~?qPm|R*`%+tY6OD9?$5KSuEEKPQL^IMsh{ZyCn%sMT7Tpy)OE3)a&eL znf%1aQ3%*X28ul#zQhVd=01{{s>h%Nc@H_FYYW( z8?@&5MxWf^N1Gt)s8?M!@5l~h;GePkLxC|Y08VOYf2*pBk)UurL?n^piJVN}<;Or> zYu(-3?$tkAB@?_MOoh>NU8-JSvDQ#AYqo4KI2Z73VKn11m+YHxcVFfC<^2KNhE2#h z6*Yz$O`Fpgi&Qb3rZsOc!KJM4Gag`K+?iL_b)lPAmlF(wzv_kL`7l=VCLm7mq)X`qJ1=xL%c zCnOx?DqAdJzMOX@9|T+|FH!lGl;ByDIJC~T`_Mivh$8L(8AdcV;g}@cS1YkXHrnq+_dppo04M zg-$nh`YG>K%I;sWFH0dcFXfb(ycm5<9Dp`bO>liqeiveFr(y`EH|_F=7Sv%bJ-7uA zrPp50#3VrO_H6L zdX1CH+|DThI=TEc39Y7R0yjnwsVP~Gtq9n6lM_$OSZ-I=(LY-=yWC_gUcxb?+fh-s75Si)1Tuw-#@_fm*RB4@!? z+!2)|0!!%sH|^#x+uI9vq=_8oS`8$u-es3r@+?4H=D2cgTo>T$({V3l&9yY`fNsa~ zUF}$vc(0=OqquIDW$^3c&iH|S%lVi0D z1uWVxzC`Z7hJmuSKKwt&fBv_4@_(HivYr!Kz9Ne?6AeG(2q%kFby0K=R|W`GcmwZ) z4o4AZ`5Nb$fE@IfB4++axjN|18}Ht<1WPz#jz**cv;IHNyZrYN9y1N<1?4*Hr zP{N!$Hzj82-%D0w;E8R4Bp}P;#_S?J#3JsCYvaKpN388&C7nvV3JWqdr(na+$e_Z3 zfSW+Vb_4^>R~UfM#@7PgD36*S7%xJg{){0mGl)fQ zoP~;>8aiW_enxvJ-alY;Q_c^XIhy%PQZY9XCu6XCZD>zK;{TVfN?p^uBH8z%*H(#) zU9X@U^0}d2aden|`lZcp2T1!&QYhlLZy%8(`T$LkuWB~kw*V7gEFS|ZiC`(Bmb z$qTK~SF<6wF#qNIf)=9|lxVgh9*yyShpzq~fUu`SgZO2w0+4aKTGi=%1qP|k|Mg)s z*w0pOuT_+OF;>*6~q#_SPJE zGJScp0%%`T0iDxykE+E_ro`5u8@{h|wUWTuV!-YPv$gM20lc&SW>XEE-NL>J036O% z0Xz8CEIWQ3U&|em*Iti#4a{9^83n$}Tc45$uMh;+%N9xH%&^pMX6Vq_Gd}MQkC$isXg#)6;PIA3_PE zH%~2|6nCG)flkoEtkaY2DhjM)lzycs4}Yhca;s--b0hjlFO-Bn{~j#}I%Ee|El=S+ zmsacq~gPcuoE(PxROs1v?SL)z*y)--#&3g`qbs zE6(9X)rem(ZL2lL&k_(3c=-}ldccsCl?5P7#2{Eibh9P{PU5(knVF4iA7D@xnUwFL8kL$bqDXqKANU(U+ zv0!!$zbJVB<(tVD(ew0?L$yYgBWS?4U3|JAZr0{A&lbw!LAA~5Nfk_U|I&OpSE`28 zYCf+-7I2L5WHBZw#J=x{o1`reBsI+t+-e*%KO%NnXDTO_X0VO8atT{L~2V=(Z=0vMB!ZdF!u9H;^GRU&kNJ=j^l- z!AsrzerOyv+25%Ny&Yv1C&qud(V%5EP@Y~{gB6n}3_+QW-nio|9}U0=$Vr@5r3;@& zlkswTA{kjhx@#&mZRXJ2mzu7JP}Rtt)S+A6_a#Hi9Na}LJ>mK;LrK{KGi_}&L>_uh zo-FwEp85l+r&Qj(sJkYjF;&*qn=~R@J_}%D#@2cZ4Rj1l{=&p4T~$hX7Ct~7!j)K2 zTN`rtlePq%RN6TJ>tg{r@85W<)=fKRZEZ>s2?tjp&;Q5CpOB_Nks65_DupM?7ZmcI`Y3n|F&g$RR1GRD}c@IV7y5)n;>^iQ4tVcib~}8 zH?f!7gV6x7vc%F6C+h9${YgnjR64?bGZNf_EtD^^=R_(sCU`{eM}$pC!DuXY-{-?=d?fKUyky7+UL)@`hYG} zBo)j#p4wTh9D!}@_u~>tZA5}(C_FsH)1j$uB6x1eK7jq)r1UvQL9>bJK%)_SS4|rh z>&>u)b;QxZT(K}K<6w$<55y&+2@}Tw|F}jn;XipN(C^Oj)GNnuP2$f#f!pTQF~b6h zs4z`8dFl}rk+IRcvRz|ABayrm2NQ>^{UeBpPx6x5)MN9Z&%;cWCG;iAy~St6%b4mx zo56Z$*AvrID#|vbc9qdg#vxt16Hs|I_{2;yZHjd4ff z08+nU7?DW*x&n$evQtA}LTi}5xUDD*q7c(`qDeowUqNJTuQ&_Bp@>o`%6tC#)52B8 z8aw~20^<;Rqdsbtu8Kqfve7AU22Y=TVHn`v^HBPk5KWlZ3v&>m?GJI`uO~~(wZ(MM zS7jbsU;TpXG?9W9k5&tv-@UYQ*!ghiIIs{rAHV@Ol5AGxA>T2WkjK1LW{?YLOiOqoXjH#b;5D+$y-rm{O zftT6TANeU_>fda6?G^S&QJ4i36yn$u}AENG}OC(58B**YNgF` z2n^ttJ+@v=Xqm(ll2ZSG=F(+=fm?rNm;iAH3(Cg3%^RMG%gjD_dB0>q*97kV#-;yk zr+>>O-{RbpLNflF{RL+{C?iZi-+Z%ZV8z;COj`XZrKT%K<5$}MZ~6&x}f*!PWLEBGngYNsZ5%2NUv5HgI>w{DTufNZ);_kbL{g_w@oLz`LFk#twj7n8d<+222^6WY|9KdkLn0>LXd4%6H3A*&au%e zMsby1uK_> zGXJ+Kvx5P)<5Z2WjZ-g3yhYmd3gl^+B`S>_=?1S7h|g)1hW} z^l1XtqLoP{-H$-2sXi(E0N!d@3yEmr!5Cl=#%HA@yWU^#ujcl5&ZYp~-UXLe#wNsd^;ocQm=FfqvC_FQyCC&Ei$u#CX%b9$82p_mF z$2)Pf<9UQJ_?R)QJ42s;j#NM!P{X=gCF+VdDiahDv&a1KXeDO<7j2- z`9-T33fmC!K7#>XZ8cS*#P461_y@k$F}z-O3@2Q8yok{yl5JF3=xy6;&;)6;N= zGdBQn_05cQ1+>%N&zju{ZB8Rt%VP9K`=}5dbEBi7ti3akGcFv?R8f+ogg*xh5IV|5 z(a&yDTODrgPx4X3EdEx?GRf@G!&Xrwj}UdD8o2DF$-LU@VpD=+B7g;ixK*20=28}J=3#n;MMf~#!fD@RmT zOmlrj^OxWN_MRC3x960jJP~3`Xkz`)iuw`Z6(iyYc{LYiS1O~uR-+KERWa;2Lk}@L z9-5@_yKBz%pVi{a3Qppc4`l43|5!i=D49=R9`#d6@&2#I-a06*=-C>@B@hVi7Tn$4 z-JRg>1b25G+}+*X3GNQT-Q69&$^G4XU)5LjUcLE?8cv;=K6_7h@9x!WbtZub_CUMl zK<B_bnOJ{$$~n6CUkg~pxaO-hTE+fy#p9bbh|2D5rJ=P##L7aXZX+G z-vX{@$(VMjGszZ$>1HCx7O?PxSVh2CxrmcOK2$ltDn`MZN5PuY(6K-rQHXz=CerCB2ncDm^#GXxD??2@ichv4rt*Zj zXREhcwr_v$Q%t64j7vBOAE4&{ptWkoEs}yR6*IoVz5LoxZ*|n9 z9JHkN7T4P!&UvMM6K3K|@EPzum5JJ{wBkO? zUhO;7!g%`Jlb!&dYO@V0C-n3@UU^`e=6yoU)>aSZyH#LtrgZf&h17dq0Q+_!)(C-l zyb9!p$v&8tuQoC>7G6;wbJlB5nf5ZmQr8qRU)wZZB$lr?HKW~NEYAA~E{f;3rAwp4gB6PE_zm{_p4%C z00UZWW4QRw7NgN8Q?e}2FbbV|IT$Fr&Z6DT918T`wYdI|f^2X!V|s7T&%QffkF>4I z3L*Yy*Uz^ahbP&2N=9!Mp#||h)o&m`G;Gr0p((Jdl?}HpO!B768h3yO4O~3+1l-Ayy5tRM9cQ0rAlvH#dehq+7uo$9hIk>?zWf1Y@ct6X)AK^vyy@OF&X*Z@WDLFmc2k~SjQ86zJOYiuy_%*v zW$p~XBuK-K;dJ3OJ>_I9u&>GFAto996qYyl3Y;u`gM$h2C*@90!DyiGQHLvv zm3*%8C|33xy%@wU;71NnKUWlTn*WPuJcXYBYC^+kawzr5WG1~IvK+Z>G?%J0K0?e& zpn#d!0<)RT;o0@Od1DZU@MEBZM*}$@V&9=@42!&h!z@HZaocZA!6dwat+uFo+BI1G z>O8|wcrs#8Q^U+~k~ZyDv5I?;*6B0VY-xJkCqCUbZ=C9v9Q~zRtJFOy)8FRl4^z|g zcpl*wO*OZxn~>`n3gh9X80}?{GFf|n&{k&L`whpa*tgdjLN{#gBoaZRQjIc6vQL_# z!Vx(aB!z9b><3SbkJ^71MXeVD{HuRFyh&5Kvt+G@-;fNWE9lLK9kf;9dgKPBxo`t@ zdvDtVdKGnjJMkL$0Bd|MtSC`N&)3&YbFRDIYM+H!WqNJd^|#jA1xXJ}b4{+Si2Pki z)js^O(w`GnZBMfq6af-v0?bX^Y;~{0^tEW$%42`f*d5Ly9Bz#XoNRXi6*v}r_F=gl z0HbV3p6h2k8CNaNz1qIIrRimD?%)NUR17W3?|#K zas)uHXsJuIdqSfvI^*6N&p6~H+41{8o0wHdH;yg48=QG$+g9~q?io*k103I+$X8-~ zfMp7^x4WAD1(hY6Re5i3=;jGzG96!jL{gh=bzkqCEY-Mr6TO|hVA#L1`AAxE^w<%#$YVfJ_gI4&tef-Ar!spI+#t9`zqeMm@WP4 z2<)Q&2rF5Jnng`gxNP|0SRBnNCXqUQv6UW!N&py7isIEL_A$W1`dXB*Q^H%6b{N4K z=j`|sF7S>NpOPXjE)ETifZJ=?#AG&w8y_D(^zJ2TCVZ3%fsMz2=~rM!qyWC-9EV0< zQor*%Hw0-7h3kV5n^?>7XLTcfIRZYRrxLb%(aC^$v_?I;9!V8UHp*;UAtzt{EA3_IhVO4HWoFvx+y}3n~LI>QW!WxQ6l4& z2Xpn$BnV=2@09WYU7@R3lSRIPZ0R zhd>i|?Tc~h*0qF|#}jAolw0&msTh9Ifx2=4r*c|SVw<)Bh%bAd&JyZbi z@|LxB^S~SA*A~dDNqXfyTWM~~S{HSspc*CI*btMi$w|&OCPOVj@~mzbDdU?BX0MKY z--S)}!1?<+@oV4v!t#9H87Ot`c;BV|_p~E4^BFc#lXR6Ea62{s)!&=RB4dw2K^<>? zWxexZwqm62+ET2y5Tm!Z2Mtj++Kc&FTNUYu=oq^92?JaIfQ2D#u~sy#D@B(Ho) zMAPWin~aHOUBF_ho5ugO;e4o(*>)hK6E9;>m($g!CfAr{U?d5bOhY!wsai{UZpYkh|TX@E3}LMoY)lm`eA!t6l5L-0 zAh)ox*1!8zd%aOp$3Y&GYINpiw`HJfeJY-$nw!#&_r_7*lk#`^ogGmx2L$>v^vk;{ z+S>{+qsfIs-aE=?cw23{WY#^#n?e(PyYm3SxsuhlxaA$z#_6II(6Q3&!OQ=3xt941 zNHYexcV{?JPOaTV!lwyHjnQcI$1823yL^5{CSwk%gGTaR@*1n@38mK|h%C0`1#EmF zs}4Jkj7<0YN6`eE*G=zQJxv%YI`DSrdS?^(9@%v=KKQ=)K1~7NV_j408Jzw!0vB(u zA*Dsn4fZL@QM_3Y4>rhWx9cwI)h1c;g&d91u^Fq7e?mQQR-yeE|E$>%Gnq#%s zhXK7#LR#8r1RAy5ZaBHySyf9cN%%h<32S+^q~C=2SlZ&I!@{6$i8O8$j(oy|LqVgu z19RfpMkoHN@3$vC*BeRDAb2Ay>-Pj(2i3nY7^Y!=fVf<*e%T(_5kp%YRBeAw*KCis z3^0b+F4iTGkOYEyOCj5v?s1AaTlyQDdLIr?Xf?(-SE$=>9r>dBNXV7EPrbF?^~wLX z%7$wA_B$1?rfVuALkxaNN@t++;ORC}lCn_r(L?N$(6R+leiz>M{gA!&rr2R@mj~Vn z|A0Q{4Z*XaJCt!Px}+tP3t7x60aNZ|XuctGk=`Qp^~1|lu6=~uxDAe;oJy>_(lW(HbqRgBx)hK|27U82g1vYF_qWY`lAH)JuR~J zAlw*muz^}xcz=%o7UCOysb^3q3isN`@2tjyDV#>1DU&rH%LZikdnv*}q=NuW+kdb4RmJHpD( zyYZ5VX5`2y;%;xxYZ@Hh;GUBYEG`rI)--`l#we@%By&x_Zk*hY&qC+L03?4ILv|%i z;g^9^aL4iSBb<-u(M^sPG*d*je?QwxHJ;cX@of8Bwhb<~N%3oB$m#8nsmF9$p<0~j z3=Z%6TNjB{*o7%T>43xBl95CD{b`1gbRt5LY6K#RXo;yBm8RU9i?o^Wl+Pemz69BH zh_tItV+l=hAP8OLYaE?s;Ni?ZA}&fibt&)d26!IgY!-KXlPx|?gkG|4|2yJjXTr$8SmR z9|w$Hj9m0g3gWKQAeW$oeW5fhvvY)dMvnJkvgD6Oh8`Fwvl zTH%*5ZggbuQvS)#iit2admzjY4Q&hgr>DaI`U+Tep2N%vsJtk?sFAO8f3q)d|9KGq z4IR>?H)zSOmtm<-OAFdV9CW@odwV3DDrO1(QUSER>~C|{kU!{zXj?00KXk>C|E%J` zVv!E6hZ!?YvgX`9U(_Dv5@l(U%N+ErB&PrvGD`UcMrHWv{)b0viUE|M15f;ee* z&=mokk5Ij%lgIj4c^L7UR>0AD5$&^rrw06qdhg>I4MHd`5sbuq%c0#@@JDo=zjWileC?orX~}kX*gF4 zR0m`s9H*~QSx!q}%qdl~_35BWeX9F1z0t~?`vk4rP_@&{eAN#a?cO@^B9JcJ@-kot z5Du&hf{SY9mu3(vS#nUM<wX@n1r?YLOIj^96u386Pd)Z2xaA z>i5DFAmlD}CDj?H-O~5BV&7i22e@?IOi=93E#MIo1VCT0ju(+`aTvTr=;BbYZp0;= zomq!t@CphGgMf%m?cM?Wv9iw%pp%KX1do{t6DF=VG`WxZiwz*PgK{nE>ff=!acgRc zdsq4MRvg~{0XeWQN5qd*%0I48OUTyc7X|xLsCk>_y{zJbzd8Qt>cxSr)L#>ffY7t% zx5gP+cF<;IWjGWutJSOeG-dMTxQMI!MI}X%vp!P5nz3o<+Y|Y`!tSsrLM&$LXfq_& zobz|g%6D;|t(C}TVF@d44@2P)ED&RgLnHDob&_hIbVjrP(N*jCtfrW$UlRUX{g$-! zxx+UHrV$6Onb!E!PLh!=UH9mgjQQ{gi3t<29m{eAYXiKh1xxH>j!j_(RGiJBWns?;+s$WBW-be&6E&3LWU3fvEehJ{ zKL#^-gQ81~5KLUIcTfDESxs;#b!;|=S;ZXdDAfnA74vPmP1?gsJ+Vj$l;MT2bWoP; z*FGs}{dsDZINXeDmgbh{S!@i{J#qU29Et}{W)k}Mtu9n-EA-ED z)b}zi0<*htZBP3%z5Aefb?&Wy&7;^qvfI0@!M-Bk7j{v?9gXzd*;|l*UH>~N88W3& z(9m>V!}5kO?UsUSj+ujUFj<6Bl`$CitGGG)g71THsY1ae!-qZf#d%iwxP-N@vmPgT3r6_QQ z{DJMGw+P1(CP{JRzr`;nSk1hC&TB!(?#n!IgM)w2w(Mz+jr+qz54KL2`|f8bnA^JC zE^E4@TotF33By{k{he6?keM>)u;|Fce*Z|>?Ji3@V^yG85-_DIWMDzBx9LIv;Janw z-Mr?^=-#Kp*KA4*4-&`e7^}%^Y)P?s^3D<0g}T~)>F`D$jfZYjJHK&ZX^v}%*D?Mu z{5DE^wzmoR3Y`8t{26c+vA&Bam>XDKi;91HmKq1VJTz21UtVc(TwHmb`zEWiNUAQvy)sd1 zyVJQuNIP#+Sl&^wSjNtZ3j@x<@mJJwfw78J@LV_fBoF6sM&`I(9LAhLL^PFUAN6PCJj!*J3&`c?|=G4XL%5bh#;H90EOS z!e7^TA<*HP@QRb`f?glCP_JFj@<92XmvPg+!f2U?<-MUZM8?%t;;OzN&Y|#0kaS1L zfj&x(4bXR@;NM@lpc%~Q<1?X60YBgDT_1Oo(DwU44P2B}x`ZLTeRz0%8mBZSUg2Pd zh)?rpPiE3+kJp((IN+cX@MUL0w>Cs;5K++t0DZsb(}c-^@|3={yjE!2HK0=piJ^SV@LGb)^y?hBI(L_NcP4+0dm zPjdEwPzI|;#Ur~~D8(;%H2O^K;XOok{mxTMTkn0fv1xY9aXy|)q$86=rorV<&)#uA zy~D4&g5(_-jXrbB^Nrju^`~ zCZqF5BfQwcV1mROH~ks%m<55wUsr`xJ5a8y(ylWq|9ObIc5r_02M9OPe zWAA_cbs+iw3Ti>l!ZQ9JEWrOlVg4h9`Tulm{##WUH$1JW`gi#ggw&O;iYr<W%Mtrzao%t2#sYe?yY z=@$~9-H5@!zWK=B&Gi^{4TJBe7Z9IEZ%tl~tZAvh%rjDsTwW+Rr#Zv<@PuaP zLQw#==6hxN&Y~S@6%wUFI7td9aekr^)!pS-{)o{}yeXrdhlW}?LOVhDuWXux69yDV z%13uGs-39TP|!f=EpxcfZvli+C`e($iVT>A<>lWrlm8770fqdIx)8G*$*{AKNOX*8 z^;wavRaI0-q7kY%A*(3yB`d&Hp;#dz;Dh8g)J;^1a3mjcd}8$xv%bqNJPmA9$de~S zxpXOr_pFckbtQCpcEHl7x$qVxFiEll@^)`QE~n6A@L+y0b3=>QhV(aMx^wE{-CYQ7y=R;^dA41;*;!qJfpxq>E^{*wV)kUxJr4Cj-tP-n z9x43%mqV?FWZ^3HPgxh8?{c&#B~8lec4SWV2yKdax-osMWf88~H6*FKgk+>KGF3Qw zM?_0}U+Az)U?h9?omVx7H5GtuS>}Rvz&s5#Jju$--$ID|9-QYlEpwimZ#7+QaZ(ld zI;MP=e2AA_^tVsyk8`H6*HAPA3r;iKHefm9j>rWVf$Kn<^~2;-?2YR*T92|lfho`a z^-e!fEGPN%(`U*q+#GA)2gXUD7A1h3n7`vsivs-!_>O)hRDo^YwLB@qJL8bYIWMkt z;N}3dyXnK%&DiwO4=-16yRPQwF*uvo3myqQdHSjYAQJkk>kq%rgQzLDu(j_OMHc1Y zMBQacRY5{KKBV(DN%m{k`9e}c;;{hlHQn3e5~24QR`$yp_50rP-RL*9+oKXTWqM%> zhp<>+{gn9E%KMx$F69@W-pA6>^Lji_VLGw(*SsT(?>l4nLuk*Mr zj>{!1@F-rtUq?wrYkK1hC&`>TJN1m&BDbt$e45{N2PP-v1~4wBJ+N^~$Jim3U0)xm5hK?x-r4{PZ2O~q zDKD(N9CjMP0AwFF?|^I`iTn3oa=7|BR!ARZch6p(NTJMui7MdX544%3cMQ}UQL{So z(k*}x1zb|}87UB0k|Fsa)~+z*H#MJbA2>++NPDd+Oxo~5*@*$4WeiQe715Yg$zN}h zkFFY&l8lC5Al=$PAgJFlF}^xDIC$svA2=r$7be$B?dp!pcDTQhxQpbtC)8@fih;F4 zih%FQkReZS;wjN>fYziy@u!=mkSvzv#ko#{?^kY0$I=r;Gwz`Ddzp;_Ou@<*PKyKv z^X=XmM=5cJEc!nIm7`R!oWSI!2D+4YR^o2yLj_7UlZLj41`A%1*&2_SbVHwz>c66}a<+=w&FOCpmoQd%HsBy(`}X|Xv`;Aq!#9)(bV zS$|U61k?ifO|h7B0)Ys?a1ue};IiPuVL!_om>a`?VLbja{(IKE|I(MdC0{~UYoW^; zL0AM4WGyrWVE(jl4gYILP-7=YnEAJ8a~#Qc>?}y5TWcrH95JJD{&A#_UeEU{+UdE> zF2CEWcbpb6d7T5B!p{->&zDu*RSsoarAm46{**7s=dZ}C&;-SoiQYpaP6cK@N|U5mr{k|^~CnzK_ztt#vGDpiFQ z?ff%jlwT0%S4g2Nh~Wd+Kf}X;hW`oX+WhI{fMYpA0NcBo$62(f0J5SJ_%%a3veEJ9 z4B=lAoq`73`8z6hI8wRf^{4Sc3^?!YYda_>3j9bz;U#+=xSIk-g-l0}R}nJFZ( zVwQ7!1~U^wk8uS$E8}_ZizPozd!iHVU|;85_uq3l2ovCm0ZM58YOyr|YEYAqlIqOx zsgS}%M3q}&!Vd^nP)lmfV9shX&tOhUr2qI4MiW^2BL=9Vh7I!)x9-`O4VUushcq?= zNh}{y;erMYMvpkq9$(3SV91>5;h|`p8;>qv+fPS2OM;8Jlt{ruK`3rZSlFa|E~3y)yn=G$LDs3o^+!Dpr%z|FzQRyuVjwkZIBYr@ z8-Z;fMp&ZB0VAa*;t<5#?WDvFLgh2;YkS$|dN|vtY|FH)rzcF;>}U|yyo4)etvRSK zL3d1g-iIKK{U{b{vf19g*Q=6;MFp3fjS2CEIS6+eX~L)sYyQP$zO5ZbGAuX?%hT*u z4KZ1t=+uH_VTRzDT~T*?C>+LEx2C0GL`q1+QE;q6KJ?X2nG1o(d*HVoIjmD2GHks->=h7MA48tCDuj#ihO#rF)L9^p$v%gOO+ALCxa`gOSP5xFagfw^abDnKQ_%@WDg z%NM;(=c?hf+c&?hI4HTet*6HbmFjjn4 zwdLl3-^U-v8fqfF4xTOH=HX(e>*#Bsp+|FAE(_s5F4F6^8Flxub9z2UTmBCQx7*!@ z$7#iP;}p7sJ^pw6oNUYfm8L9b`3rr=sz}eT8`4A2q1myivn*hQ#>{$F;*YUr!vQL0 z61KIq{euIk>$)FwJ`oWGu0#8?!88lj;sxOSI1k#EgmDQxhZ-b67_jk^MW}}MsPTr)N$+#FsV(0 zXQ{I|kV1H6*0?^GbLoCU=l11JsQ&11bKDc;GVi<4n^w*+b69rGIk;HdIvk(hczPT`b_dYyw?1 zd@M#hk#V=qU@iEk_i#ZtF{?Xr3tg71OLBsSGkO9!zKOw`q|@>g8TGhiC0ATjE0tyW zS(#1X$?b@Dsb6S-=3OeMBZ4TTpjSIi>%+@YUQbH358kT)eb>gMTOx#E)=lArUQE?C zRq@ElK>EWGAAti1murKWJWn?z-YDE%%tQg!LIn*8~mRUub8x^fms9RK$2h+?DV<` z@%*vvliXh^{;YIKGSGhb$PpCsARI&fAEx)O@KRFbvA9-!`m)4)v`J~4ste7b*M%`3 z_x~)Q`IjR;JUlo#IsHIE0TQtBd3<0p^#}@k|0yu;Fq`x#xC#}6I6;)+__1a~Msqmg zJ?b~QFPJPGWK2HlKCkf_Y)j=^A41%OzYfk6GG=O-`Qr7l>J&ezHN?W7DhZIQF}i2A z5Gt_WiCQ#d2s+D~wPe8Lg#bIPg&hM%OFr{|PC-=_cvARxELvUFl9H18cUGFRBags6 zIg0+)DdqGd#<-1`d8<#x-B_Q`h~TCOxpxn48!Tnz-NsSp;vY1uwOFucN}1~6%hC7s{q!kBj=}l30|>qD!}_%L zMu0L8`w8+&z!VlpW~tHb^#XZr!cYsY)4{_hx39-i;a{ z06bmWnyr089a|1`ov~&kBpOJ`5LUP{XXtqa6e0FZeB#p==twxrX@M6`8d@5VV*5gd z#(>phr0bdj6;j3p%ife^$BBZYla__W zpGNp-=L5HbU+$uamk1aJe-h)%N91q2bZB4Skv(t=ZJXC?FjP*h@1RM=I;?hA@n*MUXDUG{*^eVtG;j@?jSt))@gjuy;$#Wo zz|(=w`h-?FycB~MRsuF&m^hm#U`ZVp8^4!TOw5iXoXF^vN8(053^MRg#-t3DrW0Mb z88`~*=g*Y9o)MgwB<%K{02M}BV~%}zuF=Q~8U-W`)KeDl34jdj6Iv~7TlY4@t3%uV z9`cly%pYwv)({rTc#kOU7n~@$%-~sv7X3)bYVK!TyrnI7Lc*`}Nk28B$B=?@gAq^hXw;ILY{T)4=!xmd`mYtCw(&vIFxy{s(y z<*ep9xHxyAU@};%mPp%9xLLaMv(hh)BK9|2oc0v$(Jhbs7YA%xtUx_DZt2$YL>lLj zYxdUY3n}@_{+qT>4~kl4vv&E>vQea{LP7HatU+Yt^;%y*ibYeTg#c;mku*p#a4@&V zDbDOhfhF$=$iIP7ka}pcfk8>f{IL%eb&1IM#?AQfxlnB~4+1aa_?)&-_NcP9%_dB4 zMv0E2wM0WBikR2J zbZ2(THEnk8X~WF_>jQld$G5NL@Rc%dJSpgh1qs>>>r^c|N~Et)rxpLG20Q!&E3Y9a z42lfYVLrZg+NcWDDh)+Bkk4_L`2ihQYnw^cld7B)T)sDS%><`3m%J}baJj?!eYuIH zXL)Rtk^Oe}X4(F0m9?_`R*~f}+vj^le>D4a=vuL1oGMZ94-2w?AIP$s`($)lcSpyI z{o1EXV}q)oqB0q7SXY8>-MSAC&ns3+9k6?&?<&I<1wHMBfD}!N_4bVzO|)s}(PXDF z2BTgQ`GfH%FC&nzmuYB24u+^2{=cMPe@5@$k^-OS&*=Zq2eSN!1Y+(#%CHi||9#Q_ z^-t5K_9ZMv8Q%DG_tQ@4KWGZ9sFQHzLxbdxK-wnzBFP_mdlQ@J@#ITJneK4RSdy~D zHpRsa1M&W+RQ+6UiYn?@5eK_g7(o8P)_Rh#8v9Y^U$fJl(MWvXLikuxSiX^Ai*+L2 z&FuX(^&yZ}qb*%>>M;R+$$kmojiYAFFyjzp`ax7=9DnygGcYpl2}Utr=~H2qRwFAk z`g4{-V}ydBez#sRUvZpSXI8Atj?*J?3){HDKhgk%a>_cR{)Xk_m_>-eGdFr`=4e8s z$@{yvT~8B$dPU}N3X-9FnrD3AH8uwROt*C85Cv4%7$Wl3o1;jRnOj;C14b2mz|k(= zkUm*Ksz-pzb9q@TuR2miu6Zdsx!BflY96?LdTMVQ<&Z22Ds==g#^QN@qO@2YVd!j> zp%lnkfxLJM$_#s~Ptq$>h>ugoCd?mV7!=yo4m$w*6ao_}Eb=PslygaZ>T1+&e3xhns^EUuxi`RawD-)_sO5N|A4#Z7(9k33a=t6bn=U@k zd$?$R3*)E7F$rV1h#`pi6wSJeLW1HHRA>_?9>)b|t8~iUHo*B@Q|??W(~U-s!P;NRljhZh6wV0_3;sQx)DYtlZetB=-bKXzxBrPk<=s9k2Bp3p+bd=R~vJ>7?*&wRkH!t%0J+E3XXDnr4a| zOroEg%5~fYK254DXmQ#*^LQ#ih!_q|YwdOpsq5}cPV0f>X)Ap_ZO0=byba^&^NCAe zy)wea3q)fWz5sc&F0Bq$Z_+sfM|UAD*Ipk8%bb)1{}U|Lt^VzUuknyK&0|7C7Zkf!oJFen9{WX3>Bh5}ZK^?MnZ_ z^Rlk*`UjsYP95>mH_8Sv56A^76>jPxyN!j^~*xpG?2_ zR->2COq{bKe_tE1@qCgVu=Dmt`yvy*-6L_iboI}lxyHRkBbVE0ja`WMH&y}Wp9?(A zOS8o;A;m4@%ft8$h8f9c+w_iBa(uw2tj+q1fwN!7GNv1DZ?(u?EepyucTTUFApU-Of}?=BI&ux=b~ouqzpS*()xIL1!znzf48?@qCakI9 z_TOm@?(ujOG`$ZMk9z7*W~R(ioa%A)lC(?0n4sJJ=(%`pK@;3Xg}4ab%d{rdVEepSqdqAwyDT+T?PBHr}fHwqzyubc`W z{#cM|yQH-}Y8Pvxk@{uAiiSAHWpjO14p5X{Zs(i8eVBTm>@~GnvU+k$a3G>XIrWT% zaCt)V#l2;)Lkm}W&OcN(MibB5wr~0ji;AJ_;tk1J6Oy{@hBxRx0gF%EoPb49v>#%! zUbg_<#TR4!s~;gUlF~8Ret6FMSoQByMGFjpO$jeYQspc?Qj31LDWlO19?dUp5tF~- zL&YsGH5iY-f2#4Ha@2!5*%v;r+>Ch~(su*>LF`S}cICxqYaBF-YQD7uacGVdFn({L;JshR zHFdT&Cnbcym6SwuWWTd_yY{nCk@5XuX#iWSe2z@G=k1Cy`?}Q3W?~JKKeGCIrto!J zHpDJA(N}y&<#usAPfVG|1Fe5Ms-@8%beZjDqdCFP|M9a57%9OfCnwL>S^z-lgUhZb zT_6$o0C$F1`A>YsmzdQLp53;6OmeI5i2LEXmCDmLi0_QPU%!bLk5*aE>DcMm^+)|I zTyJKWqt^+f^Ih@s9goJ>Kh~`#rarmcnaTMEDgt`^lK>M(hy0OoQIL5DSorUuj&T*yk}?w$B4wxC#QxBoc))DNKlEAXXx9(-^=4*0Jy*QXdH}q83tqG!jLWi z1qHb)nW%Ky0$Y1;BdK}HifFw|dEG)`HC(W}EK(%Mjm^zUYHDKM-n_xV!3n-dj@#+_ zVygXn!58ks!Qzk)8fbOoIhg|R&dZ+G&nXV|_!>g97mgMmSHkD-qek!ZGSH2_V|f8d z`tIOh+gMff4 zONt1p?A%o&vP}n{UlZb6EjNKiM4XNYQ+`^FRJH{WGYA6amQj9UOUE=+sEI1tw0diD zR8b{YShI>N0}^1e_pPm%<*jq39u}M4XP1r35r_r`Bt*TU=V>7a0y@H7FUhdZpd8H^ zq32aF)0I5*8N>P((`1yMKt*S3If}O_d$2-DpT@EWE5vu6D|lW;w9>b%4)#-V+;5)G zT756D)l^?79CSz7-Rx&$y1Z^H#5F%;5`zKne({_r>9at^QjoH+8h5dC8nJs4v2$q| zUcMPF%mLvi=(S0Mr_dH^bnbLduH>l91*bIih%({EKyU)zzVK?oSw{AH!=^WiH2#zm zU7V?ka}NSuhvdx|@J25L|FIQRxraC#>8B24A#Lja&dAdTCXj&KsX?s^|5u9skD)l| dfAjZG#DSivAIF2ciG~ literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530010303825.png b/README.assets/image-20220530010303825.png new file mode 100644 index 0000000000000000000000000000000000000000..243d26f7d476b52850f42c5fcf65097d96f38322 GIT binary patch literal 31831 zcmd42Ra9I}7d8liKp?og1b26L2o{{+?k-K^4#C~s-QC@#ad&rj9o}!P|9&oJX3b6S zKIg2iQ?+Y9+xn@HKXMZAusE<_U|{f4lA?-WVBZwJzMuVo`ubFEy43;$BLb5W6;cMK zpRK#-Y0alxeO_i1QpK8xd(MTa(2mL4U~yFUU@5@`2>u{W>rOM0+K}~Hem9l^#Cg^k z)lubJaTDVP!{={JF+t&SXvMTyjU^hDJ#x>4vw9wMdJl^w8jldHLf-IaeKxl`%BLKr z-`ZWKSPq=tm;N9QKob5(llyF`_BD0@(oUabEam_1QA(naeLeeu{9P*dKS`WRBo+Uk z6h$KqLHUva|NKZ5{*y=w(WJlslfPhNMPdH?v8d4hqk|lgf7GQ-#<{ybx^$U%q5=yA zy8X)%Z@RUHjI~<*2j6*s=g_Am!!2?0o^IGbiwcoBE?WHI9@TDcP%W3OQ$g)*YIc{Q zzfjQjW7X7NPdS?n`D|_1d$t>646*Cfsy*gm6DL!i>i)MDHOpSo-}itSZOxt_OpfXt zTwWEbJ#L4;%!@rn=JBNnyBGXo`>Sb7oE6FYkK=}wrM=A~vOd{W5hrw))pU~qt^lqw z2G@P0snH%aovnc+U474e`;!;(k686tx%KGZgx9=)zag3bQ=}8QOs-$Ygj0Iuj$~8f zUOj8;s-+pfHfY56nbRsSE{BLfjluf7L0?HhQTlhVrKBGLh2R({zI-LDT-;7bPdn?;X4qVD!pV#xep0#0Wg@;$sMH=P! zFV|i{kpWw#b##=zDFYwfd3{8st{X;*>+xQ?0CG^q-DAC7Z3TMLPi1sQjhX@@#q=!y zbx52RaEdPrYG)vq%ON}>W!P{ z#0$DWX!YcWI-5;yJz?^?+B@HSRJlp2diP0sfSO`&P$(;nr-4n~_F8$cHMk|r++92c z{DFX^%C9TIluMIUeGB8`62d%-aGVj*$8~k)}i^3K32kvU7LO-YFA= zR%ke`XX50q#{6x#wT1NlO_rXwKkU)l!SBkq_^r5b%&4|RB~c&V#-y8FB)+Ikw3zuNR(>(+gMXXzjA6Ew>$+;L5Pk-s$wi@DEYpfG-$(1`m1&Zew9mm?}1 zumfA2RJc8SveUgn@jNEIx}<){Y{iLH&JWBl{Yh>uO@N8sdx5WGs7?)GN@o)Nz@M?nb2_%y57 ze{M@{Z^k7zy@55;=3prrz3;|&oNDBk`W-vnYTD6;+CYtbl0q)!QF_B%R{6eQLgc?~ z1pb$*M+c?M?~b#o4>qn5x|dE_T?c<~`R*l_Yc^%8+`-5A>w?gKIu2he&sM*?@HTY9 zfXHZ^f>aTySW-0fNKSze2`W{$hu&O+a%~~GE| z>`@W<+k?o+r23l?9j+20+8fSEWvjaS2YG(0|HYDhED=QdoO5^GdMMy+u0|5^pq>>T zdUiHOr8tcnp=?hH7VxGS2=T0Mzm;CFEz2+AiV7WlrIKD5c&KPNvz#Pz9b!X#*c-rQqJ}*(WLk2h`WHq_ zo@(-+>UKi4nL}_aIK{OMN!H1ESQ6<-Cotrn>+t}D-2KyoB4@U4(Qh(S_YG4U>wQ$# zD21*~H{Gf8Yssi#HDdt@2!P8q;fdw2RyV98vz!@Jk!mL@8rAhliKP9Q9hz*af`oI; zOw&&zHdQCe11j3)NANWq)FA7Gv*IN=2s`GQ#FJLy)Yq-uD72Vqg^`*AaGZ&Oc)GuR zB#0Z*e@%FyY?1$hGh93*ajw@UjV^%Qvg94}(?$1|577K|2A!8@#()WNSj^+H-nH5n zB{}q+KVENjj17moOvhDHSgMlHr3(M16S~VVJy|S6v8+0DN9|-OPB%aT`qfs$hOg+DPo@c#6}SQ=y4r^1R~s zW2>Bxvw{u+4-p&gJMQF6d3$l%6!PwP$(yt1amMmIzznq|7_Jx%0ntXHxZ;T_Ep*y7 z*XpsEb+!e_Er=BZR!x?;Wm8I*@gEHx?&@7i{Nai?J+hk2L464ts20imqMHke94p*} zA_ha!P}QE`IprZnB<2TPc>L+uZ!`j*BRZk_`#Klg*o=VEUp=gX9rmQ;KE^229; z!zx<}{u${{y<|Z-fdaX&pfJyf>Yo~0&{6}!E+-T`gD-U?Ty8m5{jgc+Ib_6`)L z)<=)m^YH<>Zx1>|Kt-sA>8QZCzCZcte?y*<5Dwt&1FAURMC@AxRJ-{2ZiDS@^wa5f z`nx-Uw<2`(o`T*nPaBn|*?<8gL))qq7#X?Q@K8V8JAiNcGEj8C`z5+h`z}Mk-0C%q z=h85Hi%T)Ri9|VbbAtxWhm0oUd8Rl7r8PM|>7X+FR2&PvRJ6$voVyY%9kL{fmpu3}#;R(s1YIj7#fs~dk^SeDFeUjUaL-}e& zgu||DMAG9PxfEcnPm;c>F4rE>+;0@>32wozT7CQAx_3~duw#+4eUG`cbw7nIU?14G z0luQ^?pMX{?$a@trVjkf^Eli_Q5-vDdKCPI9-RGCuY#^6tpl%}Qx6xDm0?$^pOV_wjJnU`bn!(r{bnE?8KG&c>Lu&sdlCtm z2RPV7&)D)n#9Hp9!A{w(J$Vp6C`|>og!2jg;43rP*;iKnpO@avC8fr@nsqlrobT|2 zEUGe@uztK5d4@Us*s$OF4rsrJ!qwQ!*;zWIO#3S%rvqhd?hdTm{hsN$19sVeI^Cvu zWM9k|PBQ$iiSH(GXbVEFTb_|G%< zWh4HsW7VKxZ&=weBz(np(uuTz@)UBoLKRxgCs;P?%bLR@nztv*gmyiSTzJ5&_M%K2 z8T#(TV=Xl(yf1&iHjIRcEW9em-^J?+(it>pcvr8x78zm&AFU&|jK=d?Cikb~Gs)xJ z(bj;&udOXL$ON^~JaDa<6~eF=|LYY{Y@RA-tIu!(*6#3a_H%8S26femYdr$q`b;f! ztFHF%jki_OVBH`=7koNdm?P)gWDO%C{)d}Vs{b%n=BR*z4hvbbqABIR36{7_Hs0w9 zUzU{d`R<)|%zBYZ*RHtPzwmy)rjjf%61&>c#}(lCu0xGrwXZxCL?RGY-%l0qJfF3y zUU?KJNuxc!9`%XeQPnwCY52PAxaPygmGM@>lCq#>@AWxHM#)WbK-FY_3DIG;0Zg+_ zXj|5CK8OnWz6WZF+kae}Y&XJ(s-^0>o%N836F$>~Ue>IMKov|D#d~H+sXJh|X+1Rg z9cRFJ>Xe@_VRBF*oubj?pK9oC{*z*da_kq~WiLQRu}1-Sb93wdD*`O3I(K@p*y`_l zx;Qw>@iO%*c^$r&Uz_WBk_|QD?|~sf?chJ7(GTa)3LwYHg$<^M)A3^%7H4z}MNX~r z-Hg)i;FDr*jE8Cx>f1MdZ+qjF|1vV5u2#HgNoZtsLp;~dS;lyfp2VcM!O$G8(u)HVJFGU&8!;b6Bfe!h!N^3->2=erYaL(HTYj)^T_2$3?;t` zW~Nlv5ca}(vOZkZ@Ag^Fl-=G@DIXuzcWcB?`#3w#3*+b<%KRL9r!UoANq29_5LGm6 zy1CeHWV!dx_xn5E@yvdq!SQ|&b%{@T3y0&-`WRJ& z3f8@s<9`L7mPF{{X~)_7%>Qa8gMhb4>HjeL|5gF`|D#fro*xZdYtHH~D5q5XL~GY$ zG(Mcn5aW>{a94A^-{_Fh*_=4C=J0z4kh|>f=MGVe%ecvJ1!|bZPWZUn#uVN()-pAk~afS_w(1QX3%vJ$WY@sqMS0aEz~kI%W);aYNwFi_+lV# zq{ZRY@sfz5FTCay0uO}Rn*Q*C9**zNYHuOWGXY^g4z#0B32)Q;N5fn@iRWr7FtmoD zh_MD5JvKL5zV|*4^%QiqZ)E+`_R2}y5tnPkqBgIh);g&bWIq@XTKa-*#WQhSYKV7y zgJkFIaF?BwkG-6q->)Az(R(6mJU_?2;o6CPyHl`~DASWeiK#=4N5r}&wq8R(8zw#6 zIyx#&$2$JUmZB)?br?Qq1nUq@1wZ%xN*r)*V?g-vf|IN8(LQjDZ0)*OZky z!x2rdSh(Krrqp+;2AEvc=#W)6xyZ`SJ}VO-N5M9%U~3phe8a9bFyC!egsv+?izLjN zamK)Qslhww#r^uncMbp?IX3jM^?7#5szhdK?kKR;qO>aE1YZ-l3(_p1N$x2>Tm7qy z2Spl!qx<7?3T)lknUO>ELIp67Ud586pUx^2mYdJ~8MkTlLE*a%BX0f9!X&uF5zyA+lJ zAb&_<92r!6p4CPlOqZ%OL8D}$qMwg{{()tS_dcz!-vQiV0)@(=da#lN%fVTZ2?=bG zvKamafpumhhpqdK6lX`C&?I2V)R@rPi{GW24+;Jl(Cg-$X8H#A*mnKm4~b3}I_VR` z*t*0C7ZbyuTJ3e{MIDqaMLqD#bu&^b-`nMhy?r_ zKSQMuqUkJ62Ngyf8A6y>JM*t%ZjQblM&$FQP61p7FW$c{rB{+hqdn?B+sJ!WQZ32n1CwPPQS4D3-aftCoh zML%LGVU%}%;o*V%I&gC}+1`dx4~vH>$m6M|rXPDs=aPw&I+HI#qL>TWWcY(f7kI*yNWN5k-1oEwkz}*ld^`4hjeFAq z1L+?ChdF4(m`lda4|RTYX=wHS3;bIrn8?MCLTP*wAKNu&ePu1}Cf6BZ2O+L8LI&UF zB^D;Y_DY2u4g;8*j4CS5V;~cMx?Yc0CH`~^`J+baL-~HnLRF2+(6Bed`;0BnXaZI> zzn;l%$2t?(o`Bo+io{Ws{JXL)aw7v|2a3Zz#<}`7o6@l3)p;{cL8%tc0y7z?+>p9% zxp=cCuVWaz0XfiAqr54xY+aVp;y~=^HWa^&uVmAbl-cBRTbG4!yH%ET7&He&G2g$t zSbUl=_39Px)~rr8@MIA?4(X3nqbJ{D@4QO`RhtYbJAi)^DGv4;K$WjB9gATng3vs{ ze_JifGL^F64KZ9%c)vkCLrl!cdK4p|y3cLw8f5U=CAMF&THuY2C~?8;YCn|PIK#=d zmg&NBbGaFuO*pfa-6uiC!#(a&l_La(=?Z*EBXEnHy_z!MXHgZG``Ze;uB&WuN^9#HHQGh1vr^!4hLM>J-!!t+EngXa9QQ9C&!*` zqhfF9E{`|!#)XF&uQRlwRLtw;Pkd>xVz+%5c7e@_kzKvo0*BSEj#1O3e8pJcL0tzA z!!ihSaC4bkZ3>-N%2tE#bb$?GfcNU$_Nx2*mXhOZ`%bJgpQLCGdaPLiVNSov$hj`83I_i$oulfc6M_m#@Wqw|5Rjb&k4q@%{vBDvbO+ zq%~CHVTr%_vgkYqCZzY0%3%MQr@I$(JW4irM>qc15W}3s;*u~pD9t^%_Lmm_E*E;P zXIGhkQ=ky@Pfy}vs;kQ*RVeCW4S=M%BT4C^xW#B982|=c#p1k%mFMkDgz&V1!nPe3 zRk~Puh;$BFdV0WYNn3m#SaHKCd)RilcXTq_K^6)UR z=QwBR9RK8PhvuaX?MpT+&Th&d^onhym%o5o#VBaC3bzzKQ>p@M<}5-Sg$?rzdc#6cOI`Ooez#{F8_fQN@@=I1r8f+!aX2s6W3qkow=)mXQVSP zWn3qR0uL{@YboW?=@nkBWy97!&gQjm#>yuTJG1oi>VG z%>YnbF&J`93%Bc+HU~Vq>M~ya!KPCag5I>IpWYGIk>JrX;@96UUT<(BdFT7;K^6M< z)=YLDJjDBq&WWJwE6myvY<@WvZH}tW`jmOHFsksUD^~oRu0@d<5rI9;Pnw8hW9$Hg zPA7fc27D8>ON9k~%po-ao!^Q}{$-%Rg>&4N+w4-t19iJ4+50hhg%n2r8*gAV$i&q? z!z+rg;yiGJ==K**w&~8xKr-Vuq+lv9D9ev)8w;X=0>0I`f+35uf^kziTDv?-S-rs9?uLIzJ zgySpA+Nz%uGF+^997P`5za*6dvM7%QXdU%N% z-@VJLRP1gwikDK~KCglJe~095Z9HP2PyYV60?==Ebm+w<&s~KC8ZM?tmxFh}-w~{a zoKIKXE{S{}PmTGP^TNljv&aMlz)$5-iqSqV{XT&{KWbHK+215EFczZq*Q79C<-C=S z$xUxNjZKgDo5&muDYOx0iOa5nkCO9eAc+G;rJ>Y3z!dEwE3Kt&D$ZvR5>^PbhPAJu_gT+6WH~&BDA>Y;q`7#`bU@WOxU)o z70%F6jIVZqL#l9{e~?hOmB>~;3C&g%viMOK>^lf>o5wrDOy>!A&rX}A2ufypH%XL} zBGNa33WT3ng0Sy58{*gc0bY^5bTDX}GU^vqq3`UA(4ewERY~xY>%m@HiqER{Faw|t zycxRGS4l}&>g0q7nQgma{w9DE97fk_Fo+cUeWcd`Te zXZA8w89cY+h0gb#d0GC%_38}VeVibf29nX$BV{G`%;8E)vL;hyXbS6ZGp-N8AHg5T z)3^HXa~%9Rt1;B-%IJFQjE(I6#thzWVjz1gqv?#>WK6B@gs)sqxT-eweENR22Jk7J zFIWRk@3167cNN9FdtV!N9717KXbn2J6M7Cow7>smNp#d^vwyGUOcTYP!kwY~t1hFF z>(^KvZSLqG$=iqs54bU*H5?f=rj4>Lq^XI^`aG3#b2r^qgoo6?;cWJb?jKUEeJbRI zgNfh3%IR~zsnA=k@%FcIZXN1?{ zwroF$(Mn!1&N;@yW7aptW$wPeZHMs`YyOe34~4O{#^-4~8h$-?NK7D$J7mbcazg!` zhhA10_^yWSUFt?Rmj4uf<fQne9&nTq_2xM~l9^rHyFU2DF#_HL_Se5~!%& z50=2jX%1P6#Vd?QkGXq6+8-;5$-8s(u-XrTBi)lVJpkVFrC`xprbn?$s%diYbuh(m zHm4@2#_Eku{~s8J4=P9 zJW!xnu#i0&1|pszshApje}gBRII7syfY+qlA+ip#E%ek)uDT0b$G`l|Diit=2Mv z=nLB^G2$8b#`RSf5O8+#%4@rPA57ri-^t3;t^2YmquKpqb3IyLqcx6`ZP90q}Bd@HqW@1!Q;d0^zaz`%jh`!E^^f`)08S6bGZ zd>gkaG{O?9L5V@1R?W6vD&N7w5Gy5`vH%Kc$P#w z3nJ~th!HNhWu;{(Wa$WYB2^U6Ta(~;c4d$-9AIIS6?6h*F@+}nj>8Y6ahf0H6RvqEg>3j;JbDsmz zCLZ%j-Cb{~cjXmw@oXDLjt(=iXMZC(j8e{Dg4Khr6BhL1RO!I#>-DPEu zY$ob|Y{C8`BHFH^#+gJKt-+d=;L2jRaDK2yFCZrmEjzFMguM*ou)Hrfw^7sn4yR4c zJ{qi`X*nGyZy=0=Z4Rcd>|Fb7!5`VIsOnJ?-%|*|ipMR!-%ZpvX`sW(WHP$mzmVsM>+}2%AdP!2)Fr|isCLQ zD?+wINY*MkaI)@8%;iXV_A|Ph@cu<5IIStlrVw-&crrE1X!+ow$PQ{(di2Hb=w}sG z9pmh}nUBwprsjK->fIurE0d^E-eDZCYj8nlMhR7W8{VJXS=4NX^E8LH58}O3iy~d? z|JDhl>$zsdpfZ|+gO3Ok{Ha3|mViGSA&>Z6>XTCOd4RiDWp5vAHQy2~5}A0-24Y#0 z*j1vME%OsY3=E8q$Y!e6VMhi8jo zZBfLOROY(HABuHFG`5Zv2m<(ULCGdYh*o^{FjvbW1SFhxCoT!mn{bH0HA{VcYux`1 zveo9)bvQt`ecplI%y8k{Jb*!=RN9GSo-vGfkC9ZnR#`aJkPP$QOlA#Iq($ccux&{e zjV2S_#T-Y5p;S$!NrFG_*t}|5l1dxFz;&6qZ!H$Iq*_oLTzKOK2Z3MBlOM>QJ~=v= zLmO`}-X4w|wpl+=VW{B{D)nBBlbC!d2U~K{7#}CaidWb>@2ft$vwZa!BbE_)M~0$er1TikcsAlo;42OP=TM`{kEgs?7Iq`O&>zvkP{?# z0f4iTJxu}E3^DojiF(no=boZ@Ka#lm3)S9rh`XL)lA^MNWIw)*-z&u;r7L5CpG4~! zdGcD_qeCB&6ynzE5co_OKTX2EX`udo`Kp;_HG#B9zt+^GA3HH!pImU0Ei`3U-mJu< zAjG78@i1gw40>&>*(JZ+v@ueU={3ACQ4~gpS&gD(d>+I?aeg)^|6R^5k-T00;f!(kT}hM> zJXVB>6P4jBNSbm^&e9Oec5?5&SyK5w!&o@{_!K~T8~Qv5i6V;w5hGXuqjcYXIk?6h z?$^7tgJf}VcT*^JpeC)AFS|}H%by-Eui@Q)zEiN@^zU|PO=xybh5*usl9(K2!7XiH zP=o~e9w;)snlifDtHZ=TYaxeJ2KNFsqL_dswN*VpTx5A+MU?%0aGmu(LY_O+g@?v* zMvC^jle|vaT79lJzXswro}xV7IP$#l91qkIYG4Ne*(K0w2W;cmk)CFk9{cUuJCHnZa*NBz@bp|EhO2v&a8{(M)*zpU|cI+EHj|2CD! zn321D4jE22SC3;)IuN(emSU>AHc9iUan+1_ym`Cnaj=>Otl|kD+3t=>6|7YW8#?bH zghf^uiu^{`c!pGBBNjw#Zy78RXAW+&T=Th9aV0EDmlPEcg&6QQy9+-=TMZp432YPooROSszYtL1 zT5u`wK>EKw$rBi-8FF7^17>DtYE1iC)@vg2DBkZ7zg^(S*}VLe_c{Qb9fK&GRafT+ zbccM81~pwtE~XR!moCDLU_*!wQ^})tsu)Ux?&*xFb#avleD7!q>>wfWL*-NRKVPa)K{4=eHKWpw%5h!bmK`tr(i<|}&p%I5mvxoXueuzg3@lpq6TZ}!C0J%naVq%V9 zDkXf*8AVAcX5>8cq2s%)))jlK0Zz5kje|ge&SCFPbrDXw2((}biCAoZ6cgaE1lBv} zI|n)WY_2*4`T3zGD-?qUgg7n(d!=1Fcy>>G^gqKvT8*a0=omd>n$@6(+JhXR3=BEm zwrXozAJCI=ZbNwNIBt%mmgM|KJJ{7h22e%$-3TL~`Y=OJJ^>?*FOXH9jHl7+0Mk}= zcj5Gpk|`rw5rRiiNhNeI|6HZZ(>q7jJ|Y8N_C@FlYs=%KoU#nB+kBYAo4MC}Uq=5a z{85Go91Y;YQ;!`XOn;niK4t=_q&BfPm&SJX`TY1C6{}tyaP$};IR(K@!*ozWtNnm- zdG>~SPq9hNvk{CFPQjIn{g_yrt3Hy-6Q*d3>0HG(ApfW_9RSVgyb`i;ghi!>tz_ei ztRb(EW)EG0@zbp%GkQea>dSz3UD|*g8$lzx6mvzU1KM>|BejM&hx<-1`BqlgEW^4tlzke&q^rzlXQZ_o40ua4jPgc|G zh06<~7KlmAch`d#G^Z$x6q9RWM5=6i&}4eKC(YyPV%eIKg-!9HGrdATSB%9LIRw2G znH(>*1#`rrGR?q2Cm(_AlJ@6W=b^y&Px7b)bEaC7 zB3&bug^4~YDn%fayBcu;9G-^dHgpd4jbRKoZrKuD)4eWCiOh&ut)ZYI60ft;ai+QC zXX|et-y{mYRTLe8n*Fh7rH5IeT7dZYMI8Y69DYJF#0nE}bDR+j68i#{=KGvJE8w;o zZ_{6i@SVX!wr!A>a5;V8+^XrcC)+h9YUj(fs$S57PCZK^llw@)ihE`*h`ef8$l4t} zE%Sq&0?b+_xiZoO&IGXnAEy^4L`J*e-$I58-pB0MuF9HRJY5eDv#Q-IPK1KNR7Ne z%9J9c%cOJ3eTbx5j22xXGt9#at8^ZJh5E1m+8;LPhoUKru5}mjHwAe3+pHzU406Zjlx1y@1aqw&=Cd#b$Fp;!1d16=(iBahNW?Z| zoCK-joTS;C%cz@d^tRjK6^s?dW|m6WLu22qB)hs}BgBEb8&KDXlUU4~Z1BuWg|SDK zhbv=DQWAAIG0n!JpQYrDo}U!WrVY%v+nO$?f15EhoF3pAzPZSLae{7e&TxA0UF3|C z_dLch$sdUF{;6}nb%vXp^LOaY{V*0A(;u0!KlPtW{`PuJk`jK!T*NV^KT7cO7BQO5 z;Z}}DD-VxC*gLRRtF4u;=c-$&>gB_7XO3}xy6-=zAOFyMzuU*CVubB#5z7z z>?JkpighuY-B75&ed1OqN&{67cfK+)eIch2e3R@ti?XoBmf<88mb+A)>UMNtyW1b) z<_5KXG-_L*oYp&@@@yn4O(9j)mzosVRhzn?)R2A!Wj|;dyE-NPA{#a`)`WW4b;X0D zDG)qj_c0xu>%)YhRdjp~&xqEjzzFiKniW1?=ESD}pwgclV(mB_+I^BVDVWS7JN9%e z$LR9mYq_LW>quK+q?cN>Ga@+cMj=MXx$CWl))g(a2%+=1vrj4!OG-e@Oko@)Mc_tzYNC|xDy|k8TPnI>4 zl`>jADK0h7Z7fWYQ%e?7;{O@ymmj|_sv}2_5Qb=6oOl9-%f%AQIIvWsF-xhPF7IF$ zT^VxlI);51h|Osr-oQqWPor(-j#&3A1fg^i{UIjh~^FI*R z_*>Q{x6fPyY_zX;AKN$qq>>|{DQJ7-+6TNwz1g#R5$Af|#(Wvp=TC99Qj-}&!f_E) zO-V6sAbk3FbPiezJY(7Jn-GorR1alAY zZ+AQ${q)+Ssh_rYbtj08)u4et?%&<1ae*KGPF^pF`=o;sb%t{b1_CpI6PUXSY>gwM|Z)&R7UHRrR z+K}|F3x+uQ8}QG?ZE^OZ^S1%D=f0PYvm>x6A|Q=Z8ywGX19u2ceA)F9ZefJ!HuBLGX)u3(kg7=Zr)6{NP<{W^>@Y`9|@f``E;m zZH9a>iQH3b(HH9T_vaDQ-2c!1Lz}*G%(4L=TyPqvu8Oh*JfJ4=~ z>+I{2(iaBDJeNS6If7$EgPh7^SsF=W@ec<=9CRI6;?Yxm<22`<3I)acR1k&D(YPI# zJZ(L#rb_cC^Ox_w_0b(!<>VCvp4jy1mSk0dc)4nI8fRIH`}9D@li^M~@U1j!Mb7V@ z-Eoxv5wQLt7Ct_rL;sI{;Ifru8x$J)w?SANid?{s8l%C7SEa~hwFM%GtXgkjETuL)moUbddF2btC zuw^T9a&o8$aT|yK4m$1FChgq2%}c*upRE^NT-da>wbiVilai6?H)t^7L==~Xf({Ms z?4ma|bfBQ1BxPmExVW(EmOZ|^6#NqH^$K$9FxxR;!h**lAMfdX(t?2eaxaE>81G_i z690oF%z!#mKNgeD178y&Cz}lEk#RRR`Je^)U~$*mY6v0eVky2pVdgfGZ#0yW-**T` z{kivwyR0wk=;A*A3i0>0Iww(meSLR#cUw-}RMgbJ`1tV4=0kh*1oNh|r_H8L@6~BB ztk`jDYHI2m8jwRozwThc1&x)93tVJoyxn9HDjJXVBxm^c0ZSbFiY<6nz2D^9U8~bD zUcZ?XMryNn0MmzD-$R0zkEq3E$0;@eDJsv|w~afzA76i(wpblAQQ{82*ff%TZ9od=*?z+MA- zvyn8KHSzIK<1kx}sL!S40f zJjhG@Fij+TbwakmEM6kJoZTg_WThiTXT`H2xpvf8LH4!2*MQ*K!?c>KFE59 ztw3w#OpCleBXKtDAFlr4X@=la@@nVy8=6i27DSTZ#?ptidS5g`NieOU<=UpKk4kc3 ze#G++MOFURe{Y;5hnlQ~S~C6Wwd!`C88S`vQ_8cGBdK!Z+a{%L(&|q!xRf+=sJzZ0 z4j`Qc?YXes&S2u*uP43!>sVTj`DVVF7OhOh<2?t!DzS0)TKRy zkP^#^CiLo~YjyC)oZXS3zX5ocV0VHr(uAC|&=Hu8efg&a0@4!qon9!#g*gmq<*tr@ z?L<%(Dh!+XGAG*-!nuu|=XU`=9A_UBsUHkL?R9pjol68Ve*Up?&x75fm2wMxXREX^hPr zr2xw9*vi&Wx*((%`oNI4A(2gI&kD$k)4Y}A|)Z^9q=B} z1`Y5y#}6=+IBJ^j!Kw! zFk02wSXz=iKx6TwCuwOKC+%npT2R=3ag(3HgV_bi9rUaLyQOwF@XwZ;vs^4+e_;1+ zSsogBv+J8Mu20EZTH{`1CoQ}HxVg39n)RQCb%FN{Bu+zSS5Pwj3y(XgF=Kg3DF0@o zHuMU=>2S;27;ZkSTWwBDdE;%tDcZ^qn}w6{*9BiFEdJEb>okt`eM2M2Op)vTLl@k1 zzI$&yA(OH!;use5N0$Y9^;i8-7-a{^cT~Alz?nWM(%nE6nG=(zh%)6y~Qf9Ri8ldB<&k4;x9GjtJETw(5O%L@Y8j`l6Tp=|1I4wo_D zB)?YCBo~8eJDb6(*^fXVIvkGIiEqdMP}pSJ@Oa~Tsd{B<@;3cGRsj!msWP5#jpDk9 z#y+_eq)Qp@c%V2K z*$ZG8Bo-@+9vhRM7w%_MvOfONrEMNsMs-Q;gD$gw!QU++BNSdwdVZY;Bm3f4GCV)t zXL#K8*tAx)1^u#EZr=#jf2iPnj>9bue?8u~Lqg0l+un*XNThE+8wb$h%;S|8pgeH-_F_*A)sh}cQOIH%1kXx6 zu2R@ORl9da6^R6Vl?oU{HEay;t+^qZb#wDZ5HS_H0HdZc$N9`hf1FSe4SQ zx&!)8z@=E*AtiMDv-0nRwYNFt8613#I!Ft)J&b5WD_ld1+Bn}#8w8uI!FG^5QJ-;t zB2Vz~IWqmHw|nvHgD@=u1a?tq5z5wca%#{>K4!XA+Jc|5D}%hOO3s4wtj@Zm^}TcX z3jik2RXqD&dOIF{)vA#7t3@a?*eKQb*v>)%#p@RXrCgn2Il~j^^9{`HN6_2dy+8Mu z(1xu1bzD9{h8$u^q{2$9zg(MNX$zE=oXpSZB%1wUp#endXhu z2Qs?dDqp&d6t)2u+rX&r0Dl=F|4hF@RxDBF=99|Bj^^5hvPo@ErBXV;lc-7a>b2JaW%^Cu?YS` z-(z8=bcOYOQzp@nqN48_XL*ZBG|NPa5(Js^*b*39L`C%Kmqoo1AwGoKN8rZE*{ETr zOk%d<`v#Bx4;P>@Is=_36DRZT8=pl4#<^KpLINu+l|kS@^SKG0h2Tss`^pHrABq}D zj#$A=-eQJUTlp~QzSjzZYTZ39UArMz16qEQRG@Qjfy`+_^7(=x;Q0DXQ~v(Ixm+L_ z>aG4ft2=hIg_f`Am()xNk#A<7vcQ9j@~Ttv9CB|53>4H)%182)i-2$?c^+!m{2kKT zTKnd&Cg-D{sgQ>kT28_c+=AXfB^o)O45=ZWK(1=Okm1JLH5bzD;GbnK2gZ z%vH4oe{O8&l`sf5tI7H-)8gDt&g9KzwCgIOn9UU{ndd8~-f!kVo}e0+yRYTh5Of+Hq{ z6h)Q3rv5IYfsfM=#4>~xOS(^b69^6B&!I#LA)%0{OlU=-U|%#cVJOW83+l?Iu`iH%q|g4A!b?(n*YH?d;C%t4z+R3;b6^)L~V=$v+A`2(!;sE{hFvi zH(4l0%w@ai<15Mqba5J*aEa$3`C?fZ`w>JIO5W%NvT+UW3rbc`@oEC zMTS0);dR%oYvL#zvbC;vHcz7?BXhBxg4F8Qb6f=;+H{?E!i!V1(=>cozn!-gOwN8le<)1KsI&TtAO3LO=_5#D z@8!`sI>*oA{tilje+#?fhhx!$1Pa_O=N4Z;%v{b{Er?I*jt*&i!#$PCPF74iJ> zFq(bGYrG$J-2L8oxR8scir~IU%&4=Ow>T3DdHHmBJtHK#VG&+W9;s85yW_jDg}tYM zh09sEWKVbB30Pb9OK)4^ZnJFyz09**G`=nLTsUQOTrxMJ)-hyoSV9G_h@Kdr<^IrY zi?iD-4t&EQ3YZ^P`Ee9;UB*qEFFt z+$`Qgm5)u=+iNawO1W#VygpWwqUCn620NoDr6E-7KDsU%EBx(upov^re>yZ{A%^ZB z9rf(GK}Q*0+IIP9DkEv0L5^P zf4n@;OSb#?50eX#ETc_Ii;C}pwk<7Vn?;u&$EO}e=_G{+Om)}eA^aX#SZ7x}JeP1~=s^5qfp zNw(?o>)(-HLNXY0Z;@@^+~Z@rSe)C`B|*qs?y#wvM_IpU0qjIL3G~=;bvp7nHTw`;CA7 z=@gx}Vv0srleX1`4Dm-j<WhxMmhmP8QQZI!Xu;VV0|7FCC1ZA<9rs!4!he$#!-eD?hj*qz4ucs@uTEr zhUz$$Y&*_%VE*=iqNZH}%Bt89aD$JJFPaFTQAqzfX(drj>K{RqA_svbR<^d#)f8fD!u&Q*Y-2f+v0REP(+c27Zhk78TJx>cXZ$ZP z3ogTSb$R@TO!m3&9@V90ENBL}%Y*MUA# zl{D)!y9|&0Sf{7O^FOowUe60#hfXl zYE7|7EA3^n=99VHW_=VFu0&g8RN(Nu&%6M?)@)l% z(3RmqN+mAy3HE}!abj*pQ3TVd&}cvd(e(>&Bf_@!dc@VDvl)&`Km`dK3(2TuqkXdJ zMw5So+wBxd$i}SUV)AH?j6o9$2Yq7X1ntRSy=imBzO9^UOG`3xFfK`a)IEaxEU24W zg0lQ;PweFP{%QpA4U?#mPv1yrx5h@n1SciN+wKB;x)w%C*^7Y>i}AdmJbsoz`aj3F zvCeo%kTG@O;@H#sO)tTK$DLog)wu1ev5*(Zh&9`QGgpBovfl(U8^c6~O)!7BmX8A0 z3;lY-Ra8{0(rb1Y8K1Ax5!caK%&V1xoaY<)GkuPyeT_j4cmqE`$kx!13c)#x`bctP4R5|p1TEOtwmcAf((jaUbJg5ki=&zZJA9}+QL>jMRC4k9F zr58^x_b&lr`4a~~&Kn;g%}SiK;n3*=iDJwovVX7l(7q2q48tl{7ojTGsF)V{Clx*r zL3kGFP_h63DH5b>S1^G77*Ys@gQS8X&)SUL zn3FI8a1f`d^Y6`#Mskzx4(m*i~f3SrK!yQ9fA;!K*&LzRvtPEvpX49s;nz?<7?t`b|Cre|mg+Liq6B z%+fL`BO`Li>=C@#x0p(LA-TKM6a{@Me}C-`M%(N2=16fRdRR;-pkYr~c`%1eyOh>P^)%a@{Q z>jqsW{+v_F$_=WOJBl~ZVK}inwsCsA@(<&xI(qElth>N#rhw+|G*nBR`ug!#n^?>X zvJGH(*UwZHKDhx28h++FhCKI4rDth_y?hos3XNRlfj)(Rw~{Xkc>z9h>mCMg2WR)Q zj{Ht*ywQxZkI>Y9f1AU(h~vmvgB!mhD?R`-Qbj`}q<2HKayFOri(0ZWY%S#3`*f0) zPRlwwvysNZL5ja<*VQsv_6O?Vu``6$rtAncX_=s8%9y0E_SbpY5R|byezc$u0W~$& zg*SqvNna9TAh#*GTvW1P#5fTprhK9X_I>Ak{y&9E^v8{M$oZLE7W7_r6OFCqpJtqg zV@ji%AoBq-SI$sqSv}>zESr=`4AHFYKk>kV{}6AUAp`gZDTF9a!M)JxjGg0v-wiRR zqA+E(P>7}W0|0nAq0t%cKPzpeX-obw&CK$v%w+j^k|^!doc*4YIv!~uLVp<*K?;EY z+4+XO;IGr0*%@f|;t_5BxQb%)?Gh|>{$EXBg#FgI6G8B+7uJm3u54JsKW-%_U`CZr725=jR_s?+l6Fe2WDE2wr6hmyDL{Hfx~ z44z)#sCut2OQ*Cg;HSV*G@H&%I?E`S&+8jWw_kXhQ!;t$cG~FfCD#?5QC0La{S&r; z)R7LvJ0pMJ#~kpWB(zb6Yza<*Mt1XL3jxUT630g8rX~RpAkAfXhY}kR12L32 zU4lL`z^AQ!!DB&Y@el?-(FP2WOtNK_k(nr2i%YCfE{OC_*D)=rJyNI+i{RKMeY?uN#E-Jb zxme99{$K%m17{8`izTNAkJ{4*Tz2_3naU*O>pm4sV-JRCr&V?m%gBQ&jB0X-`(oj4 z+1^fQ1B@`Zmf(NL+uWH!bKZa1W>6ebwDUSDkM_wPW4W+LwZZpdW zu06DPQFq&l2h3w%{OCkP`_1_pV^rs*s=F-E7t*`@%3Dj9)!-!_fQU7Xy5s3>?f9CN zDJpb*fByV|8D7J9J``hb#UP)h$<>_J3mtWX|E z2ba4My{D}>)+jiy@U4x^^~qDS zc4g_S=bf%*^;7y5YDWGm>P%wfO8Z+@DFd~gPsXESjf!ha zu>@Ar-yT)BI04PjmR!w=+OxYQvvL(9`4mO)amSRil|B9T#{BsNE5M`1dM_&c%&6a8 z9Yh=uePTO5<$tA1+Tjel15M;@x{Uhz68ci*<3?Z+Zrm4U^t*I_I&V_#^~;a$Ga836 zyY2n6fI$*l5sRQvv7zHnOPQHoFXlvskAGxw@pvc5^v9P4ZZDH~GVd#WKZ3FsjrSs# z#Y^AJKpNPYf%41Qfg7;`nl4Wv%z|XEiNm>pd10ZZzjPUeHUU zpV|0EVwOH~sIB)7SanzE1>LaS7#AkzseJhv>vVPLXB}hdKVui+-T^;YrBri(tXR$4 zbzmO~EOa6OBM!`>%{?4RXQ2blVxF-2gyfM z3Jzr(rf2{)sL$9tX&jw?$x+h&eap6ss-Ap&-h9|NP-AKq_u2X6)km#1#Wo{v{O2eQUHIK**{GH#H6tlbhcTI7JcYIP* zW2(Nj|G`Z&um+t7K%?os*L8@@>viF6R>W@vJ1kAgwhQ&PyYjdzpY$f@55bs(*`ZLl+PNWZLB1YJKAq$v?P+K z{3nPNyM#`BK`L-B)d9CT+MoKXlE8?#^p)ajr z<|Gs&H}*3hSq1HveJnyraK<0KWgjqKjPp)hNi+qW9_y2s>vdUyBSfN zh4nkUaNOPf!j3|o-KL^E3ra~fAyqJoGq0l(zn_-(5sO8qj9JS>Aq-BQj*)dbUT?w>?^o+_3!)Cd$(x5 zOIJ@8kl0H$BuY_8R@LG+uf~X@$mq^U2`oyfY}x=C$~1hg+mdX%aWaZll$U#KngR+# zJ(0hse!J!_uT^SEw(i8NU-cPb7RvQMDqrh}y@8wln%DG#rLD%7R=lSHkmbh#Ot_{W zLd^FzS*S_;Vl6y9KaJk)tO2HT;++qz!5WCnGo?kU$?z9e0=@=bF?Z{3n-etgrWBb% zn#eCaZ2qNcSU zIsJDI(<$qTN@bj6C@QJmAzOMh+C*JG80*k$ooYxV{_Yo^w3fP*o4b|Yjws({9!6Rn zs6PsOQX?TxsxDQ+exdMgB{XY~@w=4;7fB_??7L&y;KVB>&e_W1rl=TA8L7QvfQALW z3+9V07#zHCKz%udX_|GksD9mUT(LCMltq|+_9)?HcsQax)Ok9sf6ki^6qU2>G0Xdf zg0==W@0UV0;p&2X5iIA@Ws{{io)Z{{t)xdO2WW=bqYAQx!RfGiRwwEk^DKXwQj$Q> zm?_viTnTDqMvlvJa(4V~46_j|;~Ul#dh*sT8Fv+isnkseQuW5NvmCZy>w4#3g26Lu7T*>RO#vRa{)0F6vtk>#l_|RG&Z`d%TCKp$7`u ziU?UVARkt6cKp0&4ccyv%xw0i7<=cWfMYcdOcc(D(C?XE$OL(RSmkX$WvTv}`Q=G~ z{BQwd#tI|rg;rlGOC#u>{4@1^oohpjfREKd1iQ$31oO%#Wpb&~W0Nop4Gd7Gi}{rN45 z%Ce({MHA}s;Be{GS5r($ZvpVBx?9<7hS_erv!Uz9=o+2D_paFsq5=Z^G08ZV@hP{P zCzq+=|uns?RjnTkP0tN%ls+9WZY}uLFuAV3Tf!OtXdc))CiVh zoI-aIjARsNCp9grNfYJgy2Z-X0J_jC zCGqc@HkEE$0I~H%6`&)-ip>6UkyM2b6@#>ZQ40a(A?!|fU>OOn97~q+?a&8Aa!WD3 z*lgM3Rrjw(ZtUu~DCk?PWL;WurG+TtKbjYH_llXJjHE5I#b$4SoOxv%KXWYv!Euvq zS0vor;C)ha<5ob58mA&f;XRb2J+GLaEnaSCBj+G2?CwZDJCfU>Yv36&EZpO_494mT z@cN{fKM+p&NHz9Me;n;~<8#xT+oUIkbNk(MW}2Y^_%2YrSCm1~hg?QN2uD4PsB|*8 z6dVoCBbVjL|3ua)jFYGv{t3^N4&B6QB9e(ESV!x0uX8lKywbj~-GXR2@CDQGDUO5~ z4a~=JHbp7RkIlvEfCi{ zb$IdT0Eq*C{*PP6L`8AE!w+@mr-&ldi&udgFaD(qzh~y%(;;NVgbCABHzdIFU=+~!U!<(q(53*7un{)9_ntjz59G|Rs5ZXV7Bi{jGq zA5plZ_v6hAO#4!+V9b<8EH*~OiIo?cX8&om87m6E8h1 zUWX4n+E1!TJx+K*FEy7Zv~O98?KZq?t3dEkDGR{ZHJ#Opt4!iOWEy>*!L=)syy`%U zjW{_!51E9um8Btlj1uD{G&eGWithim>OfYweU7^5&V^cpxz~!+j1)Bp;;Fr^cDH+Y z7E3jJB2RO8}@*6YMq8 zq!A{`pTAk~!jX|)craExT$%Z&u;B_ZgXa2>y`ipH?!Z_6Gn%;-&E9&*ip=e)et6Y$ zP)Vt37&Wx>tZ7}J@E#F3bOcWb=3bA;N&F2rPoGLaf1(X{di6**L59ear7d(-`eW-t zO^NJT)-wm+FSE$Dr?kfBOSu`kFX^7To{4L^&&312gN*8wOn1<_N1unh7npPuYLG8x zN$xHun8sPL)8Z4&6?Ezn!2xZF^r%>{XI9Q{RL%j z^#gvMxdn8{$jGb^#Q`9zkk0z9a56$y=n-9!A%zk%a$;@{R@B0RhJb*;H01MFx;0ZF z0Fwn{=wfz;0}96F?WF2*obxH8OO^Fzt_8nR!z6)fFcVSpHh7=mXR4l5!pqEqjrA4s zL>_wqx4_UqG`}P2V#Z>j-4w6H;PPnXi=tN$w!`J`C_4J#fgeTWOZ}iF3P4))N?rYt z=kM~+Unp+3ux74 zj>v)FhsSF{`}zacate&o;u>! zU0@sOQ*oN>4)kzF+PPZ2NR+PyMaClcNV#%}j53+PliV%$YE^vDCn4 z=zrk%+Rzn!`G?6Lgf@CF$jHB~m~g9FVbXOAS}gE3-AW?vu3bCmB{w$J*pZi#Y!5L9 zL0wnZFM}=r2WF2?HNDUBocI%o74aT_l5rZB1qzDj@$Vi1hprh-Ey*L(Y>>}<$auk3 z*H>QBxV(VYS_md{Xf_3Dv*II{;sI%sWKBT$!NI{02x_Jy{F1ndWFJ=>@Zv*ALSunLTehS^Xptbft=v!myvEH*N&T4{ikTDeAP;J=*v6;t1c zXM`hCLiS%go<11yZ^r)=0RMl2=dGBVz8BC*P+}BJ(m}Kc4F)d1_dwWAgSa8HUsjwD z#|Bw--Cvwb4xfjEr%*6;zzOjdxxI%No)gS7G#EkwvSk_!5FG;o(ych7hRnoj<_py# zKQaG9-e3J>C#^IHj(XJ#l{-5-uWxTR-T0l`S0QFwh{Fvseu(aeRP^=T9fZFQj*Zc9 za9|}3UDHbyPZg;#AuVm_` zH<3in4M>uyU~L=OhhoEJfZX3ReHoeec0wTOQ7^=f@c8(6{`8`dE11#IAqau~{5cTy zHWWhGD`!o(vz&Q}Au1+V% zbN05c_v{eJLNdl+VVU>RNI<Gh>wuLdxdpAi=EyBM z4|zy<9kV4<0WS%d!hat=?{xY)4@C4ZVwC}4=9iVhhxZ0)RtgEV718A(8A(q zl_qU&nh27jL2eJ?8+R^L?RhtK%8N^SF9G?7^_@gGVbNd8|ay+gy&Mono@ z&^t&WUtV6IAQBA3rtRFS4|(h>4m?4kP&%m)Yj^tSE|LaC)cUmI=&i+w*7&FCZK|my zaj&oxrjKYzGJ*V_YGXspirafJ>4m1@@bP6ScHDdcVc?D@vqiz|Pg*AakIYinyJ8g% zok1D9s7r)xd~*}Q^s`F-XV}cG<`f*i8wM3k`-I$=oS?%!NR95mqt|(Y8f|V|R~9WG zZyT?(;yWwg2QN#1HkwM(tKtV_ETiExU}y65t7LWBSe8`aHu8QXcmZ_oN>Qg zcqVEw4ntAzh!huSw?@;>aIawA2vd$-WeKXR`)TYpY3to9Fqs-FCvyyIEtv`O9* zcXu(lOg4e3c|WS$WTcxD-o-Lx^fSue0K-F+>oS0^-M%hQ#*oTUQ#|Yyy|YU=Qz);m z#jGHuYSKZ+5DO@M3+ifnn8D$@Yx_dype*F*0I%lf50fM%ph?FuGxh7XQ&@jynw>T1 z*TYp=8|PWoku6od7yp%GOCkaHMEMvN9yvkq7)jN#fwa07daY?gtcS>7bvADRf_~|+ zA^IILD)_*fFK-+SG6k1aR~J`SB7J>+_Olqx>~FB1cH+<3cjMP*#>-cUP@!|{0m#W- zPfxG*H}y*W)@1oP(GaW=7qk@w!N_6K+V87pkG%tl9J{9#8RtJVA*-DPR4u9?7VXe= zZDlPqnWKd-!OEKHs$To3`6H~DnyHGfQ4ue9CKz_BDg(y9vM+?u=FlWsn}5!L5&uK3 z$8%h?xYe7R0jzRmHB?Fv^bf-x3W+=ItxF#;{>AmXFl`(?+g zS6>v)YqSJ4$@nSfSlExXZ;d$RHF3EfX!%8%sY^toH4C-ttF-)`!A6*5a`h|^^8uvHJ^Cc8bM&$^aH!vR?G zB@*EcTs|FYs#Bat6>~9=1sVKOQRQxdga0^1Cd6={u1K+YcjP35dyo|Y8KOZ zck5+;RrEH9Dg_DP=`s3g)0msvR#{nTdbZZ-=HZdcJU=rdL75<0tOj!05QD1H{0M1+ zJv}{0nxY5|)9Yu&0}V0b=A+cAkHqb8(;7UCr3G?G0IP*-e#LUk-){%bq+e_#_|B0H zpK~+EphPqK;^SUe1eKp=!dow1Q&tSNd#-xMwN;t&V`FeXmzds3&&)OaERhipU})+#UfI#+&#xJs@5%p+}E5Fg}I6Rr{G_CaE7mLS*$I{OtF7I?TRjXGfd)L=cfm7|F6Rfs# zzk7LR-&cP^+_rRGL5#ZydNoOF3qyB2aMs8Bwa1!TZ7K}EJK0=;mC-pg0c~}=?v@t3 zX_#PPz_{}@n&VE;uuI0_aq&Yhu;ca`cFJ(^wljTr2`7(49-x;eC!Ku=9RW4-^0u}|2Y}!IVHL-LcW;nk$Auv`eJmT&Uzf3J zRd0@EWbNadTc;GvOlvyQ%z$FJ;&x0pEAsvLciM1$&}Pp;mM}2%Um2n<@yVS zH%}Um%i6Om+Fj`wpfrkGYVL7~SX50B9L-msc3QF*H9mh+@?>zx&K+>U4dlb?R05g~ zeP&$f#5?&bdhDvxe|EW2SC_SQvl_)Ln~m2KjRo1qln*Jv`n2)2_!C|Uiv%I3Vd$L_ zmo!VaJindfpDrVTc#+MruY83*hzC4Ae#+S)KPxG{msN{XDh<~F(>YhA136k3}F_kg^Ta4~|66lW_8cI7fN zB|?I9tD#w0RRO~_KQvg6Z!Qn4kNgwyhrY{Yfb9K**{;gkjJO~%^@o;mzUDkDPQ_9< zHSa%N*TP*O70PmUsL1FTUpAKsYb_P7`LDwWA^iJ}H}z+Ihz>dKm+Ag&(OTnsqgiUa z$L<|<;4lV9Opel4RU)kIANsv@!0`CPwRf_y}^_vrM^4b$&!sxPH z^I~!DOv(}fR6aQ&x-dmaMK`*MlGNDgoaq{0e}DaC`qL=3kdED@BTKy7H^}}bOQ%xA zyZe}fy|O68IzT|3IOX{U>!!;8PUm&}NQAt&(Wp*&BMk0rtImW97DQ+W@ptJDC=_sJ zZp1+*@SSBVJ1&q=BZ$GwGPzNkkvC^-dODzvv5@ZffoqI)ZRngZPQc512R%Ll0diGY zXLT(4n|HTO)kS?J;-zZ9dlRDEx&$oiL~GGvv8e+#nW+f+O3tW6a#D5PR?uTc13#w? zilxKPcmO?Z0*j#6ErMi_3^5;{OZ7}BFQ}DS7)?= zIt-4h89Zr^R;l@Mc3+65*6#+G`XLa$QtSdUi%VXTabE?gjwXzmirVGBKsmg?$LPlx(qUp z6gU|#9&lOw-$^I;@|+f_rktp6IzXwy(xkGfDYb7s2Jrk30sJ?17t z>PTD%z+N|wZTetU|C6yA#$F0R9ckU1bsLNq--8X<5E{v)$vB@;eXoZ&I5xR?x}RT6 z_50b6s?7;bC=3m(Lh}^8Zsy*Fab+Z+n2Rsm--F#AL!%20uW=|6dSk#1xC)rVmQ>*n?4L;JE!z12 za!nNE@G+(FPC^8&Uf!+n3Wb~Whc`QZT?*jfsCQqGisdXaKj*2hQ3pCNaXp_P(uR4V zo6q01-lTBH&Um_4(4gns+`yE?$_T3=?^Kx(6&Z?7ts9 zb6wqIu`I7n>B?N6IGRv8OKfhr%3^)a;DJy827qq><8i@LQ89Se96zX^Vd} zUv`PcUQXSoXd*c{tZX2@t)f^`+yov`hM1O2 zno@8yBm^?Uxa~8sWS_a6v-`$+JcyT{;<**4N*YKr(>-1QfuPIBTi<)92k%os<a(hpgQ?ZnZA z$0Ij>+0to0L*mip z6z%OJFv6hjerZO0JAi^w;k0}QBYE|(y(Jz}ILoMyMLA$B{QMoGu#jYHOXTWx(jgWV zs-<>^(dAcr&+)YR#y;?piRVtxNXK0Hna*X;a{!3vD208nTv~nInQh(SguBjLKuZegfOHdm1 zJlS?|H}UR%g2(%tz#T`&u3y33YvV&byy`AmlyZ-K%XWdzXaaWu5~k!|jonPIsX@DD zNolrEhaSZqcpF!l&T;M&3q}*O=1z4RbWHDpT?LN5PO_=_v%$L7{MzF%RV2a}qWG4; zyIZB{^Av`FW^UY+3Caj3*pFl-mUr@~b@r>ctZO5u8XCWU@&)1>x|tjc4DNNgjBvT? zKn4lZGJ&AD&YJGu)9q`;6zJcFSy_FyVlwP_b37RF)SKzjstVL9zLetc9~TraelKhU zZrz}`0Wc*j%j|!%^z+P*r!?j{A15j4W+K0*MRPJbI}*Ga%;Uw*1!uSA%DU?zJe$%k z8>~P~JWZIS$0mRNR6hT)?A|+xJK`gNH*&kfib;3E-8N~qFxLEvi7_-71C7d@7A*sS zgor@G)fMcR^;K0rIXhqU!S>-s!(@$y4Vh6w=q*qR62c0xr0O%zBj*Ws9o|nqzE?;& zbtP(+AEtL9*~|1a*jhc)A8I2a+dOPG+-xKvDtl689{D0(O@N#2kO<;iVeEE<%URCd z1(FF5a}-K0$l-ztkh3|e7Ik!+W6cv-pUzfCN=|S$O+U82=IXV+y*6TJso`M&Tn3r6 z2OsT~C+~jBA3ydN3fefwAGO6OD!(N+;=Gx>S%x2Ed(5=DM{76jC~>cYQa2d|Qa2r4 zhj)EEIxZOX=7nQtZNeYsYZ=!D?Vb?7iIdjt&8Rg)tQ7(564K|Wr)_~4T7GxFek}*a zxl4QstS9+)5B#SAHbS4rR?5}6xZz56?&@x)eZ6+7(-zOOQCyc$Be_;?f6;KSwxs`Z z!}B-vc{Lm})0H_nRMS=J7)i=nH))4qm=DAfNvRTEe|Kw={h8&z@sL{VU8y4OrE%P~xmRt>G!&E4 zxT^U*G*$)Lg&3~+2%w=z?Dxn&)VZ&8Y#IN!fKUy>TQgszfQ;R z-1Nv@Xiivv_M#n!VMxhnZjFc3T%NJnLvL!6`FKLUb(Yvx{POhELG=r zmA05_Kvc`5g0#Fq4i&D`BR%I$(iVL`Uwf3xe8#wdSUW}mPew5HI55wFv0wh;>3L5_ z)ERR0*VJG|H)vTz`X3CXb-&|2=7c~(uVRr+FTK*gaJ@X`IG04;@#Y9Yhkz2zUDaDn z5U861#O$H3B~OxnFoH)jjJprqujm-_k5diR=550NHUS71KNpYJUXHUjVuj&g3-8lH9=jDc=OZVeL?e8NF# zTDnnGsft~Tv7V9$r&eFLl77^4@X0k)=2F?egoI%l<@m5zKCEnml_%Yg@vAXJa3K3$ z5-MQix#aY^@ib1YVSm4qAGZ&?D-mH5Qv9%#X_bjDmUZ2c-C4mg4>L7AHhSn3FVdd8 zGDnv?JnYn-)TeyoQb#YVvntr(adgntsfr2u19N(|-A40M_F$9nw}r2h9z{yTBxIk( zEvf7vI#JZQ<3+}btZ>JIu!so#3M2J$cWYfkORL^|IQ4C_850BJVcoUob>sNh4iRxc z%M=whIHcDYqCs$H*;7hTC&~UBRxvrL>L!D_XEBX$gq@-k5ij;vQ0iY38A^#`|R3acH#2ET2mK+fgAp?tD0LheK z|Bg-#$xM6~N(aeIK&F$3gyfouQpo+!A9~M|TWnQp8uFeGvSB!stfZ2}4>6-}{|l`E B&6WTF literal 0 HcmV?d00001 diff --git a/README.assets/image-20220530010351991.png b/README.assets/image-20220530010351991.png new file mode 100644 index 0000000000000000000000000000000000000000..5201cc551603147dd93a483ff38aa0d624d4161a GIT binary patch literal 16898 zcmd74Wl&sUw>5}saF?JB1b26*aSQJ5?ry=Qad(0Qcemi~?h@Q3I1G93y*2Yy&D6~N zn5y~H-F50z_dfgVXFqGLz4}Bb%1a_4;3I&6fgu5<#FW9nz`uQdZia*Te9af?;{^jF z0RxH&t9oReb$a@Izt8^o;5)p~{+oTq3x!Ss6&*klgs`Z~BVK;5RK8*MY@IFtQfXY0 zX{>E-^>WHJseW#BuG*jljf3f6sMN>cjZQ)r7-D16{^B(G^zL|x#7Qc&EX|aAxaT-B zahNl8xbA#85%qBBE13HrGs`9?>L9-T@KRP@Zu~n0zUb%A>?PbTIroBwYN0uRP~;PQ zMiJyn$Yx5g4Nx*+A|SHZGOtYNuH?(0#~pm~QQd_|6E?CyM17zwapUy*X`a=Hixb!z zv@Z8Hzr^h(AkY9uCE>$#o7(2Ap$pGFnl}A3=gc{vpYWiR( z@POh&MFIX?fRMnUy95)VNM03*iRPeP^KCCIF)AFCMvVcuTKRp}Ad?A$h;$kF3NAL0 z93B~;u%d6C7wJ5TSgg`Q;sZOhB1jclQGp-$AfYDM9&sO5-*OpK&6Jqk@wQBZ?1|5% zJWMUEpd$e9pToycSlC@l`th zyAOf|IM1!%_o`d7{a^Q%G%Yxd;(t1O=|lCAhrA>F{!GR~wO?{U0olpPiAIyn3U?f7 ze!whBpc`D1XboggHtJc>Hay(lfL(|MVr*J^xD!xr?L!zwsbN{+MP6=7i@(XrQ2Fwe zAiGQV6NkUAC;$DS4;I?$>CuTrzTqf~o_=HC1fx&f$}y>cMt4+I1x?kWZBb!;6uECe zGlBmp@**v(l#HD4>NSIQvtQ&(ylF?P9b~3{np~_uPWRinmKGSr0ow*_)73TW*4`Vn z!qu?CNBZR^5Bysozs+M`^@{sLB43lu*UPsZdAq9RJ{14<9|G#zKGjl8P^60Ls0n}_ z2QG~U3p6Y&EH*Z_tKBHZ-D?jCfpF|EQE?}*1H=(2uYK!eWJQBwYD$KYn+-w$Dt7eO z{iI}O-$@9X+nbTDziL&qSBZF5haL}}orHP&pd6NLaZdGw+*~;|P13y}{J+IS@*2)% zW$=y-g^8j=S&v?A7Hf_0?hBa8DqctBsYg7j6BD`BfNqk^idCA?F9He8w#L@HP-F-T z9fs89oA0!j#eBax?aP0<`S4sXGI(jl)!lE%QmQHx)Kml{XtJhhsYwhFxXyb+-en(B zz{8Lid#IDNwzd`(7uVUYar`}BlVrjr^faf3vI0}=+eJ^W%Fend+c8#zZAOy47hxU> z3kTFm2qC1ecqS#A8YF+0N+0k4y;Z-l43xwHx!6?;r+J(;$s*iT?4Z<*1c`%3(MnC@ zN)9ZTLM^$>Iv$Y>&CBCAW#u{8kx~x^&l96eA5ZR|SZqD&uwYE=A9)|$1r&h0?5KJj z9WnNjnJe*4#%}zATz}-Jvf!WYy*5?2J%b^L7{q8`cboN_7co``C5VL+1MTD-BtnFA z1KBt^=T=rC`gZaf8Zd)*D)6!rzwBp`J(1IMRI}~7+d52II!w~2bx4RHsL2pIx`Dwn z88X2LA)vNEv677#kU8$k&Zb`Wx_cn5xxzGk9XDBBN&wap0g6I!eY7CGf{B8;nk3aqBAM?5+_tk_l7lWI}3Msa1 z(P2=l(CFRi3oEOr*uQAM6lfM!rC`yGLIbd?Wsxb(OiNMYYa(G)pdIFkJVN^Mbs2CS zArS6cX!A&$!K9ZRy1|o+n1|e1{o36$w|6EdZliKo=7?%%kp)niCnT6qi5~WyD=E_R zz%@D+jEQT9#XItV00EBsX5SMX@1aI*FK_DI9}*1HrKKZ?G*gA07DW!;rsC34b7fNw zh7M7tPnQyt40=ftsBoaKS@eWIdtdgz-h;KJ*~1K&2;e zC~Uo9SngiZkN6n#lF5~~x$d>k3(muEY)fM^QC7x>6pQ-M5zky4HoCB2R90pWCZ)TJ zXyXjeBt2RKS3$2evt=E{JBQR`_Jikn-|$} zTm6H8pi7auDk!rlcQ?ny%52|={UjbVob8E}_|m@o*q{1zqfcj11zShseJf;)xNY;+oiDkyf(zT*G1uTcNF*Z=M)_Qeee!`T%RS%5nIJ%l&VGX zvr2{2Cd>{dv%Q6BN7&`S*>Uyk@&*v*r>Qp_T1%%53=`$P5QOlKrqxZ$J5>imgjZ14 zC8j6Jk9^;oalZpQmepkXQT8JuP2uZ~Y6bVce0wOP0Ab#5!@)tOL)?Ro=Pa#*_2lsu zWJGZawefg`4*Jdnc=f)+IKUhj6t&T8*0BydDI_foNN6P}Q>xx9;b=Oal_H+=l(Oph zLS$5igw&1@sM6h&-Aqw4^yg?%?bg|kwLaS!V|mH}iflAr5$?7QdlGKSoSkUDZR7Ws6da3*+=;snR+BZU zys(SCiL;dzS;3O1p|c_^%y{)InZfXR*(*(9F-7Aq3!pf`nlPay29bB7@Uwxai?KP- z@6`}OJ5dPw=d>?JAQOHb6@=LFr?mTH@^Ea~e&NypXJ+I zEaYH`2Ejf!{oI6Vr5m~WB%n2nv1wNFqq#A!o@7m$N%j%1t`Z7J^*0%gfl=i13i2l( z6nO-NT#3QIbGI%b!z1xq_Vauc*N#2-FEOw3Xq4?hItbay5Qz>P4G4=!8&V2XyIH_!S~jR|mj5 z%b@9{L;TzL@)g62iz(~s>KwQx6)+n>ICAjl*c9Bm8+b8!CZM}v9$KppWVR)}X*Ras ze?t2pElBV{g zq}$i%S5GrvSQt`K zEXpJSB~$^EM8Eft&=7z}a@c3^jv6i`)B=1}VBq3m6keM>E!w$(pJ#Ba&W zue}EOr32DNpev5unvYAl_;&j;XTK^Ea8n`l0N%F9&(B1p%3|6pcolqjX^x*Idc5Ja zDELA+CHRDI%>=fmc{7$s*QBEX8zOVz}DxFAn~8Sjt1vi zV>cxNrh7AAuqCH>b=J7Mwf|EU9GNi`GAT7i0|)|7`xp>`U`zV`Z`?7Y#}iVd{8DJO z5v{-wTI-lK|`wrpzv9R*RLewk5{I14yq%zK{KL1>WENfQc%C#}?DPqHi ztkcK$sRLtIyMsbk@Qkh3@a(0H9*+UJj|e}L)Ho8FU$bHLzTD*}luAx}Z+u;faekLD zInT|4Xdm{?^`(nadHFeNh2o+M3yEeP8aGhTt`D3%n zUGE$_&#s;K2r`{9*#Z=4g%lBw{J-{2hEcBA|L}Psm z#~U2)1Z~;N$I{HaC!(nl`yhqr=Oqo#m#G{d9U1%?O|HgVp3_)5Am`s9GH^fO1p9DS!%Qmdu>kReAN~A&0N8v{2+ipMi%D z?e$(h6fT|CuAL9xaGz=5oA6>8hcJQ6BWsiJX>_bA9L>K;^e|v~<)tNwdH2UJhg8Ur z(C^{Gz7pwN(A|_XAzbGm#4fnoig>ByuxS7nrkIjP- zmliE{3?@Q!v`XMpD}B$wD(w80j~q+H&?`V58{*NEASbdQ%GY{h2k|S^>j+Zd^+?6< zu6!x|EpshB&Bj#hB2bd&XzchW;xPAVudm0tpH^Hf6|G#{f>U5B1sAWbm4rCO-!-%wf!PGxLgbbOl@` zq;kg}JKna}6yCsvu7zKu-ye@IpXO#K2z!1EsZY(iH_iBTplCffnfQ}4TC1}PjEU{G zn4lBVAnU^ptqCjTd4K33H?ldOp?C2ZgZ~3?P{G3g2nY}e-`Lo=e{hiVLV~s@FVB2I znDHu*>3FzB9+Ut^8@fmEcyzz#!f=avbkfiKA|QRs3UqaG61gQgf3$ypiE!;Fh{jdm zavX_RZ!F57E03?Yn~%RUpwD-^{^DbeQg#Md`d{=YXpYS!AhPMSb=9U+WUxc{myq}Sk+ zX(VaZn`P&635#hMIVqY;`$?`9oMtyn8z?2pAA*}wGB>CF7NRkuJ^DG_>8^PpcdI)WUhe z3W}nb$Vqe(LqRc0SMn8!9MDox17$hC^!r`o<^N*aa zc$?9VmO1)0(`vl0dQ#elDR;rm4Szp?17{0asrJ5gBG)t6LQVco1s@>LOn>K1@$HD) z>m$PSKN)rDEfx6>PTYz);g3BL3@nBst5gc)@f2JY=vb=>DPqlUHZQC%3T>Xyae0OE zrQ)jT!qc^+E=vaja%2P~ReHRmJ9&|3R{!+#o(aQzDFz^v$WiichP!I~be-GU?2Z4L zt?_x}wqXdK0a_#v3Zl1EeE;GL9 ze2u^SbSH?cM@u3hk)(-~*_r6g2s$|zvh_ogYs!nNh8Ph#6W~LF2jBtC#hXmYGiO0A zqB@X1wrs>lKi7;Yy}bm0Iw3kD{{VRQ*;)yRw>{0IerI->i<$_+cW9++K-B6xk>#;t zR-;Gn&lWv!5~!0%kvTRU1{~}t=+5`oO&Lz93n@8jd2aM(?koj`YHGzeGd9j8{0gLLzjr-MvtT3X(Z zKsIh0S0ef{^fIG7AP=AuQuIbOIsyX}9os8@3UiVeR!(bqLJC-LWoEFwGZ>-FKhew4 zDKn6+iIufbK5#g7x7I8@ssSqqKN$G8^@aTU^FO>9_^6vU42_E^t z$$VgeOGYsnkc7a-FjyhNL3|6>+J%iaI}(o{ZvOV~T=mtYcINWY$j;*% zN7u)`(XYhVxfU00+LS6&0?ND;inz_*tm7vWaHtK%4+KGPL;lPMSBNsM1hd=i#HjQH zm#o3&&4X%%?$MGBubdV^_$lL$p8J`uK6LhdpBN5x&Iu^ZPA>wm6~wOIbBvh&=E}X= zpUk$1W_2W6F{jg1d~Y7G-#=W)7xsMbE-dy3n)y{t8O+a-Q6{oMT3UT)FMh+j*9OiP z+k5H{wI%!!o`M|_*8w{{YjnErL^4Ypy`a;^ubcgw3kvn#yNPsZAhE9Xp3Sc@9d(1_ z8(SHo@aQ-J4UC|5VU%Ggjxr$v=q-0{K-{$lF=s(&l5}oydS=6LvZFrbUmd zB47|t1BYh?MKV5GiN+ihyaOmBQ&`#xW~B2NQyyP3NLX^H_>WDQ{WhpFiTa1xv)e+g zl`(U12-n3o_8sSQ^Ec;qhm5)5>dAqbImxXVl&8L5K%c`^F7(;i;o%9g3y_4NDRLP+ z_T*V=8934EiJ-{>^AW?Ze6LZ!(b_;0d-at_A6Mk zbrrq+;+JiS#m=Tg<0z+*VTOWLxA3Me%9O6gIJ!*2CzGo2p zc(&K@oELuWc=0%CqC4`+Cf;Zdym+QWX2=qGnkMaFII<#Fed5yB&=@uO(AxC96@5QW zzGw6QnRF)%OWQ-rQGG6wp*q&N)t#vI{280}`)OK8_fl9TUCiqVHXe(-K zkKEaed!+cSf=6_#HWam#7Ia$OP4xY{W~&p0Oe(`4-mNF(>uYkCxOow@u~I`>4EaME zLR(^!^)d%D^PO+P22?R?bWkc7BjL9*o9AIb*0RS1v;8|W{A9vWQ^?pP1|ID=XA^(g zhzKA+=gl@Jb{?_h#Yex=QIi%AkcC0|L&dZ&guW}+?a&cy6m-1?F)&2<2s}fSH)Ea2AT^pX5Fr6t7U$!|kU}YJWpgE!BbD`nv7uWc@ z`va%3BvL}1ydYs!`=HhXh$Iea>o$uJIUJQ5j|AWUeSI{QsM16@6~kU1@$H4VgVdx2eeaq-eX-vY+d z6l?zkaF@oERcrqQSJIS=^lyngzWII54VLRn5wEYW=NA`qUYvqU88?q_=-zDX71@WNDEPhWffN)FE)PHuc4>$mPDpEMriQ3&04Jw zJox!1O$wj{(u(JabPYG+0f*_07AII89=%BoX{S1;#bvZn1Y7{Pd*52yqOtrfBt}$$ zxoN?!V!lJz|GL|M&9U%MOKvsIn3h{^*}B|o$=Hqvx^@V|!Xom<;kkB2q%J6%sx}pR z&y1uGhGtsw1KU1)V~WbKOZ7*#+KQD}1+($Q&E{j@d>$pp`8yZb4odcptcM!)ryfUI zO(->)@z2w~QliVXFF(E8-Befib0mD<^tWe&&Z4)`tw(GoPmE1rNeB`seL&0Alohrk zGZW%Slgi@4NNi3etPh+egSEIoyZ;L@ zOb+WkWM#d8WEItGqLEX<{ijPRrMt=ImV@G#wAm{{-W;Eh>bDuNX!8-q@^pV!Zs7HH zwcc-(U)VRdg5ABu+F*n6AU{MwZ*x-hlA)a*F)K%GcGESFi!jE-w0PMQJatc*0Ayz! z2#$8F`U@9ZFiIQXXKpIf?s-fKvx}lV&deaaR>EfvNT_vx7bNxp*Hl)=HTJ#&04q#* zHj18t4{}|(hkAYylJ8&!;Mg};xAiTy!X}Z$bE2ajkuoT|^wOlP@CG5iL#V&qP7rnr zY+NmUiPqcutkXirI0xj9jhq#0JxhkAo$eeJufFv!eBq7~>Dl|ece67`*I%;Ce2fVp zk7HMYBZ!_il!5wgHu^2NmBI<8)ypj@x0H3dKi-_4-gd3e%pXPhm z_pAGMxDlAUlu{BT+qnR+3p>Wh$?zGo-=$v1=dl$4PODM@LHUwU_Gg`Wu)t*wh({f8 zh)86a1SE1)C-=RZ$1508x@a>(AoG-_qv%*U-*Z94@9XdD-lvb?nSZxeo?}TvgkqRQ zY|G&qDgpDIkQCFz7+{u=;PKe+RCOqEfiE+0k${n-=xYrp`~D<%oI3iCOLy={l(xm2 zp%1Ubd)~}r{J$i;i;wW@&%@0vO(e0=N*s(gjpu)+VY~OPQ?+Wgu29|A9k381B{xi5 zRhbr{JjcnoM`x(@qlWzRbo-)YhlGSi>ql#j|Y-1JDS5G!&4FB$g=!YR2{(K z0`XxQUyPHC8S`B1xhzqL?qd@thEsIdJ7$5 z6vsAs36#>hq#}WT1VEd_6ZY+cOW|S;tQV zcM2Z;Q_INg(vF`${>KZ@Fr^RRTn|ybO4>K+gb>A6Fjjjm_{PfbP^_zA!B~e5IgQW(3ZrgCJt0q}jhPQ;GbK7Uf@? z(~M8D?KZn{@w>c~yb7BEHCio12q{>g3`Wx)0!UmHSY(NYHak82PcoN*;c;e3koT`k z%lrjaE53!v)(8uXO3p)dNRqR!G`}5`v$>oYyeU^kC(4jZFU(9~Cs=N9!;!-ca5|t% z2bx-XwImodnBBj4FE7o)_8Zr#fA;%&YA2VuI!o5m&1Vp0$zZucRnOmP*LjH-1SoZq zTB&>VmG=b_7Pe%$8an)|6yVg~)##PhVzL*|a z|5|!x71fdLPLDP1lfw&I#`A01I!}WTWar#XtG_g8GZuL@L;D!zguCVTTXyFrv$~1? z)ygg_g<@r8WykBy*eCE$q0JTfIGC$IZHY?$K$!3W^;!nS7>X+l;Dk!?ZfA#AA_rdeCWdx4p#GH!_{&40{s__ z^0a0}bo-m#0sDioHJ1oK>fd}`S;>;jO@SH{h2oRV5{;*~r*Q^s4DMd@xG7brpG&7B z!^7J--WP@gkyt)ABUFT34grea#Js(EZx1F4+uHEU7rYJvVb)z2662=>%(I-V#IRzD z3Wl;$TYu&TbSK-|zw4_lRc}w3K_Bg0Q6hd97nePYHTMx=fB0}>^w)dB?Dn|F`8K$` zx`xfdaI}B{CqevKM?p1GpLb)&t^J?9Wh#e1O_tJZB17EOmEF>kJninwC?}HZ2EVSh z2~R1qqu`84^g0n=c60}ulX(i-eOX17e6htd)Xf*lF9$Y*TX)=5-<5&<>%i{vI3aa% z8T~D(6G2&WfgK+`=0JnHn{ZuOS8OUuYHOFbl*2*+bgML1?k{VlCLdO#itW+bBwZ>GH z);akH4{Mff#o^SSjWL&5pdJF+FrJ6;LDy)4o*X8*kD|K~wM0x?E4&wb=j4j}TQ+#7 za4;w;$Bl6_DMB`F1K1Z>>2oz{^6OB`aEz6&izceBb?N#FNv&bRe`jqf{b_W`Zu_~+ z6X51Lx59{)YA|3kPdeu10)tn0R$SeQ;+_yQjeDnz;p6rwOEJQTuM{6a*cK5%A3W^G=$;OANyjMVb*vKD)Gpg(fTMjPoYse3pg!%CS<2VQ3!ag= zYKds7#N3{yS|7IQ3(LLk5shp@61zT%;KZ6J#TJBrH{)x-k5nn(#RsMqePE#vNeSW6 z7Uyg;MTGp zI1+J7B$$|VVyQfTKf3J-v0?12SOTExM1)cdLzPA;zl4;(6DqBhPYnYRT9K=bXPFM<`)|9mMDLwY_*z|cb(1XH(rJ*4vvckE} zjG?cvAln~0P~HlG+mXVu*9@$`O47Gyy7RnvXE3oqGX4jtE6A0yhuswA};#{PHqY??jbXW+5F=<6X-~ z!lTt75>zC~L787)M0(0T{hCGhg3f^Q=*9bYURIhCT8izcKTQ0} zUDD@(0R#z)tf;RaH(^#-S_;?szOJVXycELGhfiQ8li#7%Y3ahWs6)=CfE3js<*_~h zvGfJoXZ#A7ObSReUL#OCgW<`xQ)f#D5xJ{OiQw<{h=r9#kP!da+HG3HQp&W^KItRmiY!^uDS9D(fi{g ztqrMA0DZ@e4rfyqtf%3v8ApY8qG?>qlgp{vrY<8*5#l7$_0|fs5li|vMn?0I1PVIs zrf4i$wQaZdDN?GRq2xsxy!RTc)Ayc8M;YPB=-MkP+a{WX6ol6q3=%SaQ4?p#bsDS_W8TAT%qMEN?zmi{8lzq9` zCa{_ns<0?y7GaNeJi>#PhS?qYoQbl}!0>?1kBg`PMpF?@t??DugbA4-Mlq670<$cx zU5uFM%nZp6aF-_Zo0~5UF6@pC-zC4*24qbAskM9H*!1d%KtjfoG9Nv(15nAEaJ*TSsUrp#D`i5{>LlVh9BDmT(25Wdvulqc0z7h z0b=V>3Ki2^luFtI2rauCN8p{ixuYhrvCMK_Z60~K4H3#*6fnXFYHQ>9gfpQVc8B?4 zL!4?6wYPKo^>#M2 zdNNT31n~#`p#tbXfX`o`dbIiM!VuI943zZr=j+9;wH7oP*a+2z_#7WaU&z%&6Lx0= z5|9CXOjOJU4Q5K6`$P~}t@|1ZOJ;p%r3UYP`u$w=saXI#*Hw0(>m4vGWM`B3pXrbN zd`{IlKe`&f0)a&q&kM5Uqdhc`)O+dm2BgLFzGpl{0w_tW=5|=gtz;hnF3u3fO;ZWy zOG!&#_yu1m`u#{TF)gtc)!z}f3otb)vt#>Ch` zt$q3=SM2c=;4Ed9fPk?V0~&7E*$W;@C>J$Moa&bfJOllI?~8P-pJv+sb4Sg)Q2TH^B2>^! zMAsDgf4nyG{g?{>EI0kqH)F9u70;mWoT${v=mhi9EWd0-lPkkN6rhZeNEK7@L`xyt zttlcpr}7cq#H{$mU#~%mF4T8an{xKQH%gzA#@<|@gSu%y3!e3PTWQzpBWPwVpva5- zsMaMkFMqG1+ZQr)HsFT*yh4iGE$}A zgayHyactmm?-3%0ek}c=2!KkfrC4T8|8m3z&AvbIM@{HHzmz3mGLpg{-2F|c7uS4X z+p_Ra5+Wknjra9m9{9}0Or|wk4V!~B6kSjNuah1Sq7#pt#w!uJb08AvL&fyzt8z`B z;f`dE^M?Z3$2DZRU@x*k!;$8bXK8pYMrLK zHzo86kT85*&fdb?4)ud!KN448v194pzS_UNyEYkt+wJF2bq#i`U<}_hZu2z+=?l7J z)}Q)n@gz)}>JNNHDXzPTH^A-%(0!hJ)u|poUMdnVCvs;kJ`OLG?tMqaV&m@4}P}Vkb!YN0Vp|Sv3w2^j?1>N zH(M%R0F%w=3fRA!lWhm^*Y!$s*+g=+<^@!cAk9;$8vV&oH@d;tD%eB z=j8bh5kQ%3Oho^vPfNoC2(%!%n-gye!I`Fw@zm}?;=9}B-98iF#^6z>tu2~|?KKA{Rm2G(C;ib>_`*G3gVot9 zl+A zSdINkQeuIQVSQlCqOBkpUMxXZ7}^5I8twU8NIM$xS~G^1o(o-NI5%lLvmIqt+oo@J zQA9zKk$T}zKf%MCFF=g(eE4PQ%F!GS3F(gzMpd+t*6Z=UAsA(RPL7ZW-!}gk;+~+C zd6cZaJvS>Ar2z;aMN2l6H!rhe2O?Le0@m0O_ab8^HgH|S&6bqLcKyAHzy<|0m7mtvcez7R zyJrLEjx!1s3!Z!_Tm+6~0*c>{j*A30MRc;h=1T_6eeP~#AdV`KXS2XC>{xE!p`)^n zBi3ii;wtKkk^eSDAxs5u{g9WCwX!K-yppKlP7f-&Q|W#oN$vWBR3vg z7qCX1w;znRJ?aN4eAB?V8LJ_>#+_rnAshg843{L|NHBi8L-tY03+}QDkJJ=pYdPM% z7-OfzW!gR?SdYO*sj8qd&b(Bbk=$jGX`hh3N;BoeUEs0i z#7(o{{@eM)pTY&e3~L7)@`vqPeNyaS@%;wt=+{7f=ZIhzH<^p+dN}&aknu zhhy@JM>TQ@?jK`~B|i6a2S;U2$vwD4dUS zjMMMVEq{9x5qY4EaXtyESqCXE{iKi0Mm70MTp+qDb_&-q-T25vAJaAmp)VoWiU>(Q zoc&3|m@D;RKu~dG&3W9%Z|zIp-%ZFubHN!yljE@H__IgcDJmGcg>C zh$QU@hJ0j1RHjlZ;X7vA?LevaB2jigVFrs561;!vq2IejKq>~Tn?uJr6u%#wzy2Oc zXGc(U17KH-NIKv@rr$`ku`mBuMv;OkSycT)gnuBW$TH&*`yYIf{%;iX-^StP6PCg0 zEM6rZ^}@e)FayM!5*XJjq8y~!&eMm2AvPm0nrF*cI(q-621!-y-zux~{$5I`{JtM! zmy12iU?xkSotZWsZiQV@LP&TFhhre#o#Px-^lHxMA`pg$VA;v`pP3j!_|**A_$1D@ z62#Dj0D!E00b>V%KJ86)^aLwOp+&4H0uj|Q2augE-s2_;Q&bUAAQ`y3Y2S`S-xo|L zbDTsQ4hP^a?|^9DCD&TBhg9V#IX%Cf;?AyNE9Md{*k^3q4S5*!`xLKKm{^q5%2=c~ ztpDW_iKsBLS!73=PXAOf(wr`Tr!~TjB=A21HV8D|&L|iE$)}uMBeE?H%#IxYE5ns0 zITslsME0kuD*n#*#weNomixeBFH8t+emd729H;-D6eG#1!T07@?1)yS4)&@4XIk8h zB+x6(2#X}TNO{4A?w8?WP?6w$r8<=_V~!n+Z#&HJf&;qhPSUnMYSaNs+fu32Y0}Uu z$T2dKxYwUIw6JM-=mM_M1qW(FP)nKrcQ43KUHOb)tBgoMpiRv`w=4S2=r>4HU6W~( z-|4QK=!cayEDS4zGR$TmDYW3&0^uowh72nWZ`;48^eo$xDOD zJD)nRAiGlkAGw`1ITJ5DfvSYSde5to0a+lA{GPV`?NW*UpE)~zh4tK!!&?9CXNxUE zr2qzw_iOf5oeee&llv1}FcZc{m}Uhw^sT1Yp_IV}`m~WCAI>V#+^f62uc~izF{*J7 zGwp@(I9q=elUuVIdHLAfMXW55>MvhNqlSVfT0axGF_iNcaPW3TIS3gFXh5oi%>DK9_Sy0|=iN&%^E2hfM>gDf zOM!p^)uU*7MnZNAxGbBc&?K^0)$61J*LheF7;IT9UQv-5XgyPYr^pe2>*8XgHJS1Z zgS;Z0u53|kul}{11KU_Sd@oiRLtx2oQLq`Yg!|J*phL*-d-wGXBv_Hr?_L!{PD&pW zy-v4_Y>BCM0Ln1vULE7lgIiW|(KUqr3*Q4URfinS|*jsqcz z{p~o~-7>GfP8wYc>PtdzROnyBOTO(N|-fb?%Jm2dPPuCl+kPW#kSB>e6PgUU0m z=K*tjmjjpA@!a)UCUbsj+4+|mpROtmQADIm6TXT}N3lGZj%N{3C>skXcEbPHUJiNb z9xG7(iw~m*p~@JQl7{w|Hq;^oGZ9DVgCvVg;#pQ8E3c*NUnisG+ae=o{ULhJ{e)!0 zPz=XqBn|`=!b35s9n}>k!>G%W4bLpm`%27W8K&cMA9puCwR*ID`MW>g_XV%1C!f;K z_+}&z9f|9!CVEWx+zz^ozg*iMX^@}Pm;4}8X-(U2#$O}an=5%FFTmbgDv?-|XiL6j za%B`8bjMlzG;1VgWK`ewKR=Y7o)#C0+ZC)`=T^#*c zUa44=#F8+;k0NeOvDrK<`@udxKd-FfOdQwQl&$LvhV24K?4u$)(V1%N^V0GvPh*}8 zS8{LaGDbubj$to|M`ex&@wm{GAjc-aJY5YuUy2u$qbUK;>2EbUib4wlIe0Ch#rFrs zhC`utY3%;U#HrQgjYTw9|9JQPgxd~4C|0}D;hrYKv27x%>}kgahN*9N@LI?*rhT=RyHo& z+F17t-N&$-e?~0J)_qLnTjos8O;S$So9Da<-YQJ9&X1{wRqdJavt%xzX)dlWl7TN+ zoq#vymFU$M=f&KAl0#HmCuq~+a4MQ_16y1V6I|H}?sN6zy~``*uXiIj%W>Kce*n1( z0=AblARsWg10T>>#KL$p8G#nc0>6vf;9hNLed#H& zB_OeO^1Xpk^G_uhz8RS~8+PwJHUT74_$u}82%MRe=z{Tbd1C)K6X|!!xWQUhgp^`6 z9NQ0eGj!k}a78KF0rUBx&U{QyBJQi{2PqgL?oJH(ny01tIkp_4FpuOz=oYo>&yiKI zv8*+b{Xkdx!H-ioOh$F42JZnR@<17SRdJytl1p{}d6^bP>&0HO`N*L!*}d~MVb&ls z;V3lh&_d1GHy%Z5d8IUJl}~8El+k}4>g*Q9bd3iq!0w^3O9t`zpn%$c&jkQ*_LR3f z&1-{CZrIx)e%>eMWCH!YbuOUk2}G51$qvMDZa2wIx&8$QY^AUMhq@9bmYjl-D_`98 z6>aIvJ?#U;I*aUk&kjo0{`kPDEC>HL2|#Ov?#siqjd{=lcsnD_*5eQBE&t(mNvd$9 z?!mFXwdIwsEtv~K7L7u7p3*+#8K=Pu!CGbhe)?NXI_w`lrK?k~(7Lf$nBw9{k~6cA zc_r$P(4~1Lo~7m(aiMFib9W>dyY_`l%{NMo$}!>f)9{Y&FEZTa^XrMc)Os`5fm z1F?D@a7aT+69Ujhpi-ccP|0cl{|-}tQ-r|L!G9waGXM&~lS0TqNW-CNC<8Y`^xHx? z-&p;2)P3x$I5f%|)P8@H;LRV0i_C#x@0hPf7kPz6SCsQm5!`)$Lc5q>X+Q5h?c7tv zSUBl<;1@|ZRCTs>effd98<-ei^*ftS?$4rU>A3P%6vvk2WOg6@dmyJ9s(7Qpg4=Y4 ztAdKqjA8>^q**`#J9lw}xBKW4@%43&YAzeoY0G1ZoGk43){hE`x64DFy><_0Bn5nn f-i^1)1L8`Hd~(SgcihisJAeVj<;AK*41)eQi3hyG literal 0 HcmV?d00001 -- Gitee