仓库 - LinYang (LinYangPhil)

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LinYang/verilog-pcie forked from funzero/verilog-pcie

Verilog PCI express components

最近更新：接近5年前

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LinYang/tinyriscv forked from liangkangnan/tinyriscv

一个从零开始写的极简、非常易懂的RISC-V处理器核。

Verilog

最近更新：接近5年前

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LinYang/e200_opensource forked from fei532/e200_opensource

the while project e200_opensource

最近更新：接近5年前

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LinYang/Cores-SweRV

SweRV EH1是WD开发的其中一款RISC-V core，支持RV32IMC，双发射，单线程，9级流水，性能应该说是相当不错，28nm可以跑到1GHz。而且还有份详细的文档，不愧是大厂出品。SweRV是使用Verilog/System Verilog开发，使用AXI接口，对熟悉AMBA且不想去学Chisel及Scala的同学来说是相当友好了。而且支持verilator，必须点赞。值得一提的是SweRV带指令cache，且实现了丰富的cache maintenance自定义指令，非常值得学习。

最近更新：接近5年前

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LinYang/wujian100_open forked from LittleJober/wujian100_open

https://github.com/T-head-Semi/wujian100_open, IC design and development should be faster，simpler and more reliable

最近更新：接近5年前

LinYang

1 0 5 LinYang/verilog-pcie forked from funzero/verilog-pcie

1 0 858 LinYang/tinyriscv forked from liangkangnan/tinyriscv

1 0 3 LinYang/e200_opensource forked from fei532/e200_opensource

1 0 0 LinYang/Cores-SweRV

1 0 1 LinYang/wujian100_open forked from LittleJober/wujian100_open

搜索帮助

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LinYang/verilog-pcie forked from funzero/verilog-pcie

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858

LinYang/tinyriscv forked from liangkangnan/tinyriscv

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LinYang/e200_opensource forked from fei532/e200_opensource

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LinYang/Cores-SweRV

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LinYang/wujian100_open forked from LittleJober/wujian100_open