Perception and AI components for autonomous mobile robotics.
Express DLA implementation for FPGA, revised based on NVDLA.
NVDLA Shanghai Jiaotong Univerity DEMO using RCNN. C++ and Python implementation for embedded system.
header only, dependency-free deep learning framework in C++11
The Ultra-Low Power RISC Core
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
Ariane is a 6-stage RISC-V CPU
Open Source Software for Developing on the Freedom E Platform
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
PicoRV32 - A Size-Optimized RISC-V CPU
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
OpenXuantie - OpenE906 Core
