@qlf_123
qlf 暂无简介
it's a github uvm project.
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
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一个从零开始写的极简、非常易懂的RISC-V处理器核。